High-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit
Through high-power subdivided interpolation circuit, 90-degree phase shift circuit and DC bias circuit, combined with digital calibration technology, the linear region limitation and error problems of grating MOEMS accelerometer are solved, and high-precision and high-resolution accelerometer measurement is achieved.
Patent Information
- Application Number
- CN202510565536.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-08-19
AI Technical Summary
When measuring the grating MOEMS accelerometer, there are problems such as linear region limitation and poor signal linearity. Grating processing and assembly errors lead to phase, amplitude and bias errors during subdividing interpolation, affecting resolution and accuracy.
High-power subdivided interpolation circuit, 90-degree phase shift circuit and high-precision DC bias circuit are used, combined with the DSP microprocessor of iC-TW8 for digital calibration, the sinusoidal signal is converted into two quadrature signals through the 90-degree phase shift circuit, and the bias voltage is adjusted through the DC bias circuit to achieve high-precision digital square wave output.
It effectively suppresses phase, amplitude and bias errors, significantly improves the linearity and resolution of the grating MOEMS accelerometer, and realizes high-precision linear measurements for the full range.
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Figure CN120507537A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of grating MOEMS accelerometer sensors, and specifically relates to a high-resolution grating MOEMS accelerometer structure interpolation linear processing circuit. This circuit effectively suppresses amplitude, bias, and phase errors present in the interpolation process through a high-multiplication interpolation circuit, a 90-degree phase shift circuit, and a DC bias circuit. This circuit achieves high precision while significantly improving the linearity and resolution of the grating MOEMS accelerometer. Background Art
[0002] Due to the advantages of grating detection, such as high precision, immunity to electromagnetic interference, and fast response, micro-opto-electromechanical systems (MOEMS) accelerometers based on grating detection have been widely used in many fields. For example, in aerospace, accelerometers, as core components of inertial measurement units, can be used to measure and control the attitude of aircraft. In military equipment, MOEMS accelerometers are used in weapon systems to assist in the precise guidance of artillery shells and missiles. In industrial automation, MOEMS accelerometers can be used for robot navigation and attitude control, thereby achieving precise regulation of robot motion and improving production efficiency. Compared with other optical detection methods, gratings not only have a simple structure and are easy to process and integrate, but also have high precision, good stability, and reliability. These advantages give grating technology broad application prospects and huge development potential in the field of optical detection. As a result, many researchers have applied it to sensors such as micro-displacement, accelerometers, and micro-gyros. Taking grating MOEMS acceleration as an example, when there's no acceleration, the fixed and movable gratings remain fixed relative to each other. When acceleration acts on the sensitive structure, the mass causes the movable grating to shift, causing the relative position between the two gratings to change. Due to the grating Talbot effect, positive and negative images of the gratings periodically appear in the near-field diffraction region behind the gratings. Therefore, changes in the relative displacement between the gratings are converted into changes in the intensity of the diffracted light behind the gratings, resulting in a sinusoidal signal detected by photoelectric detection. Therefore, by analyzing the sinusoidal relationship between the diffracted light intensity and acceleration, the magnitude of the external acceleration can be determined.
[0003] Because the output signal is sinusoidal, full-scale linear measurement cannot be achieved, resulting in problems such as a small linear region and poor linearity. To address the limited linear region in grating MOEMS accelerometers, a subdivision interpolation circuit solution was proposed to convert the sinusoidal signal into a digital square wave signal, thereby expanding the measurement range, widening the linear region, and improving the linearity of the signal. However, during the grating manufacturing process, problems such as machining and assembly errors may occur, resulting in errors in phase, amplitude, and offset between the two orthogonal signals during the interpolation process. These errors lead to a low subdivision factor and poor signal stability after subdivision, resulting in low accuracy and resolution of the accelerometer. Summary of the Invention
[0004] In response to the technical problems of the above-mentioned traditional grating accelerometers, the present invention provides a high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit. Through a high-multiplication interpolation circuit, a 90-degree phase shift circuit and a DC bias circuit, the amplitude error, bias error and phase error existing in the subdivision interpolation process are effectively suppressed, thereby achieving high precision while significantly improving the linearity and resolution of the grating MOEMS accelerometer.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0006] A high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit includes an accelerometer structure, a 90-degree phase shift circuit, a DC bias circuit, and a subdivision interpolation circuit. The accelerometer structure is electrically connected to the 90-degree phase shift circuit, the 90-degree phase shift circuit is electrically connected to the DC bias circuit, and the DC bias circuit is electrically connected to the subdivision interpolation circuit.
[0007] The 90-degree phase shift circuit includes an adder, a feedback integrator, an integrator, a first resistor, and a second resistor. The negative input terminal of the adder is electrically connected to the first resistor, the positive input terminal of the adder is electrically connected to the output terminal of the feedback integrator, the output terminal of the adder is electrically connected to the negative input terminal of the integrator, the positive input terminal of the integrator is grounded, and the negative input terminal of the adder is electrically connected to the output terminal of the adder through the second resistor.
[0008] The DC bias circuit adopts the LM399H voltage reference chip, which generates a standard DC bias voltage and has excellent temperature stability.
[0009] The subdivision interpolation circuit uses the iC-TW8 DSP microprocessor, which has a digital self-calibration function. During operation, the DSP microprocessor continuously adjusts the digital gain, offset, and phase to maintain stability and minimize errors. After digital calibration and correction, the two differential input signals are processed using the inverse tangent and interpolation algorithms to achieve high-resolution subdivision. The DSP microprocessor adjusts the interpolation factor, adaptive mode, and filter mode parameters through external configuration circuits.
[0010] The accelerometer structure includes an upper grating layer, a sensitive structure layer, a detector, a base, a first in-plane accelerometer, an out-of-plane accelerometer, and a second in-plane accelerometer. The upper grating layer is arranged on the sensitive structure layer, the sensitive structure layer is arranged on the detector, and the detector is arranged on the base; the first in-plane accelerometer, the out-of-plane accelerometer, and the second in-plane accelerometer are arranged in the sensitive structure layer, and the first in-plane accelerometer, the out-of-plane accelerometer, and the second in-plane accelerometer are arranged in parallel.
[0011] The out-of-plane accelerometer includes a first sensitive mass block and an L-shaped beam structure. The sensitive mass block is arranged at the center of the L-shaped beam structure. A second grating is prepared on the sensitive mass block by a magnetron sputtering process.
[0012] The first in-plane accelerometer and the second in-plane accelerometer both include a second sensitive mass block and four reflective cantilever beam structures, and the second sensitive mass block is arranged at the center of the four reflective cantilever beam structures.
[0013] A first grating is provided on the second sensitive mass of the first in-plane accelerometer.
[0014] A third grating is provided on the second sensitive mass of the second in-plane accelerometer.
[0015] The detector is electrically connected to the 90-degree phase shift circuit.
[0016] Compared with the prior art, the present invention has the following beneficial effects:
[0017] By incorporating high-multiplication interpolation technology, 90-degree phase-shift circuits, and high-precision DC bias circuits, this invention significantly improves the interpolation factor and output signal stability of the interpolation circuit. This invention effectively suppresses phase, amplitude, and bias errors caused by grating processing and assembly errors, thereby stably converting the input sinusoidal signal into a square wave signal output after 10,000-fold subdivision, achieving high-precision linear measurement across the entire measurement range. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are merely exemplary, and those skilled in the art can, without inventive effort, derive other implementation drawings based on the provided drawings.
[0019] The structures, proportions, sizes, etc. illustrated in this specification are intended solely to complement the contents disclosed herein and to facilitate understanding and reading by persons skilled in the art. They are not intended to limit the conditions under which the present invention may be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in sizes, without affecting the efficacy and objectives of the present invention, shall remain within the scope of the technical contents disclosed herein.
[0020] Figure 1 This is a functional flow chart of the signal processing circuit of the present invention;
[0021] Figure 2 This is a schematic diagram of the 90-degree phase shift circuit of the present invention;
[0022] Figure 3 This is a schematic diagram of the subdivision interpolation circuit of the present invention;
[0023] Figure 4 This is a schematic diagram of the DC bias circuit of the present invention;
[0024] Figure 5 Schematic diagram of the accelerometer structure of the present invention;
[0025] Figure 6 Schematic diagram of the structure of the sensitive structural layer of the present invention;
[0026] Figure 7 Schematic diagram of the structure of the out-of-plane accelerometer of the present invention;
[0027] Figure 8 Schematic diagram of the structure of the in-plane accelerometer of the present invention;
[0028] Figure 9 This is a diagram of the output signal of the 90-degree phase shift circuit of the present invention;
[0029] Figure 10 This is a diagram of the output signal of the subdivision interpolation circuit of the present invention.
[0030] Among them: 101 is a 90-degree phase shift circuit, U1A is an adder, U2A is a feedback integrator, U1B is an integrator, R1 is a first resistor, R2 is a second resistor, 102 is a DC bias circuit, 103 is a subdivision interpolation circuit, 1 is an upper grating layer, 2 is a sensitive structure layer, 3 is a detector, 4 is a base, 5 is a first in-plane accelerometer, 6 is an out-of-plane accelerometer, 7 is a second in-plane accelerometer, 8 is a first grating, 9 is a second grating, 10 is a third grating, 11 is a first sensitive mass block, 12 is an L-shaped beam structure, 13 is a second sensitive mass block, and 14 is a folded cantilever beam structure. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all the embodiments. These descriptions are only to further illustrate the features and advantages of the present invention, rather than to limit the claims of the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0032] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following embodiments are used to illustrate the present invention but are not intended to limit the scope of the present invention.
[0033] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.
[0034] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0035] This embodiment provides a high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit, such as Figure 1As shown, it includes an accelerometer structure, a 90-degree phase shift circuit 101, a DC bias circuit 102, and a subdivision interpolation circuit 103. The accelerometer structure is electrically connected to the 90-degree phase shift circuit 101, the 90-degree phase shift circuit 101 is electrically connected to the DC bias circuit 102, and the DC bias circuit 102 is electrically connected to the subdivision interpolation circuit 103.
[0036] Further, if Figure 2 As shown, the 90-degree phase shift circuit 101 includes an adder U1A, a feedback integrator U2A, an integrator U1B, a first resistor R1 and a second resistor R2. The negative input terminal of the adder U1A is electrically connected to the first resistor R1, the positive input terminal of the adder U1A is electrically connected to the output terminal of the feedback integrator U2A, the output terminal of the adder U1A is electrically connected to the negative input terminal of the integrator U1B, the positive input terminal of the integrator U1B is grounded, and the negative input terminal of the adder U1A is electrically connected to the output terminal of the adder U1A through the second resistor R2.
[0037] Further, if Figure 4 As shown, the DC bias circuit 102 uses the LM399H voltage reference chip, which generates a standard DC bias voltage and has excellent temperature stability.
[0038] Further, if Figure 3 As shown, the subdivision interpolation circuit 103 adopts the iC-TW8 DSP microprocessor. The DSP microprocessor has a digital self-calibration function. During operation, it continuously adjusts the digital gain, offset, and phase to maintain stability and minimize errors. After digital calibration and correction, the two differential input signals are processed using the inverse tangent and interpolation algorithms to achieve high-resolution subdivision. The DSP microprocessor adjusts the interpolation factor, adaptive mode, and filter mode parameters through an external configuration circuit.
[0039] Further, if Figure 5 As shown, the accelerometer structure includes an upper grating layer 1, a sensitive structure layer 2, a detector 3 and a base 4. The upper grating layer 1 is arranged on the sensitive structure layer 2, the sensitive structure layer 2 is arranged on the detector 3, and the detector 3 is arranged on the base 4. Figure 6 As shown, the sensitive structure layer 2 is provided with a first in-plane accelerometer 5, an out-of-plane accelerometer 6 and a second in-plane accelerometer 7. The first in-plane accelerometer 5, the out-of-plane accelerometer 6 and the second in-plane accelerometer 7 are arranged in parallel. Figure 7 As shown, the off-plane accelerometer 6 includes a first sensitive mass block 11 and an L-shaped beam structure 12. The sensitive mass block 11 is arranged at the center of the L-shaped beam structure 12. A second grating 9 is prepared on the sensitive mass block 11 by a magnetron sputtering process. Figure 8As shown, both the first in-plane accelerometer 5 and the second in-plane accelerometer 7 include a second sensitive mass 13 and four reflective cantilever beam structures 14. The second sensitive mass 13 is disposed at the center of the four reflective cantilever beam structures 14. The first grating 8 is disposed on the second sensitive mass 13 of the first in-plane accelerometer 5. The third grating 10 is disposed on the second sensitive mass 13 of the second in-plane accelerometer 7.
[0040] The operating principle of this embodiment is as follows: When laser light vertically transmits through the upper grating layer 1, a Talbot image distribution is formed behind the upper grating layer 1. If the sensitive structure layer 2 is placed within the Talbot image region and acceleration is applied in the out-of-plane sensitive direction, the sensitive mass 13 of the sensitive structure layer 2 will drive the first grating 8, the second grating 9, and the third grating 10 to move in the out-of-plane direction, resulting in a change in the relative displacement between the two grating layers. The magnitude of the out-of-plane acceleration can be detected by detecting the change in the diffracted light intensity behind the gratings received by the detector 3. Similarly, if acceleration is applied in the in-plane sensitive direction and the spacing between the sensitive structure layer 2 and the upper grating layer 1 satisfies an integer multiple of the Talbot distance, the double-layer grating will produce relative motion in the in-plane direction. The magnitude of the in-plane acceleration can be determined by detecting the change in the diffracted light intensity.
[0041] Detector 3 converts the change in diffracted light intensity into an electrical signal. According to the principle of the Talbot effect, the change in light intensity exhibits a sinusoidal shape. This detection signal gives the accelerometer high sensitivity within the linear region. However, due to the limited linear region, acceleration measurement over the full range cannot be achieved. To further expand the linear measurement region and improve linearity and resolution, the present invention proposes a high-resolution grating MOEMS accelerometer subdivision interpolation linear processing circuit. This technology utilizes a high-multiplication interpolation circuit, combined with a 90-degree phase shift circuit and a high-precision DC bias circuit, to convert an input sinusoidal signal into two orthogonal signals via a phase shift circuit. These signals are then stably output as digital square wave signals via a high-multiplication interpolation circuit. This not only improves the resolution and accuracy of the signal, but also expands the linear measurement region and enhances the linearity of the signal.
[0042] In order to achieve signal subdivision, a four-quadrant grating is usually used instead of the lower grating. For in-plane detection, the spacing of the grating array of the four quadrants is set to (N+1 / 4)d to ensure that the four signals are orthogonal to each other; for out-of-plane detection, the thickness of the grating array of the four quadrants is set to differ by (N+1 / 4)z T , where z T =2d 2 / λ is the Talbot distance, d is the grating constant, and λ is the laser wavelength. However, due to errors in grating processing and assembly alignment, the four output signals have phase, amplitude, and offset errors. These errors lead to interpolation errors, affecting the resolution and accuracy of the sensor.
[0043] To reduce these three types of errors and further increase the subdivision factor, the present invention uses a 90-degree phase-shift circuit to convert one signal into two orthogonal, equal-amplitude sine and cosine signals, effectively suppressing both phase and amplitude errors. Furthermore, a DC bias circuit adjusts the bias voltages of the two signals to match the differential inputs of the subsequent subdivision circuit. The high-multiplication interpolation circuit is implemented based on the iC-Haus iC-TW8 DSP microprocessor, a universal 16-bit Sin / Cos interpolator with advanced autocalibration capabilities. It can process single-ended or differential analog input signals and calculate their phase values, achieving 10,000-fold subdivision.
[0044] The schematic diagram of the 90-degree phase shift circuit is as follows Figure 2 As shown. The adder U1A compares the sinusoidal input signal with the feedback signal of the feedback integrator U2A, and compensates for the gain of the input sinusoidal signal. When the frequency of the input signal changes, the two output signals can still maintain a 90° phase difference, and the gain is adjusted by the adder to keep the amplitude of the input and output signals consistent. The amplitude of the phase-shifted signal is adjusted by the ratio of the first resistor R1 and the second resistor R2 to ensure that the output amplitude is consistent with the input amplitude. Integrator U1B is used to achieve a 90° phase shift, and its output signal is a cosine wave, which is 90° ahead of the input signal in phase. By adjusting the value of R3 / C1, the integrator U1B can maintain a constant 90° phase difference between the two output signals at different operating frequencies. The feedback integrator U2A acts as a linear low-pass filter that can eliminate the bias voltage generated by the integrator U1B and filter out the high-frequency components and noise in the output signal. In order to quantitatively represent the function of the phase shift, the transfer function of the entire circuit is derived as follows:
[0045] H(s)=sC2R2R4R6 / [R1(s 2 C1C2R3R4R6+R2)]
[0046] Let s = jω and the phase angle of the transfer function be Arg[H(jω)] = 90°, ensuring that the subdivision interpolation factor is not affected by the phase error.
[0047] To minimize bias errors during the interpolation process and meet the input signal bias voltage requirements of the subsequent subdivision interpolation circuit, the bias voltage of the two input sine and cosine signals is adjusted to +2.5V. To this end, a high-precision DC bias circuit was designed. This circuit uses the Analog Devices LM399H voltage reference chip to generate the DC bias voltage. This chip has excellent temperature stability and can provide a stable DC bias voltage.
[0048] In summary, if Figure 9 、 Figure 10As shown, this high-resolution grating MOEMS accelerometer linear processing circuit technology effectively reduces the three types of errors in the interpolation process, achieves high-magnification interpolation, and ensures output signal stability. This technology not only achieves high-precision and high-resolution output of the accelerometer, but also expands the linear measurement area, enabling full-scale measurement and significantly improving signal linearity.
[0049] The above only describes in detail the preferred embodiments of the present invention, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in this field without departing from the purpose of the present invention, and various changes should be included in the scope of protection of the present invention.
Claims
1. A high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit, characterized by: The invention comprises an accelerometer structure, a 90-degree phase shift circuit (101), a DC bias circuit (102), and a subdivision interpolation circuit (103); the accelerometer structure is electrically connected to the 90-degree phase shift circuit (101); the 90-degree phase shift circuit (101) is electrically connected to the DC bias circuit (102); and the DC bias circuit (102) is electrically connected to the subdivision interpolation circuit (103).
2. The high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit according to claim 1, characterized in that: The 90-degree phase shift circuit (101) comprises an adder (U1A), a feedback integrator (U2A), an integrator (U1B), a first resistor (R1) and a second resistor (R2); the negative input end of the adder (U1A) is electrically connected to the first resistor (R1); the positive input end of the adder (U1A) is electrically connected to the output end of the feedback integrator (U2A); the output end of the adder (U1A) is electrically connected to the negative input end of the integrator (U1B); the positive input end of the integrator (U1B) is grounded; and the negative input end of the adder (U1A) is electrically connected to the output end of the adder (U1A) via the second resistor (R2).
3. The high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit according to claim 1, characterized in that: The DC bias circuit (102) adopts an LM399H voltage reference chip, which generates a standard DC bias voltage and has excellent temperature stability.
4. The high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit according to claim 1, characterized in that: The subdivision interpolation circuit (103) adopts an iC-TW8 DSP microprocessor. The DSP microprocessor has a digital self-calibration function. During operation, the digital gain, offset and phase are continuously adjusted to maintain stability and minimize errors. After digital calibration and correction, the two differential input signals are processed using an inverse tangent and interpolation algorithm to achieve high-resolution subdivision. The DSP microprocessor adjusts the interpolation factor, adaptive mode and filtering mode parameters through an external configuration circuit.
5. The high-resolution grating MOEMS accelerometer structure subdivision interpolation linear processing circuit according to claim 1, characterized in that: The accelerometer structure comprises an upper grating layer (1), a sensitive structural layer (2), a detector (3), a base (4), a first in-plane accelerometer (5), an off-plane accelerometer (6), and a second in-plane accelerometer (7); the upper grating layer (1) is arranged on the sensitive structural layer (2); the sensitive structural layer (2) is arranged on the detector (3); and the detector (3) is arranged on the base (4); the first in-plane accelerometer (5), the off-plane accelerometer (6), and the second in-plane accelerometer (7) are arranged in the sensitive structural layer (2); the first in-plane accelerometer (5), the off-plane accelerometer (6), and the second in-plane accelerometer (7) are arranged in parallel.
6. The high-resolution grating MOEMS accelerometer structure according to claim 5, characterized in that: The off-plane accelerometer (6) comprises a first sensitive mass block (11) and an L-shaped beam structure (12), wherein the sensitive mass block (11) is arranged at the center of the L-shaped beam structure (12), and a second grating (9) is prepared on the sensitive mass block (11) by a magnetron sputtering process.
7. The high-resolution grating MOEMS accelerometer structure according to claim 5, characterized in that: The first in-plane accelerometer (5) and the second in-plane accelerometer (7) both comprise a second sensitive mass block (13) and four folded-back cantilever beam structures (14), wherein the second sensitive mass block (13) is arranged at the center of the four folded-back cantilever beam structures (14).
8. The high-resolution grating MOEMS accelerometer structure according to claim 7, characterized in that: A first grating (8) is provided on the second sensitive mass block (13) of the first in-plane accelerometer (5).
9. The high-resolution grating MOEMS accelerometer structure according to claim 7, characterized in that: A third grating (10) is provided on the second sensitive mass block (13) of the second in-plane accelerometer (7).
10. The high-resolution grating MOEMS accelerometer structure according to claim 5, characterized in that: The detector (3) is electrically connected to the 90-degree phase shift circuit (101).