Instruction processing method

Abstract

The invention discloses an instruction processing method, the method is suitable for a CPU (Central Processing Unit) adopting a pipeline mode to process an instruction, and the method comprises the following steps: performing instruction matching based on indication information representing the instruction, and determining whether the instruction needs to be subjected to bypass processing or not; if it is determined that the instruction needs to be subjected to bypass processing, pausing an assembly line where the instruction is located; and determining an instruction result obtained after the instruction is processed through the bypass as an instruction result of the instruction, and recovering the assembly line at a target address indicated by the bypass. By the adoption of the method, the specified instruction can be recognized through instruction matching, and then the instruction is processed through the bypass.

Description

Technical Field

[0001] The present application relates to the technical field of computer instruction processing, and in particular to an instruction processing method. Background Art

[0002] In modern computer systems, the instruction set of the central processing unit (CPU) is the foundation for program execution. The CPU contains a decoder that parses instructions. If the decoder cannot parse an instruction, it considers it illegal. In this case, the CPU switches to kernel mode to process the illegal instruction. This processing may involve simulating the execution of the illegal instruction or terminating the current program.

[0003] However, this approach involves software processing for illegal instructions, which is inefficient and cumbersome, and will seriously affect the execution performance of the system. Therefore, how to improve the efficiency of handling illegal instructions requires further research.

[0004] Furthermore, some instructions do not cause the CPU to switch to kernel mode, but their execution may potentially impact system stability or security in some way, and therefore need to be identified and handled promptly. Therefore, how to identify specific instructions and how to handle them after identification also requires further research. Summary of the Invention

[0005] The present application provides an instruction processing method for identifying a specified instruction through instruction matching, and then processing the instruction through a bypass.

[0006] In a first aspect, an embodiment of the present application provides an instruction processing method, which can be executed by a CPU that processes instructions in pipeline mode, the method comprising: performing instruction matching based on indication information characterizing the instruction, and determining whether the instruction requires bypass processing; if it is determined that the instruction requires bypass processing, pausing the pipeline where the instruction is located; determining the instruction result after processing the instruction through the bypass as the instruction result of the instruction, and restoring the pipeline at the target address indicated by the bypass.

[0007] By adopting the above method, the matching instructions are bypassed through the instruction matching method, thereby bypassing the normal execution pipeline path, so that the matching instructions can be bypassed; by determining the instruction result after the instruction is processed through the bypass as the instruction result of the instruction, the processing logic of the instruction can be changed; by restoring the pipeline at the target address indicated by the bypass, the bypass can be allowed to specify the next instruction to be executed, thereby changing the execution flow of the program.

[0008] In one possible implementation, the pipeline includes an instruction fetch stage and an execution effect stage; the execution effect stage is a pipeline stage located after the instruction fetch stage and needs to be rolled back in the event of an exception; instruction matching is performed based on indication information representing the instruction, including: performing instruction matching based on the indication information representing the instruction on the instruction obtained by the instruction fetch stage of the pipeline, and the pipeline continues to be in an execution state; if the pipeline executes to any execution effect stage and no instruction matching result is obtained, the pipeline is paused until the instruction matching result is obtained, and the instruction matching result indicates whether the instruction needs to be bypassed.

[0009] In one possible implementation, the pipeline includes an instruction fetch stage and an execution effect stage; the execution effect stage is a pipeline stage located after the instruction fetch stage and needs to be rolled back in the event of an exception; instruction matching is performed based on indication information representing the instruction, including: performing instruction matching based on indication information representing the instruction on the instruction obtained by the instruction fetch stage of the pipeline, and the pipeline continues to be in an execution state; if it is determined that the instruction needs to be bypassed, pausing the pipeline where the instruction is located, including: if it is determined that the instruction needs to be bypassed, the pipeline executes to any execution effect stage, then after rolling back the pipeline, pausing the pipeline where the instruction is located.

[0010] In one possible implementation, the pipeline also includes a non-execution effect stage located after the instruction fetch stage and before the execution effect stage; the non-execution effect stage is a pipeline stage that does not need to be rolled back in the event of an exception; if it is determined that the instruction requires bypass processing, the pipeline where the instruction is located is paused, including: if it is determined that the instruction requires bypass processing, the pipeline executes to any non-execution effect stage, then the pipeline where the instruction is located is paused.

[0011] In one possible implementation, the non-execution effect stage includes a decoding stage.

[0012] In one possible implementation, the pipeline includes an instruction fetch stage and a decoding stage; instruction matching is performed based on indication information representing the instruction to determine whether the instruction needs to be bypassed, including: after the pipeline completes the instruction fetch stage and before starting the decoding stage, instruction matching is performed based on indication information representing the instruction to determine whether the instruction needs to be bypassed.

[0013] In a possible implementation, the method further includes: if it is determined that the instruction does not need to be bypassed, continuing to execute the pipeline until an instruction result of the instruction is obtained.

[0014] In one possible implementation, the pipeline includes an instruction fetch stage and an instruction adjustment stage in sequence; the instruction adjustment stage is located after the instruction fetch stage; and instruction matching is performed based on indication information representing the instruction, including: during the processing of any instruction adjustment stage by the pipeline, instruction matching is performed based on the indication information representing the instruction for the first instruction before adjustment by the instruction adjustment stage and the second instruction after adjustment by the instruction adjustment stage.

[0015] In one possible implementation, instruction matching is performed based on the indication information representing the instruction to determine whether the instruction needs to be bypassed, including: for any matching item, determining whether the indication information representing the instruction matches the mask and / or target value in the matching item; if so, determining that the instruction needs to be bypassed.

[0016] In a possible implementation, the target value of the matching item represents an opcode for obtaining the current clock; the mask of the matching item is the bit where the opcode is located; and the instruction result is clock information unrelated to the current clock or inaccurate clock information.

[0017] In one possible implementation, the instruction that needs to be bypassed is a new instruction; the target value of the matching item is a reserved opcode, and / or the mask of the matching item is a reserved bit field, and the target value of the matching item is at least one level of opcode.

[0018] In a possible implementation, an instruction requiring bypass processing has an error in the CPU hardware implementation, and the error causes an unexpected instruction result; the bypass result is the expected instruction result or causes an exception or is empty.

[0019] In one possible implementation, the CPU includes an instruction matching unit and an instruction bypass unit; instruction matching is performed based on indication information representing the instruction to determine whether the instruction needs to be bypassed, including: the instruction matching unit performs a coarse match on the instruction based on the mask and / or target value in the matching item, and uses the matched instruction as a coarse match instruction; the instruction bypass unit performs a fine match on the coarse match instruction to determine whether the instruction is an illegal instruction that needs to be bypassed.

[0020] In a possible implementation, the effective bits of the mask and / or target value in the matching item corresponding to the coarse match are smaller than the effective bits formed by summing up the matching rules used in the fine match.

[0021] In the second aspect, an embodiment of the present application provides a central processing unit (CPU), which includes an instruction matching unit and an instruction bypass unit. The instruction matching unit is used to execute the method in any possible implementation of the first aspect; the instruction bypass unit is a programmable logic device, which is used to bypass the instruction based on the instruction of the instruction matching unit and feed back the bypass processed instruction result to the instruction matching unit.

[0022] In one possible implementation, the instruction matching unit is specifically used to perform a coarse match on the instruction based on the mask and / or target value in the matching item, and use the matched instruction as a coarse matching instruction; the bypass processing unit is also used to perform a fine match based on the coarse matching instruction to determine whether the instruction is an illegal instruction that requires bypass processing.

[0023] In a third aspect, an embodiment of the present application provides an instruction processing device, which includes a memory for storing computer programs or instructions; and a processor for calling the computer programs or instructions stored in the memory to execute a method as in any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0025] Figure 1 A flowchart corresponding to an instruction processing method provided in an embodiment of the present application; Figure 2 A schematic diagram of a flow chart corresponding to the first instruction matching opportunity provided in an embodiment of the present application; Figure 3 A schematic diagram of a flow chart corresponding to the second instruction matching opportunity provided in an embodiment of the present application; Figure 4 A schematic diagram of a flow chart corresponding to the third instruction matching opportunity provided in an embodiment of the present application; Figure 5 A schematic diagram of a flow chart corresponding to the fourth instruction matching opportunity provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of an instruction processing device 6000 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of this application more clear, this application will be further described in detail below with reference to the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0027] An embodiment of the present application provides an instruction processing method for identifying a specified instruction through instruction matching, and then processing the instruction through a bypass.

[0028] To facilitate understanding, some terms involved in this application are first explained.

[0029] An instruction is a shorthand term for a machine code instruction, the foundation of program execution. The core of a machine code instruction is its opcode. The decoder must first determine the opcode before it can determine the arrangement and meaning of the operands, and then send the instruction to the subsequent pipeline stages for execution according to the behavior defined in the instruction set.

[0030] Pipelining is an essential component of modern computer processors. It involves breaking down the instruction processing process into multiple steps and executing them in parallel across multiple hardware processing units to accelerate instruction execution. Pipelining is a fixed form of hardware logic. Pipelining implementations vary, and different CPUs may have varying numbers of pipeline stages. The most classic pipeline design is the five-stage pipeline. The five-stage pipeline consists of instruction fetch (IF), decode (ID), execute (EX), memory access (MEM), and write back (WB). IF fetches the instruction to be executed from memory; ID parses and interprets the fetched instruction; EX performs arithmetic, logical, and control transfer operations based on the decoded result, particularly the operation type and operands; MEM handles memory-related operations, including reading data and storing results; and WB writes the execution result to the corresponding register for subsequent instructions.

[0031] Figure 1 This is a flowchart corresponding to an instruction processing method provided in an embodiment of the present application, which can be executed by a CPU that processes instructions in a pipeline mode. Figure 1 As shown, the process includes the following steps: In step 101 , the CPU performs instruction matching based on indication information representing the instruction, and determines whether the instruction needs to be bypassed.

[0032] The indication information of an instruction can be the machine code of the instruction, the address of the instruction in the memory, or the internal number of the instruction, which is not limited here; the instruction can be determined based on the indication information. The premise of instruction matching is that the processor has completed instruction fetching. Under this premise, instruction matching is performed based on the indication information that represents the instruction to determine whether the instruction needs to be bypassed. The bypass is another path different from the usual path. In most cases, the instruction will not be matched, and it is only necessary to continue executing the pipeline until the instruction result of the instruction is obtained (in other words, the pipeline is the usual path); when the instruction is matched, the instruction bypasses the usual path, and the bypass is another path that the instruction takes in this case.

[0033] Step 102: If it is determined that the instruction needs to be bypassed, the pipeline where the instruction is located is paused.

[0034] There are many opportunities for performing instruction matching based on the indication information representing the instruction. The embodiments of the present application provide the following four opportunities.

[0035] (1) After the pipeline completes the instruction fetch stage and before the decode stage begins

[0036] After the pipeline completes the instruction fetch stage and before the decode stage begins, instruction matching is performed based on the indication information representing the instruction to determine whether the instruction needs to be bypassed. Figure 2 The flowchart corresponding to the first instruction matching opportunity provided in the embodiment of the present application is as follows. It can be understood that the pipeline can include an instruction fetch stage and a decoding stage. Figure 2 As can be seen, the instruction match is inserted before the decode stage. If a match is found, the pipeline is paused and the instruction is bypassed, no longer entering the decode stage and subsequent pipeline stages. After the bypass process is completed, the pipeline is restored at the specified address. If no match is found, the instruction does not need to be bypassed, and the instruction enters the decode stage and then the subsequent pipeline stages, continuing to execute the pipeline until the instruction execution result is obtained. In this way, the instruction matching result is determined before the decode stage begins execution. If the match is successful, the decode stage and the pipeline stages after the decode stage can be omitted, which minimizes the execution of unnecessary pipeline stages and reduces unnecessary power consumption or overhead.

[0037] The pipeline also includes other pipeline stages. The embodiment of the present application is not limited to instruction matching only before the decoding stage, and instruction matching can also be performed before other pipeline stages.

[0038] (2) When the pipeline is executed simultaneously and the instruction matching is completed, the pipeline is executed to the non-execution effect level

[0039] It's understandable that the pipeline consists of multiple pipeline stages besides the instruction fetch stage. These stages can be categorized as non-execution-effect stages and execution-effect stages. The non-execution-effect stages are located after the instruction fetch stage and before the execution-effect stages. These pipeline stages don't require rollback in the event of an exception, and they include the decode stage. This is because in the processor pipeline, instructions don't take effect until quite late. If execution is interrupted before this point, the instruction will have no effect. In the classic five-stage pipeline, the decode stage is a non-execution-effect stage.

[0040] Optionally, the instructions obtained through the instruction fetch stage of the pipeline are matched based on the indication information representing the instructions, and the pipeline is kept in the execution state. If it is determined that the instruction needs to be bypassed, the pipeline is executed to any non-execution effect stage, and the pipeline where the instruction is located is paused. Figure 3 The flowchart corresponding to the second instruction matching opportunity provided in the embodiment of the present application is as follows. Figure 3 As can be seen, after the instruction fetch stage, the instruction is matched. While the instruction is being matched, the instruction is in the execution state in the pipeline. If a match is found, the pipeline will execute to any non-execution effect stage, causing the pipeline to pause and send the instruction into the bypass. At this time, the result obtained by the non-execution effect stage is equivalent to being discarded and no longer enters the subsequent pipeline stage. If no match is found, it is determined that the instruction does not need to be bypassed, and the pipeline will continue to execute until the execution result of the instruction is obtained. In this way, the instruction matching and pipeline run simultaneously. If the instruction matching is unsuccessful, the pipeline can continue to execute until the execution result of the instruction is obtained. The pipeline execution will not be delayed due to the instruction matching, thereby improving the execution efficiency of the pipeline.

[0041] (3) The pipeline is executed simultaneously, and the pipeline has not yet obtained an instruction matching result at any execution effect level.

[0042] Optionally, the instructions obtained through the instruction fetch stage of the pipeline are matched based on the indication information representing the instructions, and the pipeline continues to be in the execution state. If the instruction matching result has not been obtained when the pipeline executes to any execution effect level, the pipeline is paused until the instruction matching result is obtained. The instruction matching result indicates whether the instruction needs to be bypassed.

[0043] Specifically, in some cases, instruction matching may use overly complex matching methods, resulting in a slow matching process. Because instructions don't take effect until quite late in the processor's pipeline, pausing pipeline execution before that stage prevents the instruction from taking effect. In other words, by halting the pipeline before the stage that produces the effect (i.e., the stage that executes the effect), the results of the completed stage are simply discarded without requiring an additional rollback, rendering the instruction as if it had never been executed. More simply, this is an efficient rollback, but without requiring any backup or restore, simply discarding the current state. This design is significant because once the pipeline enters a subsequent stage where an effect may occur, the additional overhead and time of a rollback are incurred, increasing the processor's design complexity and power consumption.

[0044] Figure 4 This is a flow chart corresponding to the third instruction matching timing provided in an embodiment of the present application. Instruction matching can be performed simultaneously with pipeline stages that will not yet produce an effect on the instruction. When the pipeline reaches any execution effect stage, it indicates that the pipeline is about to enter a pipeline stage that will produce an effect. The execution effect stage of the pipeline is located after the instruction fetch stage and is the pipeline stage that needs to be rolled back in the event of an exception. Before the pipeline reaches any execution effect stage, it confirms whether the instruction matching is complete. If not, it waits for the instruction matching to complete before deciding whether to send the instruction to the bypass or allow it to enter the subsequent pipeline stage. After the instruction is matched, if a match is found, the pipeline is paused and the instruction is sent to the bypass. At this time, the result obtained by the non-execution effect stage is equivalent to being discarded and no longer enters the subsequent pipeline stage. If no match is found, it is determined that the instruction does not need to be bypassed, and the pipeline execution continues until the instruction result is obtained. In the case of a slow instruction matching process, if the instruction matching is not completed before the pipeline enters the execution effect stage, the pipeline is paused until the instruction matching is completed. This can save CPU overhead. Because, if the pipeline is not paused, when the instruction matching is completed, the pipeline will execute to the execution effect level. In this way, if it is determined that the instruction matching is successful, the instruction is sent to the bypass execution, and the pipeline level needs to be rolled back.

[0045] (IV) When the instruction matching is completed, the pipeline is executed to the execution effect level.

[0046] Optionally, the instructions obtained through the instruction fetch stage of the pipeline are matched based on the indication information representing the instructions, and the pipeline continues to be in the execution state. If it is determined that the instruction needs to be bypassed, the pipeline executes to any execution effect level, then after rolling back the pipeline, the pipeline where the instruction is located is paused.

[0047] Specifically, in some cases, instruction matching may be even slower, so that when instruction matching is completed, the pipeline has already reached the execution effect stage. Figure 5 A flow chart corresponding to the fourth instruction matching opportunity provided in the embodiment of the present application, from Figure 5 It can be seen that instruction matching can be performed together with the pipeline stage. If a match is found, the instruction is sent to the bypass, at which time the pipeline is rolled back and the effects of the pipeline are undone. If no match is found, the execution status of the pipeline does not need to be affected and the pipeline proceeds normally.

[0048] The four timings (i), (ii), (iii), and (iv) above are provided for illustrative purposes only. They are not mutually exclusive, nor do they encompass all possible timings. In practice, various timings can be combined within the same product. For example, the timings can be dynamically selected based on the complexity of the matching item and / or the progress of the instruction matching process. In another example, the timings can be dynamically selected based on the pipeline stage at which the pipeline has reached upon completion of the instruction matching process.

[0049] It's important to note that pausing or rolling back the pipeline can occur simultaneously with bypassing instructions, with no timing dependencies. This allows for improved instruction processing efficiency. Alternatively, if the CPU can't perform these operations simultaneously, it can pause or roll back the pipeline before bypassing the instruction. This is because fewer pipeline stages result in fewer effects and a lower rollback overhead.

[0050] In addition, it should be noted that on the same pipeline, if instruction 1 needs to pause at pipeline stage n because the instruction matching result has not yet been determined, the next instruction after instruction 1 on the same pipeline, such as instruction 2, will be executed to pipeline stage n-1 at most, and the next instruction after instruction 2 on the same pipeline, such as instruction 3, will be executed to pipeline stage n-2 at most, and so on.

[0051] Of course, in some cases there will be multiple pipelines. In this case, if instruction 1 is on pipeline 1 and instruction 2 is on pipeline 2, then instruction 2 does not need to be queued after instruction 1, but instruction 2 cannot enter the execution effect level of pipeline 2, otherwise instruction 2 will produce an execution effect, thus violating the principle that instruction 2 must produce an execution effect later than the instruction before instruction 2 (including instruction 1).

[0052] In step 103 , the CPU determines the instruction result after processing the instruction through the bypass as the instruction result of the instruction, and restores the pipeline at the target address indicated by the bypass.

[0053] Specifically, after the instruction is sent to the bypass, the instruction bypass unit in the CPU determines the instruction result after processing the instruction as the instruction result of the instruction, and restores the pipeline at the target address indicated by the bypass. The pipeline is paused until the instruction bypass simulation completes the execution of the instruction. After the target address is determined, the paused pipeline will resume operation at the target address.

[0054] Generally speaking, the target address is the address of the next instruction after the instruction that has been simulated, which is equivalent to causing the pipeline to process the next instruction. This is because the instruction in the match has already been simulated and executed by the instruction bypass unit and does not need to be executed again. Optionally, the target address can also be other addresses. For example, if the bypassed instruction is a jump instruction or a branch instruction, then the target address should be the target address of the jump or branch; if the instruction bypass unit does not completely execute the bypassed instruction, but only corrects some internal states of the processor, then the target address can be set to the bypassed instruction itself, and then temporarily skip an instruction match for the instruction, so that the instruction is executed by the pipeline and the correct internal state of the processor can be obtained when it is executed on the pipeline this time; if it is only necessary to skip an instruction completely, then after receiving the bypassed instruction and determining that it should be skipped, the instruction bypass unit does nothing and directly specifies the address of the next instruction after the bypassed instruction as the target address, thus skipping the instruction.

[0055] In a five-stage pipeline, the instruction fetch stage is followed by the decode stage. Optionally, in a more complex pipeline, additional pipeline stages may be present after the instruction fetch stage to perform further processing on the fetched instruction. Exemplarily, the pipeline includes an instruction fetch stage, an instruction adjustment stage, and a decode stage, and instruction matching is performed based on indication information representing the instruction, including: during processing of any instruction adjustment stage by the pipeline, performing instruction matching based on the indication information representing the instruction on a first instruction before adjustment by the instruction adjustment stage and a second instruction after adjustment by the instruction adjustment stage.

[0056] Specifically, the instruction matcher can work before or after any pipeline stage, or work together with any pipeline stage. Any pipeline stage can modify and transform instructions. The instruction matcher can match both the instructions before modification and transformation and the instructions after modification and transformation, and configure different sets of matching items for these two matches. Furthermore, if multiple pipeline stages have modified and transformed the instructions fetched by the instruction fetch stage multiple times, the instruction matcher can also perform multiple matches on the instructions after each modification and transformation. In this way, the instruction matcher can match instructions before and after modification and transformation, which increases the chance of instruction matching and expands the application of instruction matching in actual business.

[0057] In one possible implementation, the pipeline includes an instruction fetch stage, and resuming the pipeline at the target address indicated by the bypass includes resuming the pipeline starting from the instruction fetch stage, and the first instruction obtained by the instruction fetch stage is the instruction at the target address indicated by the bypass.

[0058] In the embodiments of the present application, there are multiple methods for performing instruction matching based on the indicative information representing the instruction, including tree matching and graph matching, and optionally, mask matching. Performing instruction matching based on the indicative information representing the instruction and determining whether the instruction requires bypass processing includes: for any matching item, determining whether the indicative information representing the instruction matches the mask and / or target value in the matching item; if so, determining that the instruction requires bypass processing.

[0059] Specifically, each match item consists of a mask and a target value. The mask indicates the binary bits in each instruction that are involved in the match, and the target value is used to compare with the instruction to be matched. For example, an 8-bit instruction is matched with a match item, as shown in Table 1.

[0060] Table 1

[0061] Here, 1 indicates that the bit is 1, 0 indicates that the bit is 0, and x indicates that the bit can have any value. As shown in Table 1, bits masked as 1 participate in the match, while bits masked as 0 do not. Since the instruction and target values in this example have the same binary number under the masked 1 bits, the instruction successfully matches the match, or in other words, the instruction successfully matches the match.

[0062] Optionally, the instruction set can be either a fixed-length or variable-length instruction set. Instructions in a variable-length instruction set are not unique in length. For variable-length instruction sets, the mask and target values are both of maximum length. Bits set to 0 in the mask allow non-existent bits to pass the match, but bits set to 1 in the mask require the corresponding bits in the instruction to exist. Instructions shorter than the maximum length can be matched in two ways: aligning the high bits or aligning the low bits. If instructions in a variable-length instruction set can be either 8 or 12 bits long, and the mask and target values are both 12 bits long, assuming that instructions shorter than the maximum length are aligned to the high bits during matching, then if at least four consecutive bits in the lowest order of the mask are 0, the match will match both 8-bit and 12-bit instructions. Conversely, if any of the four lowest order bits of the mask are 1, the match will only match 12-bit instructions.

[0063] Assuming that instructions shorter than the maximum length are aligned with the low bits during matching, then when the highest bit of the mask has at least 4 consecutive binary bits that are 0, this match can match both 8-bit long instructions and 12-bit long instructions; conversely, if any of the last 4 binary bits of the mask is 1, this match can only match 12-bit instructions.

[0064] Therefore, for variable-length instruction sets, the same match term may match instructions of two different lengths, which may seem ambiguous. However, this problem can be avoided by writing the match term appropriately.

[0065] For example, the instruction length of some variable-length instruction sets is directly determined by the opcode. Therefore, as long as the matching item includes a match for the opcode, it is actually equivalent to limiting the instruction length, so there will be no ambiguity in the instruction length.

[0066] Therefore, to ensure that the match does not create instruction length ambiguity for variable-length instruction sets, ensure that the matching bits include the opcode bits. If matching the first-level opcode is sufficient to determine the instruction length, then only the first-level opcode bits are included. Otherwise, if matching the opcodes from levels 1 to n is sufficient to determine the instruction length, then the opcode bits from levels 1 to n are included.

[0067] Alternatively, some variable-length instruction sets may be too complex, so we can also add a new parameter to the matching item, namely the instruction length. This parameter is used to specify the expected instruction length of this matching item. If the instruction length is not equal to this parameter, then the match must be considered failed.

[0068] According to an instruction processing method proposed in an embodiment of the present application, this embodiment also provides a method for correcting logic defects in an application-specific integrated circuit (ASIC). An ASIC is an integrated circuit designed specifically to meet the requirements of a specific electronic system. Its circuit structure and functions are customized for a specific application. Once an ASIC is manufactured, its internal logic is fixed and cannot be changed. A typical CPU is an ASIC.

[0069] For side-channel attacks, since side-channel attacks always require measuring the side effects of hardware, the following instruction sequence is often repeatedly executed during the measurement phase of the side-channel attack: Step 1: Get and record the current clock; Step 2: Execute instructions that may be affected by the aforementioned side effects; Step 3: Get and record the current clock.

[0070] Steps 1 and 3 can be used to determine the execution time of step 2. After repeatedly executing this instruction sequence, an attacker can use statistical analysis to determine the execution time of step 2 under different conditions. The statistical characteristics obtained from this analysis can be used to leak sensitive information through side channels. For example, in the cache side channel used by both Meltdown and Spectre, the aforementioned side effect affects the access latency of each element in the array. Therefore, the access latency of each element in the array must always be measured (corresponding to step 2 above). Therefore, the following loop execution pattern exists: obtain and record the current clock; access an array element; obtain and record the current clock.

[0071] Therefore, an embodiment of the present application proposes an instruction matching method, wherein the target value of the matching item represents the opcode for obtaining the current clock, the mask of the matching item is the bit where the opcode is located, and the instruction result is clock information unrelated to the current clock or inaccurate clock information.

[0072] Specifically, an embodiment of the present application proposes to bypass the instruction for obtaining the current clock, so that the instruction cannot obtain the accurate clock or obtains clock information that is irrelevant to the current clock, thereby destroying the difference in statistical characteristics caused by the side channel and avoiding the leakage of sensitive data from the side channel. Furthermore, if the instruction matching method is mask matching, the mask of the matching item should select the bit where the opcode of the instruction for obtaining the current clock is located, and the corresponding target value is the opcode of the instruction for obtaining the current clock. Of course, if there are multiple levels of opcodes, all the multiple levels of opcodes are included in the mask and target value. In this way, when the instruction is matched, the instruction bypass unit obtains full control over the instruction and can directly make it return an incorrect or inaccurate clock.

[0073] The embodiment of the present application also provides a method for correcting an error in the hardware implementation of a CPU, which error leads to an unexpected instruction result, and setting such an instruction as an instruction that needs to be bypassed, so that the bypass result is the expected instruction result or an exception is caused or it is empty. Since the bypass result is determined to be the instruction result of the instruction, the bypass result is made the expected instruction result, and the error in the hardware implementation can be corrected so that the result generated by the instruction is the expected result. To correct some logical defects, it is only necessary to prevent the instruction from being executed; there are two ways to prevent the instruction from being executed, one is to cause an exception, and the other is to ignore such instructions. These two methods each have their advantages: the method of causing an exception is more in line with the provisions of the instruction set; since the overhead of handling exceptions is high, it is beneficial to performance if such instructions are directly ignored without causing an exception. Ignoring instructions means that the instruction bypass unit directly sets the target address to the address of the next instruction after receiving such instructions, or directly outputs the bypass result as an empty result.

[0074] The CPU includes an instruction matching unit and an instruction bypass unit. Instruction matching is achieved by setting matching items. There are two possible approaches: the first is to match instructions precisely; the second is to first match a category of instructions (coarse matching), and then further identify whether the instruction requires bypass processing in the instruction bypass unit (fine matching). Each approach has its own advantages and disadvantages. The first approach does not require the additional overhead of fine matching compared to the second approach, but consumes more matching items when many instructions require bypass processing. The second approach saves matching items, but introduces additional overhead for fine matching. In other words, it is possible to share the same matching item for different target instructions (i.e., instructions requiring bypass processing). As long as their masks and target values share common bits, these common bits can be configured as shared matching items. For the first matching approach, if the instruction matching method is mask matching, the matching item's mask and target value should select the minimum number of bits sufficient to identify the target instruction and exclude non-target instructions. In other words, while ensuring matching accuracy, it should cover the widest possible range of matching results. For the second matching method, the bits selected by the mask of the matching item and the target value may determine both the target instruction and the non-target instruction. Then the instruction matching unit performs a coarse match on the instruction based on the mask and / or target value in the matching item, and uses the matched instruction as the coarse match instruction. The instruction bypass unit performs a fine match on the coarse match instruction to determine whether the instruction is an instruction that needs to be bypassed.

[0075] The method by which the instruction matching unit performs coarse and fine matching on instructions can also be applied to instructions that contain errors in the CPU hardware implementation, resulting in unexpected instruction results. If the instruction does not contain errors in the CPU hardware implementation, it is allowed to execute normally. Otherwise, the bypass result is set to the expected instruction result, an exception is raised, or it is left empty. Optionally, the effective bits of the mask and / or target value in the matching item corresponding to the coarse match are less than the effective bits formed by summing the matching rules used for the fine match. In other words, the mask and target value of the matching item select opcodes of several levels, or certain bits within the opcode, thereby abandoning some matching accuracy and handing over the fine matching of the instruction to the instruction bypass unit, thus saving the use of matching items. In this case, in addition to implementing the aforementioned behavior of ignoring instructions or raising exceptions, the instruction bypass unit also needs to allow legal instructions to execute normally. That is, after determining that the instruction is legally executable, the target address is set to the address of the instruction. This causes the instruction to temporarily skip an instruction match, allowing the instruction to be executed normally, i.e., executed on the pipeline.

[0076] Taking the GhostWrite logic flaw as an example, we will illustrate how to use the two matching methods. Taking mask matching as an example, if we want to use the first matching method to cover all illegal mop field values under STORE-FP, namely 001, 100, 101, and 110, we would set the following matching items, as shown in Table 2.

[0077] Table 2

[0078] At this point, the mask and target value for each match item cover the minimum number of bits needed to identify a class of instructions. In other words, matching any additional bit would unnecessarily narrow the match range; matching any fewer bits would result in matching potentially legal instructions. Note that match item 2 does not match bit 26, the lowest bit of the mop field. This is because mop field values 100 and 101 are both illegal. Therefore, matching only the upper two bits is sufficient to match both values; in other words, both values share the same match item. Generally speaking, the number of match items is limited, and their use should be carefully planned. Therefore, combining these two values into a single match item can save on match item usage. Of course, in practice, splitting match item 2 into two matches, one matching mop=100 and the other matching mop=101, would achieve the same effect, but would require more matches.

[0079] If the second matching method is to be used to cover all illegal mop field values (ie, 001, 100, 101, 110) under STORE-FP, the following matching items are set, for example.

[0080]

[0081] In this case, the mop field is not included in the match, so even valid mop field values are matched. The instruction bypass unit then needs to analyze the mop field of the bypassed instruction to determine if it is valid. Based on this, it determines whether to execute the instruction normally, raise an exception, or set the instruction result to null. This approach significantly reduces the number of matching entries.

[0082] The present application also provides a method for adding new instructions using instruction bypass, wherein the instruction that needs to be bypassed is a new instruction, the target value of the matching item is a reserved opcode, and / or the mask of the matching item is a reserved bit field, and the target value of the matching item is at least one level of opcode.

[0083] Specifically, a general instruction set contains many reserved opcodes and even certain bitfield values within certain instructions. Optionally, new instructions can be constructed using the reserved opcodes or bitfield fetches to implement new functionality. New instructions can be constructed by configuring instruction matching items, and the functionality of the new instructions can be implemented using logic within the instruction bypass unit. For example, if a new instruction is added using a reserved opcode, the matching item includes the opcode in the match, sets the corresponding bit mask to 1, and sets the target value to the target opcode. If the reserved opcode is an n-level opcode, then all opcodes from levels 1 to n should be included in the match.

[0084] If some reserved bit field values for a certain type of instruction are defined, not only the opcodes at all levels that can identify this type of instruction need to be included in the match, but also the new bit field value needs to be included in the match, that is, the mask of the corresponding bit is set to 1, and the target value is set to the new bit field value.

[0085] An embodiment of the present application also provides a CPU comprising an instruction matching unit and an instruction bypass unit. The instruction bypass unit can be a programmable logic device (PLD). The PLD can implement specified logic to read or modify the processor's internal state, thereby simulating the effects of instruction execution at certain pipeline stages. Specifically, bypassed instructions are processed by logic programmed (burned or flashed) into the PLD. The logic programmed into the PLD should be compatible with each matching item. In other words, the logic in the PLD should be capable of executing all machine code that would be matched by the matching item. This does not mean that all machine code that would be matched by the matching item will be deemed legal by the logic in the PLD. Determining the machine code of certain bypassed instructions as abnormal and causing an exception is also one implementation method. Optionally, multiple instruction bypass units can be implemented to simultaneously process multiple bypassed instructions. This can be achieved by providing multiple PLDs or by programming multiple logic for handling instruction bypass within a single PLD. The instruction matching unit in the present application can be a PLD or an ASIC.

[0086] The instruction matching unit is used to execute any of the above-mentioned instruction processing methods, and the instruction bypass unit is used to bypass the instruction based on the instruction matching unit's instructions and feed back the bypassed instruction results to the instruction matching unit. The instruction matching unit is specifically used to perform a coarse match on the instruction based on the mask and / or target value in the matching item, and use the matched instruction as the coarse matching instruction. The bypass processing unit is also used to perform a fine match based on the coarse matching instruction to determine whether the instruction is an illegal instruction that needs to be bypassed.

[0087] Figure 6This is a structural diagram of an instruction processing device 6000 provided in an embodiment of the present application. Figure 6 As shown, it includes at least one processor 601 and a memory 602 connected to the at least one processor 601. The specific connection medium between the processor 601 and the memory 602 is not limited in the embodiment of the present application. Figure 6 For example, the processor 601 and the memory 602 are connected via a bus. The bus can be divided into an address bus, a data bus, a control bus, and the like.

[0088] In an embodiment of the present application, the memory 602 stores instructions that can be executed by at least one processor 601. The at least one processor 601 can implement the steps of the above-mentioned instruction processing method by executing the instructions stored in the memory 602.

[0089] The processor 601 is the control center of the computer device. It can connect the various parts of the computer device using various interfaces and lines, and perform resource settings by running or executing instructions stored in the memory 602 and calling data stored in the memory 602. Optionally, the processor 601 may include one or more processing units. The processor 601 may integrate an application processor and a modem processor. The application processor mainly processes the operating system, user interface, and application programs, while the modem processor mainly processes wireless communications. It is understood that the modem processor may not be integrated into the processor 601. In some embodiments, the processor 601 and the memory 602 may be implemented on the same chip. In some embodiments, they may also be implemented on separate chips.

[0090] The processor 601 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0091] Memory 602, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs, and modules. Memory 602 may include at least one type of storage medium, such as flash memory, a hard disk, a multimedia card, a card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, a magnetic disk, an optical disk, and the like. Memory 602 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. Memory 602 in the embodiments of the present application may also be a circuit or any other device capable of performing a storage function, used to store program instructions and / or data.

[0092] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0093] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0094] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0095] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0096] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for processing an instruction, characterized in that: Applicable to a CPU that processes instructions in pipeline mode, the method includes: Performing instruction matching based on the instruction information representing the instruction to determine whether the instruction needs to be bypassed; If it is determined that the instruction needs to be bypassed, pausing the pipeline where the instruction is located; An instruction result after the instruction is processed through the bypass is determined as the instruction result of the instruction, and the pipeline is restored at the target address indicated by the bypass.

2. The method according to claim 1, characterized in that The pipeline includes an instruction fetch stage and an execution effect stage; the execution effect stage is a pipeline stage located after the instruction fetch stage and needs to be rolled back in case of an exception; Instruction matching is performed based on the instruction information representing the instruction, including: performing instruction matching based on indication information representing the instructions on the instructions obtained by the instruction fetch stage of the pipeline, while the pipeline continues to be in an execution state; If the pipeline is executed to any execution effect stage and no instruction matching result is obtained, the pipeline is paused until the instruction matching result is obtained, and the instruction matching result indicates whether the instruction needs to be bypassed.

3. The method according to claim 1, characterized in that The pipeline includes an instruction fetch stage and an execution effect stage; the execution effect stage is a pipeline stage located after the instruction fetch stage and needs to be rolled back in case of an exception; Instruction matching is performed based on the instruction information representing the instruction, including: performing instruction matching based on instruction information representing the instruction on the instruction obtained by the instruction fetch stage of the pipeline, while the pipeline continues to be in an execution state; If it is determined that the instruction needs to be bypassed, pausing the pipeline where the instruction is located, including: If it is determined that the instruction needs to be bypassed, the pipeline is executed to any execution effect stage, then the pipeline is rolled back and the pipeline where the instruction is located is paused.

4. The method according to claim 2 or 3, characterized in that The pipeline further includes a non-execution effect stage located after the instruction fetch stage and before the execution effect stage; the non-execution effect stage is a pipeline stage that does not need to be rolled back in the event of an exception; If it is determined that the instruction needs to be bypassed, pausing the pipeline where the instruction is located, including: If it is determined that the instruction needs to be bypassed, the pipeline is executed to any non-execution effect stage, and the pipeline where the instruction is located is paused.

5. The method according to claim 1, wherein The pipeline includes an instruction fetch stage and a decoding stage; Performing instruction matching based on indication information representing the instruction and determining whether the instruction requires bypass processing includes: After the pipeline completes the instruction fetch stage and before starting the decode stage, instruction matching is performed based on indication information representing the instruction to determine whether the instruction needs to be bypassed.

6. The method according to claim 1, characterized in that The pipeline includes an instruction fetch stage and an instruction adjustment stage; the instruction adjustment stage is located after the instruction fetch stage; Instruction matching is performed based on the instruction information representing the instruction, including: During the processing of any instruction adjustment stage by the pipeline, instruction matching based on indication information representing the instructions is performed on the first instruction before adjustment by the instruction adjustment stage and the second instruction after adjustment by the instruction adjustment stage.

7. The method according to any one of claims 1, 2, 3 and 5, characterized in that: Performing instruction matching based on indication information representing the instruction and determining whether the instruction requires bypass processing includes: For any matching item, determine whether the indication information representing the instruction matches the mask and / or target value in the matching item; if so, determine that the instruction needs to be bypassed.

8. The method according to claim 7, characterized in that The target value of the matching item represents an operation code for obtaining the current clock; the mask of the matching item is the bit where the operation code is located; and the instruction result is clock information that is irrelevant to the current clock or inaccurate clock information.

9. The method according to claim 7, characterized in that The instructions that need to be bypassed are new instructions; The target value of the matching item is a reserved opcode, and / or the mask of the matching item is a reserved bit field, and the target value of the matching item is at least one level of opcode.

10. The method according to claim 7, characterized in that There is an error in the hardware implementation of the CPU for the instruction that needs to be bypassed, and the error causes an unexpected instruction result; the bypass result is the expected instruction result or causes an exception or is empty.

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