Quick-response band-gap reference starting circuit

Abstract

The invention discloses a quick-response band-gap reference starting circuit. The quick-response band-gap reference starting circuit comprises a first transistor group, a second transistor group, a third transistor group, an MN7 transistor and an AMP3 transconductance amplifier, the drain electrode of the last MP transistor in the first transistor group is electrically connected with the source electrodes of the MP4 transistor and the MP5 transistor in the second transistor, and the drain electrode of the MP4 transistor is electrically connected with the grid electrode of the MN6 transistor in the third transistor group and the grid electrode and the drain electrode of the MN5 transistor; the drain electrode of the MP5 transistor is electrically connected with the bias end of the AMP3 transconductance amplifier and outputs IBIAS2 current to the bias end of the AMP3 transconductance amplifier; the drain electrode of the MN6 transistor is electrically connected with the drain electrode of the MN7 transistor, and the grid electrode of the MN7 transistor is electrically connected with the output end of the AMP3 transconductance amplifier; through a current branch formed by the first transistor group and the second transistor group, quick response of the band-gap reference starting circuit is realized; and meanwhile, by reasonably distributing the proportion of the current mirror, a higher starting speed is obtained with weak power consumption cost.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fast-response bandgap reference startup circuit. Background Art

[0002] In integrated circuit systems, the bandgap reference module is a critical circuit functional module. A crucial issue for bandgap reference module circuits is preventing the occurrence of circuit dead zones. Once the circuit enters this dead zone during power-up, the overall circuit will not function properly, a problem that must be avoided. To address potential dead zone issues, most existing analog circuits incorporate a bandgap reference circuit startup circuit to eliminate the circuit's merging points during power-up. However, for specialized applications, the circuit startup time is also factored into overall performance considerations, leading to long startup times in existing startup circuits. Traditional bandgap reference circuits require turning on a set of NMOS transistors, then turning off this set, and then turning on another set of NMOS transistors to start the bandgap reference circuit. This results in a slow startup time for traditional bandgap reference startup circuits. Summary of the Invention

[0003] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a fast-response bandgap reference startup circuit, which injects a normally-on current into the op amp used for clamping by adding an additional current branch, and at the same time, by reasonably allocating the current mirror ratio, achieves a faster startup speed at a low power consumption cost.

[0004] Technical solution: To achieve the above-mentioned objectives, the present invention provides a fast-response bandgap reference startup circuit, comprising a first transistor group, a second transistor group, a third transistor group, an MN7 transistor, and an AMP3 transconductance amplifier; the drain of the last MP transistor in the first transistor group is electrically connected to the source of the MP4 transistor and the MP5 transistor in the second transistor group, and the drain of the MP4 transistor is electrically connected to the gate of the MN6 transistor and the gate and drain of the MN5 transistor in the third transistor group; the drain of the MP5 transistor is electrically connected to the bias terminal of the AMP3 transconductance amplifier and outputs the IBIAS2 current to the bias terminal of the AMP3 transconductance amplifier; the drain of the MN6 transistor is electrically connected to the drain of the MN7 transistor, and the gate of the MN7 transistor is electrically connected to the output terminal of the AMP3 transconductance amplifier; the fast response of the bandgap reference startup circuit is achieved through the current branch formed by the first transistor group and the second transistor group.

[0005] Furthermore, the first transistor group includes a plurality of MP transistors connected in series; the drain of each of the plurality of MP transistors is electrically connected to the source of the next MP transistor, and the source of the first MP transistor among the plurality of MP transistors is electrically connected to VDD; the gates of the plurality of MP transistors are electrically connected to one end of the R3 resistor, and the other end of the R3 resistor is electrically connected to VSS.

[0006] Furthermore, the gate of the MP5 transistor in the second transistor group is electrically connected to the gate of the MP4 transistor in the second transistor group, and the gate of the MN5 transistor and the gate of the MN6 transistor in the third transistor group; the source of the MN5 transistor and the source of the MN6 transistor are electrically connected to VSS.

[0007] Furthermore, the size ratio of the MP4 transistor to the MP5 transistor is 1:3.

[0008] Furthermore, the size ratio of the MN5 transistor to the MN6 transistor is 1:1.

[0009] Furthermore, it also includes an MP1 transistor, an MP2 transistor and an MP3 transistor; the drain of the MN7 transistor is electrically connected to the drain of the MP1 transistor, the gate of the MP1 transistor, the gate of the MP2 transistor and the gate of the MP3 transistor; the drain of the MP2 transistor is electrically connected to one input terminal of the AMP3 transconductance amplifier, and the drain of the MP3 transistor is electrically connected to the other input terminal of the AMP3 transconductance amplifier.

[0010] Furthermore, it also includes a Q3 transistor and a Q4 transistor; the emitter of the Q3 transistor is electrically connected to one end of the R4 resistor, and the other end of the R4 resistor is electrically connected to an input end of the AMP3 transconductance amplifier; the emitter of the Q4 transistor is electrically connected to the other input end of the AMP3 transconductance amplifier.

[0011] Beneficial effects: A fast-response bandgap reference startup circuit of the present invention injects a normally-on current into the op amp used for clamping by adding an additional current branch, thereby achieving fast startup. The tail current IBIAS2 used by the clamping op amp is generated by the startup circuit, which is faster than the tail current in the traditional structure, thus eliminating the time for the tail current to establish. Compared with the traditional structure, there is no need to turn off one group of NMOS and then turn on another group of NMOS. Instead, only one group of NMOS needs to be turned on, which greatly saves the startup time. The extra power consumption current is not wasted, and is used to pull down the merging point and the tail current of the clamping op amp respectively under the configuration of an appropriate proportional relationship, and the op amp dedicated to startup is eliminated, thereby reducing the cost. At the same time, the current will not be excessively wasted. By reasonably allocating the current mirror ratio, a faster startup speed is achieved at a slight power consumption cost. Compared with the traditional bandgap reference dual op amp startup circuit structure, the area is smaller, and better performance can be achieved at a lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a circuit diagram of a bandgap reference startup circuit;

[0013] Figure 2 This is a simulation diagram of the startup time of the bandgap reference startup circuit. DETAILED DESCRIPTION

[0014] The present invention will be further described below with reference to the accompanying drawings.

[0015] like Figure 1 As shown, a fast-response bandgap reference startup circuit includes a first transistor group 1, a second transistor group, a third transistor group, an MN7 transistor 15, and an AMP3 transconductance amplifier 2; the drain of the last MP transistor in the first transistor group 1 is electrically connected to the source of the MP4 transistor 11 and the MP5 transistor 12 in the second transistor group, the drain of the MP4 transistor 11 is electrically connected to the gate of the MN6 transistor 14 and the gate and drain of the MN5 transistor 13 in the third transistor group; the drain of the MP5 transistor 12 is electrically connected to the gate of the AMP3 transconductance amplifier 2. The bias terminal is connected to the bias terminal of the AMP3 transconductance amplifier 2, and the IBIAS2 current is output to the bias terminal of the AMP3 transconductance amplifier 2; the drain of the MN6 transistor 14 is electrically connected to the drain of the MN7 transistor 15, and the gate of the MN7 transistor 15 is electrically connected to the output terminal of the AMP3 transconductance amplifier 2; through the current branch formed by the first transistor group and the second transistor group, the output IBIAS2 current is input to the bias terminal of the AMP3 transconductance amplifier 2, and a small part of the current is input to the drain of the MN5 transistor 13, so that the drain merger point of the MN6 transistor is pulled down, thereby realizing a fast response of the bandgap reference startup circuit.

[0016] The source of transistor MN7 15 is electrically connected to VSS, effectively grounding the source of transistor MN7 15. Furthermore, the size of transistor MN7 15 is larger than that of transistor MN6 14 to ensure that after the circuit is powered on and started, transistor MN6 has minimal impact on the normal operation of the main circuit. Transconductance amplifier AMP 3 2 is an operational amplifier used to start the circuit. Before the circuit is powered on, the voltages at its internal nodes are all zero.

[0017] The first transistor group 1 includes several MP transistors connected in series. The drain of each MP transistor is electrically connected to the source of the next MP transistor. The source of the first MP transistor is electrically connected to VDD, i.e., it is electrically connected to the power supply voltage. The drain of the last MP transistor is electrically connected to the source of MP4 transistor 11 and MP5 transistor 12. The gates of the MP transistors are electrically connected to one end of resistor R3, and the other end of resistor R3 is electrically connected to VSS, i.e., the other end of resistor R3 is grounded. By connecting the MP transistors in series in the first transistor group 1 instead of resistors in traditional circuits, the circuit area occupied is saved. At the same time, the gates of the MP transistors are all grounded through resistor R3, ensuring that real-time current is generated and input to the drains of MP4 transistor 11 and MP5 transistor 12 when the circuit is powered on.

[0018] The gate of the MP5 transistor 12 in the second transistor group is electrically connected to the gate of the MP4 transistor 11 in the second transistor group, and the gate of the MN5 transistor 13 and the gate of the MN6 transistor 14 in the third transistor group; the source of the MN5 transistor 13 and the source of the MN6 transistor 14 are electrically connected to VSS.

[0019] The size ratio of the MP4 transistor 11 and the MP5 transistor 12 is 1:3. Because the size ratio of the MP4 transistor 11 and the MP5 transistor 12 is set, most of the current is output through the drain of the MP5 transistor 12 and supplied to the AMP3 transconductance amplifier 2 as the IBIAS2 current; a small portion of the current is output to the MN5 transistor through the drain of the MP4 transistor 11. By setting a current branch to provide the IBIAS2 current used by the clamping operational amplifier to the AMP3 transconductance amplifier 2, the time for tail current establishment is saved. The size ratio of the MN5 transistor 13 and the MN6 transistor 14 is 1:1.

[0020] The circuit also includes an MP1 transistor 21, an MP2 transistor 22, and an MP3 transistor 23. The drain of the MN7 transistor 15 is electrically connected to the drain of the MP1 transistor 21, the gate of the MP1 transistor 21, the gate of the MP2 transistor 22, and the gate of the MP3 transistor 23. The drain of the MP2 transistor 22 is electrically connected to one input terminal of the AMP3 transconductance amplifier 2, and the drain of the MP3 transistor 23 is electrically connected to the other input terminal of the AMP3 transconductance amplifier 2. The sources of the MP1 transistor 21, the MP2 transistor 22, and the MP3 transistor 23 are all electrically connected to VDD, that is, electrically connected to the power supply voltage. Due to the proportional size of the MN5 transistor 13 and the MN6 transistor 14, when the MN6 transistor 14 is powered on, that is, when the MN6 transistor 14 is turned on, the combined point of the drain is pulled down, allowing the MP1 transistor 21, the MP2 transistor 22, and the MP3 transistor 23 to operate normally.

[0021] It also includes a Q3 transistor 31 and a Q4 transistor 32; the emitter of the Q3 transistor 31 is electrically connected to one end of the R4 resistor, and the other end of the R4 resistor is electrically connected to one input end of the AMP3 transconductance amplifier 2; the emitter of the Q4 transistor 32 is electrically connected to the other input end of the AMP3 transconductance amplifier 2; the collector and base of the Q3 transistor 31 are electrically connected to VSS, that is, the collector and base of the Q3 transistor 31 are grounded; the collector and base of the Q4 transistor 32 are electrically connected to VSS, that is, the collector and base of the Q4 transistor 32 are grounded.

[0022] Before the bandgap reference startup circuit is powered on, the internal node voltages are all 0; when the bandgap reference startup circuit is powered on, the first transistor group 1 generates a real-time current, which is input to the drains of the MP4 transistor and the MP5 transistor; at this time, the MP4 transistor 11 and the MP5 transistor are turned on, and at the same time, due to the size ratio of the MP4 transistor and the MP5 transistor, most of the current is input as the IBIAS2 current to the bias end of the AMP3 transconductance amplifier 2, that is, the IBIAS2 current or tail current generated by the current branch formed by the connection of the first transistor group and the second transistor group is transmitted to the bias end of the AMP3 transconductance amplifier 2; a small part of the current is output to the MN5 transistor through the drain of the MP4 transistor, and at this time the MN5 transistor and the MN6 transistor are connected. The body transistor is turned on, and after MN6 is turned on, the merging point of the drain end is pulled down, and the MP1 transistor, MP2 transistor and MP3 transistor gradually work normally as a current mirror; at the same time, the AMP3 transconductance amplifier 2 also works normally, and the output end voltage gradually increases, so that the MN7 transistor is turned on, and the positive input end and the negative input end of the AMP3 transconductance amplifier 2 remain in a virtual short state, that is, the two input ends of the AMP3 transconductance amplifier 2 remain in a virtual short state; at this time, the bandgap reference startup circuit achieves a fast response. Compared with the traditional bandgap reference startup circuit, the process of turning on a group of NMOS tubes, then turning off this group of NMOS tubes, and then turning on another group of NMOS tubes to realize the startup of the bandgap reference circuit is reduced. Therefore, the response of the present invention is faster than that of the traditional bandgap reference startup current.

[0023] like Figure 2 As shown, the startup time simulation of the bandgap reference startup circuit in the present invention is carried out, wherein the broken lines from top to bottom respectively represent the tail power supply voltage line, the voltage line output by the drain of the MN6 transistor and the subsequent VREF reference voltage line; it can be seen that the power-on time is within 100μs, the startup process is basically completed at 50μs, and VREF is normally output at about 55μs; the additional current branch current added by the fast startup bandgap reference circuit of the present invention is not wasted, most of it flows to the clamping operational amplifier as a tail current to provide gain, and a small part is used to pull down the merging point, thereby realizing the fast startup of the bandgap reference startup circuit and ensuring that the additional power consumption current is not wasted, thereby reducing the cost of the bandgap reference startup circuit.

[0024] The above is only a description of the preferred embodiment of the present invention. Ordinary technicians in this technical field can make several modifications and optimizations based on the above disclosure without departing from the above basic principles. These improvements and optimizations should be regarded as the scope of protection understood by the present invention.

Claims

1. A fast-response bandgap reference startup circuit, characterized in that: The invention comprises a first transistor group (1), a second transistor group, a third transistor group, an MN7 transistor (15) and an AMP3 transconductance amplifier (2); the drain of the last MP transistor in the first transistor group (1) is electrically connected to the source of the MP4 transistor (11) and the MP5 transistor (12) in the second transistor group, the drain of the MP4 transistor (11) is electrically connected to the gate of the MN6 transistor (14) and the gate and drain of the MN5 transistor (13) in the third transistor group; the drain of the MP5 transistor (12) is electrically connected to the bias terminal of the AMP3 transconductance amplifier (2) and outputs the IBIAS2 current to the bias terminal of the AMP3 transconductance amplifier (2); the drain of the MN6 transistor (14) is electrically connected to the drain of the MN7 transistor (15), and the gate of the MN7 transistor (15) is electrically connected to the output terminal of the AMP3 transconductance amplifier (2); and the fast response of the bandgap reference startup circuit is achieved through the current branch formed by the first transistor group (1) and the second transistor group.

2. The fast-response bandgap reference startup circuit according to claim 1, characterized in that: The first transistor group (1) comprises a plurality of MP transistors connected in series; the drain of each of the plurality of MP transistors is electrically connected to the source of the next MP transistor, and the source of the first MP transistor among the plurality of MP transistors is electrically connected to VDD; the gates of the plurality of MP transistors are electrically connected to one end of an R3 resistor, and the other end of the R3 resistor is electrically connected to VSS.

3. The fast-response bandgap reference startup circuit according to claim 1, wherein: The gate of the MP5 transistor (12) in the second transistor group is electrically connected to the gate of the MP4 transistor (11) in the second transistor group, and the gate of the MN5 transistor (13) and the gate of the MN6 transistor (14) in the third transistor group; the source of the MN5 transistor (13) and the source of the MN6 transistor (14) are electrically connected to VSS.

4. The fast-response bandgap reference startup circuit according to claim 3, wherein: The size ratio of the MP4 transistor (11) to the MP5 transistor (12) is 1:

3.

5. The fast-response bandgap reference startup circuit according to claim 3, wherein: The size ratio of the MN5 transistor (13) to the MN6 transistor (14) is 1:

1.

6. The fast-response bandgap reference startup circuit according to claim 1, characterized in that: It also includes an MP1 transistor (21), an MP2 transistor (22) and an MP3 transistor (23); the drain of the MN7 transistor (15) is electrically connected to the drain of the MP1 transistor (21), the gate of the MP1 transistor (21), the gate of the MP2 transistor (22) and the gate of the MP3 transistor (23); the drain of the MP2 transistor (22) is electrically connected to one input terminal of the AMP3 transconductance amplifier (2), and the drain of the MP3 transistor (23) is electrically connected to the other input terminal of the AMP3 transconductance amplifier (2).

7. The fast-response bandgap reference startup circuit according to claim 1, characterized in that: It also includes a Q3 transistor (31) and a Q4 transistor (32); the emitter of the Q3 transistor (31) is electrically connected to one end of the R4 resistor, and the other end of the R4 resistor is electrically connected to an input end of the AMP3 transconductance amplifier (2); the emitter of the Q4 transistor (32) is electrically connected to the other input end of the AMP3 transconductance amplifier (2).

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