Periodic March test system and method for volatile memory

Abstract

The invention provides a method for performing a self-test on a memory. The method may include determining an operation mode of a memory built-in self-test (MBIST) unit based on a state of the memory; in response to the operation mode being a start mode, configuring the MBIST unit to execute a first type of memory self-test; and in response to the operation mode being a runtime mode, configuring the MBIST unit to periodically execute a second type of memory self-test.

Description

Technical Field

[0001] The present disclosure generally relates to memory self-testing. More specifically, the disclosed systems and methods relate to performing periodic March tests on a memory during operation. Background Art

[0002] The reliability and performance of computer systems are highly dependent on the integrity of their memory devices. Like any other hardware component, memory devices may degrade, malfunction, or fail over time. To ensure the continued functionality and stability of computer systems, memory self-tests have become essential tools for diagnosing potential issues and proactively identifying memory-related problems. Memory self-tests are diagnostic programs that enable a computer system to automatically assess the integrity of its memory. By implementing a series of self-checking algorithms and tests, these assessments are designed to detect errors, faults, or weaknesses in the memory before they escalate into serious system failures.

[0003] Modern memory devices often include built-in self-test (BIST) circuits or cells that execute complex test algorithms, performing a series of read and write operations on memory cells. Among various memory test algorithms, March algorithms (or March testing) provide an effective tool for identifying multiple types of faults, including stuck-at faults (memory cells stuck at a specific logic level), transition faults (logic level switching issues), and coupling faults (which can be caused by interference between adjacent cells). Note that the name "March" derives from the acronym for the basic memory operations involved in the algorithm: Move, And, Read, Write, Check, and Hold. March testing involves a large number of read and write operations across the entire memory, potentially disrupting normal data access patterns and task execution. If not managed properly, this can lead to unpredictable behavior, data corruption, or even system crashes. Therefore, March testing is typically performed during system startup or shutdown. Summary of the Invention

[0004] The present disclosure provides a method for performing a self-test on a memory. The method may include: determining an operating mode of a memory built-in self-test (MBIST) unit based on a memory state; in response to the operating mode being a startup mode, configuring the MBIST unit to perform a first type of memory self-test; and in response to the operating mode being a runtime mode, configuring the MBIST unit to periodically perform a second type of memory self-test.

[0005] In a variation of this embodiment, determining the operation mode of the MBIST unit may include: in response to detecting that the memory is starting up, determining the operation mode of the MBIST unit to be the startup mode; in response to detecting that the memory is running, determining the operation mode of the MBIST unit to be the runtime mode.

[0006] In a variation of this embodiment, the first type of memory self-test has a longer test pattern than the second type of memory self-test.

[0007] In a variation of this embodiment, the first or second type of memory self-test may include a March test.

[0008] In another variation, the first type of memory self-test may include a March A test or a March B test.

[0009] In another variation, the second type of memory self-test includes a March X test or a March Y test.

[0010] In a variation of this embodiment, periodically performing the second type of memory self-test may include detecting that a processor associated with the memory enters a periodic interval during which the processor does not access the memory, and performing the second type of memory self-test during the periodic interval.

[0011] In another variation, the processor is an image signal processor (ISP), and the periodic interval may include a vertical blanking interval or a horizontal blanking interval.

[0012] In another variation, detecting that the processor has entered a periodic interval may include receiving a signal from the processor.

[0013] In another variation, the memory belongs to an autonomous driving system, and the method may further include: in response to detecting a memory error, generating and sending a notification to an upper-level safety control unit in the autonomous driving system, so that the upper-level safety control unit can take corresponding safety control measures to ensure vehicle safety.

[0014] The present disclosure also provides a memory built-in self-test (MBIST) system for performing self-tests on a memory. The MBIST system may include: a mode configuration logic unit for configuring an MBIST unit's operating mode based on a state of the memory to be tested; a test pattern generation logic unit for generating a test pattern based on the operating mode; and a read / write logic unit for performing memory read and write operations based on the test pattern. The test pattern generation logic unit generates a first type of test pattern in response to the operating mode being a startup mode, and the test pattern generation logic unit periodically generates a second type of test pattern in response to the operating mode being a runtime mode.

[0015] In a variation of this embodiment, the mode configuration logic unit configures the operation mode to the boot mode in response to detecting that the memory is booting, and configures the operation mode to the runtime mode in response to detecting that the memory is running.

[0016] In a variation of this embodiment, the first type of test pattern is longer than the second type of test pattern.

[0017] In a variation of this embodiment, the first or second type of test pattern may include a March test pattern.

[0018] In another variation, the first type of test pattern may include a March A test pattern or a March B test pattern, and the second type of test pattern may include a March X test pattern or a March Y test pattern.

[0019] In a variation of this embodiment, the MBIST system may further include a test trigger logic unit for triggering the memory self-test using the second type of test mode in response to detecting that the processor associated with the memory enters a periodic interval during which the processor does not access the memory.

[0020] In another variation, the processor is an image signal processor (ISP), and the periodic interval may include a vertical blanking interval or a horizontal blanking interval.

[0021] In another variation, the test trigger logic detects the processor entering a periodic interval based on a signal received from the processor.

[0022] In a further variation, the MBIST system, memory, and processor may be integrated into the same semiconductor chip.

[0023] In a variation of this embodiment, the memory belongs to an autonomous driving system, and the MBIST system may further include an error reporting logic unit for generating and sending a notification to an upper-level safety control unit in the autonomous driving system in response to a memory error detected in a self-test, thereby enabling the upper-level safety control unit to take corresponding safety control measures to ensure vehicle safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 An exemplary timing diagram related to a memory built-in self-test (MBIST) according to one embodiment of the present application is shown;

[0025] Figure 2 The algorithm of the March B test and the March X test according to one embodiment of the present application is shown;

[0026] Figure 3 An exemplary architecture of a memory system with a built-in self-test (BIST) function according to one embodiment of the present application is shown;

[0027] Figure 4 An exemplary process of executing a memory self-test according to an embodiment of the present application is presented through a flowchart;

[0028] Figure 5 A block diagram illustrating an exemplary apparatus for memory self-testing according to an embodiment of the present application is shown;

[0029] Figure 6 An exemplary computer system for implementing a memory self-test according to one embodiment of the present application is shown;

[0030] In the various drawings, the same reference numerals denote the same graphical elements. DETAILED DESCRIPTION

[0031] The following description is intended to enable those skilled in the art to make and use the disclosed embodiments, and is provided in the context of one or more specific applications and their requirements. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the scope of the disclosure. Therefore, the present invention and its various aspects are not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the disclosure.

[0032] Overview

[0033] This disclosure describes a system and method for performing memory self-tests during memory system startup and operation. The proposed built-in self-test (BIST) system can be configured to periodically perform March tests during memory operation. To test memory used by processors executing frame-based applications, periodic March tests can be performed during the intervals between consecutive frames. For example, to test memory used in image signal processing (ISP) applications, March tests can be performed during the vertical blanking interval (VBI) or field blanking interval (VBLANK). In one embodiment, periodic March tests can use an algorithm with fewer March elements (e.g., MarchX). In addition to periodic tests, the BIST system can also perform March tests during memory system startup. In one embodiment, startup March tests can use an algorithm with more March elements (e.g., March B). Both periodic and startup March tests can meet the memory testing requirements set by autonomous driving safety standards.

[0034] Memory testing for autonomous driving

[0035] Similar to other computing systems, autonomous driving systems may face the risk of system failure due to memory failures. Promptly detecting memory failures is crucial to ensuring the safety of autonomous vehicles. The vehicle safety standard ISO 26262 specifies a series of memory testing mechanisms that provide high diagnostic coverage for volatile memory (e.g., random-access memory). More specifically, memory monitoring using error-correction codes (ECC) or error-detection codes (EDC), block replication mechanisms, running checksums such as cyclic redundancy checks (CRC), and performing March tests are all expected to achieve high diagnostic coverage.

[0036] ECC and EDC schemes can be used to detect and correct n-bit data corruption, including every single-bit failure, every double-bit failure, partial triple-bit failures, and partial full-bit failures. While ECC / EDC schemes offer the advantage of detecting errors without requiring dedicated test cycles, they rely on additional redundant ECC bits, potentially increasing memory size. For example, a 128-bit memory requires an additional 9 bits of ECC, which increases area costs in application-specific integrated circuit (ASIC) design.

[0037] The diagnostic coverage of block replication may be degraded due to certain common failure modes. Additionally, running checksums requires special consideration to ensure that the values ​​used to calculate the checksum are not altered during the checksum calculation process.

[0038] Many memory protection systems use Single Error Correction Double Error Detection (SECDED) technology, which requires running fault injection tests during the boot process. March testing is a preferred method for detecting persistent bit faults (for example, stuck-at faults, or SAFs), bit transition faults (for example, transition faults, or TFs), addressing faults (for example, address-decoder faults, or AFs), and coupled cell faults (for example, coupling faults, or CFs).

[0039] A March test can contain a finite sequence of March elements, each of which contains a finite sequence of operations applied to each cell in the memory before proceeding to the next cell in the specified address order. Example operations can include: writing a "0" to the cell (denoted by "W0"), writing a "1" (denoted by "W1"), reading the expected "0" from the cell (denoted by "R0"), and reading the expected "1" (denoted by "R1"). Typical address orders include ascending order (denoted by ⇑), descending order (denoted by ⇓), and don't care order (denoted by ⇕). Note that all operations of the March element must be completed before performing the test on the next address.

[0040] Depending on the algorithm, the test pattern may contain fewer or more operations. For example, the test pattern for the MATS (Mixed Affine Time-Varying Systems) algorithm may contain four operations: ⇕(W0); ⇕(R0, W1); ⇕(R1); while the test pattern for the MATS+ algorithm may contain five operations: ⇕(W0); ⇑(R0, W1); ⇓(R1, W0).

[0041] Built-in self-test (BIST) systems (or testers) can include circuitry embedded within memory systems to reduce test complexity and cost. Traditional BIST systems typically perform memory tests at system power-up but may not be able to test at runtime. However, memory calls can fail at runtime, and undetected faults in memory can sometimes cause system failure. For autonomous driving, performing runtime memory testing is crucial to ensuring data integrity in safety-critical systems.

[0042] In certain embodiments of the present application, a BIST system may utilize blanking intervals (e.g., VBLANKs) present during image processing. It is important to note that VBLANK was originally a term associated with the raster scanning process in cathode-ray tube (CRT) displays. VBLANK refers to the period in a CRT display where the electron beam returns from the bottom of the screen to the top in preparation for the next frame. This interval occurs during the vertical retrace of the electron beam. Image sensors may have similar vertical and horizontal blanking intervals to facilitate sensor element reset and provide additional time for processing. During VBLANK, the image signal processor (ISP) does not read from or write to memory, thus enabling the execution of memory self-tests.

[0043] Figure 1 FIG. 4 shows an exemplary timing diagram related to a memory built-in self-test (MBIST) according to an embodiment of the present application. Figure 1 The upper portion of the diagram illustrates the interval (e.g., VBLANK) between image frames generated by a camera sensor, such as a charge-coupled device (CCD) sensor. For example, after capturing Image 0, the camera sensor's sensor elements need to be reset before the sensor can capture the next image (i.e., Image 1). The interval required to reset the sensor elements between consecutive image frames is called the vertical blanking interval, or VBLANK. There is also a horizontal blanking interval (HBLANK), which refers to the time required to reset each row of sensor elements. During VBLANK and HBLANK, the image sensor does not output data.

[0044] Image data (e.g., the output of an image sensor) can be sent frame by frame to an image signal processor (ISP) for processing. The ISP processes the images in the order they are received. Figure 1 As shown in the middle, there is also a VBLANK between two consecutive image processing. During the VBLANK period, the ISP does not receive any data from the camera sensor, and therefore does not read or write from the memory. Figure 1 As shown at the bottom, the memory tester can perform MBIST without interrupting normal memory operations.

[0045] The duration of VBLANK may be several milliseconds. Depending on the camera sensor type, VBLANK may last from 1 to 5 milliseconds. The memory tester can be designed to run MBIST on the entire memory during VBLANK. In some embodiments, the memory tester can run MBIST on different memory partitions in parallel.

[0046] In some embodiments, the memory tester can be configured to operate in two modes, such as boot mode and runtime mode. More specifically, the memory tester can be configured to run different test algorithms when operating in different modes. Because the time allocated for memory testing during system boot may be greater than during VBLANK, the memory tester can apply more complex test algorithms when operating in boot mode. Various March algorithms have been developed to detect specific types of memory faults (e.g., AFs, SAFs, TFs, and CFs). In some embodiments, the memory tester can perform March B testing when operating in boot mode and March X testing when operating in runtime mode.

[0047] Figure 2 FIG. 4 shows an algorithm for the March B test and the March X test according to an embodiment of the present application. Figure 2As shown, the March B algorithm test pattern can include 17 read and write operations, meaning the test time is approximately 17N, where N is the number of address locations. On the other hand, the March X algorithm test pattern can include 6 read and write operations, resulting in a test time of approximately 6N. Although March X's diagnostic coverage is less than that of March B, it still meets the requirements of vehicle safety standards (e.g., ISO 26262), making it an ideal choice for runtime memory testing. In addition to March X, other memory test algorithms can be used during runtime, as long as MBIST provides sufficient diagnostic coverage (e.g., greater than 99%) and meets time constraints (e.g., test time is less than the VBLANK duration). In one example, March Y testing can be used during runtime. Similarly, in addition to March B, other memory test algorithms can be used during startup. In one example, March A testing can be used during startup.

[0048] Memory with BIST

[0049] Figure 3 FIG2 shows an exemplary architecture of a memory system with a built-in self-test (BIST) function according to an embodiment of the present application. Figure 3 , the memory system 300 may include a memory 302 , a controller 304 , a BIST engine 306 , and a comparator 308 .

[0050] Memory 302 may be volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some embodiments, memory 302 may be SRAM that is part of the ISP's internal memory (e.g., cache). In one example, memory 302 may be integrated with the processor on the same semiconductor chip. In another example, memory 302 may be off-chip memory.

[0051] Controller 304 can interact with the ISP to determine test nodes based on the ISP state (e.g., startup or runtime). More specifically, controller 304 can configure the operating mode of BIST engine 306. If the ISP is startup, controller 304 can configure BIST engine 306 to operate in startup mode. If the ISP is running, controller 304 can configure BIST engine 306 to operate in runtime mode. Furthermore, while the ISP is running, controller 304 can receive a signal from the ISP indicating the arrival of each VBLANK. In response, controller 304 can send a trigger signal to BIST engine 306 to trigger a memory test.

[0052] In addition to performing MBIST during VBLANK of the ISP, the controller 304 can also configure the BIST engine 306 to run a memory test during each HBLANK. The controller 304 can receive a signal from the ISP indicating the start of HBLANK and then send a trigger signal to the BIST engine 306 to trigger the memory test.

[0053] The MBIST scheme can also be used for the memory associated with processor outside the ISP to carry out self-test during this runtime, particularly operates based on the processor of the data of frame.For example, the processor that is developed for machine application is usually used in neural network computing, to carry out multiplication operation to a large amount of weights read frame by frame from memory.Between the reading / update of every group of weight, the machine learning processor may not need to access memory, thereby produces the idle period that allows MBIST during runtime.Depending on the difference of application, the interval between the continuous idle period may be different.Controller 304 can be by being provided with the frequency of MBIST to be used for configuration BIST engine 306.

[0054] The BIST engine 306 may include multiple subunits (not shown) that play different roles in memory testing. Figure 3 ). For example, BIST engine 306 may include a pattern generator capable of generating test patterns based on a predetermined test algorithm. It is noteworthy that the test algorithm depends on the operating mode of BIST engine 306. In some embodiments, when BIST engine 306 operates in startup mode, the pattern generator may generate test patterns based on the March B algorithm; when BIST engine 306 operates in runtime mode, the pattern generator may generate test patterns based on the March X algorithm.

[0055] The BIST engine 306 may include a read / write controller that provides the location where data is written to the memory during a write operation or the location where data is read from the memory during a read operation. The BIST engine 306 may also include a data generator that provides the memory with the correct data corresponding to a specific element of a specific test pattern (e.g., March B or March X).

[0056] The BIST engine 306 can be implemented in various ways, including but not limited to microcode, hardware logic, and processor-based implementations. For example, a test algorithm (e.g., March B or March X) can be implemented using hardware-based finite-state machines. A processor-based BIST can rely on a processor to execute instructions to generate test patterns. A microcode-based BIST relies on a microcontroller to execute the microcode of the test algorithm. The scope of this disclosure is not limited to a particular implementation of the BIST engine 306.

[0057] Comparator 308 can be used to compare the data actually read from memory 302 with the data expected based on the test mode. For example, the expected return value of the R1 operation is "1", and the expected return value of the R0 operation is "0". If the read value is different from the expected value, an error is detected. Comparator 308 can generate a memory error report in response to the error detected by the BIST process. In some embodiments, the memory error report can be sent to the upper-level safety control unit of the advanced driver-assistance system (ADAS) or automated driving system (ADS). The upper-level safety control unit can determine whether further action is required based on the memory error report and the vehicle status. For example, if the detected memory error may cause a widespread system failure, the upper-level safety control unit can display a warning signal to the user. The user can stop operating the vehicle to prevent an accident.

[0058] Figure 4 The flowchart presents an exemplary process of performing a memory self-test according to an embodiment of the present application. In one or more embodiments, Figure 4 One or more steps in the may be repeated and / or performed in a different order. Figure 4 The specific arrangement of steps shown is not to be construed as limiting the scope of the technology.

[0059] During operation, the memory system starts up (operation 402). In most cases, the memory system starts up when the entire computer system is powered on. The tester may enter a startup mode (operation 404) and run a first type MBIST (operation 406). It is worth noting that running the first type MBIST may be part of the system startup sequence. In some embodiments, the first type MBIST may include a March A test or a March B test. In startup mode, the tester may be configured to generate a test pattern based on the first type MBIST (e.g., March A or March B). The tester may determine whether a memory error is detected (operation 408). If so, the tester may generate and send an error report to the upper-level security control unit (410). The upper-level security control unit may then take appropriate action based on the type and location of the reported memory error. If no memory error is detected, the process continues.

[0060] After performing the first type of MBIST, the tester may enter a runtime mode (operation 412) and determine whether the processor has entered a memory-idle interval (operation 414). A memory-idle interval is a periodic interval when the processor does not access memory. In some embodiments, the processor may be an ISP, and the memory-idle interval may be a VBLANK interval or an HBLANK interval. In one example, the tester may receive a signal from the ISP indicating that it is entering a VBLANK or HBLANK interval.

[0061] If the processor enters a memory idle interval, the tester may run a second type of MBIST (operation 416). Otherwise, the tester waits for the processor to enter a memory idle interval (operation 414). In some embodiments, the second type of MBIST may include a March X or March Y test. In runtime mode, the configurable tester generates a test pattern based on a second type of MBIST algorithm (e.g., March X or March Y). Due to time constraints during runtime testing, the second type of MBIST typically has a shorter test pattern than the first type of MBIST. Similarly, the tester may determine whether a memory error is detected (operation 418). If so, the tester may generate and send an error report to the upper-level security control unit (420). Otherwise, the tester may wait for the next memory idle interval (operation 414).

[0062] Figure 5 FIG. 1 shows a block diagram of an exemplary device for memory self-testing according to an embodiment of the present application. Figure 5In the embodiment, the memory test apparatus 500 may include a mode configuration logic unit 502, a test pattern generation logic unit 504, an address controller logic unit 506, a data generation logic unit 508, a test trigger logic unit 510, a read / write logic unit 512, a comparator logic unit 514, and an error reporting logic unit 516. In some embodiments, the memory test apparatus 500 may be located on the same semiconductor chip as the processor and on-chip memory. The various logic units in the memory test apparatus 500 may be implemented using hardware, software, firmware, or a combination thereof.

[0063] The mode configuration logic unit 502 may be used to determine and configure the operating mode of the memory testing apparatus 500 based on the state of the entire memory system. If the memory system is being powered on, the mode configuration logic unit 502 may configure the operating mode of the memory testing apparatus 500 to be the startup mode. On the other hand, if the memory system has already been powered on and is running, the mode configuration logic unit 502 may configure the operating mode of the memory testing apparatus 500 to be the runtime mode.

[0064] The test pattern generation logic unit 504 may be configured to generate a memory test pattern based on the operating mode. In some embodiments, if the operating mode is the boot mode, the test pattern generation logic unit 504 may generate a test pattern according to the March B algorithm (referred to as the March B test pattern). If the operating mode is the runtime mode, the test pattern generation logic unit 504 may periodically generate a test pattern according to the March X algorithm (referred to as the March X test pattern). Exemplary March B and March X test patterns are described in Figure 2 Each test pattern determines a specific sequence of memory operations that specifies the read / write mode and address order. In addition to March B and March X, other test algorithms can also be used.

[0065] The address controller logic unit 506 may be used to determine the starting and ending addresses for each memory test and to increment / decrement the read / write address based on the test mode. Note that the memory may be partitioned into smaller regions to allow multiple tests to be performed in parallel. The address controller logic unit 506 may determine the starting and ending addresses for each test.

[0066] The data generation logic unit 508 may be used to generate data to be written to the memory. The test trigger logic unit 510 may be used to trigger memory testing at runtime. More specifically, the test trigger logic unit 510 may receive a trigger signal from the processor indicating that the processor is entering a memory idle interval. In response to receiving this signal, the test trigger logic unit 510 may trigger a memory test (e.g., initiate a write / read operation based on a test pattern generated by the test pattern generation logic unit 504). The read / write logic unit 512 may be used to read and write to the memory based on the test pattern. More specifically, the read / write logic unit 512 may interact with the address controller logic unit 506 and the data generation logic unit 508 to read / write the correct data. The read / write logic unit 512 may also determine the number of cycles a given address should be held before incrementing or decrementing the address.

[0067] Comparator logic 514 can be used to compare data read from the memory by read / write logic 512 with its expected value to detect memory errors. For example, if the "R1" operation returns "0," a memory error has been detected. A memory error can indicate AF, SAF, TF, or CF, depending on where in the test sequence the error is detected. Error reporting logic 516 can be used to generate an error report based on the memory test results. Error reporting logic 516 can also be used to send the error report to a higher-level safety control unit so that the higher-level safety control unit can take appropriate measures to ensure vehicle safety.

[0068] Figure 6 An exemplary computer system for implementing memory self-testing according to one embodiment of the present application is shown. Computer system 600 includes a processor 602, memory 604, and storage device 606. In addition, computer system 600 may be coupled to peripheral input / output (I / O) user devices 610, such as a display device 612, a keyboard 614, and a pointing device 616. Storage device 606 may store an operating system 618, a memory test system 620, and data 640. In certain embodiments, computer system 600 may be implemented as part of an advanced driver assistance system (ADAS) or automated driving (ADS) system installed in a vehicle. Memory test system 620 may be used to detect errors in memory 604, which may be integrated on the same chip as processor 602. In alternative embodiments, memory 604 may be off-chip.

[0069] The memory test system 620 may include instructions that, when executed by the computer system 600, may cause the computer system 600 or the processor 602 to perform the methods and / or processes described in the present disclosure. Specifically, the memory test system 620 may include instructions for configuring an operating mode for a memory self-test (mode configuration instructions 622), generating a test pattern based on the operating mode (pattern generation instructions 624), determining a memory read / write address (address control instructions 626), generating data to be written to the memory (data generation instructions 628), triggering a memory self-test (test trigger instructions 630), reading / writing a memory location to be tested (memory read / write instructions 632), comparing data read from the memory to be tested with an expected value (data comparison instructions 634), and reporting memory errors to an upper-level security control unit (error reporting instructions 636).

[0070] Generally speaking, the disclosure proposes a kind of solution that performs memory self-test when running and need not increase tested memory area overhead.According to some embodiments, can configure mbist system to perform memory self-test when memory system starts, and periodically perform memory self-test when memory system is running.Can configure mbist system to run with startup mode when memory system starts, and run with runtime mode when memory system is normally running.In startup mode, mbist system can run the self-test with longer test pattern, for example March A or March B test.In runtime mode, mbist system can run the self-test with shorter test pattern, for example March X or March Y test.More specifically, when memory system is running, mbist system can utilize periodic memory idle interval by running self-test during memory idle interval, and processor does not access memory system during this period.For the memory associated with ISP, mbist system can run self-test during periodic VBLANK or HBLANK.In certain embodiments, mbist system can be the part of the memory system of ADS or ADAS of vehicle. If the MBIST system detects one or more memory errors, it can generate and send an error report to the upper-level safety control unit within the ADS or ADAS, which can then take appropriate measures to ensure vehicle safety.

[0071] The data structures and program codes described in this detailed description are typically stored on a non-transitory computer-readable storage medium, which can be any device or medium capable of storing code and / or data for use by a computer system. Non-transitory computer-readable storage media include, but are not limited to, volatile memory; non-volatile memory; electrical, magnetic, and optical storage devices, solid-state drives, and / or other non-transitory computer-readable media now known or later developed.

[0072] The methods and processes described in the detailed description may be embodied as code and / or data, which may be stored in the aforementioned non-transitory computer-readable storage medium. When a processor or computer system reads and executes the code stored on the medium and operates on the data stored on the medium, the processor or computer system executes the methods and processes embodied in the form of code and data structures and stored in the medium.

[0073] Furthermore, the optimized parameters derived from the above methods and processes can be programmed into hardware modules, including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and other programmable logic devices now known or later developed. When such a hardware module is activated, it executes the methods and processes contained within the module.

[0074] The foregoing embodiments are for illustration and description only and are not intended to be exhaustive or to limit the scope of the present disclosure to only the disclosed forms. Therefore, many modifications and variations will be apparent to those skilled in the art. The scope of the present disclosure is defined by the appended claims, not by the foregoing disclosure.

Claims

1. A method for performing a self-test on a memory, characterized in that: The method includes: determining an operating mode of a memory built-in self-test (MBIST) unit based on a state of the memory; in response to the operating mode being a startup mode, configuring the MBIST unit to perform a first type of memory self-test; and in response to the operating mode being a runtime mode, configuring the MBIST unit to periodically perform a second type of memory self-test.

2. The method according to claim 1, characterized in that Determining the operating mode of the MBIST unit includes: in response to detecting that the memory is starting up, determining the operating mode of the MBIST unit to be the startup mode; and in response to detecting that the memory is running, determining the operating mode of the MBIST unit to be the runtime mode.

3. The method according to claim 1, characterized in that The memory self-test of the first type has a longer test pattern than the memory self-test of the second type.

4. The method according to claim 1, wherein The first type or the second type of memory self-test comprises a March test.

5. The method according to claim 4, characterized in that The memory self-test of the first type comprises a March A or March B test.

6. The method according to claim 4, characterized in that The memory self-test of the second type comprises a March X or March Y test.

7. The method according to claim 1, characterized in that Periodically performing the second type of the memory self-test includes detecting that a processor associated with the memory enters a periodic interval during which the processor does not access the memory; and performing the second type of the memory self-test during the periodic interval.

8. The method according to claim 7, characterized in that The processor is an image signal processor (ISP), wherein the periodic interval comprises a vertical blanking interval or a horizontal blanking interval.

9. The method according to claim 7, characterized in that Detecting that the processor has entered the periodic interval includes receiving a signal from the processor.

10. The method according to claim 1, characterized in that The memory belongs to an autonomous driving system, and the method further includes: in response to detecting a memory error, generating and sending a notification to an upper-level safety control unit in the autonomous driving system, thereby prompting the upper-level safety control unit to take corresponding safety control measures to ensure vehicle safety.

11. A memory built-in self-test (MBIST) system for performing self-test on a memory, characterized in that include: A mode configuration logic unit is used for configuring an operating mode of the MBIST system based on the state of the memory to be tested; a test pattern generation logic unit, configured to generate a test pattern based on the operation mode; and a read / write logic unit for performing memory read and write operations based on the test mode; wherein, in response to the operation mode being a startup mode, the test mode generation logic unit generates a first type of test pattern; And, in response to the operating mode being the runtime mode, the test pattern generation logic unit periodically generates a second type of test pattern.

12. MBIST system according to claim 11, is characterized in that, The mode configuration logic unit is configured to: in response to detecting that the memory is starting up, configure the operation mode to the startup mode; and configuring the operation mode to the runtime mode in response to detecting that the memory is operating.

13. MBIST system according to claim 11, is characterized in that, The test pattern of the first type is longer than the test pattern of the second type.

14. MBIST system according to claim 11, is characterized in that, The test pattern of the first type or the second type includes a March test pattern.

15. MBIST system according to claim 14, is characterized in that, The test pattern of the first type includes a March A test or a March B test pattern, and the test pattern of the second type includes a March X test or a March Y test.

16. MBIST system according to claim 11, is characterized in that, Also included is a test trigger logic unit for triggering the memory self-test using the second type of test pattern in response to detecting that a processor associated with the memory enters a periodic interval during which the processor does not access the memory.

17. MBIST system according to claim 16, is characterized in that, The processor is an image signal processor (ISP), wherein the periodic interval comprises a vertical blanking interval or a horizontal blanking interval.

18. MBIST system according to claim 16, is characterized in that, The test trigger logic unit detects entry of the processor into the periodic interval based on a signal received from the processor.

19. MBIST system according to claim 16, is characterized in that, The MBIST system, the memory and the processor are integrated into the same semiconductor chip.

20. MBIST system according to claim 11, characterized in that, The memory belongs to an autonomous driving system, and the MBIST system further includes: an error reporting logic unit, for generating and sending a notification to an upper-level safety control unit in the autonomous driving system in response to a memory error detected by the self-test, so as to promote the upper-level safety control unit to take corresponding safety control measures to ensure vehicle safety.

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