Built-in self-test circuit and method for high-speed interface intellectual property cores

Abstract

This invention belongs to the field of electronic technology and provides a built-in self-test circuit and method for high-speed interface IP intellectual property cores. The built-in self-test circuit includes: a pseudo-random binary sequence generator for generating corresponding code pattern data; a serializer for converting the code pattern data into serial data; a signal transceiver unit; a deserializer for deserializing the serial data to obtain deserialized data and an encoded clock signal; a synchronization module for performing delay compensation on the deserialized data according to the encoded clock signal and aligning the delay-compensated data with the pseudo-random binary sequence code pattern data to obtain aligned data pairs; and a comparator for performing logical decisions on the aligned data pairs to determine whether the built-in self-test of the high-speed interface IP is successful or failed. The built-in self-test circuit of this invention has a simple structure, does not occupy additional convex resources, and improves the self-test efficiency and accuracy of high-speed interface IP in BIST mode.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a built-in self-test circuit and method for a high-speed interface intellectual property core. Background Technology

[0002] With technological advancements, chips are placing increasingly higher demands on the performance of their high-speed interface intellectual property cores (IPs), and the success rate of chip tape-out has a significant impact on chip yield. Therefore, it is becoming increasingly important to test the performance of IPs during the CP (creation testing) or FT (finished product testing) stages.

[0003] In related technologies, the correctness of data is generally verified by integrating a "PRBS checker" into the digital circuitry within the chip. This digital circuitry often requires complex software operations, increasing the complexity of the process. Existing technologies also bring out additional "test bumps" to bring the internal analog signals outside the chip so that they can be directly measured using an oscilloscope or other instruments. This method consumes bump resources and introduces additional loading (such as load effects) that affects the performance of the circuit, resulting in inaccurate test results. Summary of the Invention

[0004] This invention provides a built-in self-test circuit and method for high-speed interface intellectual property cores, which solves the defects of existing technologies that use the internal PRBS verifier of the chip to compare the correctness of data, which is complicated, and use additional test bumps to lead the internal analog signal to the outside of the chip for direct measurement, which results in inaccurate test results and occupies bump resources.

[0005] This invention provides a built-in self-test circuit for a high-speed interface intellectual property core, comprising:

[0006] A pseudo-random binary sequence generator is used to generate pseudo-random binary sequence code data in a built-in self-test mode. The pseudo-random binary sequence code data is multi-bit parallel data.

[0007] A serializer, connected to the pseudo-random binary sequence generator, is used to convert the pseudo-random binary sequence code data into serial data.

[0008] A signal transceiver unit, connected to the serializer, is used to forward the serial data;

[0009] A deserializer, connected to the signal transceiver unit, is used to deserialize the serial data to obtain deserialized data and an encoded clock signal.

[0010] A synchronization module, connected to the deserializer, is used to perform delay compensation on the deserialized data according to the encoded clock signal, and to time-align the delay-compensated data with the pseudo-random binary sequence code data to obtain an aligned data pair, wherein the aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data.

[0011] A comparator, connected to the synchronization module, is used to make logical decisions on the aligned data pairs, obtain multiple logical decision results, and determine whether the built-in self-test of the high-speed interface intellectual property core is successful or unsuccessful based on the multiple logical decision results.

[0012] According to the present invention, a built-in self-test circuit for a high-speed interface intellectual property core is provided, wherein the signal transceiver unit includes:

[0013] A transmitter driver is connected to the serializer;

[0014] The pads are connected to the transmit driver;

[0015] The receiver front end is connected to the pads and the deserializer at both ends, respectively.

[0016] According to the present invention, a built-in self-test circuit for a high-speed interface intellectual property core is provided, wherein the synchronization module includes multiple synchronization units, the number of which is related to the number of bits of the pseudo-random binary sequence code data.

[0017] According to the present invention, a built-in self-test circuit for a high-speed interface intellectual property core is provided, wherein the comparator is a NAND logic circuit.

[0018] According to the present invention, a built-in self-test circuit for a high-speed interface intellectual property core is provided, wherein the comparator is further used for:

[0019] If at least one of the multiple logical decision results passes the self-test, the built-in self-test of the high-speed interface intellectual property core is determined to be successful.

[0020] This invention also provides a built-in self-test method, comprising:

[0021] In the built-in self-test mode, pseudo-random binary sequence code data is generated, and the pseudo-random binary sequence code data is multi-bit parallel data.

[0022] Convert the pseudo-random binary sequence code data into serial data;

[0023] The serial data is deserialized to obtain deserialized data and an encoded clock signal;

[0024] The deserialized data is delayed and compensated according to the encoded clock signal, and the delayed and compensated data is time-aligned with the pseudo-random binary sequence code data to obtain an aligned data pair. The aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data.

[0025] Logical decisions are made on the aligned data pairs to obtain multiple logical decision results, and the success or failure of the built-in self-test of the high-speed interface intellectual property core is determined by the multiple logical decision results.

[0026] According to a built-in self-test method provided by the present invention, after converting the pseudo-random binary sequence code data into serial data and before deserializing the serial data, the method further includes:

[0027] The serial data is transmitted to the pads, and the serial data transmitted by the pads is received.

[0028] According to a built-in self-testing method provided by the present invention, the step of performing logical decision on the aligned data pair to obtain multiple logical decision results includes:

[0029] Based on the AND-NOT logic circuitry, multiple logic decision results are obtained by making decisions on the aligned data pairs.

[0030] The process of determining the success or failure of the built-in self-test of the high-speed interface intellectual property core through the multiple logical decision results includes:

[0031] If at least one of the multiple logical decision results passes the self-test, the built-in self-test of the high-speed interface intellectual property core is determined to be successful.

[0032] The present invention also provides a chip, comprising:

[0033] The built-in self-test circuit for the high-speed interface intellectual property core.

[0034] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the built-in self-test method as described above.

[0035] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the built-in self-test method as described above.

[0036] The present invention provides a built-in self-test circuit and method for high-speed interface intellectual property cores. It generates pseudo-random binary sequence pattern data in BIST mode using a pseudo-random binary sequence generator (PRBS GEN) as the data source for self-testing. A serializer converts the pseudo-random binary sequence pattern data into serial data, and a deserializer deserializes the serial data to obtain deserialized data and an encoded clock signal. This deserialized data is used to simulate signal attenuation or delay information during transmission. A synchronization module then performs delay compensation on the deserialized data based on the encoded clock signal and aligns the time-compensated data with the pseudo-random binary sequence pattern data to obtain aligned data pairs. This eliminates the phase difference caused by the physical transmission delay of the pseudo-random binary sequence pattern data. Finally, a comparator performs logical judgment on the aligned data pairs, and the success or failure of the built-in self-test of the high-speed interface intellectual property core IP is determined by multiple logical judgment results. This circuit has a simple structure, is easy to implement, does not occupy additional convex resources, and improves the efficiency and accuracy of self-testing of high-speed interface IP in BIST mode. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 This is one of the structural schematic diagrams of the built-in self-test circuit for the high-speed interface intellectual property core provided by the present invention.

[0039] Figure 2 This is a schematic diagram of the synchronization unit provided by the present invention.

[0040] Figure 3 This is the second schematic diagram of the built-in self-test circuit for the high-speed interface intellectual property core provided by this invention.

[0041] Figure 4 This is a flowchart illustrating the built-in self-test method provided by the present invention.

[0042] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0043] Figure label:

[0044] 100: Pseudo-random binary sequence generator; 200: Serializer; 300: Signal transceiver unit;

[0045] 310: Transmit driver; 320: Pad; 330: Receiver front end;

[0046] 400: Deserializer; 500: Synchronization module; 600: Comparator. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0048] The following is combined Figures 1-4 This invention describes a built-in self-test circuit and method for a high-speed interface intellectual property core.

[0049] Figure 1 This is one of the structural schematic diagrams of the built-in self-test circuit for high-speed interface intellectual property core provided by the present invention, such as... Figure 1 As shown, the built-in self-test circuit for the high-speed interface intellectual property core includes: a pseudo-random binary sequence generator 100, a serializer 200, a signal transceiver unit 300, a deserializer 400, a synchronization module 500, and a comparator 600.

[0050] It should be noted that the built-in self-test circuit for the high-speed interface IP can completely reuse the actual circuit when the chip is working normally, that is, directly use the actual transmitting and receiving path for testing, so as to most realistically reflect the performance of the circuit in the actual working scenario; or it can be a replica circuit independent of the actual circuit, which can perform separate testing without interfering with the main path or for extremely low power mode.

[0051] The pseudo-random binary sequence generator 100 is used to generate pseudo-random binary sequence code data in the built-in self-test mode. The pseudo-random binary sequence code data is multi-bit parallel data.

[0052] In this embodiment, the pseudo-random binary sequence generator 100 (PRBS GEN) is used to generate a data stream with statistical randomness, i.e., pseudo-random binary sequence code data, when the BIST (Built-in Self-Test) mode is activated.

[0053] In this embodiment, the pseudo-random binary sequence generator 100 is equipped with a control module (or configuration register group), and the corresponding control bits include the BIST enable register (BIST_EN). When BIST_EN=0 (invalid / default state), it indicates that the chip is in "normal function mode (Mission Mode)"; when BIST_EN=1 (valid / set state), it indicates that the chip has entered "built-in self-test mode (BIST Mode)".

[0054] In this embodiment, PRBS GEN can obtain the corresponding pseudo-random binary sequence code data using noise or a logic-based approach.

[0055] For example, thermal noise or Zener diode breakdown noise can be used as a source of physical entropy. After amplification and sampling, a true random number seed can be generated, and then PRBS code data can be generated from it.

[0056] This embodiment can also use a linear feedback shift register (LFSR) structure to perform shift and XOR operations through a preset polynomial to generate pseudo-random sequences with extremely long cycle periods (such as PRBS7, PRBS31, etc.), thereby obtaining pseudo-random binary sequence code data.

[0057] In this embodiment, in a high-speed testing scenario, PRBS GEN generates a set of parallel data of arbitrary bit width, which includes long strings of "0", long strings of "1" and high-frequency hopping patterns to simulate an extremely harsh data transmission environment.

[0058] The serializer 200, connected to the pseudo-random binary sequence generator 100, is used to convert pseudo-random binary sequence code data into serial data.

[0059] In this embodiment, the serializer 200 is used to perform a parallel-to-serial (P2S) conversion function, which can convert the low-speed, wide-bit-width parallel data generated by PRBS GEN into a high-speed, single-bit serial data stream.

[0060] For example, serializer 200 receives 32-bit parallel data from PRBS GEN and, driven by an internal high-frequency clock, converts it into a differential serial signal according to the timing sequence, namely the aforementioned serial data.

[0061] It should be noted that when the built-in self-test process is implemented in the replication circuit, the serializer 200 can be a 1:1 physical copy of the master function serializer 200, ensuring that its electrical characteristics (such as setup time and hold time) are completely consistent with the actual circuit.

[0062] The signal transceiver unit 300 is connected to the serializer 200 and is used to forward serial data.

[0063] In this embodiment, the signal transceiver unit 300 can be used in near-end loopback scenarios, that is, the transmitting end of the signal transceiver unit 300 is connected to the receiving end of the signal transceiver unit 300, and the serial data output by the transmitting end is directly forwarded to the receiving end inside the chip without passing through external pins, which is used to quickly verify the basic functions of digital logic and analog front end.

[0064] In this embodiment, the signal transceiver unit 300 constructs a complete signal transmission closed loop, enabling the test to cover analog driving capability, receiving sensitivity, and signal attenuation along the transmission path without relying on external test instrument probes.

[0065] The deserializer 400 is connected to the signal transceiver unit 300 and is used to deserialize serial data to obtain deserialized data and encoded clock signals.

[0066] In this embodiment, the serializer 400 performs the serial-to-parallel (S2P) conversion function, which is the reverse process of the serializer 200 performing the function.

[0067] In this embodiment, when the signal transceiver unit 300 sends serial data that has passed through a loop (which may be accompanied by jitter or attenuation), the deserializer 400 first extracts the synchronization clock (i.e. the encoded clock signal) from the data stream, uses the clock to sample the high-speed data, and restores it to multi-bit parallel data consistent with the pseudo-random binary sequence code data, i.e., deserialized data.

[0068] In this embodiment, the encoded clock signal can be the clock signal output from the last stage of the deserializer 400.

[0069] It should be noted that the deserializer 400 (DESER) used in this embodiment is a multi-stage structure (e.g., 1:2→2:4→4:8). The clock frequency corresponding to each stage is halved, that is, the first stage has the highest clock frequency (corresponding to the serial line rate); while the clock of the last stage is a down-clocked clock, whose frequency is strictly matched with the word rate of the pseudo-random binary sequence code data, so that the subsequent synchronization module 500 can use this encoded clock signal to sample data, thereby ensuring that the setup time and hold time of data sampling meet the requirements.

[0070] The synchronization module 500, connected to the deserializer 400, is used to perform delay compensation on the deserialized data according to the encoding clock signal, and to time-align the delay-compensated data with the pseudo-random binary sequence code data to obtain an aligned data pair. The aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data.

[0071] In this embodiment, since the pseudo-random binary sequence code data has undergone serialization, transmission, and deserialization processes, the received data will inevitably lag behind the originally generated PRBS data on the timeline. This embodiment solves the timing deviation problem of the pseudo-random binary sequence code data after transmission and reception by using the synchronization module 500.

[0072] In this embodiment, the synchronization module 500 uses a delay compensation mechanism to sample the data.

[0073] Specifically, the synchronization module 500 includes a delay selection control circuit that fine-tunes the timing position of the received data by configuring DLY_SEL<1:0> to compensate for the fixed delay caused by the physical link and ensure that the deserialized data and the locally generated PRBS reference data are strictly aligned on the time axis.

[0074] Wherein, since DLY_SEL is 2 bits wide (<1:0>), it means Different states can control a 4-to-1 multiplexer (MUX) to select a path that passes through different levels of D flip-flops (DFFs).

[0075] The mapping relationship between the delay paths corresponding to different states is as follows:

[0076] When the delay selection control signal of DLY_SEL input is 00, the 0th level of delay is selected (e.g.: pass-through or minimum delay, Latency=T0).

[0077] When the input delay selection control signal is 01, the first level of delay is selected (e.g., increase the delay by 1 clock cycle, Latency=T0+1clk).

[0078] When the input delay selection control signal is 10, select the second delay level (e.g., increase the delay by 2 clock cycles, Latency=T0+2clk).

[0079] When the input delay selection control signal is 11, select the 3rd level of delay (for example: increase the delay by 3 clock cycles, Latency=T0+3clk).

[0080] In addition, the synchronization module 500 may also include a configurable-depth FIFO (First-In-First-Out) or flexible buffer. The encoded clock signal extracted by the deserializer 400 is used to write the deserialized data and adjust the read pointer. The synchronization module 500 performs corresponding delay or sliding window operations on the deserialized data. By comparing the feature code of the header, the nth bit of the deserialized data is forcibly aligned in time with the nth bit of the currently output or buffered pseudo-random binary sequence code data to form an aligned data pair; 1≤n≤the highest number of bits of the pseudo-random binary sequence code data, where n is an integer.

[0081] The aforementioned synchronization module 500 can eliminate the phase difference caused by the physical transmission delay of pseudo-random binary sequence code data, avoid false errors caused by timing misalignment, and ensure the logical correctness of BIST testing.

[0082] Comparator 600, connected to synchronization module 500, is used to make logical decisions on the aligned data pairs, obtain multiple logical decision results, and determine whether the built-in self-test of the high-speed interface intellectual property core is successful or unsuccessful through the multiple logical decision results.

[0083] In this embodiment, comparator 600 is used to perform bit-by-bit logical comparison of the aligned data pairs.

[0084] In this embodiment, comparator 600 can be a logic decision circuit; for example, comparator 600 can be an XOR logic circuit, an XNOR logic circuit, a NAND logic circuit, etc.

[0085] In this embodiment, the comparator 600 performs logical judgment on the aligned data pairs respectively, obtains the corresponding logical judgment results, and determines whether the built-in self-test of the high-speed interface intellectual property core IP is successful or unsuccessful according to preset rules.

[0086] In this embodiment, the preset rule can be that if all, partially, or completely aligned data are at a high level, the built-in self-test of the high-speed interface IP is confirmed to be successful; otherwise, the built-in self-test of the high-speed interface IP is determined to have failed.

[0087] The built-in self-test circuit for high-speed interface intellectual property cores provided in this invention generates pseudo-random binary sequence pattern data in BIST mode using a pseudo-random binary sequence generator (PRBS GEN) as the data source for self-testing. A serializer converts the pseudo-random binary sequence pattern data into serial data, and a deserializer deserializes the serial data to obtain deserialized data and an encoded clock signal. This deserialized data is used to simulate signal attenuation or delay information during transmission. A synchronization module then performs delay compensation on the deserialized data based on the encoded clock signal and aligns the time-compensated data with the pseudo-random binary sequence pattern data to obtain aligned data pairs. This eliminates the phase difference caused by the physical transmission delay of the pseudo-random binary sequence pattern data. Finally, a comparator performs logical judgment on the aligned data pairs, and the success or failure of the built-in self-test of the high-speed interface intellectual property core IP is determined by multiple logical judgment results. This circuit has a simple structure, is easy to implement, does not occupy additional convex resources, and improves the efficiency and accuracy of self-testing of high-speed interface IPs in BIST mode.

[0088] Optionally, the signal transceiver unit 300 includes: a transmitter driver 310 connected to the serializer 200; a pad 320 connected to the transmitter driver 310; and a receiver front end 330, with its two ends connected to the pad 320 and the deserializer 400, respectively.

[0089] In this embodiment, the transmit driver 310 (TX Driver) is an analog driving device for the transmit channel, used to receive high-speed serial digital signals (logic levels) and convert them into analog signals with sufficient current driving capability and a specific voltage swing.

[0090] In this embodiment, the receiver front end 330 (RX FE) is an analog entry point for the receiving channel, used to sense voltage changes on the pad 320 (PAD).

[0091] In this embodiment, PAD is a physical metal contact (such as a bump or wire bond) that electrically connects the internal circuitry of the chip to the external packaging substrate or PCB traces.

[0092] In this embodiment, the signal transceiver unit 300 can be used in a near-end loopback scenario, i.e., the transmit driver 310 (TXDriver) is connected to the receiver front end 330 (RX FE).

[0093] In this embodiment, the signal transceiver unit 300 can also be used in a remote loopback scenario, that is, serial data is output to the PAD outside the chip via the TXDriver, and then the PAD transfers the serial data back to the RX input terminal.

[0094] The built-in self-test circuit for high-speed interface intellectual property core provided in this embodiment of the invention, by setting the signal transceiver unit 300 to include a transmitter driver 310, a pad 320 and a receiver front end 330, can be applied to remote loopback scenarios and can truly reflect the communication capability of the chip in the physical world after packaging, achieving full-coverage test effect.

[0095] Furthermore, the synchronization module 500 includes multiple synchronization units, the number of which is related to the number of bits in the pseudo-random binary sequence code data.

[0096] In this embodiment, the synchronization module 500 adopts a parallel multi-channel architecture and integrates multiple independent synchronization units. The number of these units is directly related to or mapped to the parallel data bit width (i.e., the number of bits of the pseudo-random binary sequence PRBS code data) generated by the pseudo-random binary sequence generator.

[0097] In this embodiment, the number of synchronization units inside the synchronization module 500 can be the same as the bit width of the parallel data.

[0098] For example, the size of the PRBS code pattern data includes 8 bits, and the number of synchronization units inside the synchronization module 500 is 8. Each synchronization unit processes one bit of aligned deserialized data and the corresponding PRBS code pattern data.

[0099] The built-in self-test circuit for high-speed interface intellectual property core provided in this embodiment of the invention includes multiple synchronization units in the synchronization module 500. The number of synchronization units is related to the number of bits in the pseudo-random binary sequence code data. When performing self-tests on interface IPs with different bit width standards (such as 16-bit, 64-bit, or 128-bit), only the number of synchronization units needs to be increased or decreased, without redesigning the core algorithm, thus improving the scalability of the circuit.

[0100] Furthermore, comparator 600 is a NAND logic circuit.

[0101] In this embodiment, the density of NAND gates in the standard cell library is extremely high, and using NAND logic circuits can effectively reduce the additional area occupied by BIST circuits on the chip.

[0102] In this embodiment, when the aligned data pairs are fed into the NOT logic circuit for decision-making: it is assumed that the received deserialized data bits need to be compared. and local PRBS data bits Whether they match is determined internally by a pre-designed netlist using a set of NAND gates in comparator 600. Logical operations, The result is a logical decision; the specific decision process is as follows:

[0103] when The nth position and When the nth bit is different (i.e., an error occurs, one is 1 and the other is 0), the combined output of this AND-NOT logic circuit is high (Logic'1'), indicating that an error has been detected. When the two are the same, the output is low. The AND-NOT logic circuit sequentially performs logical decisions on each group of data pairs in the aligned data pair to obtain multiple logical decision results.

[0104] The built-in self-test circuit for high-speed interface intellectual property core provided in this embodiment of the invention enables the self-test process of high-speed interface IP by setting comparator 600 as a NAND logic circuit, while reducing the area occupied by comparator 600 and optimizing the size of the built-in self-test circuit.

[0105] Furthermore, comparator 600 is also used to determine that the built-in self-test of the high-speed interface intellectual property core is successful if at least one of the multiple logical decision results passes the self-test.

[0106] In this embodiment, in BIST mode, the system iterates through the output of each configuration. If any configuration passes, the test is successful; if none of them pass, the test fails.

[0107] Specifically, when the comparator 600 outputs multiple parallel logical decision results (e.g. from 8 parallel receive channels) through logical decision, it does not require all results to pass the self-test. Instead, as long as at least one logical decision result passes the self-test, it reports to the system that the built-in self-test of the high-speed interface IP is successfully determined.

[0108] Figure 2 This is a schematic diagram of the structure of the synchronization unit provided by the present invention. Figure 2 In the illustrated embodiment, each synchronization unit can select the delay of the deserialized data by configuring DLY_SEL "<1:0>", receive PRBS pattern data directly generated by PRBS GEN through the DIN_IN interface, receive the encoded clock signal sent by the deserializer through the CLK interface, and receive different bits of the deserialized data through the DOUT_IN interface. The synchronization unit samples, aligns, and performs NAND logic decisions on the different bits of the deserialized data and their corresponding bits of the PRBS pattern data in sequence, and outputs multiple logic decision results through the O_COMP interface. "D" and "Q" are the input and output terminals of the D flip-flop, respectively.

[0109] Figure 3 This is the second schematic diagram of the built-in self-test circuit for the high-speed interface intellectual property core provided by this invention. Figure 3 In the illustrated embodiment, the workflow of the built-in self-test circuit includes:

[0110] (1) Set the BIST mode of "PRBS GEN" through the register "BIST_EN", 1'b1=bist mode, 1'b0=normal mode; DATA_IN<7:0> on "PRBS GEN" are signal input bits with a bit width of 8;

[0111] (2) PRBS GEN generates 8-bit parallel data (corresponding to DATA) through noise. <0> To DATA <7> The data is sent to the SER (serializer), which then sends the serial data to the TX DRV (transmit driver) and finally to the PAD (pad / pin).

[0112] (3) The RX FE (receiver front end) receives the PAD signal and sends it to the DESER (deserializer). The DESER sends the last stage clock signal (corresponding to CLK) and the 8-bit parallel signal (corresponding to DOUT) used for decoding. <0> To DOUT <7> ( ) are sent together to the synchronization module;

[0113] (4) The synchronization module consists of 8 Sync unit circuits (i.e., Sync unit X8), which can select the delay from input data to output data. First, the encoding clock signal CLK output by DESER is used to sample the deserialization signal of the input synchronization module, and the sampled data bits are time-aligned with the data bits of the original PRBS code pattern data to obtain 8 sets of aligned data pairs (corresponding to O_COMP). <0> To O_COMP <7> );

[0114] (5) The 8 sets of aligned data output by the synchronization module are input to the logic NAND (corresponding to the comparator Checker) for logic decision, and multiple logic decision results are obtained. If there is a logic decision result that passes the test, then O_PASS=1'b1; if the test fails, then O_PASS=1'b0.

[0115] The built-in self-test circuit for high-speed interface IP cores provided in this embodiment of the invention determines that the built-in self-test of the high-speed interface IP is successful when at least one of the multiple logical decision results passes the self-test by using a comparator. This improves the self-test efficiency and avoids the system misjudging the entire IP core as completely unusable due to individual physical link problems.

[0116] The built-in self-test method provided by this invention is described below. The built-in self-test method described below can be referred to in correspondence with the built-in self-test circuit for high-speed interface intellectual property core described above.

[0117] Figure 4 This is a flowchart illustrating the built-in self-test method provided by the present invention, as shown below. Figure 4 As shown, this built-in self-test method includes the following steps:

[0118] Step 410: In the built-in self-test mode, generate pseudo-random binary sequence code data. The pseudo-random binary sequence code data is multi-bit parallel data.

[0119] In this step, pseudo-random binary sequence PRBS code pattern data is generated in BIST mode using the pseudo-random binary sequence generator PRBS GEN.

[0120] In this embodiment, a pseudo-random binary sequence generator is used to generate a data stream with statistically random characteristics, namely PRBS code pattern data, when the BIST (Built-in Self-Test) mode is activated.

[0121] In this embodiment, the PRBS GEN contains a control module (or configuration register group), and the corresponding control bits include the BIST enable register (BIST_EN). When BIST_EN=0 (invalid / default state), it indicates that the chip is in "normal function mode (Mission Mode)"; when BIST_EN=1 (valid / set state), it indicates that the chip has entered "built-in self-test mode (BISTMode)".

[0122] In this embodiment, PRBS GEN can obtain the corresponding PRBS code pattern data using noise or a logic-based approach.

[0123] For example, thermal noise or Zener diode breakdown noise can be used as a physical entropy source, amplified and sampled to generate a true random number seed, and then PRBS code data can be generated from it.

[0124] This embodiment can also use a linear feedback shift register structure to perform shift and XOR operations through a preset polynomial to generate a pseudo-random sequence with an extremely long cycle period (such as PRBS7, PRBS31, etc.), thereby obtaining PRBS code data.

[0125] In this embodiment, in a high-speed testing scenario, PRBS GEN generates a set of parallel data of arbitrary bit width, which includes long strings of "0", long strings of "1" and high-frequency hopping patterns to simulate an extremely harsh data transmission environment.

[0126] Step 420: Convert the pseudo-random binary sequence code data into serial data;

[0127] In this step, the PRBS pattern data is converted into serial data by a serializer, which is connected to PRBSGEN.

[0128] In this embodiment, the serializer is used to perform a parallel-to-serial (P2S) conversion function, which can convert the low-speed, wide-bit-width parallel data generated by PRBS GEN into a high-speed, single-bit serial data stream.

[0129] For example, the serializer receives 32-bit parallel data from PRBS GEN and, driven by an internal high-frequency clock, converts it into a differential serial signal according to the timing sequence.

[0130] It should be noted that when the built-in self-test procedure is implemented in the replica circuit, the serializer can be a 1:1 physical copy of the master serializer, ensuring that its electrical characteristics (such as setup time and hold time) are completely consistent with the actual circuit.

[0131] In some embodiments, serial data is forwarded via a signal transceiver unit, which is connected to the serializer.

[0132] In this embodiment, the signal transceiver unit can be used in near-end loopback scenarios, that is, the transmitting end of the signal transceiver unit is connected to the receiving end of the signal transceiver unit, and the serial data output by the transmitting end is directly forwarded to the receiving end inside the chip without passing through external pins, which is used to quickly verify the basic functions of digital logic and analog front end.

[0133] In this embodiment, the above-mentioned signal transceiver unit constructs a complete signal transmission closed loop, enabling the test to cover the analog driving capability, receiving sensitivity, and signal attenuation along the transmission path, without relying on the probes of external test instruments.

[0134] Step 430: Deserialize the serial data to obtain deserialized data and encoded clock signal.

[0135] In this step, the serial data is deserialized using a deserializer to obtain deserialized data and an encoded clock signal. The deserializer is connected to the signal transceiver unit.

[0136] In this embodiment, the deserializer performs the serial-to-parallel (S2P) conversion function, which is the reverse process of the serializer performing the function.

[0137] In this embodiment, when the signal transceiver unit sends serial data that has passed through a loop (which may be accompanied by jitter or attenuation), the deserializer first extracts the synchronization clock (i.e., the encoded clock signal) from the data stream, uses the clock to sample the high-speed data, and restores it to multi-bit parallel data consistent with the PRBS code pattern data, i.e., deserialized data.

[0138] In this embodiment, the encoded clock signal can be the clock signal output from the last stage of the deserializer.

[0139] It should be noted that the deserializer (DESER) used in this embodiment is a multi-stage structure (e.g., 1:2→2:4→4:8). The clock frequency corresponding to each stage is halved, that is, the first stage has the highest clock frequency (corresponding to the serial line rate); while the clock of the last stage is the down-clocked clock, whose frequency is strictly matched with the word rate of the PRBS code data, so that the subsequent synchronization module can use this encoded clock signal to sample data, thereby ensuring that the setup time and hold time of data sampling meet the requirements.

[0140] Step 440: Perform delay compensation on the deserialized data according to the encoding clock signal, and time-align the delay-compensated data with the pseudo-random binary sequence code data to obtain an aligned data pair. The aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data.

[0141] In this step, the synchronization module performs delay compensation on the deserialized data according to the encoding clock signal, and aligns the delay-compensated data with the PRBS code pattern data in time to obtain an aligned data pair. The synchronization module is connected to the deserializer.

[0142] In this embodiment, since the PRBS code pattern data has undergone serialization, transmission, and deserialization, the received data will inevitably lag behind the originally generated PRBS data on the timeline. This embodiment solves the timing deviation problem of the PRBS code pattern data after transmission and reception by using a synchronization module.

[0143] In this embodiment, the synchronization module uses a delay compensation mechanism to sample the data.

[0144] Specifically, the synchronization module includes a delay selection control circuit that fine-tunes the timing position of the received data by configuring DLY_SEL<1:0> to compensate for the fixed delay caused by the physical link and ensure that the deserialized data and the locally generated PRBS reference data are strictly aligned on the time axis.

[0145] Wherein, since DLY_SEL is 2 bits wide (<1:0>), it means Different states can control a 4-to-1 multiplexer (MUX) to select a path that passes through different levels of D flip-flops (DFFs).

[0146] The mapping relationship between the delay paths corresponding to different states is as follows:

[0147] When the delay selection control signal of DLY_SEL input is 00, the 0th level of delay is selected (e.g.: pass-through or minimum delay, Latency=T0).

[0148] When the input delay selection control signal is 01, the first level of delay is selected (e.g., increase the delay by 1 clock cycle, Latency=T0+1clk).

[0149] When the input delay selection control signal is 10, select the second delay level (e.g., increase the delay by 2 clock cycles, Latency=T0+2clk).

[0150] When the input delay selection control signal is 11, select the 3rd level of delay (for example: increase the delay by 3 clock cycles, Latency=T0+3clk).

[0151] In addition, the synchronization module may also include a configurable-depth FIFO (First-In-First-Out) or flexible buffer. The encoded clock signal extracted by the deserializer is used to write the deserialized data and the read pointer is adjusted. The synchronization module performs corresponding delay or sliding window operations on the deserialized data. By comparing the feature code of the header, the nth bit of the deserialized data is forcibly aligned in time with the nth bit of the currently output or buffered PRBS code data to form an aligned data pair; 1≤n≤the highest number of bits of the PRBS code data, where n is an integer.

[0152] The aforementioned synchronization module can eliminate the phase difference caused by the physical transmission delay of PRBS code data, avoid false errors caused by timing misalignment, and ensure the logical correctness of BIST testing.

[0153] Step 450: Perform logical judgment on the aligned data pairs to obtain multiple logical judgment results, and determine whether the built-in self-test of the high-speed interface intellectual property core is successful or unsuccessful through multiple logical judgment results.

[0154] In this step, the comparator performs logical judgment on the aligned data pairs to obtain multiple logical judgment results, and determines whether the built-in self-test of the high-speed interface IP is successful or unsuccessful based on the multiple logical judgment results; the comparator is connected to the synchronization module.

[0155] In this embodiment, the comparator is used to perform a bit-by-bit logical comparison of the aligned data pairs.

[0156] In this embodiment, the comparator can be a logic decision circuit; for example, the comparator can be an XOR logic circuit, an XNOR logic circuit, a NAND logic circuit, etc.

[0157] In this embodiment, the comparator performs logical judgment on the aligned data pairs respectively, obtains the corresponding logical judgment results, and determines whether the built-in self-test of the high-speed interface IP is successful or unsuccessful according to preset rules.

[0158] In this embodiment, the preset rule can be that if all, partially, or completely aligned data are at a high level, the built-in self-test of the high-speed interface IP is confirmed to be successful; otherwise, the built-in self-test of the high-speed interface IP is determined to have failed.

[0159] The built-in self-test method provided in this invention generates pseudo-random binary sequence pattern data in BIST mode using a pseudo-random binary sequence generator (PRBS GEN) as the data source for self-test. A serializer converts the pseudo-random binary sequence pattern data into serial data, and a deserializer deserializes the serial data to obtain deserialized data and an encoded clock signal. This deserialized data is used to simulate signal attenuation or delay information during transmission. A synchronization module then performs delay compensation on the deserialized data based on the encoded clock signal and aligns the time-compensated data with the pseudo-random binary sequence pattern data to obtain aligned data pairs. This eliminates the phase difference caused by the physical transmission delay of the pseudo-random binary sequence pattern data. Finally, a comparator performs logical judgment on the aligned data pairs, and the success or failure of the built-in self-test of the high-speed interface IP is determined by multiple logical judgment results. This circuit structure is simple, easy to implement, and does not occupy additional convex resources, improving the efficiency and accuracy of self-testing of high-speed interface IP in BIST mode.

[0160] In some embodiments, after converting pseudo-random binary sequence code data into serial data and before deserializing the serial data, the method further includes: transmitting the serial data to the pad and receiving the serial data transmitted by the pad.

[0161] In this embodiment, serial data is transmitted to the pad PAD via a transmit driver (TX Driver), and the serial data transmitted by the PAD is received via a receiver front end (RX FE).

[0162] In this embodiment, the signal transceiver unit can be used in a near-end loopback scenario, i.e., the transmit driver (TX Driver) is connected to the receiver front end (RX FE).

[0163] In this embodiment, the signal transceiver unit can also be used in a remote loopback scenario, where serial data is output to the external pad PAD via the TXDriver, and then the PAD transfers the serial data back to the RX input.

[0164] The built-in self-test method provided in this embodiment of the invention transmits serial data to the PAD through the transmit driver, and the RX FE receives the serial data sent by the PAD. Applied to remote loopback scenarios, it can truly reflect the communication capability of the chip in the physical world after packaging, and achieve a "full coverage" test effect.

[0165] In some embodiments, performing logical decisions on aligned data pairs to obtain multiple logical decision results includes: performing decisions on data pairs aligned with NOT logic circuit pairs to obtain multiple logical decision results; determining whether the built-in self-test of the high-speed interface intellectual property core is successful or unsuccessful through multiple logical decision results includes: determining that the built-in self-test of the high-speed interface intellectual property core is successful if at least one logical decision result among the multiple logical decision results passes the self-test.

[0166] In this embodiment, the density of NAND gates in the standard cell library is extremely high, and using NAND logic circuits can effectively reduce the additional area occupied by BIST circuits on the chip.

[0167] In this embodiment, when the aligned data pairs are fed into the NOT logic circuit for decision-making: it is assumed that the received deserialized data bits need to be compared. and local PRBS data bits Whether they match is determined internally by the comparator using a pre-designed netlist and a set of NAND gates. The logical operations and decision-making process are as follows:

[0168] when The nth position and When the nth bit is different (i.e., an error occurs, one is 1 and the other is 0), the combined output of this AND-NOT logic circuit is high (Logic'1'), indicating that an error has been detected. When the two are the same, the output is low. The AND-NOT logic circuit sequentially performs logical decisions on each group of data pairs in the aligned data pair to obtain multiple logical decision results.

[0169] In this embodiment, in BIST mode, the system iterates through the output of each configuration. If any configuration passes, the test is successful; if none of them pass, the test fails.

[0170] Specifically, when the comparator outputs multiple parallel logical decision results (e.g. from 8 parallel receive channels) through logical decision, it does not require all results to pass the self-test. Instead, as long as at least one logical decision result passes the self-test, it reports to the system that the built-in self-test of the high-speed interface IP is considered successful.

[0171] The built-in self-test method provided in this embodiment of the invention enables the self-testing process of high-speed interface IP by setting the comparator as a NAND logic circuit, while reducing the area occupied by the comparator and optimizing the size of the built-in self-test circuit. By determining that the built-in self-test of the high-speed interface IP is successful when at least one of the multiple logic decision results of the comparator passes the self-test, the self-testing efficiency is improved, and the system avoids misjudging the complete failure of the IP core due to individual physical link problems.

[0172] The present invention also provides a chip comprising: a built-in self-test circuit for a high-speed interface intellectual property core.

[0173] In this embodiment, the chip can be any one of a CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose Graphics Processing Unit).

[0174] It should be noted that the built-in self-test circuit of the high-speed interface intellectual property core mentioned in this embodiment is completely consistent with the built-in self-test circuit and built-in self-test method mentioned above, and will not be repeated in this embodiment.

[0175] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5 As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communications bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other through the communications bus 540. The processor 510 can call logic instructions in the memory 530 to execute a built-in self-test method, which includes: generating pseudo-random binary sequence code data in the built-in self-test mode, wherein the pseudo-random binary sequence code data is multi-bit parallel data; converting the pseudo-random binary sequence code data into serial data; deserializing the serial data to obtain deserialized data and an encoded clock signal; performing delay compensation on the deserialized data according to the encoded clock signal, and aligning the delay-compensated data with the pseudo-random binary sequence code data in time to obtain an aligned data pair, wherein the aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data; performing logical decision on the aligned data pair to obtain multiple logical decision results, and determining whether the built-in self-test of the high-speed interface intellectual property core is successful or unsuccessful through the multiple logical decision results.

[0176] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0177] On the other hand, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the built-in self-test methods provided by the above methods. The method includes: generating pseudo-random binary sequence code data in a built-in self-test mode, wherein the pseudo-random binary sequence code data is multi-bit parallel data; converting the pseudo-random binary sequence code data into serial data; deserializing the serial data to obtain deserialized data and an encoded clock signal; performing delay compensation on the deserialized data according to the encoded clock signal, and aligning the delay-compensated data with the pseudo-random binary sequence code data in time to obtain an aligned data pair, wherein the aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data; performing logical decision on the aligned data pair to obtain multiple logical decision results, and determining whether the built-in self-test of the high-speed interface intellectual property core is successful or unsuccessful through the multiple logical decision results.

[0178] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0179] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A built-in self-test circuit for a high-speed interface intellectual property core, characterized in that, include: A pseudo-random binary sequence generator is used to generate pseudo-random binary sequences in a built-in self-test mode, wherein the pseudo-random binary sequences are multi-bit parallel data. A serializer, connected to the pseudo-random binary sequence generator, is used to convert the pseudo-random binary sequence into serial data; A signal transceiver unit, connected to the serializer, is used to forward the serial data; A deserializer, connected to the signal transceiver unit, is used to deserialize the serial data to obtain deserialized data and an encoded clock signal. A synchronization module, connected to the deserializer, is used to perform delay compensation on the deserialized data according to the encoded clock signal, and to time-align the delay-compensated data with the pseudo-random binary sequence code data to obtain an aligned data pair, wherein the aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data. The synchronization module includes a delay selection control circuit; the delay selection control circuit is used to fine-tune the timing position of the received data by controlling the multiplexer to compensate for the fixed delay caused by the physical link; the multiplexer is used to select the path that passes through D flip-flops of different levels; A comparator, connected to the synchronization module, is used to make logical decisions on the aligned data pairs, obtain multiple logical decision results, and determine whether the built-in self-test of the high-speed interface intellectual property core is successful or unsuccessful based on the multiple logical decision results.

2. The built-in self-test circuit for a high-speed interface intellectual property core according to claim 1, characterized in that, The signal transceiver unit includes: A transmitter driver is connected to the serializer; The pads are connected to the transmit driver; The receiver front end is connected to the pads and the deserializer at both ends, respectively.

3. The built-in self-test circuit for a high-speed interface intellectual property core according to claim 1, characterized in that, The synchronization module includes multiple synchronization units, the number of which is related to the number of bits in the pseudo-random binary sequence code data.

4. The built-in self-test circuit for a high-speed interface intellectual property core according to claim 1, characterized in that, The comparator is a NAND logic circuit.

5. The built-in self-test circuit for a high-speed interface intellectual property core according to claim 1 or 4, characterized in that, The comparator is also used for: If at least one of the multiple logical decision results passes the self-test, the built-in self-test of the high-speed interface intellectual property core is determined to be successful.

6. A built-in self-test method, characterized in that, include: In the built-in self-test mode, pseudo-random binary sequence code data is generated, and the pseudo-random binary sequence code data is multi-bit parallel data. Convert the pseudo-random binary sequence code data into serial data; The serial data is deserialized to obtain deserialized data and an encoded clock signal; The deserialized data is delayed and compensated according to the encoded clock signal, and the delayed and compensated data is time-aligned with the pseudo-random binary sequence code data to obtain an aligned data pair. The aligned data pair includes the aligned deserialized data and the corresponding pseudo-random binary sequence code data. The method further includes: The delay selection control circuit uses a multiplexer to fine-tune the timing of received data in order to compensate for the fixed delay caused by the physical link; the multiplexer is used to select the path that passes through D flip-flops of different levels. Logical decisions are made on the aligned data pairs to obtain multiple logical decision results, and the success or failure of the built-in self-test of the high-speed interface intellectual property core is determined by the multiple logical decision results.

7. The built-in self-test method according to claim 6, characterized in that, After converting the pseudo-random binary sequence code data into serial data, and before deserializing the serial data, the method further includes: The serial data is transmitted to the pads, and the serial data transmitted by the pads is received.

8. The built-in self-test method according to claim 6, characterized in that, The step of performing a logical decision on the aligned data pairs to obtain the logical decision result includes: Based on the AND-NOT logic circuitry, multiple logic decision results are obtained by making decisions on the aligned data pairs. The process of determining the success or failure of the built-in self-test of the high-speed interface intellectual property core through the multiple logical decision results includes: If at least one of the multiple logical decision results passes the self-test, the built-in self-test of the high-speed interface intellectual property core is determined to be successful.

9. A chip, characterized in that, include: The built-in self-test circuit for a high-speed interface intellectual property core as described in any one of claims 1-5.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the built-in self-test method as described in any one of claims 6 to 8.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the built-in self-test method as described in any one of claims 6 to 8.

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