Manufacturing method of silicon-based gallium nitride device and silicon-based gallium nitride device
By building an annular stress compensation layer on the edge of the gallium nitride epitaxial layer of the silicon-based gallium nitride device, the crack propagation problem caused by lattice mismatch is solved, and the device manufacturing yield and reliability are improved.
Patent Information
- Application Number
- CN202510671876.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-23
- Publication Date
- 2025-08-26
AI Technical Summary
In the high voltage platform of existing silicon-based gallium nitride devices, the thick epitaxial layer causes high residual tension stress due to the lattice or thermal mismatch between the III-N material and the silicon substrate, causing cracks to expand from the edge to the center during wafer storage, reducing the effective chip area and causing yield loss.
An annular stress compensation layer is built in the edge area of the gallium nitride epitaxial layer. By depositing stress compensation materials such as indium aluminum gallium nitrogen, the residual tension stress caused by thickening of the epitaxial layer is offset and cracks are prevented from spreading to the center.
It effectively suppresses the spread of cracks, maintains the integrity of the effective wafer area, and improves the manufacturing yield of high-voltage devices.
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Figure CN120545174A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a silicon-based gallium nitride device and a silicon-based gallium nitride device. Background Art
[0002] Currently, silicon-based GaN devices have achieved large-scale application. Their epitaxial layers typically consist of an AlN (aluminum nitride) buffer layer, a carbon-doped superlattice layer, a carbon-doped GaN layer, a channel layer, and a barrier layer. The AlN buffer layer, the carbon-doped superlattice layer, and the carbon-doped GaN layer serve as the core structure for vertical withstand voltage. The AlN buffer layer mitigates lattice mismatch, the carbon-doped superlattice layer disperses stress, and the carbon-doped GaN layer achieves high resistance, all contributing to device reliability.
[0003] However, to meet the needs of higher voltage platforms, the thickness of the epitaxial layer needs to be increased (mainly by thickening the carbon-doped superlattice layer and the carbon-doped gallium nitride layer). Although the initial edge cracks can be controlled within a controllable range through stress engineering technology after the epitaxial growth is completed, as the wafer is stored in the Fab (Fabrication, wafer factory) environment for a longer time, the cracks will expand to the center area (such as Figure 1 This phenomenon is closely related to the significant accumulation of residual stress in thick epitaxial layers: III-N (III-nitride) materials such as AlN, AlGaN (aluminum gallium nitride), and GaN (gallium nitride) have large lattice and thermal stress mismatches with the silicon substrate, resulting in high tensile stress in the epitaxial layer. Increased thickness leads to nonlinear stress accumulation, and crack propagation becomes the primary pathway for residual stress release, ultimately reducing the wafer's effective usable area (center radius) and yield.
[0004] Therefore, how to achieve high-voltage tolerance of the epitaxial layer while suppressing crack expansion has become a technical problem that needs to be urgently solved in the industrialization of high-voltage platform silicon-based gallium nitride technology. Summary of the Invention
[0005] The present application aims to provide a method for manufacturing a silicon-based gallium nitride device and a silicon-based gallium nitride device to address the technical problem in existing silicon-based gallium nitride devices whereby high residual tensile stress is generated in thick epitaxial layers due to lattice or thermal mismatch between the III-N material and the silicon substrate, resulting in cracks that propagate from the edge to the center over time during wafer storage, reducing the effective chip area and causing yield loss.
[0006] In order to achieve the above objectives, this application provides the following technical solutions:
[0007] In a first aspect, an embodiment of the present application provides a method for manufacturing a silicon-based gallium nitride device, the method comprising:
[0008] forming a gallium nitride epitaxial layer on a silicon substrate;
[0009] depositing a protective layer on the gallium nitride epitaxial layer;
[0010] patterning the protective layer to form a protective layer pattern, wherein the protective layer pattern is located in a central region of the gallium nitride epitaxial layer and exposes an edge region of the gallium nitride epitaxial layer;
[0011] Depositing a stress compensation layer; wherein the stress compensation layer is annular, located in the edge region of the gallium nitride epitaxial layer, and directly contacts the surface of the edge region of the gallium nitride epitaxial layer;
[0012] The protective layer pattern is removed.
[0013] Optionally, patterning the protective layer to form a protective layer pattern includes:
[0014] forming a photoresist layer on the protective layer;
[0015] exposing and developing the photoresist layer using a mask to form a photoresist pattern, wherein the photoresist pattern covers a central area of the protective layer and exposes an edge area of the protective layer;
[0016] Using the photoresist pattern as protection, etching away the edge region of the protective layer to expose the edge region of the gallium nitride epitaxial layer;
[0017] The photoresist pattern is removed to expose the central area of the protection layer to form the protection layer pattern.
[0018] Optionally, the material of the protective layer is silicon dioxide.
[0019] Optionally, the material of the stress compensation layer is: indium aluminum gallium nitride.
[0020] Optionally, the protective layer is a circle with a radius of a preset threshold, the range of the central area is: a circle with the center of the protective layer as the center and a radius within a preset range, the right endpoint of the preset range is less than the preset threshold, and the range of the edge area is: a circular ring excluding the central area.
[0021] Optionally, forming a gallium nitride epitaxial layer on a silicon substrate includes:
[0022] A gallium nitride epitaxial layer is formed on the silicon substrate by metal organic chemical vapor deposition, and the thickness of the gallium nitride epitaxial layer is between 5.0 and 20.0 μm.
[0023] Optionally, depositing the stress compensation layer includes:
[0024] The stress compensation layer is deposited by physical vapor deposition or chemical vapor deposition.
[0025] Optionally, depositing a protective layer on the gallium nitride epitaxial layer includes:
[0026] A protective layer is deposited on the gallium nitride epitaxial layer through a plasma activation reaction.
[0027] In a second aspect, an embodiment of the present application provides a silicon-based gallium nitride device, comprising:
[0028] Silicon substrate;
[0029] a gallium nitride epitaxial layer located on the silicon substrate;
[0030] A stress compensation layer is located in an edge region of the gallium nitride epitaxial layer, wherein the stress compensation layer is annular and directly contacts the surface of the edge region of the gallium nitride epitaxial layer.
[0031] Optionally, the material of the stress compensation layer is indium aluminum gallium nitride.
[0032] In summary, by precisely controlling the regional distribution of the protective layer and the stress compensation layer, an annular stress compensation structure is constructed at the edge of the GaN epitaxial layer, which effectively offsets the residual tensile stress caused by the thickening of the epitaxial layer and prevents cracks from extending from the edge of the wafer to the center, thereby maintaining the integrity of the effective area of the wafer and improving the manufacturing yield of high-voltage devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] When with Figure 1 When reading the following detailed description, various aspects of the present application can be easily understood based on the following detailed description. It is prudent that various features may not be drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for the sake of clarity of discussion.
[0034] Figure 1 This is a schematic diagram of a crack extending toward a central region when the thickness of the GaN epitaxial layer increases in an existing GaN-on-silicon device provided in an embodiment of the present application;
[0035] Figure 2 A flowchart of a method for manufacturing a silicon-based gallium nitride device provided in an embodiment of the present application;
[0036] Figure 3 A flowchart of a method for manufacturing a silicon-based gallium nitride device provided in an embodiment of the present application;
[0037] Figure 4 A top view of an embodiment of the present application showing a method of immediately growing a layer of indium aluminum gallium nitride on a 5.0-20.0 μm thick wafer that has just finished growing silicon-based gallium nitride, to inhibit cracks from extending toward the center of the wafer.
[0038] Figure 5 A flowchart of a top view of a silicon-based gallium nitride device in a method for manufacturing a silicon-based gallium nitride device provided in an embodiment of the present application;
[0039] Figure 6 A top view of a silicon-based gallium nitride device provided in an embodiment of the present application;
[0040] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. The present application will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION
[0041] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be restrictive. In this application, reference to a first feature being formed or set above or above a second feature may include an embodiment in which the first feature and the second feature are formed or set to be in direct contact, and may also include an embodiment in which additional features may be formed or set between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the application may repeat reference numerals and / or letters in each instance. This repetition is for simplicity and clarity purposes and is not intended to limit the relationship between the various embodiments and / or configurations discussed.
[0042] Figure 2 A method for manufacturing a silicon-based gallium nitride device according to an embodiment of the present application is shown. Figure 2 As shown, the method includes:
[0043] Step S101, forming a gallium nitride epitaxial layer on a silicon substrate;
[0044] Step S102: depositing a protective layer on the gallium nitride epitaxial layer;
[0045] Step S103: patterning the protective layer to form a protective layer pattern;
[0046] The protective layer pattern is located in the central area of the gallium nitride epitaxial layer, exposing the edge area of the gallium nitride epitaxial layer;
[0047] Step S104: depositing a stress compensation layer;
[0048] The stress compensation layer is annular and is located in the edge region of the gallium nitride epitaxial layer and is in direct contact with the surface of the edge region of the gallium nitride epitaxial layer;
[0049] Step S105: removing the protective layer pattern.
[0050] It should be noted that a GaN epitaxial layer is first formed on a silicon substrate (the GaN epitaxial layer can be formed on the silicon substrate through metal organic chemical vapor deposition, and the thickness of the GaN epitaxial layer is between 5.0 and 20.0 μm). A protective layer is then deposited on its surface (the protective layer can be deposited on the GaN epitaxial layer through a plasma-activated reaction). The protective layer is patterned through photolithography and etching processes so that it only covers the central area of the GaN epitaxial layer, while exposing the edge areas. A stress compensation layer is then directly deposited on the surface of the exposed edge areas, and the protective layer pattern is finally removed. The stress compensation layer has an annular structure and is in direct contact with the edge surface of the GaN epitaxial layer, similar to applying a layer of tape over a crack. Its inherent stress properties can suppress crack propagation caused by residual stress in the epitaxial layer.
[0051] In one possible implementation, Figure 3 As shown, step S103, patterning the protective layer to form a protective layer pattern includes:
[0052] Step S1031, forming a photoresist layer on the protective layer;
[0053] Step S1032: exposing and developing the photoresist layer using a mask to form a photoresist pattern;
[0054] The photoresist pattern covers the central area of the protective layer and exposes the edge area of the protective layer;
[0055] Step S1033: Using the photoresist pattern as protection, etching away the edge area of the protective layer to expose the edge area of the gallium nitride epitaxial layer;
[0056] Step S1034: remove the photoresist pattern to expose the central area of the protection layer to form a protection layer pattern.
[0057] It should be noted that in Figure 3In the method shown, the process of patterning the protective layer to form a protective layer pattern involves precise control of the photolithography process. Specifically, a layer of photoresist is first evenly coated on the surface of the protective layer, and then the photoresist is selectively exposed using a mask. The design of the mask allows the central area of the photoresist to be protected (i.e., not exposed), while the edge area is irradiated with ultraviolet light. After development, the unexposed edge area of the photoresist is dissolved and removed, thereby forming a photoresist pattern on the protective layer, and the pattern covers the central area of the protective layer while completely exposing the edge area of the protective layer. Next, using the photoresist pattern as a protective layer, the exposed edge area of the protective layer is completely removed through an etching process, so that the edge area of the gallium nitride epitaxial layer below is directly exposed. Finally, the remaining photoresist pattern is removed by chemical or physical methods, and finally a complete protective layer pattern is formed on the surface of the gallium nitride epitaxial layer: the original protective layer is retained in the central area, and the edge area is not covered by the protective layer.
[0058] Thus, through photolithography and etching techniques, the distribution area of the protective layer on the wafer can be precisely defined (retained in the center, removed at the edges). Its core function is to provide spatial selectivity for subsequent processes: it protects the epitaxial layer in the center from subsequent processing, while providing an exposed surface for deposition of the stress compensation layer in the edge areas, ensuring direct bonding of the stress compensation material to the edge of the epitaxial layer. This operation is the basis for constructing a ring-shaped stress compensation structure.
[0059] In a possible implementation, the material of the protective layer is silicon dioxide.
[0060] It should be noted that the protective layer can be made of silicon dioxide. Due to the significant difference in etching rates between silicon dioxide and gallium nitride epitaxial layers (for example, when using a hydrofluoric acid-based etchant, the etching rate of silicon dioxide is much higher than that of gallium nitride), the etching boundary can be precisely controlled to ensure that only the edge area of the epitaxial layer is exposed. After the photoresist pattern is subsequently removed, the silicon dioxide protective layer in the central area remains intact, providing a foundation for the subsequent selective deposition of the stress compensation layer.
[0061] Silicon dioxide is selected as the protective layer material because its etching process is mature and compatible with the gallium nitride epitaxial layer. It can accurately achieve the graphical requirements of protecting the central area and exposing the edge area. The high etching selectivity and stability of silicon dioxide can effectively prevent accidental damage to the underlying gallium nitride epitaxial layer, ensure process reliability, and provide support for the reliable bonding of the subsequent edge area stress compensation layer, ultimately improving the device yield and crack propagation resistance.
[0062] In one possible implementation, the protective layer is a circle with a radius of a preset threshold, the range of the central area is: a circle with the center of the protective layer as the center and a radius within the preset range, the right endpoint of the preset range is less than the preset threshold, and the range of the edge area is: a circular ring excluding the central area.
[0063] Exemplarily, the protective layer may be a circle with a radius of 100 mm, and the range of the central area is: a circle with a radius of 90 mm to 98 mm with the center of the protective layer as the center; the range of the edge area is: a ring excluding the central area; the protective layer may be a circle with a radius of 40 mm, and the range of the central area is: a circle with a radius of 32 mm to 37 mm with the center of the protective layer as the center; the range of the edge area is: a ring excluding the central area; the protective layer may be a circle with a radius of 60 mm, and the range of the central area is: a circle with a radius of 53 mm to 56 mm with the center of the protective layer as the center; the range of the edge area is: a ring excluding the central area; the protective layer may be a circle with a radius of 200 mm, and the range of the central area is: a circle with a radius of 180 mm to 196 mm with the center of the protective layer as the center; the range of the edge area is: a ring excluding the central area.
[0064] Taking a circular structure with a protective layer of 100mm radius as an example, its central area is defined as a circular area with a radius of 95mm and the center of the protective layer as the center, and the edge area is a ring area with a radius of 95mm to 100mm. The protective layer is patterned by photolithography and etching processes, so that the protective layer in the central area (radius 0-95mm) is retained, and the protective layer in the edge area (radius 95-100mm) is completely removed, thereby exposing the edge surface of the underlying GaN epitaxial layer. Subsequently, a stress compensation layer (such as an InAlGaN ring) is deposited, and the protective layer pattern in the central area is removed. Finally, the stress compensation layer is retained only in the edge ring area (radius 95-100mm), forming a ring structure that is in direct contact with the edge of the GaN epitaxial layer.
[0065] As a result, the coverage range (radius 95-100mm) of the stress compensation layer (such as the InAlGaN ring) is fully matched with the "5mm edge removal" rule of the back-end Fab process (that is, the effective area of the chip is a radius of 0-95mm). Since the 5mm edge (radius 95-100mm) area itself is not used for chip manufacturing, the introduction of a stress compensation layer within this range will not occupy the effective chip area, and there is no need to adjust the existing Fab process parameters. It not only utilizes the originally abandoned edge area to achieve crack suppression, but also ensures that the device structure and electrical performance of the central area (0-95mm) are not affected, ultimately improving the overall reliability of the wafer while ensuring the yield.
[0066] And experiments show that if Figure 4 As shown, a layer of indium aluminum gallium nitride is immediately grown on a 5.0-20.0 μm thick wafer that has just finished growing silicon-based gallium nitride, which can inhibit the crack from extending toward the center of the wafer.
[0067] In a possible implementation, the material of the stress compensation layer is: Indium Aluminum Gallium Nitride, and the stress compensation layer pattern is a ring, that is, In x Aly Ga 1-x-y InGaN ring.
[0068] Among them, 0 < x < 1, 0 < y < 1, 0 < 1 - x - y < 1. Exemplarily, In x Al y Ga 1-x-y The width of the InGaN ring is 3 - 5 mm. Among them, the width refers to In x Al y Ga 1-x-y The InGaN ring is along the plane direction of the protective layer, that is, the dimension in the radius direction from the center of the protective layer to the outer periphery, that is, the lateral extension range of the ring. In x Al y Ga 1-x-y The thickness of the InGaN ring is 1 - 7 μm. The thickness refers to the vertical thickness, that is, In x Al y Ga 1-x-y The dimension of the InGaN ring along the direction perpendicular to the surface of the protective layer (axial direction), that is, the stacking height of the material of the stress compensation layer.
[0069] It should be noted that the material of the stress compensation layer is indium aluminum gallium nitride (InAlGaN). This implementation method selects indium aluminum gallium nitride as the material of the stress compensation layer and utilizes its lattice matching with the gallium nitride epitaxial layer and compressive stress characteristics to achieve mechanical property regulation. Compared with selecting other materials as the stress compensation layer, since indium and aluminum elements and gallium element are in the same group, and the atomic radius of gallium element is between the atomic radii of indium element and aluminum element, the indium aluminum gallium nitride stress compensation layer and the gallium nitride epitaxial layer are more crystal - matched, and the lattice mismatch problem is very small. Specifically, the indium aluminum gallium nitride layer covers the exposed edge area of the gallium nitride epitaxial layer through physical vapor deposition (PVD) or chemical vapor deposition (CVD) process, and finally only the indium aluminum gallium nitride ring remains in the edge area. Since the thermal expansion coefficient and lattice constant of indium aluminum gallium nitride can be adjusted by adjusting the ratio of indium (In) and aluminum (Al) elements, its compressive stress characteristics can effectively offset the tensile stress generated by the increase in the thickness of the gallium nitride epitaxial layer, thereby inhibiting crack propagation. At the same time, its high hardness and toughness can directly block the crack propagation path, ultimately improving the structural stability and manufacturing yield of high - voltage devices.Step 1: grow a 5.0-20.0 μm epitaxial layer (such as Figure 5 (shown as gray fill in step 1);
[0073] Step 2: Grow a SiO2 (silicon dioxide) layer (such as Figure 5 (shown by the blue fill in step 2);
[0074] Step 3: Coat a layer of negative photoresist (such as Figure 5 (shown by the orange fill in step 3);
[0075] Step 4: Select the exposure range radius from 0 to 95 mm (e.g. Figure 5 In step 4, the area from the center of the circle to the dotted circle is the exposure range);
[0076] Step 5: Develop, leaving the negative photoresist within the radius of 0 to 95 mm, and remove the negative photoresist within 95 to 100 mm (such as Figure 5 In step 5, the negative photoresist is left at 0-95 mm and the negative photoresist is removed at 95-100 mm, leaving the SiO2 layer.
[0077] Step 6: Wet etching, for example, using a buffered oxide etchant to etch away the 95-100 mm of SiO2 not covered by the negative photoresist (e.g. Figure 5 In step 6, the remaining SiO2 layer is etched away to expose the GaN epitaxial layer);
[0078] Step 7: Use a photoresist remover to remove the negative photoresist, so that SiO2 is left within the radius of 0 to 95 mm and there is no SiO2 within the radius of 95 to 100 mm (such as Figure 5 In step 7, the negative photoresist within a radius of 0 to 95 mm is removed, leaving the SiO2 layer);
[0079] Step 8: Grow an InAlGaN layer on the wafer using PVD (Physical Vapor Deposition) (e.g. Figure 5 (as shown by the purple fill in Step 8).
[0080] Step 9: Use buffered oxide etching solution to remove the SiO2 layer from 0 to 95 mm, so that the InAlGaN ring in the range of 95 to 100 mm can be obtained (InAlGaN ring such as Figure 5As shown by the purple filling in step 9, 0 to 95 mm of the SiO2 layer is removed to expose the GaN epitaxial layer).
[0081] In summary, by precisely controlling the regional distribution of the protective layer and the stress compensation layer, an annular stress compensation structure is constructed at the edge of the GaN epitaxial layer, which effectively offsets the residual tensile stress caused by the thickening of the epitaxial layer and prevents cracks from extending from the edge of the wafer to the center, thereby maintaining the integrity of the effective area of the wafer and improving the manufacturing yield of high-voltage devices.
[0082] Figure 6 A silicon-based gallium nitride device according to an embodiment of the present application is shown. Figure 6 As shown, it includes: a silicon substrate;
[0083] A gallium nitride epitaxial layer 2 located on a silicon substrate;
[0084] A stress compensation layer 1 is located in the edge region of the gallium nitride epitaxial layer 2 , wherein the stress compensation layer 1 is annular and directly contacts the surface of the edge region of the gallium nitride epitaxial layer 2 .
[0085] In a possible implementation, the material of the stress compensation layer 1 is indium aluminum gallium nitride.
[0086] It should be noted that silicon-based gallium nitride devices include three core components: silicon substrate: serves as the supporting substrate of the device, providing mechanical stability and heat conduction path.
[0087] Gallium nitride epitaxial layer 2: Located on the surface of the silicon substrate, it is formed by an epitaxial growth process (such as metal organic chemical vapor deposition) and is used to support the high voltage and withstand voltage function of the device. The total thickness of the epitaxial layer 2 is 5.0 to 20.0 μm, and it includes an aluminum nitride buffer layer, a carbon-doped superlattice layer, and a carbon-doped gallium nitride layer. The high breakdown voltage and stress dispersion are achieved through interlayer synergy.
[0088] Stress compensation layer 1: Located at the edge of the GaN epitaxial layer 2 (e.g., within a wafer radius of 95-100mm), this ring-shaped layer directly contacts the edge of the GaN epitaxial layer 2. This stress compensation layer utilizes the inherent compressive stress properties of the material (e.g., InAlGaN) to offset the tensile stress generated by the increased thickness of the epitaxial layer 2, thereby suppressing crack propagation from the wafer edge toward the center.
[0089] In summary, by introducing an annular stress-compensating layer 1 (e.g., InAlGaN) at the edge of the GaN epitaxial layer 2, its compressive stress offsets the residual tensile stress in the epitaxial layer 2, effectively suppressing crack propagation. Because the stress-compensating layer 1 is located only in the non-chip-active area at the wafer edge (e.g., a radius of 95-100mm), it does not interfere with the usable area (radius 0-95mm) for subsequent fabrication processes such as lithography, etching, and metallization. This ensures high-voltage performance while maintaining device yield.
[0090] The embodiments of the present application have been discussed in detail above. However, it should be understood that the present application provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present application.
[0091] Unless otherwise specified, spatial descriptions such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "above," and "below" are relative to the orientation shown in the drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, with the proviso that the advantages of the embodiments of the present application are not deviated by such arrangements.
[0092] As used herein, the term "vertical" is used to refer to an upward and downward direction, while the term "horizontal" refers to a direction transverse to the vertical direction.
[0093] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, the terms can refer to a range of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first numerical value can be considered "substantially" the same as or equal to a second numerical value if the first numerical value is within a range of less than or equal to ±10% of the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, "substantially" vertical may refer to an angular variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.
[0094] Two surfaces are considered coplanar or substantially coplanar if the displacement between them does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm. Surfaces are considered substantially flat if the displacement between the highest and lowest points of the surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm.
[0095] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise.
[0096] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to carry an electric current. Conductive materials generally refer to those materials that present little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, a conductive material is one having a conductivity greater than about 104 S / m (e.g., at least 105 S / m or at least 106 S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.
[0097] In addition, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It should be understood that such a range format is used for convenience and brevity and should be interpreted flexibly to encompass not only the values explicitly specified as the limits of the range, but also all individual values or sub-ranges encompassed within that range, as if each value and sub-range were explicitly specified.
[0098] Although the present application has been described and illustrated with reference to specific embodiments of the present application, these descriptions and illustrations are not restrictive. Those skilled in the art will understand that various changes may be made and equivalents substituted without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this application and the actual device. There may be other embodiments of the present application that are not specifically described. This description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to make specific circumstances, materials, compositions of matter, methods or processes suitable for the objectives, spirit and scope of the present application. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present application. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of the present application.
Claims
1. A method for manufacturing a silicon-based gallium nitride device, characterized in that: The method comprises: forming a gallium nitride epitaxial layer on a silicon substrate; depositing a protective layer on the gallium nitride epitaxial layer; patterning the protective layer to form a protective layer pattern, wherein the protective layer pattern is located in a central region of the gallium nitride epitaxial layer and exposes an edge region of the gallium nitride epitaxial layer; Depositing a stress compensation layer; wherein the stress compensation layer is annular, located in the edge region of the gallium nitride epitaxial layer, and directly contacts the surface of the edge region of the gallium nitride epitaxial layer; The protective layer pattern is removed.
2. The method according to claim 1, characterized in that Patterning the protective layer to form a protective layer pattern includes: forming a photoresist layer on the protective layer; exposing and developing the photoresist layer using a mask to form a photoresist pattern, wherein the photoresist pattern covers a central area of the protective layer and exposes an edge area of the protective layer; Using the photoresist pattern as protection, etching away the edge region of the protective layer to expose the edge region of the gallium nitride epitaxial layer; The photoresist pattern is removed to expose the central area of the protection layer to form the protection layer pattern.
3. The method according to claim 1, characterized in that The material of the protective layer is silicon dioxide.
4. The method according to claim 1, wherein The material of the stress compensation layer is: indium aluminum gallium nitride.
5. The method according to claim 1, wherein The protective layer is a circle with a radius of a preset threshold, the range of the central area is: a circle with the center of the protective layer as the center and a radius within a preset range, the right endpoint of the preset range is less than the preset threshold, and the range of the edge area is: a circular ring excluding the central area.
6. The method according to claim 1, characterized in that Forming a GaN epitaxial layer on a silicon substrate includes: A gallium nitride epitaxial layer is formed on the silicon substrate by metal organic chemical vapor deposition, and the thickness of the gallium nitride epitaxial layer is between 5.0 and 20.0 μm.
7. The method according to claim 1, characterized in that Depositing a stress compensating layer includes: The stress compensation layer is deposited by physical vapor deposition or chemical vapor deposition.
8. The method according to any one of claims 1 to 7, characterized in that Depositing a protective layer on the gallium nitride epitaxial layer comprises: A protective layer is deposited on the gallium nitride epitaxial layer through a plasma activation reaction.
9. A silicon-based gallium nitride device, characterized in that: include: Silicon substrate; a gallium nitride epitaxial layer located on the silicon substrate; A stress compensation layer is located in an edge region of the gallium nitride epitaxial layer, wherein the stress compensation layer is annular and directly contacts the surface of the edge region of the gallium nitride epitaxial layer.
10. The device according to claim 9, characterized in that The material of the stress compensation layer is indium aluminum gallium nitride.