Detection circuit, charge pump circuit, and non-volatile memory

Abstract

The invention discloses a detection circuit, a charge pump circuit and a nonvolatile memory. The detection circuit comprises a detection module, an anti-phase module and a latch module. Wherein the sampling end of the detection module is coupled to the output end of the charge pump circuit and collects output voltage, and the detection module outputs a detection signal in response to the fact that the output voltage reaches a target voltage value for the first time; the detection signal is related to the load current of the charge pump circuit; the inverting module outputs an inverting signal in response to the fact that the output voltage reaches the target voltage value for the first time; and the latch module latches the detection signal according to the inversion signal, and outputs the detection signal as an output signal of the output end of the latch module, so that the output signal is used as an enable signal to enable the charge pump circuit. By means of the mode, the charge pump circuit can obtain the optimal driving capacity under different loads, and the minimum voltage ripple can be obtained under the condition that the driving requirement is met.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a detection circuit, a charge pump circuit, and a non-volatile memory. Background Art

[0002] A charge pump (PUMP) is a commonly used module in non-volatile memory (NVM) and is used to generate an output voltage VPP higher than the power supply voltage. This output voltage VPP is used to provide appropriate bias or drive when reading and writing the memory.

[0003] Output voltage VPP ripple, a type of voltage noise, can affect module performance. More seriously, ripple can cause the charge pump's output voltage VPP to exceed the target voltage during certain periods. Given that the target voltage is already high, further increases in output voltage VPP can lead to reliability issues, such as exceeding the device's withstand voltage and damaging the chip. Therefore, reducing ripple is a crucial issue in charge pump design. Summary of the Invention

[0004] The detection circuit, charge pump circuit, and non-volatile memory provided in the present application can enable the charge pump circuit to obtain optimal driving capability under different loads and obtain minimum voltage ripple while meeting driving requirements.

[0005] In a first aspect, the present application provides a detection circuit, which includes: a detection module, a sampling end of the detection module coupled to the output end of the charge pump circuit to collect the output voltage, and the detection module outputs a detection signal in response to the output voltage reaching the target voltage value for the first time; the detection signal is related to the load current of the charge pump circuit; an inverting module, an input end of the inverting module coupled to the output end of the feedback module of the charge pump circuit; the inverting module outputs an inverted signal in response to the output voltage reaching the target voltage value for the first time; a latch module, a first input end of the latch module coupled to the output end of the detection module, a second input end of the latch module coupled to the output end of the inverting module, and an output end of the latch module coupled to the input end of the charge pump circuit; wherein the latch module latches the detection signal according to the inverted signal, and outputs the detection signal as the output signal of the output end of the latch module, so that the output signal serves as an enable signal to enable the charge pump circuit.

[0006] Among them, the detection module includes: a capacitor, the upper plate of the capacitor is coupled to the output end of the charge pump circuit as the sampling end of the detection module; a current source, the first end of the current source is coupled to the lower plate of the capacitor, and the second end of the current source is grounded; a comparison unit, the first input end of the comparison unit is coupled to the lower plate of the capacitor, the second input end of the comparison unit is used to couple to the reference voltage end, and the output end of the comparison unit is coupled to the first input end of the latch module as the output end of the detection module.

[0007] In which, the comparison unit maintains the output of a high-level detection signal in response to a decrease in the lower plate voltage of the capacitor; or, in response to an increase in the lower plate voltage of the capacitor, the detection signal output by the comparison unit becomes low; wherein the lower plate voltage is determined by the load current.

[0008] Before the charge pump circuit is enabled, the voltage of the lower plate of the capacitor is equal to the reference voltage.

[0009] In which, the detection module also includes a transistor, the first end of the transistor is coupled to the reference voltage end, and the second end of the transistor is coupled to the lower plate of the capacitor; in which, before the charge pump circuit is enabled, the transistor is turned on, and the voltage of the lower plate of the capacitor is equal to the reference voltage provided by the reference voltage end.

[0010] Among them, the latch module includes: an RS trigger, the set end of the RS trigger is used to receive a set signal, and the reset end of the RS trigger is coupled to the output end of the inverting module; a selection module, the first input end of the selection module is coupled to the output end of the detection module, and the control end of the selection module is used to couple to the output end of the RS trigger; a D trigger, the data end of the D trigger is coupled to the output end of the selection module, the clock input end of the D trigger is coupled to the output end of the inverting module, and the output end of the D trigger is coupled as the output end of the latch module to the input end of the charge pump circuit and the second input end of the selection module.

[0011] Among them, the inversion module inverts the feedback signal output by the feedback module of the charge pump circuit when the output voltage reaches the target voltage value to obtain an inverted signal; the D trigger responds to the inverted signal, receives the detection signal selected and output by the selection module, and outputs the detection signal as the output signal; the RS trigger responds to the inverted signal, outputs a reset signal to the selection module, and the selection module selects and outputs the output signal input by the second input terminal to the data terminal of the D trigger according to the reset signal.

[0012] Among them, before the charge pump circuit is enabled, the D trigger responds to the control signal and outputs the first set signal as the output signal to the charge pump circuit, and the RS trigger responds to the control signal input at the set end and outputs the second set signal to the selection module. The selection module selects the detection signal to be output to the D trigger according to the second set signal.

[0013] In a second aspect, the present application provides a charge pump circuit, which includes the detection circuit provided in the first aspect.

[0014] In a third aspect, the present application provides a non-volatile memory, which includes the detection circuit provided in the first aspect or the charge pump circuit provided in the second aspect.

[0015] The beneficial effects of the present application are as follows: different from the prior art, the detection circuit, charge pump circuit and non-volatile memory provided by the present application output a detection signal related to the load current of the charge pump circuit through the detection module. After the output voltage of the charge pump circuit reaches the target voltage value for the first time, the latch module latches the detection signal according to the inverted signal, and outputs the detection signal as the output signal of the output end of the latch module, so that the output signal serves as an enable signal to enable the charge pump circuit, thereby achieving the purpose of accurately controlling the driving capability of the charge pump circuit according to the load current of the charge pump circuit, thereby enabling the charge pump circuit to obtain the optimal driving capability under different loads and obtain the minimum voltage ripple while meeting the driving requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them: Figure 1 1 is a schematic structural diagram of an embodiment of a charge pump circuit provided by the present application; Figure 2 is a structural diagram of an embodiment of a charge pump unit provided by the present application; Figure 3 yes Figure 1 Schematic diagram of the working timing of the charge pump circuit; Figure 4 is a structural diagram of an embodiment of a detection circuit provided by the present application; Figure 5 This is a schematic structural diagram of an embodiment of a detection module provided by the present application; Figure 6 This is a structural diagram of an embodiment of a latch module provided by the present application; Figure 7 is a structural diagram of another embodiment of the detection circuit provided by the present application; Figure 8 is a structural diagram of another embodiment of the charge pump circuit provided by the present application; Figure 9 This is a schematic diagram of the current threshold division provided by this application; Figure 10 is a structural diagram of another embodiment of the charge pump circuit provided by the present application; Figure 11 yes Figure 10 Schematic diagram of the working timing of the charge pump circuit; Figure 121 is a schematic structural diagram of an embodiment of a non-volatile memory provided by the present application; Figure 13 It is a structural diagram of another embodiment of the non-volatile memory provided by the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0018] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0019] A charge pump (PUMP) is a commonly used module in non-volatile memory (NVM) and is used to generate an output voltage VPP higher than the power supply voltage. This output voltage VPP is used to provide appropriate bias or drive when reading and writing the memory.

[0020] like Figure 1 As shown in the figure, the description of each submodule of the charge pump is as follows: The charge pump unit has a multi-stage series structure. Driven by the clock BUFFER, it outputs a higher voltage by transferring charges between stages. There are various structures of charge pump units, such as Figure 2 The Dickson structure shown.

[0021] Feedback path: It is generally composed of resistors or MOS tubes in series. Here, resistors R1 and R2 are connected in series as an example. It is used to sample the output voltage VPP and generate a feedback voltage VFB proportional to the output. The comparator CMP1 is used to compare the feedback voltage VFB with the reference voltage VREF, output a corresponding comparison result VCTRL, and control, together with the logic gate AND, whether the external clock signal CLK is transmitted to the charge pump unit.

[0022] The clock buffer is a buffer that drives the clock signal and drives the charge transfer between the charge pump unit stages. That is, the clock signal provided by the clock buffer is CLK_BUFFER.

[0023] CL is the decoupling capacitor, RL is the load of the charge pump circuit, and is used to calculate the power consumption of the circuit driven by the equivalent charge pump circuit.

[0024] in, Figure 1 The working process of the charge pump circuit is as follows: The module is enabled, and the initial output voltage VPP is low, generally not exceeding the power supply voltage VCC. After voltage division, the feedback voltage VFB is lower than the reference voltage VREF. The comparator CMP1 outputs a high level, controlling the external clock signal CLK to be output to the charge pump unit through the clock BUFFER.

[0025] Driven by the clock, the charge pump unit transmits the charge step by step, so that the output voltage VPP becomes higher and higher.

[0026] The increase in the output voltage VPP causes the feedback voltage VFB to increase proportionally. When the feedback voltage VFB exceeds the reference voltage VREF, the output voltage VCTRL of the comparator CMP1 becomes low. The control logic closes the path from the external clock signal CLK to the charge pump unit. The charge pump unit is no longer driven, and the output voltage VPP stops increasing. At this time, the voltage value of the output voltage VPP is near VREF*(1+R1 / R2), which is the target voltage value of the output voltage VPP.

[0027] Subsequently, the output voltage VPP decreases proportionally due to the decrease in load current, and the feedback voltage VFB decreases in proportion. When the feedback voltage VFB is lower than the reference voltage VREF, the output of the comparator CMP becomes high again, opening the path of the external clock signal CLK to the charge pump unit, driving the output voltage VPP to increase, until the feedback voltage VFB is higher than the reference voltage VREF again, and then the clock path is closed.

[0028] Throughout the charge pump circuit's operation, the aforementioned process repeats: when the feedback voltage exceeds the reference voltage, the path from the external clock signal CLK to the charge pump unit is closed; and when the feedback voltage falls below the reference voltage, the path from the external clock signal CLK to the charge pump unit is opened. Consequently, the output voltage VPP exhibits slight oscillations around the target voltage. This oscillation is known as output voltage VPP ripple. The root cause lies in the charge pump unit's clock-driven, instantaneous, rather than continuous, output drive current, resulting from switching and hysteresis within the entire control loop.

[0029] Output voltage VPP ripple, a type of voltage noise, can affect module performance. More seriously, ripple can cause the charge pump's output voltage VPP to exceed the target voltage during certain periods. Given that the target voltage is already high, further increases in output voltage VPP can lead to reliability issues, such as exceeding the device's withstand voltage and damaging the chip. Therefore, reducing ripple is a crucial issue in charge pump design.

[0030] Since ripple originates from the way the charge pump unit outputs drive current, under certain conditions, the stronger the charge pump circuit's drive capability, the greater the ripple. To reduce ripple, controlling the charge pump unit's drive capability is a common method. However, this method is limited by load requirements. Specifically, the drive capability must be greater than the load; otherwise, the output voltage VPP will fail to reach the target value. Therefore, to control the drive capability, the load size must be known.

[0031] The inventors of this application have discovered that, in actual applications, the load of the charge pump circuit may vary with the operating mode and external conditions. Without knowing the current load, the charge pump circuit can only ensure that the output voltage VPP reaches the target value by driving the charge pump circuit with a driving capability greater than the maximum load. This results in many cases where the drive of the charge pump circuit is greater than the actual demand, resulting in greater ripple.

[0032] In related PUMP designs, some ripple reduction methods have been adopted, such as dividing the charge pump unit into multiple parallel units and selectively shutting down some of them after the voltage approaches the target value to balance the output voltage VPP settling time and ripple requirements. This method has certain effects, but it has obvious limitations and is only suitable for occasions where the load current is small and fixed. Otherwise, it can easily lead to insufficient drive or excessive ripple.

[0033] The limitation of the above method is that the control signal is generated only by checking the output voltage VPP, which cannot obtain load information. Because as long as the charge pump circuit drive is greater than the load, the output voltage VPP can always reach the target value regardless of the difference between the two.

[0034] Based on this, the present application proposes a detection circuit 100, a charge pump circuit, and a non-volatile memory. A detection module 10 in the detection circuit 100 outputs a detection signal CMP_OUT related to the load current of the charge pump circuit. After the output voltage VPP of the charge pump circuit reaches a target voltage value for the first time, a latch module 30 in the detection circuit 100 latches the detection signal CMP_OUT according to an inverted signal VCTRL_B and outputs the detection signal CMP_OUT as an output signal LOAD_DET at an output terminal of the latch module 30. The output signal LOAD_DET then serves as an enable signal to enable the charge pump circuit, thereby precisely controlling the drive capability of the charge pump circuit according to the load current of the charge pump circuit. This enables the charge pump circuit to achieve optimal drive capability under different loads and minimize voltage ripple while meeting drive requirements. For details, please refer to any of the following embodiments.

[0035] See Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a detection circuit according to an embodiment of the present invention. The detection circuit 100 includes a detection module 10 , an inverting module 20 , and a latch module 30 .

[0036] A sampling terminal of the detection module 10 is coupled to the output terminal of the charge pump circuit to sample the output voltage VPP. In response to the output voltage VPP reaching the target voltage value for the first time, the detection module 10 outputs a detection signal CMP_OUT. In some embodiments, the voltage value of the detection signal CMP_OUT is related to the load current of the charge pump circuit. As the output voltage VPP of the charge pump circuit rises to the target voltage value, if the load current is low, the output voltage VPP rises quickly, and the voltage value of the detection signal CMP_OUT exhibits a downward trend, i.e., the voltage value of the detection signal CMP_OUT decreases. If the load current is high, the output voltage VPP rises slowly, and the detection signal CMP_OUT exhibits an upward trend, i.e., the voltage value of the detection signal CMP_OUT remains high.

[0037] The input of the inverting module 20 is coupled to the output of the charge pump circuit's feedback module. In response to the output voltage VPP first reaching the target voltage, the inverting module 20 outputs an inverted signal VCTRL_B. The charge pump circuit's feedback module is configured to provide feedback related to the output voltage VPP to the charge pump circuit, enabling the charge pump circuit to make adjustments based on this information to output the desired output voltage VPP. To this end, the inverting module 20 samples the output of the charge pump circuit's feedback module, capturing the feedback signal VCTRL output by the feedback module when the charge pump circuit's output voltage VPP first reaches the target voltage. The inverting module 20 then inverts the feedback signal VCTRL to generate an inverted signal VCTRL_B, which is then output to the latch module 30.

[0038] A first input terminal of the latch module 30 is coupled to the output terminal of the detection module 10 , a second input terminal of the latch module 30 is coupled to the output terminal of the inversion module 20 , and an output terminal of the latch module 30 is coupled to the input terminal of the charge pump circuit.

[0039] The latch module 30 latches the detection signal CMP_OUT based on the inverted signal VCTRL_B and outputs the detection signal CMP_OUT as the output signal LOAD_DET at the output terminal of the latch module 30. This output signal LOAD_DET then serves as an enable signal to enable the charge pump circuit. When the output voltage VPP of the charge pump circuit first reaches the target voltage, the inverted signal VCTRL_B serves as the clock signal, and the detection signal CMP_OUT at this time is output as the output signal LOAD_DET of the latch module 30 and latched. The latched detection signal CMP_OUT is used to control whether the charge pump circuit is enabled or disabled.

[0040] In this embodiment, the detection module 10 in the detection circuit 100 outputs a detection signal CMP_OUT related to the load current of the charge pump circuit. After the output voltage VPP of the charge pump circuit reaches the target voltage value for the first time, the latch module 30 in the detection circuit 100 latches the detection signal CMP_OUT according to the inverted signal VCTRL_B, and outputs the detection signal CMP_OUT as the output signal LOAD_DET at the output end of the latch module 30, so that the output signal LOAD_DET serves as an enable signal to enable the charge pump circuit, thereby achieving the purpose of accurately controlling the driving capability of the charge pump circuit according to the load current of the charge pump circuit, thereby enabling the charge pump circuit to obtain the optimal driving capability under different loads and obtain the minimum voltage ripple while meeting the driving requirements.

[0041] That is, it is equivalent to the related art and Figure 1A load current detection unit (detection circuit 100) is added to the charge pump circuit shown. The load current magnitude is determined by detecting the rising rate of the charge pump circuit output voltage VPP, taking advantage of the different rising rates of the charge pump circuit output voltage VPP under different loads. After the charge pump circuit output voltage VPP reaches a target voltage value, the drive capability of the charge pump circuit is precisely controlled based on the load current magnitude using the detection signal CMP_OUT output by the detection module 10. This ensures that the drive capability of the charge pump circuit is optimized under different loads, thereby achieving minimum voltage ripple while meeting the drive requirements.

[0042] See Figure 5 The detection module 10 includes: a capacitor C1, a current source and a comparison unit.

[0043] The upper plate of the capacitor C1 serves as a sampling terminal of the detection module 10 and is coupled to the output terminal of the charge pump circuit.

[0044] A first terminal of the current source is coupled to the lower plate of the capacitor C1 , and a second terminal of the current source is grounded.

[0045] The first input terminal of the comparison unit is coupled to the lower plate of the capacitor C1 , the second input terminal of the comparison unit is coupled to the reference voltage terminal, and the output terminal of the comparison unit, serving as the output terminal of the detection module 10 , is coupled to the first input terminal of the latch module 30 .

[0046] In some embodiments, in response to the decrease in the voltage VC of the lower plate of the capacitor C1 , the comparison unit maintains outputting the high-level detection signal CMP_OUT.

[0047] In some embodiments, in response to the increase in the lower plate voltage VC of the capacitor C1 , the comparison unit outputs a detection signal CMP_OUT that becomes low; wherein the lower plate voltage VC is determined by the load current.

[0048] Before the charge pump circuit is enabled, the voltage VC on the lower plate of capacitor C1 is equal to the reference voltage. Therefore, when the charge pump circuit is enabled, the output voltage VPP begins to rise. If the load current of the charge pump circuit is low, the output voltage VPP rises quickly, and the charging current on the top plate of capacitor C1 becomes greater than the reference current IREF. This causes the voltage VC on the lower plate of capacitor C1 to rise, and the detection signal CMP_OUT output by the comparison unit to become low. Conversely, if the load current of the charge pump circuit is high, the output voltage VPP rises slowly, and the charging current on the top plate of capacitor C1 becomes less than the reference current IREF. This causes the voltage VC on the lower plate of capacitor C1 to decrease, and the detection signal CMP_OUT output by the comparison unit to remain high.

[0049] In some embodiments, the comparison unit may be Figure 5The comparator CMP2 has a non-inverting input terminal coupled to the reference voltage terminal, an inverting input terminal coupled to the lower plate of the capacitor C1, and an output terminal of the comparator CMP2 as the output terminal of the detection module 10 coupled to the first input terminal of the latch module 30.

[0050] Furthermore, the detection module 10 also includes a transistor D1, a first end of the transistor D1 is coupled to the reference voltage end, and a second end of the transistor D1 is coupled to the lower plate of the capacitor C1; wherein, before the charge pump circuit is enabled, the transistor D1 is turned on, and the voltage VC of the lower plate of the capacitor C1 is equal to the reference voltage VREF provided by the reference voltage end.

[0051] In one application scenario, before the output voltage VPP of the charge pump circuit reaches the target voltage value, the output signal LOAD_DET of the latch module 30 is provided by the latch module 30 itself. For example, before the output voltage VPP of the charge pump circuit reaches the target voltage value, the output signal LOAD_DET of the latch module 30 controls all charge pump units in the charge pump circuit to be enabled.

[0052] See Figure 6 The latch module 30 includes: an RS trigger, a selection module and a D trigger.

[0053] The set terminal of the RS flip-flop is used to receive the set signal, and the reset terminal of the RS flip-flop is coupled to the output terminal of the inverting module 20. When the RS flip-flop receives the set signal, the RS flip-flop outputs a set bit "1".

[0054] The first input terminal in0 of the selection module is coupled to the output terminal of the detection module 10, and the control terminal of the selection module is used to couple to the output terminal of the RS trigger. The selection module can be a multiplexer.

[0055] The data terminal of the D flip-flop is coupled to the output terminal out of the selection module. The clock input terminal of the D flip-flop is coupled to the output terminal of the inverting module 20. The output terminal of the D flip-flop, serving as the output terminal of the latch module, is coupled to the input terminal of the charge pump circuit and to the second input terminal in1 of the selection module. When the D flip-flop receives a set signal, the output of the D flip-flop is set to "1." In one application scenario, before the output voltage VPP of the charge pump circuit reaches the target voltage value, the output signal LOAD_DET of the latch module 30 is provided by the latch module 30 itself. For example, before the output voltage VPP of the charge pump circuit reaches the target voltage value, the output signal LOAD_DET of the latch module 30 sets the output of the D flip-flop to "1."

[0056] In one application scenario, the inverting module 20 inverts the feedback signal VCTRL output by the feedback module of the charge pump circuit when the output voltage VPP reaches the target voltage value, generating an inverted signal VCTRL_B. When the output voltage VPP of the charge pump circuit reaches the target voltage value, the feedback signal VCTRL output by the feedback module is at a low level. Based on this, the inverting module 20 inverts the low-level feedback to generate a high-level inverted signal VCTRL_B.

[0057] Because the clock input of the D flip-flop is coupled to the output of the inverting module 20, the D flip-flop responds to the high-level inverting signal VCTRL_B, receives the detection signal CMP_OUT selected and output by the selection module, and outputs the detection signal CMP_OUT as the output signal LOAD_DET. Simultaneously, because the reset of the RS flip-flop is coupled to the output of the inverting module 20, the RS flip-flop responds to the high-level inverting signal VCTRL_B, outputs a reset signal to the selection module. Based on the reset signal, the selection module selects and outputs the output signal LOAD_DET inputted from the second input to the data terminal of the D flip-flop.

[0058] Because the output terminal of the D flip-flop actually outputs the detection signal CMP_OUT before the selection module selects and outputs the output signal LOAD_DET inputted from the second input terminal in1 to the data terminal of the D flip-flop, the detection signal CMP_OUT is latched during this process. Specifically, when the output voltage VPP of the charge pump circuit first reaches the target voltage value, the detection signal CMP_OUT related to the load current is latched. The latched detection signal CMP_OUT can then be used to enable the charge pump circuit, thereby adapting the charge pump circuit's driving capability to the load.

[0059] In one application scenario, before the charge pump circuit is enabled, the D flip-flop responds to the control signal SET and outputs the first set signal as the output signal LOAD_DET to the charge pump circuit. The RS flip-flop responds to the control signal SET input at the set end and outputs the second set signal to the selection module. The selection module selects the detection signal CMP_OUT according to the second set signal and outputs it to the D flip-flop.

[0060] In this embodiment, the detection module 10 in the detection circuit 100 outputs a detection signal CMP_OUT related to the load current of the charge pump circuit. After the output voltage VPP of the charge pump circuit reaches the target voltage value for the first time, the latch module 30 in the detection circuit 100 latches the detection signal CMP_OUT according to the inverted signal VCTRL_B, and outputs the detection signal CMP_OUT as the output signal LOAD_DET at the output end of the latch module 30, so that the output signal LOAD_DET serves as an enable signal to enable the charge pump circuit, thereby achieving the purpose of accurately controlling the driving capability of the charge pump circuit according to the load current of the charge pump circuit, thereby enabling the charge pump circuit to obtain the optimal driving capability under different loads and obtain the minimum voltage ripple while meeting the driving requirements.

[0061] That is, it is equivalent to the related art and Figure 1 A load current detection unit (detection circuit 100) is added to the charge pump circuit shown. The load current magnitude is determined by detecting the rising rate of the charge pump circuit output voltage VPP, taking advantage of the different rising rates of the charge pump circuit output voltage VPP under different loads. After the charge pump circuit output voltage VPP reaches a target voltage value, the drive capability of the charge pump circuit is precisely controlled based on the load current magnitude using the detection signal CMP_OUT output by the detection module 10. This ensures that the drive capability of the charge pump circuit is optimized under different loads, thereby achieving minimum voltage ripple while meeting the drive requirements.

[0062] See Figure 7 Detection circuit 100 includes: capacitor C1, current source, comparator CMP2, transistor D1, RS flip-flop, multiplexer, D flip-flop, and inverter (not shown). The following describes the workflow of detection circuit 100 applied to a charge pump circuit: Before the charge pump circuit is enabled, the SET signal is valid, initializing the voltage VC on the lower plate of capacitor C1 to equal the reference voltage VREF. This lower plate voltage VC is the same as the reference voltage of the comparator. Simultaneously, the output of the D flip-flop is set, enabling all charge pump units. The RS flip-flop is also set, controlling the multiplexer to select the output detection signal CMP_OUT of comparator CMP2 as the data input of the D flip-flop. As can be understood, when the output of the D flip-flop is set, LOAD_DET = 1.

[0063] After the initial state is set, the SET signal is invalid, and then the charge pump circuit is enabled, and the output voltage VPP begins to rise. If the load current of the charge pump circuit is small, the output voltage VPP rises faster, the charging current of the upper plate of capacitor C1 will be greater than the reference current IREF, the voltage VC of the lower plate of capacitor C1 increases, and the detection signal CMP_OUT output by the comparator CMP2 becomes low; conversely, if the load current of the charge pump circuit is large, the output voltage VPP rises slower, the charging current of the upper plate of capacitor C1 will be less than the reference current IREF, the voltage VC of the lower plate of capacitor C1 decreases, and the detection signal CMP_OUT output by the comparator CMP2 remains high.

[0064] After the output voltage VPP reaches the target voltage value, the signal VCTRL output by the comparator CMP1 in the charge pump circuit becomes low, and the inverted signal VCTRL_B output by the inverter becomes high. The inverted signal VCTRL_B serves as a clock to send the detection signal CMP_OUT into the D flip-flop. At the same time, the inverted signal VCTRL_B resets the output of the RS flip-flop, controls the multiplexer, and selects the output of the D flip-flop as the data input of the D flip-flop. That is, the data of the D flip-flop will be maintained.

[0065] In summary, the above approach ensures that the output LOAD_DET of the detection circuit 100 is 1 at the initial stage of the output voltage VPP's rise. This signal serves as the enable signal for the charge pump units, driving all charge pumps to be enabled. After the output voltage VPP reaches the target value for the first time, the detection signal CMP_OUT, which is determined by the rising speed of the output voltage VPP, is latched and remains unchanged, controlling whether the corresponding charge pump units are enabled.

[0066] The detection threshold of the detection circuit 100 for the load current is IL = IPUMP - (CL / C1) * IREF. That is, if the load current is less than IPUMP - (CL / C1) * IREF, the module output is low after VPP reaches the target value for the first time. If the load current is greater than IPUMP - (CL / C1) * IREF, the module output is high after VPP reaches the target value for the first time.

[0067] Wherein, IL is the load equivalent current, IPUMP is the maximum output drive current of the charge pump circuit, CL is the decoupling capacitor at the output end of the charge pump circuit, C1 and IREF are the capacitor C1 and reference current value of the detection circuit 100 respectively.

[0068] For a specific charge pump circuit, IPUMP and CL are known values, so the desired detection threshold can be obtained by simply setting C1 and IREF appropriately.

[0069] See Figure 8 , Figure 8FIG1 is a schematic diagram of another embodiment of a charge pump circuit provided in the present application. The charge pump circuit 1000 includes a detection circuit 100. The detection circuit 100 may be the detection circuit 100 in any of the above embodiments.

[0070] In practical applications, multiple such detection circuits 100 may be used, each with a different detection threshold set, to reasonably divide the entire driving range and obtain better detection accuracy.

[0071] In one application scenario, seven detection circuits 100 are provided in the charge pump circuit 1000, such as Figure 9 As shown, the thresholds of the seven detection circuits 100 are set to 1 / 8*IPUMP to 7 / 8*IPUMP, respectively, dividing the entire driving range of the charge pump circuit 1000 into 8 equal parts. At the same time, the charge pump unit is also evenly divided into 8 parts. No matter how large the load current is, after the output voltage VPP reaches the target voltage value for the first time, the driving capability retained by the charge pump circuit 1000 is always slightly greater than the load current, and the difference between the two does not exceed 1 / 8*IPUMP. In this way, the ripple can be minimized.

[0072] After the load current detection circuit 100 is added to this solution, the overall structure of the charge pump circuit 1000 is as shown in FIG. Figure 10 As shown, the working sequence is as follows Figure 11 shown.

[0073] See Figure 12 , Figure 12 FIG2 is a schematic diagram of the structure of an embodiment of a non-volatile memory provided by the present application. The non-volatile memory 2000 includes a detection circuit 100. The detection circuit 100 can be the detection circuit 100 in any of the above embodiments.

[0074] See Figure 13 , Figure 13 FIG2 is a schematic diagram of another embodiment of a non-volatile memory provided by the present application. The non-volatile memory 2000 includes a charge pump circuit 1000. The charge pump circuit 1000 may be the charge pump circuit 1000 in any of the above embodiments.

[0075] In summary, the detection circuit 100, charge pump circuit 1000, and non-volatile memory 2000 provided in the present application output a detection signal CMP_OUT related to the load current of the charge pump circuit through the detection module 10. After the output voltage VPP of the charge pump circuit reaches the target voltage value for the first time, the latch module 30 latches the detection signal CMP_OUT according to the inverted signal VCTRL_B, and outputs the detection signal CMP_OUT as the output signal LOAD_DET at the output end of the latch module 30, so that the output signal LOAD_DET is used as an enable signal to enable the charge pump circuit, thereby achieving the purpose of accurately controlling the driving capability of the charge pump circuit according to the load current of the charge pump circuit, thereby enabling the charge pump circuit to obtain the optimal driving capability under different loads and obtain the minimum voltage ripple while meeting the driving requirements.

[0076] That is, by adding a load current detection unit (detection circuit 100), the different rising rates of the output voltage VPP of the charge pump circuit under different loads are utilized, and the magnitude of the load current is obtained by detecting the rising rate of the output voltage VPP of the charge pump circuit. After the output voltage VPP of the charge pump circuit reaches the target voltage value, the driving capability of the charge pump circuit is precisely controlled according to the magnitude of the load current using the detection signal CMP_OUT output by the detection module 10 at this time, thereby ensuring the optimal value of the driving capability of the charge pump circuit under different loads and obtaining the minimum voltage ripple while meeting the driving requirements.

[0077] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0078] If the integrated units in the other embodiments described above are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0079] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A detection circuit, characterized in that: The detection circuit comprises: a detection module, wherein a sampling terminal of the detection module is coupled to an output terminal of the charge pump circuit to collect an output voltage, and the detection module outputs a detection signal in response to the output voltage reaching a target voltage value for the first time; the detection signal is related to a load current of the charge pump circuit; an inverting module, wherein an input terminal of the inverting module is coupled to an output terminal of the feedback module of the charge pump circuit; the inverting module outputs an inverting signal in response to the output voltage reaching the target voltage value for the first time; a latch module, wherein a first input terminal of the latch module is coupled to the output terminal of the detection module, a second input terminal of the latch module is coupled to the output terminal of the inverting module, and an output terminal of the latch module is coupled to the input terminal of the charge pump circuit; The latch module latches the detection signal according to the inverted signal, and outputs the detection signal as an output signal of an output terminal of the latch module, so that the output signal serves as an enable signal to enable the charge pump circuit.

2. The detection circuit according to claim 1, characterized in that The detection module includes: a capacitor, wherein an upper plate of the capacitor serves as a sampling terminal of the detection module and is coupled to an output terminal of the charge pump circuit; a current source, wherein a first terminal of the current source is coupled to the lower plate of the capacitor, and a second terminal of the current source is grounded; A comparison unit, wherein the first input terminal of the comparison unit is coupled to the lower plate of the capacitor, the second input terminal of the comparison unit is used to couple to the reference voltage terminal, and the output terminal of the comparison unit is coupled to the first input terminal of the latch module as the output terminal of the detection module.

3. The detection circuit according to claim 2, characterized in that: The comparison unit maintains outputting a high-level detection signal in response to a decrease in the voltage of the lower plate of the capacitor; Alternatively, the comparison unit responds to an increase in the voltage of the lower plate of the capacitor, and the detection signal output by the comparison unit becomes low; wherein the lower plate voltage is determined by the load current.

4. The detection circuit according to claim 3, characterized in that: Before the charge pump circuit is enabled, the voltage of the lower plate of the capacitor is equal to the reference voltage.

5. The detection circuit according to claim 2, characterized in that: The detection module also includes a transistor, a first end of the transistor is coupled to the reference voltage end, and a second end of the transistor is coupled to the lower plate of the capacitor; wherein, before the charge pump circuit is enabled, the transistor is turned on, and the voltage of the lower plate of the capacitor is equal to the reference voltage provided by the reference voltage end.

6. The detection circuit according to claim 1, characterized in that: The latch module includes: An RS trigger, wherein a set terminal of the RS trigger is used to receive a set signal, and a reset terminal of the RS trigger is coupled to the output terminal of the inverting module; a selection module, wherein a first input terminal of the selection module is coupled to the output terminal of the detection module, and a control terminal of the selection module is used to couple to the output terminal of the RS trigger; A D flip-flop, wherein the data end of the D flip-flop is coupled to the output end of the selection module, the clock input end of the D flip-flop is coupled to the output end of the inverting module, and the output end of the D flip-flop is coupled to the input end of the charge pump circuit as the output end of the latch module and coupled to the second input end of the selection module.

7. The detection circuit according to claim 6, characterized in that: The inversion module inverts the feedback signal output by the feedback module of the charge pump circuit when the output voltage reaches the target voltage value to obtain an inverted signal; the D flip-flop responds to the inverted signal, receives the detection signal selected and output by the selection module, and outputs the detection signal as the output signal; the RS flip-flop responds to the inverted signal, outputs a reset signal to the selection module, and the selection module selects and outputs the output signal input by the second input terminal to the data terminal of the D flip-flop according to the reset signal.

8. The detection circuit according to claim 6, characterized in that: Before the charge pump circuit is enabled, the D flip-flop responds to a control signal and outputs a first set signal as the output signal to the charge pump circuit, and the RS flip-flop responds to a control signal input at the set end and outputs a second set signal to the selection module, and the selection module selects the detection signal to be output to the D flip-flop according to the second set signal.

9. A charge pump circuit, characterized in that: The charge pump circuit comprises the detection circuit according to any one of claims 1-8.

10. A non-volatile memory, characterized in that: The non-volatile memory includes the detection circuit according to any one of claims 1 to 8 or the charge pump circuit according to claim 9.

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