Dry etching of boron-containing materials

Abstract

An exemplary method of semiconductor processing may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be received within the processing region. The substrate may include a boron-containing material overlying a carbon-containing material. The method may include generating a plasma effluent of the fluorine-containing precursor. The method may include contacting the substrate with the plasma effluent of the fluorine-containing precursor. The method may include removing the boron-containing material from the substrate.

Description

Technical Field

[0001] This application claims the benefit of and priority to U.S. patent application No. 18 / 098,791, filed on January 19, 2023, entitled “DRY ETCH OF BORON-CONTAINING MATERIAL,” the entire contents of which are incorporated herein by reference.

[0002] The present technology relates to semiconductor processing and materials, and more particularly to removing boron-containing materials that overlie other materials. Background Art

[0003] Integrated circuits are made possible by processes that create complex patterned material layers on substrate surfaces. Creating patterned materials on substrates requires controlled methods for forming and removing exposed materials. Stacked memory, such as vertical or 3D NAND, can include the formation of a series of alternating dielectric material layers through which multiple memory holes or apertures can be etched. The material properties of the material layers, as well as the processing conditions and materials used for etching, can affect the uniformity of the resulting structure. Etchant resistance can result in inconsistent patterns, which can further affect the uniformity of the resulting structure.

[0004] Therefore, a need exists for improved systems and methods by which high quality devices and structures can be produced. The present technology addresses these and other needs. Summary of the Invention

[0005] An exemplary method of semiconductor processing may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing material. The method may include generating a plasma effluent of the fluorine-containing precursor. The method may include contacting the substrate with the plasma effluent of the fluorine-containing precursor. The method may include removing the boron-containing material from the substrate.

[0006] In embodiments, the fluorine-containing precursor may be or include nitrogen trifluoride (NF3). The boron-containing material may be characterized by a boron content greater than or about 20 at.%. The boron-containing material may further include nitrogen. The boron-containing material and the carbon-containing material may define at least one orifice extending through both the boron-containing material and the carbon-containing material. The temperature within the semiconductor processing chamber may be maintained at less than or about 100°C. The pressure within the semiconductor processing chamber may be maintained at less than or about 1 Torr. The plasma power may be maintained at greater than or about 1,000 W while generating the plasma effluent of the fluorine-containing precursor. The plasma effluent may be greater than or about The boron-containing material is removed from the substrate at a rate of 1:1. The boron-containing material may be ...

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The methods may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing hardmask material. The boron-containing material and the carbon-containing hardmask material may define at least one orifice extending through both the boron-containing material and the carbon-containing hardmask material. The methods may include generating a plasma effluent of the fluorine-containing precursor. The methods may include contacting the substrate with the plasma effluent of the fluorine-containing precursor. The methods may include removing the boron-containing material from the substrate.

[0008] In embodiments, the fluorine-containing precursor may be or include nitrogen trifluoride (NF3). The flow rate of the fluorine-containing precursor may be less than or approximately 1,000 seem. The boron-containing material may be characterized by a thickness greater than or approximately 250 nm. The fluorine-containing precursor may be provided to a processing region of a semiconductor processing chamber in the absence of a carrier gas. The method may include, prior to providing the fluorine-containing precursor, etching a carbon-containing hardmask material to form at least one orifice extending through the carbon-containing hardmask material. Removing the boron-containing material from the substrate may be performed in the same semiconductor processing chamber as etching the carbon-containing hardmask material.

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The methods may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The fluorine-containing precursor may be or include nitrogen trifluoride (NF3). A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing material. The methods may include generating a plasma effluent of the fluorine-containing precursor. The plasma power may be maintained between about 500 W and about 3,000 W while generating the plasma effluent of the fluorine-containing precursor. The methods may include contacting the substrate with the plasma effluent of the fluorine-containing precursor. The methods may include removing the boron-containing material from the substrate.

[0010] In embodiments, the boron-containing material may be removed from the substrate in less than or about 10 minutes. The carbon-containing material may define at least one pore. Removal of the boron-containing material from the substrate may maintain sidewalls and a bottom surface of the at least one pore.

[0011] This technology can provide numerous benefits over conventional systems and techniques. For example, the processes and structures can selectively remove boron-containing materials relative to carbon-containing materials and other materials during etching operations. Additionally, the operation of embodiments of the present technology can improve etch rates without creating undercut profiles on underlying materials, such as carbon-containing materials, and other underlying materials, such as silicon oxide and / or silicon nitride. These and other embodiments, as well as their many advantages and features, are described in greater detail in conjunction with the following embodiments and accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the accompanying drawings.

[0013] Figure 1 A schematic top view of an exemplary processing system according to some embodiments of the present technology is shown.

[0014] Figure 2 A schematic cross-sectional view of an exemplary processing system according to some embodiments of the present technology is shown.

[0015] Figure 3 Selected operations in a method of formation according to some embodiments of the present technology are shown.

[0016] Figures 4A-4B Shown are schematic cross-sectional views of substrate materials upon which selected operations are being performed, in accordance with some embodiments of the present technology.

[0017] Several of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and are not to be considered drawn to scale unless specifically indicated to be drawn to scale. Additionally, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include material that is superfluous or exaggerated for illustrative purposes.

[0018] In the accompanying drawings, similar components and / or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference numeral with a letter that distinguishes the similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION

[0019] As the number of cells formed in a 3D NAND structure increases, the aspect ratio of the memory holes and other structures also increases, sometimes dramatically. During 3D NAND processing, a stack of placeholder layers and dielectric materials can be formed first, and memory cells can be formed within them. These placeholder layers may undergo a variety of operations to place the structure before the material is completely removed and replaced with metal. For example, layers are typically formed to cover conductor layers, such as polysilicon. When forming memory holes, the orifices can extend through all alternating material layers before accessing the polysilicon or other material substrate. Subsequent processing can form a staircase structure for the contacts, and the placeholder material can also be excavated laterally.

[0020] A reactive ion etching ("RIE") operation may be performed to create the high aspect ratio memory holes. The RIE process typically involves a combination of chemical and physical removal of alternating layers. As a non-limiting example, where the alternating layers may include silicon oxide and silicon nitride, the silicon oxide may be removed to a greater extent by physically bombarding the layers during RIE, and the silicon nitride may be removed to a greater extent by chemical reaction of the RIE precursor with the nitride material.

[0021] Due to the material differences between the two layer types, as well as the RIE process and materials, conventional techniques can struggle with uniformity and control during memory hole formation. Furthermore, the memory hole can extend outward during etching, widening the critical dimension within the stacked layer structure through which RIE is performed to create the memory hole. Bowing can occur anywhere throughout the structure and can be caused by a variety of issues. For example, bowing can be caused by limited passivation on the sidewalls, which may allow some lateral etching to occur. Bowing can also occur due to variations in the hardmask material or other structural features. For example, if the edges of the hardmask may be etched during RIE, ions may be projected into the feature or memory hole at a direction or angle different from the substrate normal, potentially causing additional lateral etching in some areas of the structure until the hardmask taper is removed or etched away. Furthermore, due to the redeposition of etched material, the memory hole may become partially or completely blocked. Partial blockage can affect the memory hole's cyclicity. Partial or complete blockage can also adversely affect the electrical performance of the final device. In some technologies, the hardmask may not be completely uniform due to the hardmask opening.

[0022] To compensate for these issues, conventional techniques are limited in the number of stacked layer pairs that can be etched at any one time. As the number of layers increases, many conventional techniques will produce the structure in two discrete cycles. For example, conventional techniques may produce a first set of layers and etch through them. Memory holes may become blocked, and a second set of layers may form overlying the first set of layers. To fully form the structure, the second set of layers and the plugs in the first set can then be etched. However, alignment of the holes between sets is rarely perfect, resulting in offsets that can affect production and cell formation. Furthermore, by pausing formation between sets, material differences may arise due to different exposure and processing levels.

[0023] The present technology overcomes these problems by using a boron-containing material as a mask for opening the hard mask covering the alternating layers. The boron-containing material may be less prone to clogging during the opening of the hard mask, which can form more uniform features or orifices in the hard mask. In addition, intermittent flash operations during etching can prevent clogging and thus increase uniformity. More uniform features or orifices can result in more uniform etching of the alternating layers below the hard mask. However, unlike conventional techniques, conventional wet etching may not be able to remove the boron-containing material, or may remove the boron-containing material slowly or with poor selectivity. The present technology also overcomes these problems by removing the boron-containing material with a fluorine-containing precursor. The removal operation can remove boron-containing materials of varying thicknesses across the substrate while minimizing the impact on the underlying material (such as the hard mask).

[0024] While the remainder of the disclosure will routinely identify specific materials and semiconductor structures that utilize the disclosed technology, it will be readily understood that the systems, methods, and materials are equally applicable to many other structures that can benefit from various aspects of the present technology. Therefore, the technology should not be considered limited to use solely with 3D NAND processes or materials. Furthermore, while an exemplary chamber is described to provide a basis for the present technology, it should be understood that the present technology is applicable to virtually any semiconductor processing chamber that can permit the described operations.

[0025] Figure 1 A top view of one embodiment of a processing system 10 is shown showing deposition, etch, bake, and / or cure chambers in accordance with an embodiment. Figure 1 The depicted tool or processing system 10 may contain a plurality of process chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The process chamber may include any number of structures or components, and any number or combination of process chambers.

[0026] To transfer substrates between chambers, the transfer chamber 20 may include a robotic transfer mechanism 22. The transfer mechanism 22 may include a pair of substrate transfer blades 22a, each attached to the distal end of an extendable arm 22b. The blades 22a can be used to transport individual substrates to and from a processing chamber. In operation, one of the substrate transfer blades (such as blade 22a of the transfer mechanism 22) can retrieve a substrate W from one of the load lock chambers (such as chambers 16a-b) and transport the substrate W to the first stage of processing, for example, a treatment process in chambers 24a-d as described below. Chambers may be included to perform individual or combined operations of the described technology. For example, while one or more chambers may be configured to perform deposition or etching operations, one or more other chambers may be configured to perform the described pre-treatment operations and / or one or more post-treatment operations. The present technology encompasses any number of configurations, which may also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0027] If a chamber is occupied, the robot can wait until processing is complete and then remove the processed substrate from the chamber using one blade 22a and insert a new substrate using a second blade. Once the substrate is processed, it can be moved to the second stage of processing. For each move, the transport mechanism 22 can typically have one blade carrying a substrate and one empty blade to perform substrate exchange. The transport mechanism 22 can wait at each chamber until the exchange can be completed.

[0028] Once processing is completed within the processing chamber, the transport mechanism 22 can move the substrate W from the last processing chamber and transfer the substrate W to the cassette within the load lock chamber 16a-b. The substrate can be moved from the load lock chamber 16a-b to the factory interface 12. The factory interface 12 is typically operable to transfer substrates between the container loaders 14a-d and the load lock chambers 16a-b in an atmospheric pressure clean environment. The clean environment in the factory interface 12 can typically be provided, for example, by air filtration (such as HEPA filtration). The factory interface 12 may also include a substrate orienter / aligner that can be used to correctly align the substrate before processing. At least one substrate robot (such as robot 18a-b) can be positioned in the factory interface 12 to transfer substrates between various positions / locations within the factory interface 12 and to other locations connected thereto. The robot 18a-b can be configured to travel from a first end of the factory interface 12 to a second end along a track system within the factory interface 12.

[0029] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals that can provide adaptive control of any process performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices to measure various thin film properties such as thickness, roughness, composition, and the metrology devices may further be characterized by measuring grating parameters (such as critical dimension), sidewall angle, and feature height in a vacuum in an automated manner.

[0030] Each of the processing chambers 24a-d can be configured to perform one or more processing steps in the fabrication of semiconductor structures, and any number of processing chambers and combinations of processing chambers can be used on the multi-chamber processing system 10. For example, any processing chamber can be configured to perform a variety of substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate treatments. Some specific processes that can be performed in any chamber or in any combination of chambers can be metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. Any other process can similarly be performed in a specific chamber incorporated into the multi-chamber processing system 10, including any of the processes described below, as will be readily understood by those skilled in the art.

[0031] Figure 2 A schematic cross-sectional view of an exemplary processing chamber 200 is shown, which is suitable for patterning a layer of material on a substrate 202 disposed in the processing chamber 200. The exemplary processing chamber 200 is suitable for performing a patterning process, but it should be understood that various aspects of the present technology can be performed in any number of chambers, and substrate supports according to the present technology can be included in an etch chamber, a deposition chamber, a disposal chamber, or any other processing chamber. The plasma processing chamber 200 may include a chamber body 205 defining a chamber volume 201 in which a substrate may be processed. The chamber body 205 may have sidewalls 212 and a bottom 218 coupled to a ground 226. The sidewalls 212 may have liners 215 to protect the sidewalls 212 and extend the time between maintenance cycles of the plasma processing chamber 200. The size of the chamber body 205 and associated components of the plasma processing chamber 200 is not limited and may generally be proportionally larger than the size of the substrate 202 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, 450 mm diameter, etc., such as display or solar cell substrates.

[0032] The chamber body 205 can support a chamber lid assembly 210 to enclose the chamber volume 201. The chamber body 205 can be made of aluminum or other suitable materials. A substrate access port 213 can be formed through a sidewall 212 of the chamber body 205 to facilitate transferring substrates 202 into and out of the plasma processing chamber 200. The access port 213 can be coupled to a transfer chamber and / or other chambers of a substrate processing system as described above. A pumping port 245 can be formed through the sidewall 212 of the chamber body 205 and connected to the chamber volume 201. A pumping device can be coupled to the chamber volume 201 through the pumping port 245 to evacuate and control the pressure within the processing volume. The pumping device can include one or more pumps and a throttle valve.

[0033] The gas panel 260 can be coupled to the chamber body 205 via gas lines 267 to supply process gases into the chamber volume 201. The gas panel 260 can include one or more process gas sources 261, 262, 263, 264 and can additionally include inert gases, non-reactive gases, and reactive gases, such as can be used for any number of processes. Examples of process gases that can be provided by the gas panel 260 include, but are not limited to, hydrocarbon-containing gases (including methane), sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon, chlorine, nitrogen, helium, or oxygen, as well as any number of additional materials. Additionally, process gases can include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, as well as any number of additional precursors.

[0034] A valve 266 can control the flow of process gases from sources 261, 262, 263, 264 of the gas panel 260 and can be managed by a controller 265. The flow of gas supplied from the gas panel 260 to the chamber body 205 can include a combination of gases from one or more sources. The lid assembly 210 can include a nozzle 214. The nozzle 214 can be one or more ports for introducing process gases from the sources 261, 262, 264, 263 of the gas panel 260 into the chamber volume 201. After the process gases are introduced into the plasma processing chamber 200, the gases can be energized to form a plasma. An antenna 248, such as one or more inductive coils, can be disposed adjacent to the plasma processing chamber 200. An antenna power supply 242 can provide power to the antenna 248 via a matching circuit 241 to inductively couple energy, such as RF energy, to the process gases to maintain a plasma formed from the process gases in the chamber volume 201 of the plasma processing chamber 200. Alternatively, or in addition to the antenna power supply 242, process electrodes may be used below and / or above the substrate 202 to capacitively couple RF power to the process gas to sustain a plasma within the chamber volume 201. Operation of the power supply 242 may be controlled by a controller, such as the controller 265, which also controls operation of other components in the plasma processing chamber 200.

[0035] A substrate support pedestal 235 may be disposed within the chamber volume 201 to support the substrate 202 during processing. The substrate support pedestal 235 may include an electrostatic chuck 222 for holding the substrate 202 during processing. The electrostatic chuck ("ESC") 222 may hold the substrate 202 to the substrate support pedestal 235 using electrostatic attraction. The ESC 222 may be powered by an RF power supply 225 integrated with a matching circuit 224. The ESC 222 may include an electrode 221 embedded within a dielectric body. The electrode 221 may be coupled to the RF power supply 225 and may provide a bias voltage that attracts plasma ions formed from the process gas in the chamber volume 201 toward the ESC 222 and substrate 202 seated on the pedestal. The RF power supply 225 may be cycled on and off, or pulsed, during processing of the substrate 202. The ESC 222 may have an isolator 228, the purpose of which is to make the sidewalls of the ESC 222 less attractive to the plasma to extend the maintenance life cycle of the ESC 222. In addition, the substrate support pedestal 235 may have a cathode liner 236 to protect the sidewalls of the substrate support pedestal 235 from the plasma gas and extend the time between maintenance of the plasma processing chamber 200.

[0036] The electrode 221 may be coupled to a power source 250. The power source 250 may provide a clamping voltage of approximately 200 volts to the electrode 221. The power source 250 may also include a system controller for controlling the operation of the electrode 221 by directing a DC current to the electrode 221 to clamp and unclamp the substrate 202. The ESC 222 may include a heater disposed within the pedestal and connected to the power source to heat the substrate, while a cooling base 229 supporting the ESC 222 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 222 and the substrate 202 disposed thereon. The ESC 222 may be configured to perform within a temperature range required by the thermal budget of the device fabricated on the substrate 202. For example, the ESC 222 may be configured to maintain the substrate 202 at a temperature of approximately -150°C or lower to approximately 500°C or higher, depending on the process being performed.

[0037] A cooling pedestal 229 may be provided to help control the temperature of the substrate 202. To mitigate processing drift and time, the temperature of the substrate 202 may be maintained substantially constant by the cooling pedestal 229 throughout the time the substrate 202 is in the chamber. In some embodiments, the temperature of the substrate 202 may be maintained at a temperature between approximately -150°C and approximately 500°C throughout subsequent processing, although any temperature may be utilized. A cover ring 230 may be disposed on the ESC 222 and along the perimeter of the substrate support pedestal 235. The cover ring 230 may be configured to confine etching gas to a desired portion of the exposed top surface of the substrate 202 while shielding the top surface of the substrate support pedestal 235 from the plasma environment within the plasma processing chamber 200. Lift pins may selectively translate through the substrate support pedestal 235 to lift the substrate 202 above the substrate support pedestal 235 to facilitate access to the substrate 202 by a transfer robot or other suitable transfer mechanism as previously described.

[0038] The controller 265 can be used to control the process sequence, regulate the gas flow from the gas panel 260 into the plasma processing chamber 200, and other process parameters. When executed by the CPU, the software routine transforms the CPU into a dedicated computer (such as a controller) that can control the plasma processing chamber 200 so that processes according to the present disclosure are performed. The software routine can also be stored and / or executed by a second controller that can be associated with the plasma processing chamber 200.

[0039] As described above, the present technology can open a carbon-containing material, such as a carbon-containing hardmask material, using a boron-containing material as a mask covering a carbon-containing material. Figure 3Exemplary operations in a method 300 of semiconductor processing according to embodiments of the present technology are shown. Method 300 may include one or more operations before the method begins, including front-end processing, deposition, etching, polishing, cleaning, or any other operation that may be performed before the described operations. For example, the method may begin after multiple layers of material covering the boron-containing material have been patterned and / or removed (including patterning of the boron-containing material). However, as described above, it should be understood that the accompanying drawings only show an exemplary process for patterning carbon-containing materials according to embodiments of the present technology, and the description is not intended to limit the technology to only such a process. Some or all of the operations may be performed in a chamber or system tool as described above, or may be performed in different chambers on the same system tool, which may include a chamber in which the operations of method 300 may be performed.

[0040] Method 300 may include a number of optional operations as shown, which may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many operations are described to provide a wider range of structure formation, but are not critical to the technology or may be performed by alternative methods as will be discussed further below. Method 300 describes Figures 4A-4B The operations shown schematically in FIG. 3 will be described in conjunction with the operations of method 300. Figures 4A-4B It should be understood that Figures 4A-4B Only a partial schematic diagram is shown, and the substrate may contain any number of structural segments having the aspects shown, as well as alternative structural aspects that may still benefit from operation of the present technology.

[0041] The method 300 may or may not involve the optional operation of developing the semiconductor structure to a specific manufacturing operation. It should be understood that the method 300 can be performed on any number of semiconductor structures, and Figures 4A-4B An exemplary structure in which an etching process may be performed is shown. Figure 4A As shown, the processed semiconductor structure 400 may include a substrate 405, which may have a plurality of stacked layers covering the substrate, which may be silicon-containing materials such as polysilicon, silicon germanium, or other substrate materials, and which may be conductors for subsequent metallization contacts. As a non-limiting example only, the layers may include IPD layers, which include dielectric materials 410 (which may be silicon oxide) in alternating layers with placeholder materials 415 (which may be silicon nitride). The placeholder materials 415 may be or include materials that will be removed to create individual memory cells in subsequent operations. Although only four layers of material are shown, the exemplary structure may include any number of layers previously discussed, which may include tens or hundreds of layers, and it should be understood that the figures are merely schematic diagrams for illustrating aspects of the present technology.

[0042] In embodiments, the exposed boron-containing material 425 may be characterized by a thickness greater than or about 250 nm, and may be characterized by a thickness greater than or about 300 nm, greater than or about 350 nm, greater than or about 400 nm, greater than or about 450 nm, greater than or about 500 nm, or greater. Conventional techniques may have difficulty removing the boron-containing material 425 characterized by a thickness greater than or about 250 nm because the etch selectivity between the boron-containing material 425 and the mask material 420 may be poor. In addition, conventional techniques may result in undercutting or damage to the mask material 420 and / or underlying materials (such as silicon oxide and / or silicon nitride) during removal of the boron-containing material 425. In embodiments, the boron-containing material may be characterized by a boron content greater than or about 20 at.%, such as greater than or about 22 at.%, greater than or about 24 at.%, greater than or about 26 at.%, greater than or about 28 at.%, greater than or about 30 at.%, greater than or about 32 at.%, greater than or about 34 at.%, greater than or about 36 at.%, greater than or about 38 at.%, greater than or about 40 at.%, or greater.

[0043] In an embodiment, the boron-containing material 425 and the mask material 420 may be characterized in a cell region, a peripheral region, and a combination thereof. The cell region may include a smaller width of mask material 420, and therefore include a smaller width of covered boron-containing material 425. The peripheral region may include a wider width of mask material 420, and therefore include a wider width of covered boron-containing material 425. The boron-containing material 425 covering the mask material 420 in the peripheral region may be thicker than the boron-containing material 425 covering the mask material 420 in the cell region. As described below, the present technology can remove the boron-containing material 425 from the cell region and the peripheral region without damaging the underlying mask material 420 and without leaving residues of the boron-containing material 425.

[0044] The mask material 420 may be formed overlying the IPD layer and may be a carbon-containing material, such as a carbon-containing hardmask material of amorphous carbon, or any other carbon-containing material that may form over the underlying layer during subsequent cleaning and / or etching operations. A boron-containing material 425 may be disposed over the mask material 420. In embodiments, the boron-containing material 425 may also include nitrogen and be a boron- and nitrogen-containing material. The boron-containing material 425 may include a plurality of openings or apertures 430. The openings or apertures 430 may extend through the entire thickness of the boron-containing material 425, thereby exposing the underlying mask material 420. The carbon-containing material of the mask material 420 may also include a plurality of openings or apertures 440. The openings or apertures 440 may extend through the entire thickness of the carbon-containing material of the mask material 420, thereby exposing the underlying stack of dielectric material 410 and placeholder material 415.

[0045] As shown, a variety of materials may be present and exposed to an etchant material that may be used in the etching process. Method 300 may be performed to etch or remove the boron-containing material 425 to allow subsequent processing to proceed while minimizing or eliminating etching or damage to the carbon-containing material of the mask material 420 and / or underlying materials (such as silicon oxide and / or silicon nitride). By utilizing processing conditions and precursors according to embodiments of the present technology, etching of the mask material 420 may be limited or prevented during etching and removal of the boron-containing material 425.

[0046] As previously discussed, the boron-containing material 425 may be discontinuous, such that the material includes openings or apertures 430. The mask material 420 may be exposed within recessed features, such as the openings or apertures 430, and may also include openings or apertures 440 aligned with the openings or apertures 430 of the boron-containing material 425. In embodiments, the method 300 may include etching the mask material 420 at optional operation 305 to form the openings or apertures 440. The mask material 420 may be etched using any etching method, such as using an oxygen-containing precursor or plasma effluents thereof. The boron-containing material 425 may act as a mask for opening the apertures 440 in the mask material 420. The etching at optional operation 305 may form features 440, which may be referred to as holes, in the mask material 420. The feature or aperture 440 may have an aspect ratio of greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater.

[0047] Method 300 may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber at operation 310. The processing region may house a substrate (such as processed semiconductor structure 400), which may have exposed boron-containing material 425 (such as a boron and nitrogen-containing material), and exposed carbon-containing material (such as mask material 420), which may be a carbon-containing hardmask and / or underlying material (such as silicon oxide and / or silicon nitride). In order to continue processing, such as etching the material underlying mask material 420, it may be necessary to remove the boron-containing material 425. If present on substrate 405, the boron-containing material 425 may have a negative impact on subsequent operations or may be more likely to produce defects. The fluorine-containing precursor may be provided to the processing region to selectively remove the boron-containing material 425 relative to the underlying mask material 420.

[0048] The fluorine-containing precursor used in method 300 may include any fluorine-containing precursor. An exemplary fluorine-containing precursor may be nitrogen trifluoride (NF3), which may be flowed into the processing region without passing through any plasma along the way. Other fluorine sources may be combined with nitrogen trifluoride or used as a substitute for nitrogen trifluoride. Generally speaking, the fluorine-containing precursor may be flowed into the processing region, and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride (CF4), hydrogen fluoride (HF), sulfur hexafluoride (SF6), xenon difluoride (XeF2), and various other fluorine-containing precursors used or useful in semiconductor processing. The precursor may also include any number of carrier gases, which may include nitrogen, helium, argon, or other rare, inert, or useful precursors. The carrier gas may be used to dilute the fluorine-containing precursor, which may reduce the etch rate to allow for adequate control of the etch. However, it is contemplated that the fluorine-containing precursor may be provided without any other gas.

[0049] The flow rate of one or more fluorine-containing precursors may also be adjusted along with any other processing conditions. For example, the flow rate of the fluorine-containing precursor may be reduced, maintained, or increased during method 300. During any operation of method 300, the flow rate of the fluorine-containing precursor may be between about 2 sccm and about 1,000 sccm. Additionally, the flow rate of the fluorine-containing precursor may be less than or about 900 sccm, less than or about 800 sccm, less than or about 700 sccm, less than or about 600 sccm, less than or about 500 sccm, less than or about 400 sccm, less than or about 300 sccm, less than or about 250 sccm, less than or about 200 sccm, less than or about 150 sccm, less than or about 100 sccm, or more. The flow rate may also be between any of these stated flow rates, or within a smaller range encompassed by any of these figures.

[0050] Method 300 may include forming a plasma within a processing region of a semiconductor processing chamber at operation 315. The plasma may generate a plasma effluent of a fluorine-containing precursor. In some embodiments, operations 310 and 315 may occur sequentially or be performed substantially simultaneously. Additionally, in various embodiments, the plasma may be initially formed from a fluorine-containing precursor or, if present, from one or more inert precursors prior to the addition of the fluorine-containing precursor.

[0051] The localized plasma formed from the fluorine-containing precursor can provide a directed flow of plasma effluents toward the boron-containing material 425 to provide efficient removal of the boron-containing material 425. The plasma can be a low-level plasma to limit the amount of bombardment, sputtering, and surface modification. In embodiments, the plasma power can be less than or about 5,000 W, less than or about 4,500 W, less than or about 4,000 W, less than or about 3,500 W, less than or about 3,000 W, less than or about 2,500 W, less than or about 2,000 W, less than or about 1,500 W, less than or about 1,000 W, or less. By utilizing a plasma power of, for example, about 4,000 W or less, the plasma effluents can be better controlled to reduce the profile and / or damage to exposed surfaces (such as the mask material 420). However, at too low a plasma power (such as less than or about 500 W), the etch rate of the boron-containing material 425 may be compromised, resulting in slower throughput and increased queue times. In embodiments, the plasma power may be greater than or about 500 W, greater than or about 600 W, greater than or about 700 W, greater than or about 800 W, greater than or about 900 W, greater than or about 1,000 W, greater than or about 1,250 W, greater than or about 1,500 W, greater than or about 1,750 W, greater than or about 2,000 W, or more. Thus, the plasma power may be maintained between about 500 W and about 3,000 W, or any range therebetween.

[0052] At operation 320, the semiconductor structure 400 may be contacted with plasma effluents, which may perform etching or removal of the boron-containing material 425 at operation 325. Figure 4B As shown, the plasma effluents may contact the semiconductor structure 400 and may contact all exposed surfaces, including surfaces to be etched, such as the boron-containing material 425, and surfaces to be maintained, such as the mask material 420, the placeholder material 415, and / or the dielectric material 410, which may include the sidewalls and / or bottom surfaces of the opening 440 in the material. During operation 325, the sidewalls and / or bottom surfaces of the opening 440 in the mask material may be maintained with minimal or no modification or damage.

[0053] Embodiments of the present technology can remove the boron-containing material 425 at a ratio of at least about 10:1 relative to the mask material 420 or any other material, and can etch the boron-containing material 425 at a selectivity of greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 50:1, greater than or about 100:1, greater than or about 150:1, greater than or about 200:1, greater than or about 250:1, greater than or about 300:1, greater than or about 350:1, greater than or about 400:1, greater than or about 450:1, greater than or about 500:1, or more relative to the mask material 420 or any other material. For example, an etch performed according to some embodiments of the present technology can etch the boron-containing material 425 while substantially or essentially maintaining the mask material 420 or other material.

[0054] Embodiments of the present technology can quickly and efficiently remove the boron-containing material 425. Many conventional techniques (such as wet etching processes) may require a significant amount of operating time to completely remove the boron-containing material. The precursors and / or operating conditions of the present embodiments can provide an increased removal rate. In embodiments, the removal rate may be greater than or about The boron-containing material 425 is removed from the substrate 405 at a rate greater than or about Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately The boron-containing material 425 is removed at a rate of 1000 nm or higher.

[0055] Thus, in some embodiments, the etching operation can be performed in a single cycle, although multiple etching cycles can be performed. Additionally, the process can completely remove the boron-containing material 425 in a time period of less than or about 10 minutes, less than or about 9 minutes, less than or about 8 minutes, less than or about 7 minutes, less than or about 6 minutes, less than or about 5 minutes, less than or about 4 minutes, less than or about 3 minutes, less than or about 2 minutes, less than or about 1 minute, or less.

[0056] Processing conditions can affect the operations performed in method 300. In embodiments, each operation of method 300 can be performed at a constant temperature, while in some embodiments, the temperature can be adjusted during different operations. For example, the substrate, pedestal, or chamber temperature during processing can be maintained at a temperature of less than or about 100°C, less than or about 90°C, less than or about 80°C, less than or about 70°C, less than or about 60°C, less than or about 50°C, and in some embodiments, the temperature can be maintained at less than or about 40°C, less than or about 30°C, less than or about 20°C, less than or about 10°C, less than or about 0°C, less than or about -10°C, less than or about -20°C, less than or about -30°C, or less. Maintaining the substrate, pedestal, or chamber temperature at a lower relative humidity can minimize damage to semiconductor structure 400, such as damage to the sidewalls and / or bottom surface of aperture 440 in mask material 420 during removal of boron-containing material 425. However, as the temperature decreases, the etch rate can decrease and the overall throughput can increase. Thus, the substrate, susceptor, or chamber temperature during processing may be maintained at a temperature between about -30°C and about 100°C.

[0057] During method 300, the pressure in the processing chamber can be controlled. For example, the pressure in the processing chamber can be maintained at less than or about 1 Torr. In addition, in an embodiment, the pressure in the processing chamber can be maintained at less than 750 mTorr or about 750 mTorr, less than 500 mTorr or about 500 mTorr, less than 250 mTorr or about 250 mTorr, less than 100 mTorr or about 100 mTorr, less than 80 mTorr or about 80 mTorr, less than 60 mTorr or about 60 mTorr, less than 50 mTorr or about 50 mTorr, less than 40 mTorr or about 40 mTorr, less than 30 mTorr or about 30 mTorr, less than 20 mTorr or about 20 mTorr or less, although the pressure can also be included in the range between any two of these claimed numbers or in any smaller range encompassed by any claimed range. The pressure may affect the uniformity of the removal. For example, as the pressure increases, the removal of the boron-containing material 425 becomes less uniform. Additionally, as the pressure decreases, such as below 1 mTorr, the plasma density may also decrease. At lower plasma densities, the removal rate may decrease and throughput time may be reduced.

[0058] In the foregoing description, for the purpose of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be implemented without some of these details, or with additional details.

[0059] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative configurations, and equivalent elements may be used without departing from the spirit of the embodiments. In addition, many well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be taken as limiting the scope of the present technology. In addition, methods or processes may be described as sequential or step-by-step, but it should be understood that the operations may be performed simultaneously or in an order different from that listed.

[0060] Where a numerical range is provided, it is understood that unless the context clearly dictates otherwise, every intervening value (to the smallest fraction of the unit of the lower limit) between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any declared value or undeclared intervening value in the declared range and any other declared value or intervening value in that declared range is contemplated. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range in which either, neither, or both of the upper and lower limits are included in the smaller range is also encompassed within the present technology, subject to any specific exclusions in the declared range. When the declared range includes one or both of the upper and lower limits, ranges excluding either or both of those included limits are also contemplated.

[0061] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors and reference to "the material" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0062] Furthermore, when used in this specification and the claims that follow, the words “comprise,” “comprising,” “contain,” “containing,” “include,” and “including” are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. A semiconductor processing method, comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is received within the processing region, and wherein the substrate comprises a boron-containing material overlying a carbon-containing material; generating a plurality of plasma effluents of the fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor; and The boron-containing material is removed from the substrate.

2. The semiconductor processing method of claim 1, wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF3).

3. The semiconductor processing method of claim 1, wherein the boron-containing material is characterized by a boron content greater than or about 20 at. %.

4. The semiconductor processing method of claim 1, wherein the boron-containing material further comprises nitrogen.

5. The semiconductor processing method of claim 1 wherein the boron-containing material and the carbon-containing material define at least one aperture extending through both the boron-containing material and the carbon-containing material.

6. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained at less than or about 100°C.

7. The semiconductor processing method of claim 1, wherein the pressure within the semiconductor processing chamber is maintained at less than or about 1 Torr.

8. The semiconductor processing method of claim 1, wherein plasma power is maintained at greater than or about 1,000 W while generating the plasma effluent of the fluorine-containing precursor.

9. The semiconductor processing method of claim 1, wherein the The boron-containing material is removed from the substrate at a rate of 1:1 / min.

10. The semiconductor processing method of claim 1, wherein the boron-containing material is removed relative to the carbon-containing material at a selectivity of greater than or about 10:

1.

11. A semiconductor processing method, comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is received within the processing region, wherein the substrate comprises a boron-containing material overlying a carbon-containing hardmask material, and wherein the boron-containing material and the carbon-containing hardmask material define at least one orifice extending through both the boron-containing material and the carbon-containing hardmask material; generating a plurality of plasma effluents of the fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor; and The boron-containing material is removed from the substrate.

12. The semiconductor processing method of claim 11, wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF3).

13. The semiconductor processing method of claim 11, wherein the flow rate of the fluorine-containing precursor is less than or about 1,000 seem.

14. The semiconductor processing method of claim 11, wherein the boron-containing material is characterized by a thickness greater than or about 250 nm.

15. The semiconductor processing method of claim 11, wherein the fluorine-containing precursor is provided to the processing region of the semiconductor processing chamber in the absence of a carrier gas.

16. The semiconductor processing method of claim 11, further comprising: Prior to providing the fluorine-containing precursor, the carbon-containing hardmask material is etched to form the at least one opening extending through the carbon-containing hardmask material.

17. The semiconductor processing method of claim 16, wherein removing the boron-containing material from the substrate is performed in the same semiconductor processing chamber as etching the carbon-containing hardmask material.

18. A semiconductor processing method, comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF3), wherein a substrate is contained within the processing region, and wherein the substrate comprises a boron-containing material overlying a carbon-containing material; generating a plurality of plasma effluents of the fluorine-containing precursor, wherein a plasma power is maintained between about 500 W and about 3,000 W while generating the plasma effluents of the fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor; and The boron-containing material is removed from the substrate.

19. The semiconductor processing method of claim 18, wherein the boron-containing material is removed from the substrate in less than or about 10 minutes.

20. The semiconductor processing method of claim 18, wherein: The carbonaceous material defines at least one pore; and Removing the boron-containing material from the substrate maintains a plurality of sidewalls and a bottom surface of the at least one aperture.

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