Programmable erasable non-volatile memory cell

Abstract

The invention discloses a programmable and erasable nonvolatile memory cell. The programmable and erasable nonvolatile memory cell comprises a well region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region and a third merged doped region, the first merged doped region is located on a first side of the first gate structure. The second merged doped region is located between a second side of the first gate structure and a first side of the second gate structure. The third merged doped region is located on a second side of the second gate structure. The first merged doped region, the first gate structure and the second merged doped region form a selection transistor. The second merged doped region, the second gate structure and the third merged doped region form a floating gate transistor.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory unit, and in particular to a programmable and erasable non-volatile memory unit. Background Art

[0002] As we all know, non-volatile memory (MVM) has been widely used in various electronic products, such as SD cards and solid-state drives (SSDs). Basically, a programmable and erasable non-volatile memory includes a memory array, which contains multiple programmable and erasable non-volatile memory cells.

[0003] For example, each programmable and erasable memory cell contains a floating gate transistor. The floating gate of the floating gate transistor can store hot carriers, and the amount of hot carriers stored determines the storage state of the floating gate transistor. For example, hot carriers are electrons or holes.

[0004] Please refer to Figure 1 , which shows a conventional programmable and erasable non-volatile memory cell. Figure 2 for Figure 1 A cross-sectional view of a programmable and erasable nonvolatile memory cell along the dashed line AB. This programmable and erasable nonvolatile memory cell is disclosed in US Pat. No. 11,049,564 B2. The programmable and erasable nonvolatile memory cell is referred to as memory cell 450 hereinafter.

[0005] The memory cell 450 includes two p-type transistors connected in series in an N-type well region NW. The N-type well region NW includes three p-type doped regions 451, 452, and 453. Two polysilicon gates 454 and 455 are located above the surface between the three p-type doped regions 451, 452, and 453.

[0006] The first p-type transistor is a selection transistor M S , including a selection gate 454, a p-type doping region 451 and a p-type doping region 452. The p-type doping region 451 is connected to a source line SL1.

[0007] The second p-type transistor is a floating gate transistor M F , including a floating gate 455, a p-type doping region 452 and a p-type doping region 453. The p-type doping region 453 is connected to a bit line BL1.

[0008] Furthermore, floating gate 455 extends outward through n-type well region NW and p-type well region PW, overlying n-type doped region 456 to form an erase gate region. N-type doped region 456 is connected to an erase line EL1. Furthermore, a p-type well barrier region PWBLK can be selectively formed between p-type well region PW and n-type doped region 456.

[0009] like Figure 2 As shown, a gate dielectric layer 464 is located below the select gate 454 and contacts the surface of the N-type well region NW. Similarly, a gate dielectric layer 465 is located below the floating gate 455. Furthermore, a memory cell 450 is formed on a semiconductor substrate Sub. The memory cell 450 is surrounded by an isolation structure 401, and the bottom of the memory cell 450 contacts the semiconductor substrate Sub. For example, the N-type well region NW, the P-type well region PW, and the P-type well barrier region PWBLK contact the semiconductor substrate Sub, and the isolation structure 401 is a shallow trench isolation structure (STI).

[0010] In addition, by providing appropriate bias voltages to the source line SL1, the erase line EL1, the bit line BL1, and the select gate 454, the memory cell 450 can be programmed, erased, or read. For example, during programming, the memory cell 450 receives a program voltage, causing electrons to be transferred from the floating gate transistor M1 to the memory cell 450. F During the erasing operation, the memory cell 450 receives an erase voltage, causing electrons to be ejected from the floating gate 455 to the n-type doped region 456 and then leave the floating gate transistor M through the erase line EL1. F The erase voltage is greater than the programming voltage. For example, the erase voltage is approximately between 14V and 19V, and the programming voltage is approximately between 7.5V and 9V.

[0011] As is well known, current CMOS manufacturing processes can produce input / output devices (IO devices) with higher voltage tolerances and core devices with lower voltage tolerances on a single semiconductor substrate. Core devices are referred to as low-voltage devices (LV devices), such as low-voltage P-type transistors (LV P-type transistors) and low-voltage N-type transistors (LV N-type transistors). Input / output devices are referred to as medium-voltage devices (MV devices), such as medium-voltage P-type transistors (MV P-type transistors) and medium-voltage N-type transistors (MV N-type transistors). Low-voltage devices have thinner gate dielectric layers, resulting in faster operation speeds but lower voltage stress tolerance. Medium-voltage devices have thicker gate dielectric layers, allowing them to withstand higher voltage stresses but slower operation speeds.

[0012] Since the existing memory cell 450 needs to receive a high voltage, the selection transistor M in the memory cell 450 S With floating gate transistor M F All are medium voltage components. That is to say, when designing the memory cell 450, it is necessary to comply with the design rules of medium voltage components. For example, the channel length (Lg) of the transistor of the medium voltage component is at least 0.45μm. In addition, in order to prevent the PN junction from being punched through, the concentration of the P-type well region PW is low, and the length of the P-type well region PW must be at least 0.8μm. In other words, the length Lw of the isolation structure 401 above the P-type well region PW must be at least greater than 0.8μm, and the length of the floating gate 455 extending outward is longer. For example, the channel length Lg is designed to be 0.55μm, and the length Lw of the isolation structure 401 is designed to be 1.3μm.

[0013] As can be seen from the above description, due to the design specifications of the medium voltage device and the extended floating gate 455, the size of the conventional memory cell 450 will be too large. Summary of the Invention

[0014] The present invention relates to a programmable and erasable non-volatile memory cell, comprising: a first well region formed below the surface of a semiconductor substrate; a first gate structure and a second gate structure formed in the first well region; a first spacer and a second spacer, the first spacer contacting the sidewall of the first gate structure, the second spacer contacting the sidewall of the second gate structure; a first merged doped region, a second merged doped region and a third merged doped region formed in the first well region; wherein the first merged doped region is located on a first side of the first gate structure, the second merged doped region is located between a second side of the first gate structure and a first side of the second gate structure, and the third merged doped region is located on the second gate structure. a second side of the gate structure; a metal layer located above the second gate structure, with a vertical projection of the metal layer covering the second gate structure; a source line electrically connected to the first merged doped region; a select gate line electrically connected to the first gate structure; a bit line electrically connected to the third merged doped region; an auxiliary line electrically connected to the metal layer; and a flat plate capacitor, a first end of the flat plate capacitor electrically connected to the metal layer, and a second end of the flat plate capacitor electrically connected to the second gate structure; wherein the first merged doped region, the first gate structure and the second merged doped region form a select transistor; and the second merged doped region, the second gate structure and the third merged doped region form a floating gate transistor.

[0015] In order to better understand the above and other aspects of the present invention, preferred embodiments are described in detail below with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a conventional programmable and erasable non-volatile memory cell;

[0017] Figure 2 for Figure 1 A cross-sectional view of the programmable and erasable non-volatile memory cell along the dashed line AB;

[0018] Figures 3A to 3I A flowchart of manufacturing a programmable and erasable non-volatile memory cell according to the first embodiment;

[0019] Figure 3J An equivalent circuit diagram of a programmable and erasable non-volatile memory cell;

[0020] Figure 3K A schematic diagram of a bias table for programming, erasing, and reading operations of a memory cell according to the first embodiment;

[0021] Figure 3L Schematic diagram of the operation of programming the memory cell according to the first embodiment;

[0022] Figure 3M Schematic diagram of the operation of erasing the memory cell according to the first embodiment;

[0023] Figure 3N Schematic diagram of the operation of erasing the memory cell according to the first embodiment;

[0024] Figure 3O This is a schematic diagram of the operation of the memory cell performing a read operation according to the first embodiment;

[0025] Figure 4 is a schematic diagram of a memory cell structure according to a second embodiment;

[0026] Figure 5 is a schematic diagram of a storage unit structure according to a third embodiment;

[0027] Figure 6 is a schematic diagram of a memory cell structure according to a fourth embodiment;

[0028] Figure 7 is a schematic diagram of a memory cell structure according to a fifth embodiment; and

[0029] Figure 8 FIG. 4 is a schematic diagram of a memory cell structure according to a sixth embodiment.

[0030] Explanation of symbols

[0031] 401,502:Isolation structure

[0032] 450: Storage unit

[0033] 451, 452, 453: p-type doped regions

[0034] 454: Select gate

[0035] 455: floating gate

[0036] 456: n-type doped region

[0037] 464,465,503,505,507: Gate dielectric layer

[0038] 513,515,517: Polysilicon gate layer

[0039] 523,525,527: Gate structure

[0040] 540,550:Mask

[0041] 541,542,551,552,612,622,624,631,632,633: p-type lightly doped drain region

[0042] 548,558,559: interstitial wall

[0043] 561,562,563: p-type ion implantation area

[0044] 571,572,573,576,577,578,652,672,681,682: Merged p-type doped regions

[0045] 580:Metal layer

[0046] 602: barrier layer

[0047] 604: polysilicon layer

[0048] 606: Wire DETAILED DESCRIPTION

[0049] Since current CMOS manufacturing processes can produce medium-voltage components and low-voltage components on a single semiconductor substrate, the programmable and erasable non-volatile memory cell of the present invention utilizes the manufacturing processes of the medium-voltage component manufacturing procedure (MV production procedure) and the low-voltage component manufacturing procedure (LV production procedure). In other words, when designing the programmable and erasable non-volatile memory cell of the present invention, part of the structure utilizes the design rules of the medium-voltage component, while the other part of the structure utilizes the design rules of the low-voltage component, so as to reduce the size of the programmable and erasable non-volatile memory cell of the present invention and reduce the programming voltage and erase voltage of the memory cell. The following introduces various embodiments of the present invention.

[0050] Please refer to Figures 3A to 3I , which illustrates a manufacturing flow chart of a programmable and erasable non-volatile memory cell according to a first embodiment of the present invention. Figure 3J 1 is an equivalent circuit diagram of a programmable and erasable non-volatile memory cell. In the following description, the programmable and erasable non-volatile memory cell is referred to as a memory cell.

[0051] like Figure 3A As shown, an isolation structure 502 is formed on the semiconductor substrate sub, defining regions A and B. That is, the semiconductor substrate sub is covered by the isolation structure 502, with only regions A and B exposing the surface of the semiconductor substrate sub. Next, a well region formation step is performed to form a first well region, such as an N-type well region NW, below regions A and B on the surface of the substrate sub. According to the first embodiment of the present invention, a memory cell is formed in each of regions A and B.

[0052] Next, the gate structure forming step is performed. Figure 3BAs shown, three gate structures 523, 525, and 527 are formed above the surface of the N-type well region NW. Gate structure 523 includes a gate dielectric layer 503 and a polysilicon gate layer 513. Gate structure 525 includes a gate dielectric layer 505 and a polysilicon gate layer 515. Gate structure 527 includes a gate dielectric layer 507 and a polysilicon gate layer 517. The gate dielectric layers 503, 505, and 507 are in contact with the N-type well region, and the polysilicon gate layers 513, 515, and 517 are in contact with the gate dielectric layers 503, 505, and 507, respectively.

[0053] Gate structure 525 is formed above the surface of region A, and gate structure 527 is formed above the surface of region B. Gate structures 525 and 527 do not contact each other. Furthermore, gate structure 523 is formed above the surface of region A and extends outward through the surface of isolation structure 502 to above the surface of region B. Therefore, gate structure 525 and gate structure 523 divide the surface of region A into three sub-regions, and gate structure 527 and gate structure 523 divide the surface of region B into three sub-regions. In other words, two memory cells share gate structure 523.

[0054] Furthermore, polysilicon gate layer 515 serves as the floating gate of the floating gate transistor, polysilicon gate layer 517 serves as the floating gate of the floating gate transistor, and polysilicon gate layer 513 serves as the select gate of the select transistor. That is, in two memory cells, the select gates of the two select transistors are connected to each other, while the floating gates of the two floating gate transistors are not connected to each other.

[0055] According to the first embodiment of the present invention, the channel length L of the floating gate transistor is F Less than the channel length L of the select transistor S , that is, L F <L S For example, the channel length L of the transistor is selected S The channel length L of the floating gate transistor is 0.55 μm. F 0.35μm.

[0056] like Figure 3C As shown, a mask 540, indicated by a dotted line, first covers the gate structure 525 and its two side regions in region A, exposing the gate structure 523 and its two side regions. Similarly, the mask 540 also covers the gate structure 527 and its two side regions in region B, exposing the gate structure 523 and its two side regions (not shown). The mask 540 is a photoresist.

[0057] Taking region A as an example, only a portion of the surface between gate structure 523 and gate structure 525 is covered by mask 540, while the other portion is not. Then, using a lightly doped drain process (LDD process) in the high-voltage device fabrication process, p-type lightly doped drain regions (p-LDD regions) 541 and 542 are formed below the sub-surface of the semiconductor substrate not covered by mask 540. The p-LDD regions 541 and 542 are located below the surface of region A, respectively. The doping concentrations of the p-LDD regions 541 and 542 on both sides of the gate structure 523 are equal, and the doping depths of the p-LDD regions 541 and 542 are equal.

[0058] like Figure 3D As shown, after removing the mask 540, the gate structure 523 and the areas on both sides of it in area A are covered with a mask 550 shown by a dotted line. The mask 550 is a photoresist. That is, the area previously covered by the mask 540 is exposed. Then, using the lightly doped drain manufacturing process in the low-voltage component manufacturing process, p-type lightly doped drain regions 551 and 552 are formed on the sub surface of the semiconductor substrate not covered by the mask 550. The p-type lightly doped drain regions 551 and 552 are respectively located below the surface of area A. The doping concentrations of the p-type lightly doped drain regions 551 and 552 on both sides of the gate structure 525 will be equal, and the doping depths of the p-type lightly doped drain regions 551 and 552 will be equal.

[0059] In addition, the distance between the p-type lightly doped drain region 541 and the p-type lightly doped drain region 542 is L S , used as a channel for selecting transistors. The distance between the p-type lightly doped drain region 551 and the p-type lightly doped drain region 552 is L F , used as the channel of the floating gate crystal. In this embodiment, the channel L of the floating gate crystal F Smaller than the channel L of the selector transistor S , that is, L F <L S .

[0060] According to an embodiment of the present invention, the first lightly doped drain manufacturing process is part of the high-voltage component manufacturing procedure, and the second lightly doped drain manufacturing process is part of the low-voltage component manufacturing procedure, so the doping concentration of the p-type lightly doped drain regions 541 and 542 will be lower than the doping concentration of the p-type lightly doped drain regions 551 and 552, and the doping depth of the p-type lightly doped drain regions 541 and 542 will be deeper than the doping depth of the p-type lightly doped drain regions 551 and 552.

[0061] like Figure 3E As shown, after removing the mask 550 , spacers 548 are formed on the sidewalls of the gate structure 523 , and spacers 558 are formed on the sidewalls of the gate structure 525 . The spacers 548 contact the sidewalls of the gate structure 523 , and the spacers 558 contact the sidewalls of the gate structure 525 .

[0062] Then, if Figure 3F As shown, a p-type ion implantation process is performed on the substrate sub-surface using the two gate structures 523, 525 and the spacers 548, 558 as a mask. Therefore, the three sub-regions in region A not covered by the two gate structures 523, 525 and the spacers 548, 558 form p-type ion implantation regions 561, 562, and 563, shown as three shaded areas. Essentially, the p-type ion implantation regions 561, 562, and 563 have the highest doping concentration, exceeding the doping concentration of all lightly doped drain regions 541, 542, 551, and 552.

[0063] like Figure 3F As shown, the p-type lightly doped drain region 541 and the p-type ion implanted region 561 form a merged p-doped region 571, located below the surface of the first side of the gate structure 523. The p-type lightly doped drain regions 542 and 551 and the p-type ion implanted region 562 form a merged p-doped region 572, located below the surface between the second side of the gate structure 523 and the first side of the gate structure 525. The p-type lightly doped drain region 552 and the p-type ion implanted region 563 form a merged p-doped region 573, located below the surface of the second side of the gate structure 525. In addition, the p-type lightly doped drain region 541 is located below the spacer 548 on the first side of the gate structure 523, the p-type lightly doped drain region 542 is located below the spacer 548 on the second side of the gate structure 523, the p-type lightly doped drain region 551 is located below the spacer 558 on the first side of the gate structure 525, and the p-type lightly doped drain region 552 is located below the spacer 558 on the second side of the gate structure 525.

[0064] Therefore, in the A region, the gate structure 523 and the merged n-type doped regions 571 and 572 on its two sides form a selection transistor M. S1 The gate structure 525 and the merged n-type doped regions 572 and 573 on its two sides form a floating gate transistor M. F1 In this embodiment, the floating gate transistor M F1 and select transistor M S1 It is a p-type transistor fabricated in the N-type well region NW. That is, the floating gate transistor M F1 and select transistor MS1 The body terminal is connected to the N-type well region NW.

[0065] in addition, Figure 3G for Figure 3F 3D view of the structure. In region B, spacers 559 are formed on the sidewalls of gate structure 527. Furthermore, a merged p-type doped region 576 is located below the surface of the first side of gate structure 523. A merged p-type doped region 577 is located below the surface between the second side of gate structure 523 and the first side of gate structure 527. A merged p-type doped region 578 is located below the surface of the second side of gate structure 527. Similarly, a floating gate transistor and a select transistor are also formed in region B.

[0066] Then, if Figure 3H As shown, a metal layer 580 is further formed above the polysilicon gate layers 515 and 517. The size of the metal layer 580 is greater than or equal to the polysilicon gate layers 515 and 517, so that the vertical projection of the metal layer 580 can completely cover the polysilicon gate layer 515 of the gate structure 525 and the polysilicon gate layer 517 of the gate structure 527. Of course, in other embodiments, the size of the metal layer 580 can also be designed to be smaller than the polysilicon gate layers 515 and 517, so that the vertical projection of the metal layer 580 covers the upper portion of the polysilicon gate layer 515 of the gate structure 525 and the polysilicon gate layer 517 covering the upper portion of the gate structure 527. Therefore, the polysilicon gate layer 515 and the metal layer 580 form a metal / poly plate capacitor, and the polysilicon gate layer 517 and the metal layer 580 form another metal / poly plate capacitor. Furthermore, a wire connection step is performed to complete the two memory cells of the present invention. In addition, Figure 3I for Figure 3H Cross-section of a storage unit.

[0067] like Figure 3H and Figure 3I As shown, merged p-type doped region 571 is connected to source line SL, merged p-type doped region 573 is connected to bit line BL1, polysilicon gate layer 513 is connected to select gate line SG, and metal layer 580 is connected to assist line (AG). In addition, merged p-type doped region 576 is connected to source line SL, and merged p-type doped region 578 is connected to bit line BL2.

[0068] like Figure 3J As shown, storage unit C ELL1 A selection transistor M is included S1 , a floating gate transistor M F1 、A plate capacitor C1. Select transistor MS1 The gate terminal of the transistor M is connected to a selection gate line SG. S1 The first drain / source terminal of the floating gate transistor M is connected to the source line SL. F1 The first drain / source terminal is connected to the selection transistor M S1 The second drain / source terminal of the floating gate transistor M F1 The second drain / source terminal of the panel capacitor C1 is connected to the bit line BL1. Furthermore, the first terminal of the panel capacitor C1 is connected to the floating gate transistor M F1 The floating gate 515 of the memory cell C1 is connected to the auxiliary line AG. ELL2 A selection transistor M is included S2 , a floating gate transistor M F2 、A plate capacitor C2. Select transistor M S2 The gate terminal of the transistor M is connected to a selection gate line SG. S2 The first drain / source terminal of the floating gate transistor M is connected to the source line SL. F2 The first drain / source terminal is connected to the selection transistor M S2 The second drain / source terminal of the floating gate transistor M F2 The second drain / source terminal of the panel capacitor C2 is connected to the bit line BL2. Furthermore, the first terminal of the panel capacitor C2 is connected to the floating gate transistor M F2 The floating gate 517 of the panel capacitor C1 is connected to the auxiliary line AG. The second end of the panel capacitor C2 is connected to the auxiliary line AG. The panel capacitors C1 and C2 are both metal / polysilicon panel capacitors.

[0069] From the above description, it can be seen that the memory cell C of the first embodiment of the present invention ELL1 By two transistors M F1 、M S1 The memory cell is composed of a flat-plate capacitor C1, which is called a 2T1C memory cell. The flat-plate capacitor C1 acts as a coupling capacitor, preventing hot carriers from penetrating the coupling capacitor during the erase operation.

[0070] Compared to Figure 1 The storage unit, in Figure 3H In the memory cell, the floating gate 515 does not extend to other areas. F1 The channel length L F Therefore, the size of the memory cell of the present invention can be greatly reduced, by about 50% or more. Figure 1During programming, electrons are injected into the floating gate through the channel of floating gate transistor Mf. During erasing, electrons are ejected from the floating gate to erase line EL1. However, the memory cell of the present invention does not have an erase line and therefore lacks the carrier ejection path of conventional memory cells. Therefore, the present invention employs various bias voltages to enable programming, erasing, and reading of the memory cell of the first embodiment.

[0071] Please refer to Figure 3K , which illustrates a bias table for programming, erasing, and reading operations of a memory cell according to the first embodiment of the present invention. Figure 3L FIG. 1 is a schematic diagram illustrating the operation of programming a memory cell according to the first embodiment of the present invention. Figure 3M FIG. 1 is a schematic diagram of an erase operation of a memory cell according to the first embodiment of the present invention. Figure 3N FIG. 1 is a schematic diagram of an erase operation of a memory cell according to the first embodiment of the present invention. Figure 3O FIG. 1 is a schematic diagram of the operation of the memory cell in the first embodiment of the present invention for performing a read operation. Figure 3K As shown, there are two biasing modes for the erase operation, which can utilize different effects to perform the erase operation. Furthermore, the N-type well region NW and the source line SL receive the same voltage.

[0072] like Figure 3K and Figure 3L As shown, during programming, the source line SL receives the programming voltage V PP , the gate line SG is selected to receive the first turn-on voltage V ON1 The bit line BL1 receives the ground voltage (0V), and the voltage received by the auxiliary line AG can be set between the ground voltage (0V) and 2 times the programming voltage (2×V PP ). Among them, the programming voltage V PP Between 6V and 7.5V, the first turn-on voltage V ON1 It can be set between ground voltage (0V) and 3 / 4 times the programming voltage (3 / 4×V PP ). Obviously, the programming voltage V PP Smaller than the programming voltage of existing memory cells.

[0073] During programming, transistor M is selected. S1 Turn on, and a programming current I is generated between the source line SL and the bit line BL1 P Therefore, when the programming current I P Hot carriers (such as holes) in the floating gate transistor M F1When the channel reaches the pinch off point, the channel hot hole induced hot electron injection effect (CHHIHE effect) occurs. F1 In the example, the junction between the combined p-type doped region 573 and the N-type well region NW generates electron-hole pairs. Electrons are attracted by the voltage received by the auxiliary gate AG, and thus are injected into the floating gate 515. The pinch point is at the floating gate transistor M. F1 The merged p-type doped region 573 is located in the channel close to the bit line BL1 side.

[0074] According to the first embodiment of the present invention, in the storage unit C ELL1 The difference between the combined p-type doping regions 571, 572, and 573 can reduce the programming voltage V PP And improve programming efficiency. Figure 3F Taking the memory cell as an example, the floating gate transistor M F1 In the embodiment, the p-type lightly doped drain regions 551 and 552 close to the two sides of the floating gate 515 have a higher concentration and a shallower depth. F1 Therefore, in the storage unit C ELL1 When programming, a lower programming voltage V PP A high electric field can be generated at the pinch point of the channel to improve programming efficiency. PP is lower, so the programming current I P It will also be smaller.

[0075] like Figure 3K and Figure 3M As shown, during the erase operation, the source line SL receives the erase voltage V EE , the gate line SG is selected to receive the second turn-on voltage V ON2 , the bit line BL1 receives the ground voltage (0V), and the voltage received by the auxiliary line AG can be set to the negative auxiliary voltage -V BB Between the ground voltage (0V), that is, the negative auxiliary voltage (-V BB ) is less than or equal to 0V, for example -V BB Equal to -5V. Among them, the erase voltage V EE Between 7V and 8V, the second turn-on voltage V ON2 Can be set between ground voltage (0V) and erase voltage V EESubtract the select transistor M S1 The threshold voltage V T (V EE -V T ). Obviously, the erase voltage V EE Smaller than the erase voltage of existing memory cells.

[0076] During the erase operation, transistor M is selected. S1 Turn on, an erase current I is generated between the source line SL and the bit line BL1 E Therefore, when the erase current I E Hot carriers (such as holes) in the floating gate transistor M F1 When the channel reaches the pinch point, the channel hot hole injection effect (CHH effect) occurs. F1 In the embodiment of FIG5 , the junction between the merged p-type doped region 573 and the N-type well region NW generates electron-hole pairs. Attracted by the voltage received by the auxiliary gate AG, the holes are injected into the floating gate 515. Thus, the electrons and holes combine on the floating gate 515 to complete the erase operation.

[0077] like Figure 3K and Figure 3N As shown, during the erase operation, the source line SL receives the erase voltage V EE , the N-type well region NW receives the erase voltage V EE , the selection gate line SG receives the off voltage V OFF , the bit line BL1 receives the ground voltage (0V), and the voltage received by the auxiliary line AG can be set to the negative auxiliary voltage -V BB Between the ground voltage (0V), that is, the negative auxiliary voltage (-V BB ) is less than or equal to 0V, for example -V BB Equal to -5V.

[0078] During the erase operation, transistor M is selected. S1 The floating gate transistor M is turned off and no erase current is generated between the source line SL and the bit line BL1. F1In the process, electron-hole pairs are generated at the junction of the merged p-type doped region 573 and the N-type well region NW, resulting in a band-to-band hot hole injection effect (BBHH). Attracted by the voltage received by the auxiliary gate AG, the holes are injected into the floating gate 515. Consequently, the electrons and holes combine on the floating gate 515 to complete the erase operation.

[0079] Similarly, in memory cell C ELL1 The difference between the combined p-type doping regions 571, 572, 573 and the floating gate transistor M F1 Therefore, in the storage unit C ELL1 When performing the erase operation, a lower erase voltage V is provided EE The erasing operation is completed.

[0080] like Figure 3K and Figure 3O As shown, during the reading operation, the source line SL receives the reading voltage V R The selection gate line SG receives the ground voltage (0V), the bit line BL1 receives the ground voltage (0V), and the voltage received by the auxiliary line AG can be set between the ground voltage (0V) and the read voltage V R For example, reading the voltage V R The erase voltage V EE Greater than the programming voltage V PP , programming voltage V PP Greater than the read voltage V R , read the voltage V R Greater than ground voltage (0V).

[0081] During the read operation, transistor M is selected. S1 Turn on, and a read current I is generated between the source line SL and the bit line BL1 R . According to the reading current I R The size of can determine the storage state of the memory cell. For example, when there is no electron stored in the floating gate 515, the reading current I R Very small, almost zero, the memory cell is in the erased state. When electrons are stored in the floating gate 515, the read current I R Larger, visible memory cell is in programming state.

[0082] Of course, those skilled in the art may also modify the memory cell structure of the first embodiment of the present invention, for example, by modifying the structure of the coupling capacitor to increase the voltage coupling ratio.

[0083] Please refer to Figure 4 , which illustrates the memory cell structure of the second embodiment of the present invention. Compared to the memory cell C of the first embodiment ELL1 , the memory cell C of the second embodiment ELLA A block layer 602, a polysilicon layer 604 and a conductive line 606 are further added. The following only introduces two memory cells C. ELL1 、C ELLA The different structures between them will not be described in detail.

[0084] like Figure 4 As shown, in the storage unit C ELLA In the embodiment, the gate structure 525 and the spacer 558 are covered by a barrier layer 602. For example, the barrier layer 602 is a metal silicide block layer (SAB). Furthermore, a polysilicon layer 604 is formed on the upper surface of the barrier layer 602. In addition, a conductive line 606 is formed between the metal layer 580 and the polysilicon layer 604, and the conductive line 606 is electrically connected to the metal layer 580 and the polysilicon layer 604. Therefore, the polysilicon layer 604 and the polysilicon gate layer (floating gate) 515 form a polysilicon / polysilicon planar capacitor. Since the distance between the two polysilicon layers 604 and 515 is relatively short, the voltage coupling ratio of the coupling capacitor can be effectively improved.

[0085] In addition, those skilled in the art may also modify the structure of the merged p-type doping regions 571 , 572 , and 573 of the memory cell in the first embodiment of the present invention to form a memory cell in other embodiments.

[0086] Please refer to Figure 5 , which illustrates the memory cell structure of the third embodiment of the present invention. Compared with the memory cell of the first embodiment, the difference lies in the structure of merging the p-type doping regions 571, 652, and 573. The following only introduces two memory cells C ELL1 、C ELLB The different structures between them will not be described in detail.

[0087] like Figure 5 As shown, the p-type lightly doped drain region 541 and the p-type ion implanted region 561 form a merged p-type doped region 571, located below the surface of the first side of the gate structure 523. The p-type lightly doped drain regions 542 and 612 and the p-type ion implanted region 562 form a merged p-type doped region 652, located below the surface between the second side of the gate structure 523 and the first side of the gate structure 525. The p-type lightly doped drain region 552 and the p-type ion implanted region 563 form a merged p-type doped region 573, located below the surface of the second side of the gate structure 525.

[0088] According to the third embodiment of the present invention, the p-type lightly doped drain region 552 is fabricated using a lightly doped drain fabrication process within a low-voltage device fabrication process, while the p-type lightly doped drain regions 541, 542, and 612 are fabricated using a lightly doped drain fabrication process within a high-voltage device fabrication process. Therefore, the doping concentrations of the p-type lightly doped drain regions 541, 542, and 612 are equal, and the doping concentration of the p-type lightly doped drain region 552 is greater than the doping concentration of the p-type lightly doped drain region 541. Furthermore, the doping depths of the p-type lightly doped drain regions 541, 542, and 612 are equal, and the doping depth of the p-type lightly doped drain region 541 is greater than the doping depth of the p-type lightly doped drain region 552.

[0089] Please refer to Figure 6 , which illustrates the memory cell structure of the fourth embodiment of the present invention. Compared with the memory cell of the first embodiment, the difference lies in the structure of merging the p-type doping regions 571, 672, and 573. The following only introduces two memory cells C ELL1 、C ELLC The different structures between them will not be described in detail.

[0090] like Figure 6 As shown, the p-type lightly doped drain region 541 and the p-type ion implanted region 561 form a merged p-type doped region 571, located below the surface of the first side of the gate structure 523. The p-type lightly doped drain regions 622 and 624 and the p-type ion implanted region 562 form a merged p-type doped region 672, located below the surface between the second side of the gate structure 523 and the first side of the gate structure 525. The p-type lightly doped drain region 552 and the p-type ion implanted region 563 form a merged p-type doped region 573, located below the surface of the second side of the gate structure 525.

[0091] According to the fourth embodiment of the present invention, the p-type lightly doped drain region 541 is fabricated using a lightly doped drain fabrication process within a high-voltage device fabrication process, while the p-type lightly doped drain regions 622, 624, and 552 are fabricated using a lightly doped drain fabrication process within a low-voltage device fabrication process. Therefore, the doping concentrations of the p-type lightly doped drain regions 622, 624, and 552 are equal, and the doping concentration of the p-type lightly doped drain region 552 is greater than the doping concentration of the p-type lightly doped drain region 541. Furthermore, the doping depths of the p-type lightly doped drain regions 622, 624, and 552 are equal, and the doping depth of the p-type lightly doped drain region 541 is greater than the doping depth of the p-type lightly doped drain region 552.

[0092] Please refer to Figure 7 , which illustrates the memory cell structure of the fifth embodiment of the present invention. Compared with the memory cell of the first embodiment, the difference lies in the structure of merging the p-type doping regions 681, 682, and 573. The following only introduces two memory cells CELL1 、C ELLD The different structures between them will not be described in detail.

[0093] like Figure 7 As shown, the p-type lightly doped drain region 631 and the p-type ion implanted region 561 form a merged p-type doped region 681, located below the surface of the first side of the gate structure 523. The p-type lightly doped drain regions 632, 633 and the p-type ion implanted region 562 form a merged p-type doped region 682, located below the surface between the second side of the gate structure 523 and the first side of the gate structure 525. The p-type lightly doped drain region 552 and the p-type ion implanted region 563 form a merged p-type doped region 573, located below the surface of the second side of the gate structure 525.

[0094] According to the fifth embodiment of the present invention, the p-type lightly doped drain regions 631, 632, 633, and 552 are fabricated using a lightly doped drain fabrication process within a low-voltage device fabrication process. Therefore, the p-type lightly doped drain regions 631, 632, 633, and 552 have equal doping concentrations and doping depths.

[0095] Basically, the memory cell C of the second to fifth embodiments ELLA 、C ELLB 、C ELLC 、C ELLD The equivalent circuit is the same as Figure 3J Storage cell C in ELL1 , no further details will be given here. Of course, the memory cell C of the second embodiment to the fifth embodiment ELLA 、C ELLB 、C ELLC 、C ELLD Also refer to Figures 3K to 3O The bias voltage is used to perform programming, erasing and reading operations.

[0096] In addition, in the memory cell C of the first embodiment ELL1 In the floating gate transistor M F1 and select transistor M S1 have the same channel width. Those skilled in the art can also design floating gate transistors M F1 and select transistor M S1 For example, the design of floating gate transistor M F1 The channel width is smaller than the selection transistor M S1 channel width.

[0097] In addition, those skilled in the art can also modify the structure of the storage unit in the first embodiment. For example, Figure 8 , which illustrates the memory cell structure of the sixth embodiment of the present invention. In the sixth embodiment, a deep N-well region (DNW) is further configured between the semiconductor substrate Sub and the N-well region NW. The bottom of the deep N-well region DNW contacts the semiconductor substrate Sub, and the top of the deep N-well region DNW contacts the N-well region NW.

[0098] In summary, although the present invention has been disclosed above with reference to preferred embodiments, these are not intended to limit the present invention. Persons skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A programmable and erasable non-volatile memory cell, comprising: A first well region is formed below the surface of the semiconductor substrate; A first gate structure and a second gate structure are formed in the first well region; a first spacer and a second spacer, wherein the first spacer contacts the sidewall of the first gate structure, and the second spacer contacts the sidewall of the second gate structure; A first merged doped region, a second merged doped region, and a third merged doped region are formed in the first well region; wherein the first merged doped region is located on a first side of the first gate structure, the second merged doped region is located between a second side of the first gate structure and a first side of the second gate structure, and the third merged doped region is located on a second side of the second gate structure; a metal layer, located above the second gate structure, and a vertical projection of the metal layer covers the second gate structure; a source line electrically connected to the first merged doped region; a select gate line electrically connected to the first gate structure; a bit line electrically connected to the third merged doped region; an auxiliary line electrically connected to the metal layer; and a flat plate capacitor, a first terminal of the flat plate capacitor being electrically connected to the metal layer, and a second terminal of the flat plate capacitor being electrically connected to the second gate structure; The first merged doping region, the first gate structure and the second merged doping region form a selection transistor; and the second merged doping region, the second gate structure and the third merged doping region form a floating gate transistor.

2. The programmable and erasable non-volatile memory cell according to claim 1, wherein a channel length of the floating gate transistor is smaller than a channel length of the select transistor. 3 . The programmable and erasable non-volatile memory cell according to claim 2 , wherein a channel width of the floating gate transistor is smaller than a channel width of the select transistor.

4. The programmable and erasable non-volatile memory cell according to claim 1 , wherein the first gate structure comprises a first gate dielectric layer and a first polysilicon gate layer, and the second gate structure comprises a second gate dielectric layer and a second polysilicon gate layer, the first gate dielectric layer and the second gate dielectric layer contact the first well region, the first polysilicon gate layer contacts the first gate dielectric layer, and the second polysilicon gate layer contacts the second gate dielectric layer.

5. The programmable and erasable non-volatile memory cell according to claim 4 , further comprising: a barrier layer covering the second gate structure and the second spacer; a polysilicon layer formed on an upper surface of the barrier layer; as well as a conductive line electrically connecting the polysilicon layer and the metal layer; The second polysilicon gate layer and the polysilicon layer form the flat plate capacitor, and the flat plate capacitor is a polysilicon / polysilicon flat plate capacitor. 6 . The programmable and erasable non-volatile memory cell according to claim 4 , wherein the metal layer and the second polysilicon gate layer form the planar capacitor, and the planar capacitor is a metal / polysilicon planar capacitor.

7. The programmable and erasable non-volatile memory cell according to claim 4 , wherein during programming, the source line receives a programming voltage, the select gate line receives a first turn-on voltage, the bit line receives a ground voltage, and the auxiliary line receives a voltage set between the ground voltage and twice the programming voltage; During the programming operation, a channel hot hole induced hot electron injection effect occurs, and a plurality of electrons are attracted by the voltage received by the auxiliary gate and injected into the first polysilicon gate layer of the first gate structure.

8. The programmable and erasable non-volatile memory cell according to claim 4 , wherein during an erase operation, the source line receives an erase voltage, the select gate line receives a second turn-on voltage, the bit line receives a ground voltage, and the auxiliary line receives a voltage less than or equal to the ground voltage; During the erase process, a channel hot hole injection effect occurs, and a plurality of holes are attracted by the voltage received by the auxiliary gate and injected into the first polysilicon gate layer of the first gate structure.

9. The programmable and erasable non-volatile memory cell according to claim 4, wherein during an erase operation, the source line receives an erase voltage, the select gate line receives a turn-off voltage, the bit line receives a ground voltage, and the auxiliary line receives a voltage less than or equal to the ground voltage; During the erase process, an inter-band hot hole injection effect occurs, and a plurality of holes are attracted by the voltage received by the auxiliary gate and injected into the first polysilicon gate layer of the first gate structure.

10. The programmable and erasable non-volatile memory cell according to claim 4 , wherein during a read operation, the source line receives a read voltage, the select gate line receives a ground voltage, the bit line receives the ground voltage, and the auxiliary line receives a voltage set between the read voltage and the ground voltage; During the reading operation, a reading current is generated between the source line and the bit line, and the storage state is determined according to the magnitude of the reading current.

11. The programmable and erasable non-volatile memory cell according to claim 1 , wherein the first merged doped region comprises a first ion implanted region and a first lightly doped drain region, the second merged doped region comprises a second ion implanted region, a second lightly doped drain region, and a third lightly doped drain region, and the third merged doped region comprises a third ion implanted region and a fourth lightly doped drain region; wherein, The first lightly doped drain region is located below the first spacer on the first side of the first gate structure, the second lightly doped drain region is located below the first spacer on the second side of the first gate structure, the third lightly doped drain region is located below the second spacer on the first side of the second gate structure, and the fourth lightly doped drain region is located below the second spacer on the second side of the second gate structure. 12 . The programmable and erasable non-volatile memory cell according to claim 11 , wherein a first distance between the first lightly doped drain region and the second lightly doped drain region is greater than a second distance between the third lightly doped drain region and the fourth lightly doped drain region.

13. The programmable and erasable non-volatile memory cell according to claim 11, wherein the first lightly doped drain region, the second lightly doped drain region, the third lightly doped drain region, and the fourth lightly doped drain region are fabricated using a lightly doped drain fabrication process in a low voltage device fabrication procedure.

14. The programmable and erasable non-volatile memory cell according to claim 11, wherein the doping depth of the first lightly doped drain region is equal to the doping depth of the second lightly doped drain region, the doping depth of the third lightly doped drain region is equal to the doping depth of the fourth lightly doped drain region, and the doping depth of the first lightly doped drain region is deeper than the doping depth of the fourth lightly doped drain region.

15. The programmable and erasable non-volatile memory cell according to claim 14, wherein the doping concentration of the first lightly doped drain region is equal to the doping concentration of the second lightly doped drain region, the doping concentration of the third lightly doped drain region is equal to the doping concentration of the fourth lightly doped drain region, and the doping concentration of the first lightly doped drain region is less than the doping concentration of the fourth lightly doped drain region.

16. The programmable and erasable non-volatile memory cell according to claim 11, wherein the doping depth of the first lightly doped drain region is equal to the doping depth of the second lightly doped drain region, the doping depth of the second lightly doped drain region is equal to the doping depth of the third lightly doped drain region, and the doping depth of the first lightly doped drain region is deeper than the doping depth of the fourth lightly doped drain region.

17. The programmable and erasable non-volatile memory cell of claim 16, wherein the doping concentration of the first lightly doped drain region is equal to the doping concentration of the second lightly doped drain region, the doping concentration of the second lightly doped drain region is equal to the doping concentration of the third lightly doped drain region, and the doping concentration of the first lightly doped drain region is less than the doping concentration of the fourth lightly doped drain region.

18. The programmable and erasable non-volatile memory cell according to claim 11, wherein the doping depth of the second lightly doped drain region is equal to the doping depth of the third lightly doped drain region, the doping depth of the third lightly doped drain region is equal to the doping depth of the fourth lightly doped drain region, and the doping depth of the first lightly doped drain region is deeper than the doping depth of the fourth lightly doped drain region.

19. The programmable and erasable non-volatile memory cell of claim 18, wherein the doping concentration of the second lightly doped drain region is equal to the doping concentration of the third lightly doped drain region, the doping concentration of the third lightly doped drain region is equal to the doping concentration of the fourth lightly doped drain region, and the doping concentration of the first lightly doped drain region is less than the doping concentration of the fourth lightly doped drain region. 20 . The programmable and erasable non-volatile memory cell according to claim 1 , further comprising a deep well region, wherein a bottom portion of the deep well region contacts the semiconductor substrate, and a top portion of the deep well region contacts the first well region.

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