Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a cellular region and a terminal region located at the outer side of the cellular region, the manufacturing method comprises the following steps: providing a substrate, forming a plurality of first grooves in the substrate of the cellular region, forming a second groove in the terminal region, a liner layer and a first gate material layer are formed on the side walls and the bottoms of the first groove and the second groove; forming a protection layer which at least covers the surface of the substrate in the junction area of the terminal area and the cellular area, and at least exposes the top surface of the first gate material layer in the cellular area and at least part of the top surface of the liner layer; removing a part of the first gate material layer and a part of the liner layer in the first groove to form an inner groove; forming an oxidation layer at the bottom and on the side wall of the inner groove through an oxidation process; and the inner groove is filled with a second gate material layer. According to the invention, the protection layer is formed to prevent the first groove from closing up due to the stress generated by the oxidation process, so that the gate-source-drain current test is ensured to pass, and the performance of the device is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Currently, in the manufacturing process of shielded-gate trench (SGT) MOSFETs, the stress generated by the oxidation process in the terminal region affects the trenches in the cell area, especially the trenches located in the junction area of ​​the terminal region and the active area, causing the critical dimensions of the trenches to become smaller and the top of the trenches to shrink. As a result, gaps or cracks may appear in the trenches when they are filled, affecting the seam. As a result, when the contact holes are subsequently etched, the polysilicon layer and the inter-gate dielectric layer may be etched through, causing a short circuit between the gate and the source, which in turn leads to failure of the gate-source leakage current (Igss) test and device failure. Summary of the Invention

[0003] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] In response to the current problems, the present application provides, on one hand, a method for manufacturing a semiconductor device, wherein the semiconductor device includes a cell region and a terminal region located outside the cell region, and the manufacturing method includes:

[0005] Providing a substrate, wherein a plurality of first trenches are formed in the substrate of the cell region, the first trenches extending from the surface of the substrate into the substrate, liner layers are formed on the sidewalls and bottoms of the plurality of first trenches, and the first trenches are filled with a first gate material layer; forming at least one second trench in the substrate of the terminal region, the liner layer is formed on the sidewalls and bottom of the second trench, and the second trench is filled with the first gate material layer;

[0006] forming a protective layer to cover at least the top surface of the second trench adjacent to the cell region and the substrate surface in the boundary region between the terminal region and the cell region, and to expose at least the top surface of the first gate material layer in the cell region and at least a portion of the top surface of the liner layer;

[0007] removing a portion of the first gate material layer and a portion of the liner layer in the first trench to form an inner groove, wherein the remaining first gate material layer serves as a shielding gate, and a top surface of the remaining liner layer and a top surface of the shielding gate are both lower than a surface of the substrate;

[0008] forming an oxide layer on the bottom and sidewalls of the inner groove through an oxidation process;

[0009] The inner groove is fully filled with a second gate material layer.

[0010] In some embodiments, the forming of the protection layer, which covers at least the top surface of the second trench adjacent to the cell region and the substrate surface in the boundary region between the terminal region and the cell region, and exposes at least the top surface of the first gate material layer in the cell region and at least a portion of the top surface of the liner layer, includes:

[0011] forming a protective material layer covering the surface of the substrate;

[0012] forming a first mask layer on a portion of the protective material layer, wherein the first mask layer covers at least a top surface of the second trench adjacent to the cell region and the protective material layer in a boundary region between the terminal region and the cell region, and exposes at least the protective material layer on a top surface region of the first gate material layer in the cell region and at least a portion of a top surface region of the liner layer;

[0013] The protective material layer is etched using the first mask layer as a mask to form a protective layer.

[0014] In some embodiments, removing a portion of the first gate material layer and a portion of the liner layer in the first trench to form an inner groove includes:

[0015] etching the first gate material layer using the first mask layer as a mask to remove a portion of the first gate material layer in the first trench;

[0016] removing the first mask layer;

[0017] A portion of the liner layer on the sidewall of the first trench is removed so that a top surface of the first gate material layer in the first trench is higher than a top surface of the liner layer to form an inner groove.

[0018] In some embodiments, the protection layer covers the entire substrate surface of the termination region and the top surfaces of all the second trenches; or

[0019] The liner layer further covers the substrate surface in the termination region. In the termination region, the protection layer covers the liner layer on the substrate surface and top surfaces of all the second trenches.

[0020] In some embodiments, the protective layer further covers the substrate surface between any two adjacent first grooves;

[0021] Alternatively, the liner layer further covers the surface of the substrate, and the protection layer covers the surface of the liner layer between any two adjacent first grooves.

[0022] In some embodiments, after forming the oxide layer on the bottom and sidewalls of the inner groove through an oxidation process and before forming the second gate material layer, the method further includes: removing the protective layer.

[0023] In some embodiments, after forming the oxide layer on the bottom and sidewalls of the inner recess through an oxidation process and before forming the second gate material layer, the method further includes:

[0024] The first mask layer and the protective layer are removed.

[0025] In some embodiments, the first gate material layer is an N-type doped polysilicon layer; and / or the material of the protective layer includes at least one of the following materials: silicon nitride, silicon carbide, and silicon carbonitride.

[0026] In some embodiments, the base includes a substrate and an epitaxial layer formed on the substrate, and the first trench is disposed in the epitaxial layer.

[0027] In another embodiment of the present application, a semiconductor device is provided. The semiconductor device is manufactured using the above manufacturing method.

[0028] The semiconductor device and manufacturing method of the embodiment of the present application form a protective layer on the surface of the substrate in the boundary area between the terminal area and the cell area. During the oxidation process, the area covered by the protective layer will not be oxidized, so that the oxidation process will not generate stress squeezing of the cell area groove in the boundary area between the terminal area and the cell area and in the second groove adjacent to the cell area in the terminal area, thereby avoiding the stress squeezing causing the first groove to close, thereby ensuring the effect of filling the seam, ensuring the gate-source leakage current test is passed, and further ensuring the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0030] In the attached figure:

[0031] Figure 1 An electron microscope image showing a groove top being squeezed and a gate dielectric layer and a polysilicon layer being pierced in the related art is shown;

[0032] Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown;

[0033] Figures 3A-3K A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] Next, the present application will be described more fully in conjunction with the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application relates. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0040] In order to fully understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0041] Currently, in the manufacturing process of shielded-gate trench (SGT) MOSFET, Figure 1 As shown in the left figure, the stress generated by the oxidation process in the terminal area will squeeze the trenches in the cell area, especially the trenches at the junction of the terminal area and the active area. Since the trenches are closer to the high stress area of ​​the terminal area, they are more susceptible to the stress of the terminal area, which will reduce the critical dimensions of the trenches in the cell area and shrink the top of the trenches in the cell area, as shown in Figure 2. Figure 1 As shown by the red circle in the left figure, the trench opening in the cell area is narrower than designed. As a result, when filling the trench, for example, when filling polysilicon, the polysilicon may not be able to completely fill the trench, or gaps or cracks may appear during filling, which affects the joint. Poor jointing affects the electrical performance of the device.

[0042] In addition, if Figure 1As shown in the right figure, when filling the trench of the cell area, there are gaps or cracks, which may cause the polysilicon layer and the inter-gate dielectric layer to be penetrated in some areas when the contact hole is etched, such as Figure 1 The area indicated by the red circle in the left figure causes a short circuit between the gate and the source, resulting in an increase in the source leakage current. The Igss test will detect an abnormally high current that exceeds the specification limit, causing the device to fail.

[0043] Therefore, in view of the existence of the aforementioned technical problems, the present application proposes a method for manufacturing a semiconductor device, wherein the semiconductor device includes a cell region and a terminal region located outside the cell region, as shown in FIG3 , and mainly includes the following steps:

[0044] Step S110: providing a substrate, forming a plurality of first trenches in the substrate of the cell region, wherein the first trenches extend from the surface of the substrate into the substrate, forming liner layers on the sidewalls and bottoms of the plurality of first trenches, and the first trenches are filled with a first gate material layer, and forming at least one second trench in the substrate of the terminal region, forming the liner layer on the sidewalls and bottom of the second trench, and the second trench is filled with the first gate material layer;

[0045] Step S120: forming a protection layer to cover at least the top surface of the second trench adjacent to the cell region and the substrate surface in the boundary region between the terminal region and the cell region, and to expose at least the top surface of the first gate material layer in the cell region and at least a portion of the top surface of the liner layer;

[0046] Step S130: removing a portion of the first gate material layer and a portion of the liner layer in the first trench to form an inner groove, wherein the remaining first gate material layer serves as a shielding gate, and the top surface of the remaining liner layer and the top surface of the shielding gate are both lower than the surface of the substrate;

[0047] Step S140: forming an oxide layer on the bottom and sidewalls of the inner groove through an oxidation process;

[0048] Step S150: filling the inner groove with a second gate material layer.

[0049] In the embodiment of the present application, a protective layer is formed on the surface of the substrate in the boundary area between the terminal area and the cell area. When the oxidation process is performed, the area covered by the protective layer will not be oxidized, so that the oxidation process will not generate stress in the boundary area between the terminal area and the cell area and in the second groove adjacent to the cell area in the terminal area to squeeze the first groove of the cell area, thereby avoiding stress squeezing causing the first groove to close, thereby ensuring the effect of filling the seam, ensuring that the gate-source leakage current test passes, and further ensuring the performance of the device.

[0050] Below, reference Figure 2 、 Figures 3A to 3K The manufacturing method of the semiconductor device of the present application is described in detail, wherein: Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to a first specific embodiment of the present application is shown; Figures 3A-3K A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0051] The above-mentioned semiconductor device can be any suitable type of device well known to those skilled in the art. In this embodiment, the technical solution of the present application is explained and illustrated mainly by taking the semiconductor device being SGTMOSFET as an example.

[0052] The semiconductor device of the present application includes a cell region and a terminal region located outside the cell region, and a manufacturing method thereof includes the following steps:

[0053] First, if Figure 2 As shown, step S110 is performed to provide a substrate, and a plurality of first grooves are formed in the substrate of the cell region, wherein the first grooves extend from the surface of the substrate to the inside of the substrate, and a liner layer is formed on the sidewalls and bottom of the plurality of first grooves, and the first grooves are filled with the first gate material layer. At least one second groove is formed in the substrate of the terminal region, and the liner layer is formed on the sidewalls and bottom of the second groove, and the second groove is filled with the first gate material layer.

[0054] For example, Figure 3A As shown, a base 20 is provided, which can be any suitable base layer for supporting a device structure. For example, the base 20 includes a substrate 200 and an epitaxial layer 201 formed on the substrate 200 .

[0055] The substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate. It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (DSP), or ceramic substrates such as aluminum oxide, quartz or glass substrates, etc. For example, the substrate 200 is a heavily doped silicon wafer used to provide mechanical support and a low-resistance current path.

[0056] Exemplarily, the epitaxial layer can be an epitaxial layer of the same material as the substrate 200, such as a silicon epitaxial layer. A lightly doped epitaxial layer 201 is grown on the substrate 200 by a suitable method such as vapor phase epitaxy. The epitaxial layer 201 can optimize the on-resistance.

[0057] like Figure 3B As shown, a plurality of first trenches 202 are formed in the substrate 20 in the cell region, and the first trenches 202 extend from the surface of the substrate 20 to the inside of the substrate 20. At least one second trench 212 is formed on the substrate 20 in the terminal region, and the second trench 212 extends from the surface of the substrate 20 to the inside of the substrate 20. The first trenches 202 and the second trenches 212 can be formed in any suitable manner, for example, by dry etching. Then, as shown in FIG. Figure 3C As shown, a liner layer 203 is formed on the sidewalls and bottom of the first trench 202 and the sidewalls and bottom of the second trench 212. The liner layer 203 also covers the surface of the substrate. The liner layer 203 can be used to adjust the mechanical stress distribution around the first trench 202 and the second trench 212, and can also repair damage to lattice defects (such as dangling bonds and microcracks) introduced into the substrate by, for example, dry etching.

[0058] Then as Figure 3D As shown, the first trench 202 and the second trench 212 are filled with the first gate material to form a first gate material layer in the first trench 202 and the second trench 212, and the first gate material layer fills the first trench 202 and the second trench 212. For example, a suitable method (such as chemical vapor deposition or atomic layer deposition) can be used to deposit the first gate material layer 204 in the first trench 202 and the second trench 212. Then, a suitable method (such as chemical mechanical polishing) is used to planarize the first gate material layer 204 to remove excess first gate material layer 204 outside the first trench 202 and the second trench 212, so that the surface of the first gate material layer 204 is flat. Exemplarily, the first gate material layer includes an N-type doped polysilicon layer.

[0059] Next, step S120 is performed to form a protective layer, covering at least the top surface of the second groove adjacent to the cell region and the substrate surface in the boundary area between the terminal region and the cell region, and exposing at least the top surface of the first gate material layer in the cell region and at least part of the top surface of the pad layer.

[0060] For example, first, Figure 3EAs shown, a protective material layer 2051 is formed to cover the surface of the substrate. For example, the protective material layer 2051 can be formed by a suitable method such as chemical vapor deposition or atomic layer deposition, and then the protective material layer 2051 is planarized to make its surface flat. Next, a first mask layer is formed on a portion of the protective material layer. The first mask layer at least covers the top surface of the second trench 212 adjacent to the cell region and the protective material layer 2051 in the boundary area between the terminal region and the cell region, and at least exposes the top surface of the first trench 202 in the cell region and the protective material layer on at least a portion of the top surface area of ​​the liner layer. It is worth mentioning that since the second trench 212 and the first trench 202 are both filled with the first gate material to form the first gate material layer 204, the top surface of the second trench 212 and the top surface of the first trench 202 are also the top surfaces of the first gate material layer 204 in the second trench 212 and the first trench 202.

[0061] In some examples, in some examples, a first mask layer is formed on the top surface of the second trench adjacent to the cell region, that is, on the top surface of the first gate material layer 204 in the terminal region adjacent to the cell region and the protective material layer 2051 in the boundary area between the terminal region and the cell region. In this embodiment, the subsequently formed protective layer at least covers the top surface of the second trench adjacent to the cell region and the substrate surface in the boundary area between the terminal region and the cell region to form a protective layer. Specifically, the protective layer is formed on the top surface of the second trench adjacent to the cell region and on 203 in the boundary area between the terminal region and the cell region. This can prevent the subsequent oxidation process from oxidizing the first gate material layer adjacent to the cell region and the substrate surface in the boundary area between the terminal region and the cell region.

[0062] In some examples, such as Figure 3F-1 As shown, a first mask layer 206 is formed on the protective material layer 2051 in the terminal area and the boundary area between the terminal area and the cellular area. In this embodiment, the first mask layer 206 covers the substrate surface of the entire terminal area and the top surfaces of all the second grooves, as well as the substrate surface of the boundary area between the terminal area and the cellular area, so that the protective layer 205 formed in the subsequent etching step can cover the substrate surface of the entire terminal area and the top surfaces of all the second grooves 212, as well as the substrate surface of the boundary area between the terminal area and the cellular area. In addition, when a substrate layer is formed on the substrate surface, in the terminal area, the protective layer covers the liner layer on the substrate surface and the top surfaces of the second grooves. It is worth mentioning that the terminal area is schematically illustrated with only one second groove in the figure, and the number of second grooves in the terminal area is not limited. In some examples, such as Figure 3F-2As shown, while forming the first mask layer 206 on the protective material layer 2051 in the terminal region and the boundary region between the terminal region and the cell region, the first mask layer 206 is also formed on the protective material layer 2051 between any adjacent first trenches 202. The first mask layer 206 between any adjacent first trenches 202 covers the mesa region of the cell region. Next, the protective material layer is etched using the first mask layer 206 as a mask, thereby forming the following: Figure 3G-1 or as Figure 3G-2 The stress generated by the oxidation process in the boundary area between the terminal area and the cell area mainly affects the first first trench of the cell area, but other mesa areas of the cell area may also be affected to some extent, thus forming Figure 3G-2 The protective layer 205 shown can not only prevent the stress generated by the oxidation process in the boundary area between the terminal area and the cell area from affecting the first first groove of the cell area, but also prevent other mesa areas of the cell area from being squeezed by this stress and causing the first groove on the outside to close. In addition, the liner layer 203 on the surface of the substrate 20 is usually thin or when the base layer 203 is not formed on the surface of the substrate 20, a protective layer 205 as shown in FIG. Figure 3G-2 The protective layer 205 shown can avoid the loss of the liner layer or the substrate surface when etching the first gate material layer. For example, the material of the protective layer includes but is not limited to silicon nitride, silicon carbide, silicon carbonitride, etc. The first mask layer 206 includes a photoresist layer. It is worth mentioning that in the subsequent steps, Figure 3G-1 or as Figure 3G-2 The operation principle of the semiconductor structure shown is the same, so in order to repeat the description, the following is only used as Figure 3G-1 The description is based on the cross-sectional view shown. Figure 3G-2 The subsequent description is based on Figure 3G-1 The description above is for reference only.

[0063] Next, step 130 is performed to remove part of the first gate material layer and part of the liner layer in the first groove to form an inner groove, wherein the remaining first gate material layer is used as a shielding gate, and the top surface of the remaining liner layer and the top surface of the shielding gate are both lower than the surface of the substrate.

[0064] For example, Figure 3HAs shown, first, the first mask layer 206 is used as a mask, and any etchant suitable for the first gate material layer 204 is selected to etch the first gate material layer 204, thereby removing a portion of the first gate material layer 204 in the first trench 202. The remaining first gate material layer 204 after etching serves as a shield. It is worth mentioning that the first mask layer 206 is used as a mask for etching the first gate material layer 204 and etching the protective material layer 2051. Therefore, the present application adds a protective layer without adding an additional mask, which can effectively control the cost of improving the relevant technology of the present application. Then, as shown in FIG. Figure 3I As shown, the first mask layer 206 is removed. In some examples, the first mask layer is removed simultaneously with the protective layer after forming an oxide layer on the bottom and sidewalls of the inner groove and before forming the second gate material layer. Next, a portion of the liner layer 203 on the sidewalls of the first trench 202 and the liner layer 203 on the substrate surface between adjacent first trenches 202 are removed. After etching, the top surface of the remaining liner layer 203 and the top surface of the shield gate are both lower than the surface of the substrate. The etchant used in this etching process has a higher etching selectivity for the liner layer 203 than the first gate material layer 204, so that when etching the liner layer 203, the first gate material layer 204 is hardly etched. In some examples, after etching, an inner groove 207 is formed, and the top surface of the first gate material layer 204 in the first trench 202 is higher than the top surface of the liner layer 203.

[0065] Next, step 140 is performed to form an oxide layer on the bottom and sidewalls of the inner groove through an oxidation process.

[0066] For example, Figure 3J As shown, an inter-gate dielectric layer 208 is formed in the inner groove by an oxidation process, such as thermal oxidation, to cover the first gate material layer 204 exposed in the inner groove 207. For example, the inter-gate dielectric layer 208 covers the top surface of the first gate material layer 204 in the inner groove 207, or, when the first gate material layer 204 in the inner groove 207 has sidewalls, the inter-gate dielectric layer 208 covers the top surface and sidewalls of the first gate material layer 204 in the inner groove 207. The inter-gate dielectric layer 208 is mainly used to isolate the first gate material layer 204 from the second gate material layer to be formed subsequently, so as to prevent capacitive coupling between the two and reduce gate-drain capacitance. Then, continue as shown in FIG. Figure 3J As shown, a gate dielectric layer 209 is formed in the inner groove 207 and a portion of the substrate surface, so that the gate dielectric layer 209 at least covers the sidewalls of the inner groove 207 and the surface of the substrate 20 between adjacent first trenches 202. For example, the gate dielectric layer 209 is formed on the sidewalls of the inner groove 207 and the bottom that is not covered by the inter-gate dielectric layer 208, and the gate dielectric layer 209 is formed on the substrate surface between adjacent first trenches 202.

[0067] It is worth mentioning that when the oxide layer is formed in the inner groove, the inter-gate dielectric layer and the gate dielectric layer can also be formed simultaneously by a one-step oxidation method.

[0068] Since there is a protective layer 205 on the top surface of the second trench 212 adjacent to the cell area and the boundary area between the terminal area and the cell area, during the process of generating the oxide layer 210 through the oxidation process, the area with the protective layer 205 will not be oxidized, and thus no stress will be generated to affect the first trench 202 of the cell area, especially the first first trench, thereby preventing the first trench 202 from closing due to the oxidation process, improving the seam effect, effectively preventing the gate and drain from short circuiting, and thus ensuring that the gate-source leakage current Igss test passes.

[0069] Next, step 150 is performed to fill the inner groove with a second gate material layer.

[0070] For example, the protective layer 205 is first removed, and then, as shown in FIG. Figure 3K As shown, a second gate material layer 211 is formed by any suitable method, such as deposition (such as chemical vapor deposition or atomic layer deposition). For example, the second gate material layer 211 includes polysilicon. The second gate material layer 211 fills the inner groove 207 and covers the surface of the substrate 20. More specifically, the second gate material layer 211 covers the liner layer 203 in the terminal region and the top surface of the first gate material layer 204 in the terminal region, so that the second gate material layer 211 is connected to the first gate material layer 204 in the terminal region. The second gate material layer 211 also covers the oxide layer 210 in the cell region. The second gate material layer 211 is then planarized using any suitable planarization method (such as chemical mechanical polishing) to make the surface of the second gate material layer 211 flat and remove the second gate material layer 211 above the substrate surface. After the second gate material layer 211 is formed, a gate can be formed by photolithography and etching.

[0071] Next, subsequent steps are performed using processes that can be understood by those skilled in the art to form the final SGTMOSFET. For example, a body region can be formed in the substrate on both sides of the first trench in the cell region, and a source and a body lead-out region can be formed in the body region to form a drain on the back side of the substrate.

[0072] This completes the description of the key steps of the semiconductor device manufacturing method of the present application. The complete semiconductor device manufacturing method may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0073] In summary, in the embodiments of the present application, a protective layer is formed on the surface of the substrate in the boundary area between the terminal area and the cell area. When the oxidation process is performed, the area covered by the protective layer will not be oxidized, so that the oxidation process will not cause stress to squeeze the first groove of the cell area in the boundary area between the terminal area and the cell area and in the second groove adjacent to the cell area in the terminal area, thereby avoiding stress squeezing that causes the first groove to close, thereby ensuring the effect of filling the seam, ensuring that the gate-source leakage current test passes, and further ensuring the performance of the device. At the same time, the same mask is used to form the protective layer and the shielding gate. Therefore, adding the protective layer does not lead to the addition of an additional mask, and will not significantly increase the production cost.

[0074] The present application also provides a semiconductor device, which can be manufactured using the semiconductor device manufacturing method of the aforementioned embodiment. For details of the semiconductor device of the embodiment of the present application, reference can be made to the relevant description of the method above and will not be repeated here. Since the semiconductor device of the present application is manufactured using the aforementioned manufacturing method, it has the same advantages as the aforementioned method.

[0075] Although a number of embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be devised by those skilled in the art, all of which fall within the spirit and scope of the concepts disclosed herein. More particularly, within the scope of the present disclosure, the accompanying drawings, and the appended claims, various modifications and changes may be made to the arrangements and / or components of the subject matter in combination. In addition to modifications and changes to the components and / or arrangements, the use of alternatives will also be readily apparent to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device includes a cell region and a terminal region located outside the cell region, and the manufacturing method includes: Providing a substrate, wherein a plurality of first trenches are formed in the substrate of the cell region, the first trenches extending from the surface of the substrate into the substrate, liner layers are formed on the sidewalls and bottoms of the plurality of first trenches, and the first trenches are filled with a first gate material layer; and forming at least one second trench in the substrate of the terminal region, the liner layer is formed on the sidewalls and bottom of the second trench, and the second trench is filled with the first gate material layer; forming a protective layer to cover at least the top surface of the second trench adjacent to the cell region and the surface of the substrate in the boundary region between the terminal region and the cell region, and to expose at least the top surface of the first trench in the cell region; removing a portion of the first gate material layer and a portion of the liner layer in the first trench to form an inner groove, wherein the remaining first gate material layer serves as a shielding gate, and a top surface of the remaining liner layer and a top surface of the shielding gate are both lower than a surface of the substrate; forming an oxide layer on the bottom and sidewalls of the inner groove through an oxidation process; The inner groove is fully filled with a second gate material layer.

2. The manufacturing method according to claim 1, wherein The forming of the protection layer, which covers at least the top surface of the second trench adjacent to the cell region and the substrate surface in the boundary region between the terminal region and the cell region, and exposes at least the top surface of the first gate material layer in the cell region and at least a portion of the top surface of the liner layer, comprises: forming a protective material layer covering the surface of the substrate; forming a first mask layer on a portion of the protective material layer, wherein the first mask layer covers at least a top surface of the second trench adjacent to the cell region and the protective material layer in a boundary region between the terminal region and the cell region, and exposes at least the protective material layer on a top surface region of the first gate material layer in the cell region and at least a portion of a top surface region of the liner layer; The protective material layer is etched using the first mask layer as a mask to form a protective layer.

3. The manufacturing method according to claim 2, wherein: The removing of a portion of the first gate material layer and a portion of the liner layer in the first trench to form an inner groove includes: etching the first gate material layer using the first mask layer as a mask to remove a portion of the first gate material layer in the first trench; removing the first mask layer; A portion of the liner layer on the sidewall of the first trench is removed so that a top surface of the first gate material layer in the first trench is higher than a top surface of the liner layer to form an inner groove.

4. The manufacturing method according to claim 1, wherein: The protective layer covers the entire substrate surface of the termination region and the top surfaces of all the second trenches; or The liner layer further covers the substrate surface in the termination region. In the termination region, the protection layer covers the liner layer on the substrate surface and top surfaces of all the second trenches.

5. The manufacturing method according to claim 1, wherein: The protective layer also covers the substrate surface between any two adjacent first grooves; Alternatively, the liner layer further covers the surface of the substrate, and the protection layer covers the surface of the liner layer between any two adjacent first grooves.

6. The manufacturing method according to claim 1, wherein: After forming an oxide layer on the bottom and sidewalls of the inner groove through an oxidation process and before forming the second gate material layer, the method further includes: The protective layer is removed.

7. The manufacturing method according to claim 2, wherein: After forming an oxide layer on the bottom and sidewalls of the inner groove through an oxidation process and before forming the second gate material layer, the method further includes: The first mask layer and the protective layer are removed.

8. The manufacturing method according to any one of claims 1 to 6, characterized in that The first gate material layer includes an N-type doped polysilicon layer; and / or, The material of the protective layer includes at least one of the following materials: silicon nitride, silicon carbide, and silicon carbonitride.

9. The manufacturing method according to claim 1, wherein: The base includes a substrate and an epitaxial layer formed on the substrate, and the first trench is arranged in the epitaxial layer.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 9.

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