Memory circuit, operation method thereof, memory and electronic equipment
Patent Information
- Application Number
- CN202380091907.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-08
- Publication Date
- 2025-08-29
AI Technical Summary
The existing three-state content addressing memory (TCAM) memory cells have large area and high power consumption, making it difficult to improve storage density.
Using a memory cell based on a dual-gate transistor, the high current is used when the two gates of the dual-gate transistor are turned on at the same time, which reduces the required number of transistors. Four transistors can be used to realize the write and search functions instead. Two single gate transistors in traditional static and dynamic TCAM memory cells.
The memory cell area is small and the power consumption is low, the storage density is improved, and the process difficulty is reduced, avoiding the problem of long time writing information when capacitance stores data.
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Abstract
Description
A storage circuit, an operating method thereof, a memory and an electronic device Technical Field
[0001] The present application relates to the field of circuit design technology, and in particular to a storage circuit, an operating method thereof, a memory, and an electronic device. Background Art
[0002] Ternary content-access memory (TCAM) is widely used in network processors, particularly for fast, parallel lookup tasks such as routing table lookups. While conventional memory operations rely on inputting an address and outputting the corresponding address to the stored data, a content-addressable memory (CAM) takes input data and searches for the address corresponding to that data. However, TCAM input data contains one or more mask bits, requiring it to find the address where the input data, excluding the mask bits, matches the stored data.
[0003] Current TCAM memory cells mainly fall into two categories: static TCAM cells based on static random access memory (SRAM) and dynamic TCAM cells based on capacitor-based data storage. To encode mask bits, these TCAM cells need to represent both input and stored data with two bits. For example, "01" indicates that both the stored data and input data are "0," "10" indicates that both the stored data and input data are "1," and "00" indicates that the input data is masked.
[0004] Referring to Figure 1, an SRAM-based static TCAM memory cell stores data in a 6T SRAM. A single SRAM-based static TCAM memory cell requires sixteen transistors. Two 6T SRAMs are used to store two bits of data, respectively. Both SRAMs initiate write operations via a connected word line (WL). One SRAM writes one bit of data via a connected first bit line (BL0), and the other writes another bit of data via a connected second bit line (BL1). The remaining four transistors include two storage transistors T1 and two search transistors T2. The two search transistors T2 load the two bits of data to be searched via a connected first source line (SL0) and a connected second source line (SL1). By reading the voltage changes on the match lines (ML) connected to the two storage transistors T1, it can be determined whether the search data matches the stored data. The large number of transistors required for a static TCAM memory cell occupies a large area and consumes high SRAM power.
[0005] Referring to Figure 2 , a dynamic TCAM memory cell based on capacitor data storage stores data in capacitors. A single dynamic TCAM memory cell based on capacitor data storage requires six transistors and two capacitors. Two write transistors T3 and two capacitors C can replace the two 6T SRAMs in the static TCAM memory cell described above. Because silicon-based transistors have high static leakage current, a larger capacitor C is required to maintain a longer write time for stored information.
[0006] The circuits of the above two types of current TCAM storage cells occupy a large area, which is not conducive to improving storage density.
[0007] Summary of the Invention
[0008] The present application provides a storage circuit, an operating method thereof, a memory, and an electronic device, which are used to reduce the area occupied by storage units and improve storage density.
[0009] In a first aspect, the present application provides a memory circuit that may include: a plurality of memory cells, a plurality of word lines, a plurality of match lines, a plurality of first bit lines, a plurality of second bit lines, a plurality of first conductive lines, a plurality of second conductive lines, a plurality of first source lines, and a plurality of second source lines. At least one memory cell in the plurality of memory cells includes a first write transistor, a second write transistor, a first dual-gate transistor, and a second dual-gate transistor. In a memory cell, a first control electrode of a first write transistor and a first control electrode of a second write transistor are both connected to the same word line among a plurality of word lines, a first electrode of a first double-gate transistor and a first electrode of a second double-gate transistor are both connected to a match line among a plurality of match lines, a first electrode of the first write transistor is connected to a first bit line among a plurality of first bit lines, a first electrode of the second write transistor is connected to a second bit line among a plurality of second bit lines, a second electrode of the first write transistor is connected to the first control electrode of the first double-gate transistor, a second electrode of the second write transistor is connected to the first control electrode of the second double-gate transistor, a second control electrode of the first double-gate transistor is connected to a first source line among a plurality of first source lines, a second control electrode of the second double-gate transistor is connected to a second source line among a plurality of second source lines, a second electrode of the first double-gate transistor is connected to a first wire among a plurality of first wires, and a second electrode of the second double-gate transistor is connected to a second wire among a plurality of second wires.
[0010] It is worth noting that the first electrode and the second electrode of the transistor mentioned in this application can be any one of the source and the drain. Moreover, the first electrode of the first write transistor and the first electrode of the second write transistor can be the source at the same time, or the drain at the same time, or one is the source and the other is the drain. Similarly, the first electrode of the first double-gate transistor and the first electrode of the second double-gate transistor can be the source at the same time, or the drain at the same time, or one is the source and the other is the drain. For example, the drain of the first write transistor and the drain of the second write transistor can be connected to the first bit line and the second bit line respectively, the source of the first write transistor is connected to the first control electrode of the first double-gate transistor, and the source of the second write transistor is connected to the first control electrode of the second double-gate transistor. For another example, the source of the first double-gate transistor and the drain of the second double-gate transistor can both be connected to the matching line, and the drain of the first double-gate transistor and the source of the second double-gate transistor are connected to the first wire and the second wire respectively. This is not an exhaustive list.
[0011] The storage circuit provided by the present application includes a storage cell based on a dual-gate transistor. By utilizing the characteristic that the current is larger when the two gates of the dual-gate transistor are turned on at the same time, a dual-gate transistor can be used to replace the two single-gate transistors used to store and search data in the existing storage cell. Among them, the first control electrode (i.e., the first gate) of the dual-gate transistor is used to store the written data as a storage node (SN) during the write operation, and the second control electrode (i.e., the second gate) of the dual-gate transistor is used to load the data to be searched to realize the search operation. Specifically, the first control electrode of the first dual-gate transistor constitutes the first storage node, and the first control electrode of the second dual-gate transistor constitutes the second storage node. The storage cell of the present application can realize its write and search functions using four transistors. The total number of transistors used is small, so the storage cell occupies a small area and consumes less power, which can improve the storage density. In the storage cell of the present application, the dual-gate transistor can be a transistor made of an oxide semiconductor material, which has a very small static current and is very suitable for the storage cell, and can effectively improve the data retention time of the storage cell. In addition, there is no need to set a separate capacitor device in the storage cell of the present application, so there is no need for a complex capacitor process, which can reduce the process difficulty and avoid the problem of a long time to write information when the capacitor stores data.
[0012] In some embodiments of the present application, the storage unit of the storage circuit may be a TCAM storage unit, which can realize the function of TCAM searching for address data in which the other bits in the input data except the mask bits are the same as the stored data when one or more mask bits are present in the input data. Specifically, the first write transistor and the first dual-gate transistor cooperate with each other to realize the function of storing and searching one bit of data, and the second write transistor and the second dual-gate transistor cooperate with each other to realize the function of storing and searching another bit of data. The TCAM storage unit based on dual-gate transistors provided in the present application utilizes the characteristic that the current is larger when the two gates of the dual-gate transistor are turned on at the same time, and can use a dual-gate transistor to replace the two single-gate transistors used for storing and searching data in the existing static TCAM storage unit and dynamic TCAM storage unit. The write and search functions of the TCAM can be realized by using four transistors, and the total number of transistors used is relatively small, so the storage unit occupies a smaller area and consumes less power, which can improve the storage density.
[0013] In some embodiments of the present application, the first write transistor and the second write transistor can both be NMOS (N-type metal-oxide-semiconductor) transistors. The NMOS transistors can be directly manufactured using a backend of line (BEOL) process, which is conducive to three-dimensional stacking of transistors in the memory cell, thereby improving storage density.
[0014] In other embodiments of the present application, the first write transistor and the second write transistor may also be PMOS (P-type metal-oxide-semiconductor) transistors. PMOS transistors have no threshold voltage limitation, which is beneficial to reducing the power consumption of the storage unit.
[0015] In some embodiments of the present application, the first write transistor and the second write transistor in the memory cell can both be single-gate transistors, i.e., the first write transistor and the second write transistor have only one control electrode (i.e., gate). In this case, the memory cell is composed of two single-gate transistors and two dual-gate transistors.
[0016] In other embodiments of the present application, in order to further regulate the leakage of the first write transistor and the second write transistor, the first write transistor and the second write transistor can also be set as dual-gate transistors, and in this case the storage unit is composed of four dual-gate transistors. Accordingly, the storage circuit can also include multiple write back gates, and the multiple write back gates can be connected to each other. The second control electrode of the first write transistor and the second control electrode of the second write transistor can be connected to one of the multiple write back gates, and a fixed voltage can be applied to the second control electrode of the first write transistor and the second control electrode of the second write transistor through the write back gate to regulate the leakage of the first write transistor and the second write transistor. Especially in the standby stage, the use of dual-gate transistors for the first write transistor and the second write transistor is beneficial to reduce leakage.
[0017] In some embodiments of the present application, when the storage unit only needs to implement write operations and search operations, the multiple first conductive lines and the multiple second conductive lines can all be ground lines, that is, the second electrode of the first double-gate transistor and the second electrode of the second double-gate transistor can both be grounded.
[0018] In other embodiments of the present application, when the storage unit also needs to implement a read operation, the multiple first bit lines can be multiple first write bit lines, and the multiple second bit lines can be multiple second write bit lines; the multiple first conductors can be first read bit lines, and the multiple second conductors can be second read bit lines. During the read operation, the stored data can be read by reading the voltage changes of the read bit lines.
[0019] In an embodiment of the present application, when a TCAM memory cell based on a dual-gate transistor is formed into an array structure on a substrate, multiple word lines, multiple match lines, multiple first conductive lines, and multiple second conductive lines can all be arranged along a first direction parallel to the substrate, and multiple first bit lines, multiple second bit lines, multiple first source lines, and multiple second source lines can all be arranged along a second direction parallel to the substrate. The first direction and the second direction can be arranged approximately perpendicularly. For a storage circuit in which the two write transistors of the TCAM memory cell are composed of two dual-gate transistors, the difference lies in the addition of multiple write gate lines. The multiple write gate lines can be arranged and interconnected along the first direction, or arranged and interconnected along the second direction, without limitation herein. For convenience of description, the first direction can be referred to as the row direction, and the second direction can be referred to as the column direction.
[0020] In an embodiment of the present application, to reduce the area of a memory cell, the transistors in the memory cell can be stacked on a substrate. Specifically, in a memory cell, a first write transistor and a first dual-gate transistor can be stacked on a substrate, and a second write transistor and a second dual-gate transistor can be stacked on a substrate. Furthermore, the first write transistor and the second write transistor can be arranged in the same plane parallel to the substrate, and the first dual-gate transistor and the second dual-gate transistor can be arranged in another plane parallel to the substrate.
[0021] In some embodiments of the present application, a three-dimensional stacked structure of a TCAM memory cell can be physically implemented using front-end of line (FEOL) + back-end of line (BEOL) transistors. Specifically, in a memory cell, a first write transistor and a second write transistor are respectively arranged on a substrate, a first dual-gate transistor can be stacked on the first write transistor, and a second dual-gate transistor can be stacked on the second write transistor, that is, the first dual-gate transistor is stacked on the first write transistor, and the second dual-gate transistor is stacked on the second write transistor. The first write transistor and the second write transistor can be front-end process transistors, and the first dual-gate transistor and the second dual-gate transistor are back-end process transistors. After silicon-based transistors are prepared as the first transistors and the second write transistor using the front-end process, the first dual-gate transistor, the second dual-gate transistor, the word line, the match line, the first bit line, the second bit line, the first source line, the second source line, the first wire, and the second wire can be formed using the back-end process.
[0022] In other embodiments of the present application, a three-dimensional stacked structure of a TCAM memory cell can be physically implemented using back-end-of-line (BEOL) channel all around (CAA) transistors. Specifically, in a memory cell, a first dual-gate transistor and a second dual-gate transistor are respectively disposed on a substrate, a first write transistor can be stacked on top of the first dual-gate transistor, and a second write transistor can be stacked on top of the second dual-gate transistor, that is, the first write transistor is stacked on top of the first dual-gate transistor, and the second write transistor is stacked on top of the second dual-gate transistor. The first write transistor, the second write transistor, the first dual-gate transistor, and the second dual-gate transistor are all back-end-of-line (BEOL) channel all around transistors.
[0023] In a second aspect, the present application provides a memory, which includes a controller and the storage circuit provided in the first aspect of the present application, and the controller is used to access the storage circuit.
[0024] In a third aspect, the present application provides an electronic device comprising a circuit board and the memory provided in the second aspect of the present application, wherein the memory is electrically connected to the circuit board, and the electronic device may further comprise other chips or independent devices.
[0025] In a fourth aspect, the present application provides a method for operating a storage circuit, which is applied to the storage circuit provided in the first aspect of the present application and can perform a write operation on each storage cell connected to one or more word lines. When the data to be written is defined as "0", the first storage node and the second storage node are written with "0" and "1" respectively; when the data to be written is defined as "1", the first storage node and the second storage node are written with "1" and "0" respectively. In response to the write instruction, the specific process of performing the write operation is as follows: first, the selected word line is controlled to be set to a first voltage, for example, to be set to "1", so as to control the first write transistor and the second write transistor connected to the selected word line to be turned on, and the other word lines are controlled to be set to a second voltage, for example, to be set to "0", so as to control the first write transistor and the second write transistor connected to the other word lines to be turned off. In addition, multiple matching lines, multiple first conductive lines, multiple second conductive lines, multiple first source lines, and multiple second source lines are controlled to be set to a second voltage, for example, to be set to "0", so that the first double-gate transistor and the second double-gate transistor are turned off, thereby blocking the current path between the first conductive line (or the second conductive line) and the matching line. Afterwards, the plurality of first bit lines and the plurality of second bit lines are controlled to be set to a first voltage, for example, “1”, or a second voltage, for example, “0”, according to the data to be written.
[0026] In a fifth aspect, the present application provides another method for operating a storage circuit, which is applied to the storage circuit provided in the first aspect of the present application and can perform a search operation on each storage cell connected to one or more match lines. It is defined that when the data to be searched is "0", the first source line and the second source line input "0" and "1" respectively; it is defined that when the data to be searched is "1", the first source line and the second source line input "1" and "0" respectively; it is defined that regardless of the value of a certain bit (the mask bit is "X" data), the first source line and the second source line both input "0". In response to the search instruction, the specific process of performing the search operation is: controlling multiple match lines to be precharged to a first voltage, for example, set to "1"; controlling multiple first source lines and multiple second source lines to be set to a first voltage, for example, set to "1" or a second voltage, for example, set to "0" according to the search data; after a set time, measuring the voltages on the multiple match lines, reading the voltage changes of the multiple match lines, and determining whether the search data matches the storage data in the multiple storage cells. Specifically, if the voltage on the match line drops significantly, it indicates that the search data is consistent with the stored data; if the voltage on the match line remains substantially unchanged, it indicates that the search data is different from the stored data or the bit is a mask bit.
[0027] In a sixth aspect, the present application provides another method for operating a memory circuit, which is applied to a structure in which multiple first conductive lines serve as first read bit lines and multiple second conductive lines serve as second read bit lines in the memory circuit provided in the first aspect of the present application, and can perform a read operation on each memory cell connected to a first source line and a second source line. In response to a read instruction, the specific process of performing the read operation is as follows: controlling the multiple first read bit lines and the multiple second read bit lines to be precharged to a first voltage, such as "1", and controlling the multiple matching lines to be set to a second voltage, such as "0"; then, controlling the selected first source line and the selected second source line to be set to the first voltage, such as "1", to control the first dual-gate transistor connected to the selected first source line and the second dual-gate transistor connected to the selected second source line to be conductive; after a set time, measuring the voltages on the multiple first read bit lines and the multiple second read bit lines to read the voltage changes of the multiple first read bit lines and the multiple second read bit lines. Specifically, if the data stored in the storage node is "1", the voltage of the corresponding read bit line drops significantly; if the data stored in the storage node is "0", the voltage of the corresponding read bit line remains substantially unchanged. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIG1 is a circuit diagram of a static TCAM memory cell based on SRAM;
[0029] FIG2 is a circuit diagram of a dynamic TCAM memory cell based on capacitor data storage;
[0030] FIG3 is a circuit diagram of a storage unit in a storage circuit provided in an embodiment of the present application;
[0031] FIG4 is another circuit diagram of a memory cell in a memory circuit provided by an embodiment of the present application;
[0032] FIG5 is another circuit diagram of a memory cell in a memory circuit provided by an embodiment of the present application;
[0033] FIG6 is another circuit diagram of a memory cell in a memory circuit provided in an embodiment of the present application;
[0034] FIG7 is a circuit diagram of a storage circuit provided in an embodiment of the present application;
[0035] FIG8 is a schematic diagram of a structure of a transistor stack in a memory cell in a memory circuit provided by an embodiment of the present application;
[0036] FIG9 is a schematic diagram of a structure of a storage circuit in the xy direction provided by an embodiment of the present application;
[0037] FIG10 is a schematic diagram of a structure of a storage circuit in the yz direction provided by an embodiment of the present application;
[0038] FIG11 is a circuit diagram of a transistor stack in a memory cell in a memory circuit provided by an embodiment of the present application;
[0039] FIG12 is a schematic structural diagram corresponding to FIG11;
[0040] FIG13 is another schematic diagram of the structure of the storage circuit provided in an embodiment of the present application in the xy direction;
[0041] FIG14 is another schematic diagram of the structure of the storage circuit in the yz direction provided by an embodiment of the present application;
[0042] FIG15 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;
[0043] FIG16 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.
[0045] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and appended claims of this application, the singular expressions "a", "an", "said", "above", "the", and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise.
[0046] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0047] In addition, the same reference numerals in the figures represent the same or similar structures, and their repeated description will be omitted. The words expressing positions and directions described in this application are all explained by using the drawings as examples, but they can be changed as needed, and the changes made are included in the scope of protection of this application. The drawings in this application are only used to illustrate the relative position relationship and do not represent the actual scale.
[0048] Figure 3 is a circuit schematic diagram of a memory cell in the memory circuit provided in an embodiment of the present application; Figure 4 is another circuit schematic diagram of a memory cell in the memory circuit provided in an embodiment of the present application; Figure 5 is another circuit schematic diagram of a memory cell in the memory circuit provided in an embodiment of the present application; Figure 6 is another circuit schematic diagram of a memory cell in the memory circuit provided in an embodiment of the present application.
[0049] 3 to 6 , an embodiment of the present application provides a memory circuit, specifically comprising: a plurality of memory cells 01, a plurality of word lines WL, a plurality of match lines ML, a plurality of first bit lines BL0, a plurality of second bit lines BL1, a plurality of first conductive lines D0, a plurality of second conductive lines D1, a plurality of first source lines SL0, and a plurality of second source lines SL1. At least one memory cell 01 among the plurality of memory cells 01 includes a first write transistor Tw1, a second write transistor Tw2, a first dual-gate transistor Ts1, and a second dual-gate transistor Ts2. In a memory cell 01, the first control electrode of the first write transistor Tw1 and the first control electrode of the second write transistor Tw2 are both connected to the same word line WL among the multiple word lines WL, the first electrode of the first dual-gate transistor Ts1 and the first electrode of the second dual-gate transistor Ts2 are both connected to one match line ML among the multiple match lines ML, the first electrode of the first write transistor Tw1 is connected to a first bit line BL0 among the multiple first bit lines BL0, the first electrode of the second write transistor Tw1 is connected to a second bit line BL1 among the multiple second bit lines BL1, and the second electrode of the first write transistor Tw1 is connected to the first bit line BL0. The first control electrode of the dual-gate transistor Ts1 is connected, the second electrode of the second write transistor Tw2 is connected to the first control electrode of the second dual-gate transistor Ts2, the second control electrode of the first dual-gate transistor Ts1 is connected to a first source line SL0 among the multiple first source lines SL0, the second control electrode of the second dual-gate transistor Ts2 is connected to a second source line SL1 among the multiple second source lines SL1, the second electrode of the first dual-gate transistor Ts1 is connected to a first wire D0 among the multiple first wires D0, and the second electrode of the second dual-gate transistor Ts2 is connected to a second wire D1 among the multiple second wires D1.
[0050] It is worth noting that the first electrode and the second electrode of the transistor mentioned in this application can be any one of the source and the drain. In addition, the first electrode of the first write transistor Tw1 and the first electrode of the second write transistor Tw2 can be the source at the same time, or the drain at the same time, or one is the source and the other is the drain. Similarly, the first electrode of the first dual-gate transistor Ts1 and the first electrode of the second dual-gate transistor Ts2 can be the source at the same time, or the drain at the same time, or one is the source and the other is the drain. For example, the drain of the first write transistor Tw1 and the drain of the second write transistor Tw2 can be connected to the first bit line BL0 and the second bit line BL1 respectively, the source of the first write transistor Tw1 is connected to the first control electrode of the first dual-gate transistor Ts1, and the source of the second write transistor Tw2 is connected to the first control electrode of the second dual-gate transistor Ts2. For another example, the source of the first dual-gate transistor Ts1 and the drain of the second dual-gate transistor Ts2 may both be connected to the matching line ML, and the drain of the first dual-gate transistor Ts1 and the source of the second dual-gate transistor Ts2 may be connected to the first wire D0 and the second wire D1, respectively.
[0051] The storage circuit provided in the present application includes a storage cell based on a dual-gate transistor. By utilizing the characteristic that the current is larger when the two gates of the dual-gate transistor are turned on at the same time, a dual-gate transistor can be used to replace the two single-gate transistors used to store and search data in the existing storage cell. Among them, the first control electrode (i.e., the first gate) of the dual-gate transistor is used to store the written data as a storage node (SN) during the write operation, and the second control electrode (i.e., the second gate) of the dual-gate transistor is used to load the data to be searched to realize the search operation. Specifically, the first control electrode of the first dual-gate transistor Ts1 constitutes the first storage node SN0, and the first control electrode of the second dual-gate transistor Ts2 constitutes the second storage node SN1. The storage cell of the present application can realize its write and search functions with four transistors, and the total number of transistors used is small. Therefore, the storage cell occupies a smaller area and consumes less power, which can improve the storage density. In the storage cell of the present application, the dual-gate transistor can be a transistor made of oxide semiconductor material, which has extremely small static current and is very suitable for the storage cell, and can effectively improve the data retention time of the storage cell. Furthermore, a separate capacitor device does not need to be provided in the memory cell of the present application, and therefore a complicated capacitor process is not required, which can reduce the process difficulty and avoid the problem of a long time to write information when the capacitor stores data.
[0052] In some embodiments of the present application, the storage unit 01 of the storage circuit can be a TCAM storage unit, which can realize the function of searching for address data in the input data that is identical to the stored data except for the mask bits when one or more mask bits are present in the input data of the TCAM. Specifically, the first write transistor Tw1 and the first dual-gate transistor Ts1 cooperate with each other to realize the function of storing and searching one bit of data, and the second write transistor Tw2 and the second dual-gate transistor Ts2 cooperate with each other to realize the function of storing and searching another bit of data. The TCAM storage unit based on dual-gate transistors provided in the present application utilizes the characteristic that the current is larger when the two gates of the dual-gate transistor are turned on at the same time, and can use a dual-gate transistor to replace the two single-gate transistors used for storing and searching data in existing static TCAM storage units and dynamic TCAM storage units. The write and search functions of the TCAM can be realized by using four transistors, and the total number of transistors used is relatively small, so the storage unit occupies a smaller area and consumes less power, which can improve storage density.
[0053] 3 , in some embodiments of the present application, the first write transistor Tw1 and the second write transistor Tw2 may both be NMOS (N-type metal-oxide-semiconductor) transistors. The NMOS transistors may be directly manufactured using a backend of line (BEOL) process, which is beneficial to three-dimensional stacking of transistors within the memory cell, thereby improving storage density.
[0054] 4 , in some other embodiments of the present application, the first write transistor Tw1 and the second write transistor Tw2 may both be PMOS (P-type metal-oxide-semiconductor) transistors. PMOS transistors have no threshold voltage limitation, which helps reduce the power consumption of the storage unit.
[0055] 3 and 4 , in some embodiments of the present application, the first write transistor Tw1 and the second write transistor Tw2 in the memory cell 01 can both be single-gate transistors, i.e., the first write transistor Tw1 and the second write transistor Tw2 have only one control electrode (i.e., gate). In this case, the memory cell 01 is composed of two single-gate transistors and two dual-gate transistors.
[0056] Referring to Figure 5, in other embodiments of the present application, in order to further regulate the leakage of the first write transistor Tw1 and the second write transistor Tw2, the first write transistor Tw1 and the second write transistor Tw2 can also be configured as dual-gate transistors. In this case, the storage unit 01 is composed of four dual-gate transistors. Accordingly, the storage circuit can also include multiple write back gate lines WBG (write back gates), and the multiple write back gates WBG can be interconnected. The second control electrode of the first write transistor Tw1 and the second control electrode of the second write transistor Tw2 can be connected to one of the multiple write back gates WBG. Through the write back gate WBG, a fixed voltage can be applied to the second control electrode of the first write transistor Tw1 and the second control electrode of the second write transistor Tw2 to regulate the leakage of the first write transistor Tw1 and the second write transistor Tw2. Especially in the standby phase, the use of dual-gate transistors for the first write transistor Tw1 and the second write transistor Tw2 is beneficial for reducing leakage.
[0057] 3 to 5 , in some embodiments of the present application, when the storage unit 01 only needs to implement write operations and search operations, the plurality of first conductive lines D0 and the plurality of second conductive lines D1 may all be ground lines GND, that is, the second electrode of the first dual-gate transistor Ts1 and the second electrode of the second dual-gate transistor Ts2 may both be grounded.
[0058] 6 , in some other embodiments of the present application, when the memory cell 01 also needs to implement a read operation, the plurality of first bit lines BL0 may be a plurality of first write bit lines WBL0, and the plurality of second bit lines BL1 may be a plurality of second write bit lines WBL1; the plurality of first conductive lines D0 may be a first read bit line RBL0, and the plurality of second conductive lines D1 may be a second read bit line RBL1. During the read operation, the stored data may be read by reading the voltage change of the read bit line RBL.
[0059] FIG. 7 is a circuit diagram of a storage circuit provided in an embodiment of the present application.
[0060] Referring to Figure 7 , in an embodiment of the present application, when a dual-gate transistor-based TCAM memory cell array is formed on a substrate, multiple word lines WL (WL0, WL1, ..., WLn), multiple match lines ML (ML0, ML1, ..., MLn), multiple first conductive lines D0 (D00, D01, ..., D0n), and multiple second conductive lines D1 (D10, D11, ..., D1n) can all be arranged along a first direction x parallel to the substrate. Multiple first bit lines BL0 (BL00, BL01), multiple second bit lines BL1 (BL10, BL11), multiple first source lines SL0 (SL00, SL01), and multiple second source lines SL1 (SL10, SL11) can all be arranged along a second direction y parallel to the substrate. The first direction x and the second direction y can be substantially perpendicular. Figure 7 illustrates an array arrangement of n rows and two columns of TCAM memory cells. Figure 7 illustrates an example in which both the first write transistor Tw1 and the second write transistor Tw2 are single-gate transistors. For a TCAM memory cell whose two write transistors are formed by two dual-gate transistors, the difference lies in the addition of multiple write gate lines WBG. The multiple write gate lines WBG can be arranged and interconnected along a first direction x, or arranged and interconnected along a second direction y, without limitation herein. For convenience of description, the first direction x can be referred to as the row direction, and the second direction y can be referred to as the column direction.
[0061] The above-mentioned storage circuit provided in the embodiment of the present application can perform a write operation on each storage unit connected to one or more word lines when performing a write operation. Referring to Table 1, when the data to be written is defined as "0", the first storage node SN0 and the second storage node SN1 are written as "0" and "1" respectively; when the data to be written is defined as "1", the first storage node SN0 and the second storage node SN1 are written as "1" and "0" respectively. In response to the write instruction, the specific process of performing the write operation is: first, control the selected word line WL to be set to a first voltage, for example, set to "1", to control the first write transistor Tw1 and the second write transistor Tw2 connected to the selected word line WL to be turned on, and control the other word lines WL to be set to a second voltage, for example, set to "0", to control the first write transistor Tw1 and the second write transistor Tw2 connected to the other word lines WL to be turned off. Furthermore, the multiple match lines ML, multiple first conductive lines D0, multiple second conductive lines D1, multiple first source lines SL0, and multiple second source lines SL1 are all controlled to a second voltage, such as "0," turning off the first dual-gate transistor Ts1 and the second dual-gate transistor Ts2, thereby blocking the current path between the first conductive line D0 (or second conductive line D1) and the match line ML. Subsequently, based on the data to be written, the multiple first bit lines BL0 and the multiple second bit lines BL1 are controlled to a first voltage, such as "1," or a second voltage, such as "0," according to Table 1.
[0062] Table 1
[0063] Table 2
[0064] The above-mentioned storage circuit provided by the embodiment of the present application can perform a search operation on each storage cell connected to one or more match lines when performing a search operation. Referring to Table 2, it is defined that when the data to be searched is "0", the first source line SL0 and the second source line SL1 are input with "0" and "1" respectively; it is defined that when the data to be searched is "1", the first source line SL0 and the second source line SL1 are input with "1" and "0" respectively; it is defined that regardless of the value of a certain bit (the mask bit is "X" data), the first source line SL0 and the second source line SL1 are both input with "0". In response to the search instruction, the specific process of performing the search operation is as follows: controlling the multiple match lines ML to be precharged to a first voltage, for example, set to "1"; controlling the multiple first source lines SL0 and the multiple second source lines SL1 to be set to a first voltage, for example, set to "1" or a second voltage, for example, set to "0" according to the search data in accordance with Table 2; after a set time, measuring the voltage on the multiple match lines ML, reading the voltage changes of the multiple match lines ML, and determining whether the search data matches the storage data in the multiple storage cells. In other words, when searching for data, determining whether the search data matches the stored data requires reading the voltage change on the match line. The match line is used to implement data matching for the search function. Specifically, if the voltage on the match line ML drops significantly, it indicates that the search data and the stored data are consistent. If the voltage on the match line ML remains essentially unchanged, it indicates that the search data and the stored data are different or that the bit is a mask bit, as shown in Table 3.
[0065] Table 3
[0066] When the above-mentioned storage circuit provided in the embodiment of the present application supports a read operation, that is, multiple first conductive lines D0 are first read bit lines RBL0 and multiple second conductive lines D1 are second read bit lines RBL1, when performing a read operation, a read operation can be performed on each storage unit connected to a first source line SL0 and a second source line SL1. In response to a read instruction, the specific process of executing a read operation is as follows: controlling the plurality of first read bit lines RBL0 and the plurality of second read bit lines RBL1 to be precharged to a first voltage, such as "1," and controlling the plurality of match lines ML to be set to a second voltage, such as "0." Then, controlling the selected first source line SL0 and the selected second source line SL1 to be set to a first voltage, such as "1," to turn on the first dual-gate transistor Ts1 connected to the selected first source line SL0 and the second dual-gate transistor Ts2 connected to the selected second source line SL1. After a set time, measuring the voltages on the plurality of first read bit lines RBL0 and the plurality of second read bit lines RBL1 to read the voltage changes of the plurality of first read bit lines RBL0 and the plurality of second read bit lines RBL1. Specifically, if the data stored on the storage node is "1," the voltage of the corresponding read bit line drops significantly; if the data stored on the storage node is "0," the voltage of the corresponding read bit line remains substantially unchanged.
[0067] In an embodiment of the present application, to reduce the area of the memory cell 01, the transistors in the memory cell 01 can be stacked on the substrate. Specifically, in a memory cell 01, the first write transistor Tw1 and the first dual-gate transistor Ts1 can be stacked on the substrate, and the second write transistor Tw2 and the second dual-gate transistor Ts2 can be stacked on the substrate. Furthermore, the first write transistor Tw1 and the second write transistor Tw2 can be arranged in the same plane parallel to the substrate, while the first dual-gate transistor Ts1 and the second dual-gate transistor Ts2 can be arranged in another plane parallel to the substrate.
[0068] Figure 8 is a structural schematic diagram of a transistor stack in a memory cell in a memory circuit provided in an embodiment of the present application; Figure 9 is a structural schematic diagram of the memory circuit provided in an embodiment of the present application in the xy direction; and Figure 10 is a structural schematic diagram of the memory circuit provided in an embodiment of the present application in the yz direction.
[0069] In some embodiments of the present application, the three-dimensional stacking structure of the TCAM memory cell can be physically implemented using front-end of line (FEOL) + back-end of line (BEOL) transistors. Specifically, referring to Figures 8 to 10, in a memory cell 01, the first write transistor Tw1 and the second write transistor Tw2 are respectively arranged on the substrate, the first dual-gate transistor Ts1 can be stacked on the first write transistor Tw1, and the second dual-gate transistor Ts2 can be stacked on the second write transistor Tw2, that is, the first dual-gate transistor Ts1 is stacked on the first write transistor Tw1, and the second dual-gate transistor Ts2 is stacked on the second write transistor Tw2. Figure 8 shows a structural schematic diagram of the first dual-gate transistor Ts1 stacked on the first write transistor Tw1. The first write transistor Tw1 and the second write transistor Tw2 can be front-end process transistors, and the first dual-gate transistor Ts1 and the second dual-gate transistor Ts2 are back-end process transistors. After fabricating silicon-based transistors as the first transistor Tw1 and the second write transistor Tw2 using a front-end process, a back-end process can be used to form the first dual-gate transistor Ts1, the second dual-gate transistor Ts2, the word line WL, the match line ML, the first bit line BL0, the second bit line BL1, the first source line SL0, the second source line SL1, the first conductive line D0, and the second conductive line D1. Figures 9 and 10 illustrate the structure of two memory cells arranged in a column direction, using the first conductive line D0 and the second conductive line D1 as ground lines GND as an example.
[0070] Figure 11 is a circuit schematic diagram of a transistor stack in a memory cell in a memory circuit provided in an embodiment of the present application; Figure 12 is a structural schematic diagram corresponding to Figure 11; Figure 13 is another structural schematic diagram of the memory circuit provided in an embodiment of the present application in the xy direction; Figure 14 is another structural schematic diagram of the memory circuit provided in an embodiment of the present application in the yz direction.
[0071] In other embodiments of the present application, a three-dimensional stacked structure of a TCAM memory cell can be physically implemented using back-end-of-line (BEOL) channel-all-around (CAA) transistors. Specifically, referring to Figures 11 to 14, in a memory cell 01, a first dual-gate transistor Ts1 and a second dual-gate transistor Ts2 are respectively disposed on a substrate, a first write transistor Tw1 can be stacked on the first dual-gate transistor Ts1, and a second write transistor Tw2 can be stacked on the second dual-gate transistor Ts2, that is, the first write transistor Tw1 is stacked on the first dual-gate transistor Ts1, and the second write transistor Tw2 is stacked on the second dual-gate transistor Ts2. The first write transistor Tw1, the second write transistor Tw2, the first dual-gate transistor Ts1, and the second dual-gate transistor Ts2 are all back-end-of-line (BEOL) ring-channel transistors.
[0072] Figures 11 to 14 are all illustrated by taking the first wire D0 and the second wire D1 as the ground wire GND as an example, wherein Figure 13 shows a top view structural diagram of n rows and two columns of memory cells, and Figure 14 shows a side view structural diagram of two memory cells arranged in the row direction.
[0073] Based on the same inventive concept, an embodiment of the present application further provides a memory. Referring to FIG. 15 , the memory includes a controller and the above-mentioned storage circuit provided in an embodiment of the present application. The controller is used to access the storage circuit.
[0074] Based on the same inventive concept, an embodiment of the present application also provides an electronic device. Referring to Figure 15, the electronic device includes a circuit board (not shown in Figure 15) and a memory provided by an embodiment of the present application. The memory is electrically connected to the circuit board. The electronic device may also include other chips or independent devices.
[0075] 16 , the electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The electronic device 200 includes a bus 205 and a system on chip (SoC) 210 connected to the bus 205. The SoC 210 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SoC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first RAM 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash memory (EFlash), etc. The AP 211, GPU 212, and first RAM 213 may be integrated into a die, or may be separately provided in multiple dies. The electronic device 200 may further include a second RAM 220 connected to the SOC 210 via a bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally larger than that of the first RAM 213, but the reading speed is generally slower than that of the first RAM 213. In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 connected to the SOC 210 via a bus 205. The communication chip 230 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 240 may be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 may be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, to obtain a faster data transmission rate between chips.
[0076] Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of protection of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.
Claims
1. A storage circuit, characterized in that: include: a plurality of memory cells, a plurality of word lines, a plurality of match lines, a plurality of first bit lines, a plurality of second bit lines, a plurality of first conductive lines, a plurality of second conductive lines, a plurality of first source lines, and a plurality of second source lines; At least one of the plurality of memory cells comprises a first write transistor, a second write transistor, a first double-gate transistor, and a second double-gate transistor; in one of the memory cells: The first control electrode of the first write transistor and the first control electrode of the second write transistor are both connected to the same word line among the plurality of word lines; The first electrode of the first double-gate transistor and the first electrode of the second double-gate transistor are both connected to one of the plurality of match lines; A first electrode of the first write transistor is connected to a first bit line among the plurality of first bit lines, and a first electrode of the second write transistor is connected to a second bit line among the plurality of second bit lines; The second electrode of the first write transistor is connected to the first control electrode of the first double-gate transistor, and the second electrode of the second write transistor is connected to the first control electrode of the second double-gate transistor; The second control electrode of the first double-gate transistor is connected to a first source line among the plurality of first source lines, and the second control electrode of the second double-gate transistor is connected to a second source line among the plurality of second source lines; The second electrode of the first double-gate transistor is connected to a first conductive line among the plurality of first conductive lines, and the second electrode of the second double-gate transistor is connected to a second conductive line among the plurality of second conductive lines.
2. The storage circuit according to claim 1, wherein: The plurality of first conductive lines and the plurality of second conductive lines are both ground lines.
3. The storage circuit according to claim 1, wherein: The plurality of first bit lines are a plurality of first write bit lines, and the plurality of second bit lines are a plurality of second write bit lines; The plurality of first conductive lines are first read bit lines, and the plurality of second conductive lines are second read bit lines.
4. The storage circuit according to any one of claims 1 to 3, characterized in that: The storage circuit further includes a substrate; the plurality of word lines, the plurality of match lines, the plurality of first conductive lines, and the plurality of second conductive lines are all arranged along a first direction parallel to the substrate, the plurality of first bit lines, the plurality of second bit lines, the plurality of first source lines, and the plurality of second source lines are all arranged along a second direction parallel to the substrate, and the first direction and the second direction are arranged perpendicularly; In one of the memory cells, the first write transistor and the first dual-gate transistor are stacked and arranged on the substrate, and the second write transistor and the second dual-gate transistor are stacked and arranged on the substrate.
5. The storage circuit according to claim 4, wherein: In one of the memory cells, the first write transistor and the second write transistor are respectively arranged on the substrate, the first double-gate transistor is stacked on the first write transistor, and the second double-gate transistor is stacked on the second write transistor; The first write transistor and the second write transistor are front-end process transistors, and the first double-gate transistor and the second double-gate transistor are back-end process transistors.
6. The storage circuit according to claim 4, wherein: In one of the memory cells, the first double-gate transistor and the second double-gate transistor are respectively disposed on the substrate, the first write transistor is stacked on the first double-gate transistor, and the second write transistor is stacked on the second double-gate transistor; The first write transistor, the second write transistor, the first double-gate transistor and the second double-gate transistor are all transistors of a ring-channel structure in a back-end process.
7. The storage circuit according to any one of claims 1 to 6, characterized in that: The first write transistor and the second write transistor are both NMOS transistors; or, the first write transistor and the second write transistor are both PMOS transistors.
8. The storage circuit according to any one of claims 1 to 6, characterized in that: Also included are a plurality of write gate lines; The first write transistor and the second write transistor are both dual-gate transistors, and the second control electrode of the first write transistor and the second control electrode of the second write transistor are both connected to one of the plurality of write gate lines.
9. The storage circuit according to any one of claims 1 to 8, characterized in that: The storage unit is a storage unit of a ternary content addressable memory TCAM.
10. A memory, characterized in that: The invention comprises a controller and a storage circuit as claimed in any one of claims 1 to 9; the controller is used to access the storage circuit.
11. An electronic device, characterized in that: The invention comprises a circuit board and the memory as claimed in claim 10, wherein the memory is electrically connected to the circuit board.
12. A method for operating a storage circuit, characterized in that: The storage circuit includes a plurality of storage cells, a plurality of word lines, a plurality of match lines, a plurality of first bit lines, a plurality of second bit lines, a plurality of first conductive lines, a plurality of second conductive lines, a plurality of first source lines, and a plurality of second source lines; at least one storage cell among the plurality of storage cells includes a first write transistor, a second write transistor, a first double-gate transistor, and a second double-gate transistor; in one of the storage cells: a first control electrode of the first write transistor and a first control electrode of the second write transistor are both connected to the same word line among the plurality of word lines; a first electrode of the first double-gate transistor and a first electrode of the second double-gate transistor are both connected to a match line among the plurality of match lines; a first electrode of the first write transistor is connected to a match line among the plurality of first bit lines; The first bit line is connected, the first electrode of the second write transistor is connected to a second bit line among the plurality of second bit lines; the second electrode of the first write transistor is connected to the first control electrode of the first double-gate transistor, and the second electrode of the second write transistor is connected to the first control electrode of the second double-gate transistor; the second control electrode of the first double-gate transistor is connected to a first source line among the plurality of first source lines, and the second control electrode of the second double-gate transistor is connected to a second source line among the plurality of second source lines; the second electrode of the first double-gate transistor is connected to a first wire among the plurality of first wires, and the second electrode of the second double-gate transistor is connected to a second wire among the plurality of second wires; the operation method comprises: In response to a write instruction, the selected word line is controlled to be set to a first voltage to control the first write transistor and the second write transistor connected to the selected word line to be turned on, and the other word lines are controlled to be set to a second voltage to control the first write transistor and the second write transistor connected to the other word lines to be turned off; the plurality of matching lines, the plurality of first conductive lines, the plurality of second conductive lines are controlled to be turned on, The conductive wires, the plurality of first source lines and the plurality of second source lines are all set to the second voltage; and the plurality of first bit lines and the plurality of second bit lines are controlled to be set to the first voltage or the second voltage according to the data to be written.
13. A method for operating a storage circuit, characterized in that: The storage circuit includes a plurality of storage cells, a plurality of word lines, a plurality of match lines, a plurality of first bit lines, a plurality of second bit lines, a plurality of first conductive lines, a plurality of second conductive lines, a plurality of first source lines, and a plurality of second source lines; at least one storage cell among the plurality of storage cells includes a first write transistor, a second write transistor, a first double-gate transistor, and a second double-gate transistor; in one of the storage cells: a first control electrode of the first write transistor and a first control electrode of the second write transistor are both connected to the same word line among the plurality of word lines; a first electrode of the first double-gate transistor and a first electrode of the second double-gate transistor are both connected to a match line among the plurality of match lines; a first electrode of the first write transistor is connected to a match line among the plurality of first bit lines; The first bit line is connected, the first electrode of the second write transistor is connected to a second bit line among the plurality of second bit lines; the second electrode of the first write transistor is connected to the first control electrode of the first double-gate transistor, and the second electrode of the second write transistor is connected to the first control electrode of the second double-gate transistor; the second control electrode of the first double-gate transistor is connected to a first source line among the plurality of first source lines, and the second control electrode of the second double-gate transistor is connected to a second source line among the plurality of second source lines; the second electrode of the first double-gate transistor is connected to a first wire among the plurality of first wires, and the second electrode of the second double-gate transistor is connected to a second wire among the plurality of second wires; the operation method comprises: In response to a search instruction, the plurality of match lines are controlled to be precharged to a first voltage; according to search data, the plurality of first source lines and the plurality of second source lines are controlled to be set to the first voltage or the second voltage; after a set time, the voltage changes of the plurality of match lines are read to determine whether the search data matches the storage data in the plurality of storage cells.
14. A method for operating a storage circuit, characterized in that: The storage circuit includes a plurality of storage cells, a plurality of word lines, a plurality of match lines, a plurality of first write bit lines, a plurality of second write bit lines, a plurality of first read bit lines, a plurality of second read bit lines, a plurality of first source lines and a plurality of second source lines; at least one storage cell among the plurality of storage cells includes a first write transistor, a second write transistor, a first double-gate transistor and a second double-gate transistor; in one of the storage cells: a first control electrode of the first write transistor and a first control electrode of the second write transistor are both connected to the same word line among the plurality of word lines; a first electrode of the first double-gate transistor and a first electrode of the second double-gate transistor are both connected to a match line among the plurality of match lines; a first electrode of the first write transistor is connected to a second match line among the plurality of first write bit lines; The first electrode of the second write transistor is connected to a write bit line, the first electrode of the second write transistor is connected to a second write bit line among the plurality of second write bit lines; the second electrode of the first write transistor is connected to the first control electrode of the first double-gate transistor, and the second electrode of the second write transistor is connected to the first control electrode of the second double-gate transistor; the second control electrode of the first double-gate transistor is connected to a first source line among the plurality of first source lines, and the second control electrode of the second double-gate transistor is connected to a second source line among the plurality of second source lines; the second electrode of the first double-gate transistor is connected to a first read bit line among the plurality of first read bit lines, and the second electrode of the second double-gate transistor is connected to a second read bit line among the plurality of second read bit lines; the operation method comprises: In response to a read instruction, the plurality of first read bit lines and the plurality of second read bit lines are controlled to be precharged to a first voltage, and the plurality of match lines are controlled to be set to a second voltage; the selected first source line and the selected second source line are controlled to be set to the first voltage to control the first dual-gate transistor connected to the selected first source line and the second dual-gate transistor connected to the selected second source line to be turned on; and the voltage changes of the plurality of first read bit lines and the plurality of second read bit lines are read.