Voltage-resistant silicon nitride film growth process, HEMT device and preparation method

Abstract

The invention discloses a voltage-withstanding silicon nitride film growth process, an HEMT device and a preparation method. The voltage-withstanding silicon nitride film growth process comprises the following steps: providing a substrate; introducing a first precursor; first gas is introduced for purging; introducing a second precursor; second gas is introduced for purging; and performing in-situ third gas plasma treatment to obtain the high-pressure-resistant compact silicon nitride film. The prepared high-voltage-resistant compact silicon nitride thin film layer is used as a dielectric layer between the gate metal and the enhancement structure layer, so that the threshold voltage of the HEMT device can be improved, the reliability of the gate under long-time electric stress can be improved, the problems of gate degradation and even destructive breakdown of the device are effectively avoided, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit technology, and in particular to a voltage-resistant silicon nitride film growth process and a HEMT device and a preparation method. Background Art

[0002] Power electronics, also known as power devices, are a major force in the semiconductor application market. As silicon-based power device technology matures, its performance has reached the physical limits of the material. Consequently, it is difficult to meet future demands for power and high-frequency applications.

[0003] With the widespread adoption of third-generation materials, represented by GaN, GaN-based HFETs, manufactured using these materials, are highly competitive in the current power semiconductor device market. p-GaN HEMTs (p-GaN high electron mobility transistors) offer a simple fabrication process, effectively avoid reliability issues caused by high interface defect density, and effectively reduce on-resistance through gate hole injection, making them the industry's unanimous choice for enhanced structure.

[0004] With the commercialization of p-type gate enhancement-mode GaN HEMTs (HEMTs), gate degradation and breakdown in p-GaN HEMTs under high gate electric fields have attracted widespread attention from both industry and academia. In particular, GaN, as a wide-bandgap semiconductor material, has a wide distribution of interface defect energy levels, resulting in a long time constant for carrier emission from defects, posing new challenges to the reliability research of GaN power devices.

[0005] Limited by the reverse turn-on condition of the Schottky gate, the maximum safe operating gate voltage of p-GaN HEMTs is generally less than 6V. Consequently, the safe operating gate voltage swing of p-GaN HEMTs is small, with a safe gate voltage margin of only 1-2V. Therefore, increasing the gate operating voltage while simultaneously improving gate reliability under long-term electrical stress to avoid gate degradation or even destructive breakdown is a key issue in improving the performance of p-GaN HEMTs. Summary of the Invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a pressure-resistant silicon nitride film growth process and a HEMT device and preparation method.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] The present invention provides a pressure-resistant silicon nitride film growth process, comprising the following steps:

[0009] Step S11: providing a substrate;

[0010] Step S12: introducing the first precursor;

[0011] Step S13: introducing the first gas for purging;

[0012] Step S14: introducing a second precursor;

[0013] Step S15: introducing a second gas for purging;

[0014] Step S16: performing in-situ third gas plasma treatment to obtain a dense silicon nitride film resistant to high pressure;

[0015] The steps S12 to S16 constitute a process cycle, which is performed one or more times.

[0016] Furthermore, the first precursor includes silane, the second precursor includes ammonia plasma, and the first gas to the third gas include nitrogen.

[0017] Furthermore, the in-situ third gas plasma treatment is an in-situ nitrogen plasma annealing treatment.

[0018] Furthermore, the in-situ nitrogen plasma annealing has an annealing temperature of 200-400° C., an annealing power of 30-70 W, and an annealing time of 50-70 s.

[0019] The present invention also provides a HEMT device, comprising:

[0020] A channel layer and a barrier layer are sequentially provided on the surface of the substrate;

[0021] a gate structure provided on the surface of the barrier layer, the gate structure comprising an enhancement structure layer, a silicon nitride thin film layer and a metal gate layer stacked in sequence in a direction away from the surface of the barrier layer;

[0022] The silicon nitride film layer is prepared by the above-mentioned voltage-resistant silicon nitride film growth process and with the enhanced structure layer as a substrate, so as to improve the device threshold voltage and gate reliability.

[0023] Furthermore, the channel layer includes a GaN layer, the barrier layer includes an AlGaN layer, and the enhancement structure layer includes a p-GaN layer.

[0024] Furthermore, the thickness of the silicon nitride film layer is 10-20 nm.

[0025] Furthermore, it also includes: an ohmic contact provided on the surface of the barrier layer on both sides of the gate structure, a passivation layer provided on the surface of the barrier layer, the gate structure and the ohmic contact are located in the passivation layer, and the top of the metal gate layer and the top of the ohmic contact are exposed on the surface of the passivation layer, and a field plate provided on the surface of the passivation layer, and the field plate is in contact with the top of the metal gate layer.

[0026] Furthermore, it also includes: a mesa isolation structure provided on the surface of the barrier layer, the bottom of the mesa isolation structure is located in the channel layer, and the gate structure, the ohmic contact and the field plate are located on the active area defined by the mesa isolation structure.

[0027] The present invention also provides a method for preparing a HEMT device, comprising the following steps:

[0028] Step S21: providing a substrate;

[0029] Step S22: forming a channel layer, a barrier layer and an enhancement structure layer in sequence on the surface of the substrate;

[0030] Step S23: forming a silicon nitride thin film layer and a metal gate layer in sequence on the surface of the enhancement structure layer;

[0031] Step S24: patterning the metal gate layer, the silicon nitride thin film layer, and the enhanced structure layer to form a gate structure;

[0032] The silicon nitride thin film layer is prepared by the above-mentioned voltage-resistant silicon nitride thin film growth process and with the enhanced structural layer as a substrate, so as to improve the device threshold voltage and gate reliability.

[0033] Furthermore, the channel layer includes a GaN layer, the barrier layer includes an AlGaN layer, and the enhancement structure layer includes a p-GaN layer.

[0034] Furthermore, the thickness of the silicon nitride film layer is 10-20 nm.

[0035] Furthermore, before forming the silicon nitride thin film layer, the method further includes: cleaning the surface of the enhancement structure layer;

[0036] After cleaning, the method further includes: forming a mesa isolation intermediate structure on the surface of the enhancement structure layer, so that the bottom of the mesa isolation intermediate structure is located in the channel layer;

[0037] Then, the silicon nitride thin film layer is formed on the surface of the enhancement structure layer to cover the mesa isolation intermediate structure;

[0038] When forming the gate structure, the metal gate layer, the silicon nitride thin film layer and the enhancement structure layer are patterned, and the redundant mesa isolation intermediate structure above the surface of the barrier layer is removed to form a mesa isolation structure, the active area is defined by the mesa isolation structure, and the formed gate structure is located on the surface of the barrier layer within the active area.

[0039] Furthermore, after forming the gate structure, the method further includes:

[0040] Within the active area, ohmic contacts protruding from the surface of the barrier layer are formed on the surface of the barrier layer on both sides of the gate structure;

[0041] forming a passivation layer on the surface of the barrier layer, covering the mesa isolation structure, the gate structure, and the ohmic contact, and exposing the tops of the gate structure and the ohmic contact to the surface of the passivation layer;

[0042] A field plate is formed on the surface of the passivation layer, and the field plate is in contact with the top surface of the metal gate layer.

[0043] As can be seen from the above technical solution, the present invention forms a dense, high-quality, voltage-resistant silicon nitride thin film layer between the metal gate layer and the enhancement structure layer of the HEMT device gate structure through an atomic layer deposition process based on in-situ gas plasma treatment (in-situ third gas plasma treatment). This can improve the device threshold voltage while also improving gate reliability under long-term electrical stress. Therefore, it can effectively avoid gate degradation and even destructive breakdown problems in the device, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 The figure is a flowchart of a pressure-resistant silicon nitride film growth process according to a preferred embodiment of the present invention.

[0045] Figure 2 FIG. 1 is a schematic structural diagram of a HEMT device according to a preferred embodiment of the present invention.

[0046] Figure 3-Figure 9 FIG. 1 is a schematic diagram of the process steps of a method for preparing a HEMT device according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0048] In view of the problem that existing p-GaN HEMTs devices are limited by the reverse turn-on of the Schottky gate, resulting in a low gate operating voltage, a small gate safe operating voltage swing and a small safe gate voltage margin, and are prone to gate degradation or even destructive breakdown, making it difficult to ensure the reliability of the gate under long-term electrical stress, the present invention provides a voltage-resistant silicon nitride thin film growth process, comprising the following steps:

[0049] Step S11: providing a substrate;

[0050] Step S12: introducing the first precursor;

[0051] Step S13: introducing the first gas for purging;

[0052] Step S14: introducing a second precursor;

[0053] Step S15: introducing a second gas for purging;

[0054] Step S16: performing in-situ third gas plasma treatment to obtain a dense silicon nitride film resistant to high pressure;

[0055] The steps S12 to S16 constitute a process cycle, which is performed one or more times.

[0056] The present invention also provides a HEMT device, comprising:

[0057] A channel layer and a barrier layer are sequentially provided on the surface of the substrate;

[0058] a gate structure provided on the surface of the barrier layer, the gate structure comprising an enhancement structure layer, a silicon nitride thin film layer and a metal gate layer stacked in sequence in a direction away from the surface of the barrier layer;

[0059] The silicon nitride film layer is prepared by the above-mentioned voltage-resistant silicon nitride film growth process and with the enhanced structure layer as a substrate, so as to improve the device threshold voltage and gate reliability.

[0060] The present invention also provides a method for preparing a HEMT device, comprising the following steps:

[0061] Step S21: providing a substrate;

[0062] Step S22: forming a channel layer, a barrier layer and an enhancement structure layer in sequence on the surface of the substrate;

[0063] Step S23: forming a silicon nitride thin film layer and a metal gate layer in sequence on the surface of the enhancement structure layer;

[0064] Step S24: patterning the metal gate layer, the silicon nitride thin film layer, and the enhanced structure layer to form a gate structure;

[0065] The silicon nitride thin film layer is formed by the above-mentioned voltage-resistant silicon nitride thin film growth process and with the enhanced structural layer as a substrate, so as to improve the device threshold voltage and gate reliability.

[0066] The present invention forms a dense, high-quality, voltage-resistant silicon nitride thin film layer between the metal gate layer and the enhancement structure layer of the HEMT device gate structure using an atomic layer deposition process based on in-situ gas plasma treatment (in-situ third gas plasma treatment). This can increase the device threshold voltage while improving gate reliability under long-term electrical stress. This effectively prevents gate degradation and even destructive breakdown in the device, thereby improving device performance.

[0067] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0068] refer to Figure 1 A pressure-resistant silicon nitride film growth process of the present invention is implemented by adopting the atomic layer deposition process solution based on in-situ gas plasma annealing of the present invention, and specifically includes the following steps:

[0069] In the above step S11 , a substrate is provided for forming a high-pressure-resistant dense silicon nitride film on the surface of the substrate through an atomic layer deposition process scheme based on in-situ gas plasma annealing.

[0070] In the above steps S12 to S15, a conventional silicon nitride atomic layer deposition process is performed to grow a normal silicon nitride thin film on the surface of the substrate at a process temperature of 200 to 400° C. Specifically, the process includes:

[0071] In step S12, silane as a first precursor is introduced and adsorbed on the surface of the substrate. The silane may be, for example, diisopropylaminosilane (DIPAS).

[0072] In step S13 , nitrogen gas is introduced as a first gas to perform nitrogen purge to remove excess diisopropylaminosilane first precursor on the surface of the substrate.

[0073] In step S14 , ammonia plasma as a second precursor is introduced and reacts with the diisopropylaminosilane first precursor adsorbed on the surface of the substrate to form a silicon nitride film.

[0074] In step S15 , nitrogen gas is introduced as a second gas to perform nitrogen purge to remove excess unreacted substances on the surface of the substrate, thereby forming a silicon nitride film on the surface of the substrate.

[0075] After executing one process cycle of the above-mentioned atomic layer deposition process, the following step S16 is then executed.

[0076] In step S16, an in-situ nitrogen plasma annealing is performed as an in-situ third gas plasma treatment to form a dense and high-quality silicon nitride (SiN x ) film. The annealing temperature is 200-400° C.; the annealing power is 30-70 W; and the annealing time is 50-70 s, preferably 60 s.

[0077] Steps S12 to S16 constitute a new process cycle in the atomic layer deposition process scheme based on in-situ nitrogen plasma annealing of the present invention, and one or more cycles are performed until a high-pressure-resistant dense silicon nitride film of a desired thickness is obtained.

[0078] In the present invention's pressure-resistant silicon nitride film growth process, an in-situ gas plasma annealing step S16 is added after each atomic layer deposition process cycle, steps S12 to S15, forming the present invention's atomic layer deposition process based on in-situ atomic layer annealing. During the in-situ nitrogen plasma annealing, the deposited conventional silicon nitride film is bombarded with the resulting nitrogen plasma at low power, effectively increasing the film density while replenishing nitrogen vacancies in the film. This allows the production of a dense, pressure-resistant, high-quality silicon nitride film. The high-voltage-resistant, dense silicon nitride film produced using the present invention's method, when used as the dielectric layer between the gate metal and p-GaN in p-GaN HEMTs, can increase the device threshold voltage while improving gate reliability under long-term electrical stress and preventing destructive device breakdown, thereby becoming the key to addressing the aforementioned issues with the prior art.

[0079] refer to Figure 2 A HEMT device of the present invention includes a channel layer 11 and a barrier layer 12 sequentially disposed on the surface of a substrate 10 , and a gate structure 14 disposed on the surface of the barrier layer 12 .

[0080] The gate structure 14 includes an enhanced structure layer 15, a silicon nitride film layer 16, and a metal gate layer 17 stacked in sequence in a direction away from the surface of the barrier layer 12. In addition, the silicon nitride film layer 16 in the gate structure 14 stack is a dense, high-quality, voltage-resistant silicon nitride (SiN) film obtained by the above-mentioned voltage-resistant silicon nitride film growth process of the present invention and with the enhanced structure layer 15 as the substrate (the substrate also includes the barrier layer 12, the channel layer 11, and the substrate 10 located below the enhanced structure layer 15). x ) film, which can increase the device threshold voltage and simultaneously improve the gate reliability under long-term electrical stress, thereby effectively avoiding gate degradation and device destructive breakdown problems and improving device performance.

[0081] In some embodiments, the channel layer 11 includes a GaN layer (GaN channel layer 11); the barrier layer 12 includes an AlGaN layer (AlGaN barrier layer 12); and the enhancement structure layer 15 includes a p-GaN layer (p-type GaN enhancement structure layer 15). Thus, the HEMT device of the present invention is a p-GaN HEMT device.

[0082] Furthermore, the thickness of the silicon nitride thin film layer 16 is 10-20 nm.

[0083] refer to Figure 2 In some embodiments, source and drain (S, D) ohmic contacts 13 are provided on the surfaces of the AlGaN barrier layer 12 on both sides of the gate structure 14 , and the bottoms of the ohmic contacts 13 are in contact with the surface of the underlying AlGaN barrier layer 12 .

[0084] In some embodiments, a passivation layer 19 is further provided on the surface of the AlGaN barrier layer 12 . The gate structure 14 and the two ohmic contacts 13 are located in the passivation layer 19 , and the top of the metal gate layer 17 in the gate structure 14 and the top of the ohmic contacts 13 are exposed on the surface of the passivation layer 19 .

[0085] In some embodiments, a field plate 18 is further provided on the surface of the passivation layer 19 , and the field plate 18 is in contact with the top of the metal gate layer 17 .

[0086] In some embodiments, a mesa isolation structure 20 is further provided on the surface of the barrier layer 12, and the bottom of the mesa isolation structure 20 is located in the channel layer 11. The region between the two mesa isolation structures 20 shown in the figure defines an active region, and the gate structure 14, ohmic contact 13, and field plate 18 are located on the active region. In other words, the p-GaN HEMT device is located on the active region.

[0087] In some embodiments, the substrate 10 includes a SiC substrate 10 , a sapphire substrate 10 , a silicon substrate 10 , a diamond substrate 10 , and the like.

[0088] The mesa isolation structure 20 is made of silicon dioxide.

[0089] The metal gate layer 17 is made of at least one of TiN, Ni, Ti and Au.

[0090] The ohmic contact 13 material includes at least one of Ti, Al, Ni, and Au.

[0091] The field plate 18 material includes Ti, Pt or Al.

[0092] The passivation layer 19 is made of silicon dioxide or silicon nitride.

[0093] The substrate 10 , the mesa isolation structure 20 , the metal gate layer 17 , the ohmic contact 13 , the field plate 18 , and the passivation layer 19 may also be made of any other suitable materials.

[0094] The following is a further detailed description of a method for preparing a HEMT device of the present invention through specific embodiments and in conjunction with the accompanying drawings.

[0095] refer to Figure 3-Figure 9 The HEMT device preparation method of the present invention can be used to prepare, for example Figure 2 The HEMT device of the present invention specifically includes the following steps:

[0096] Step S31: sample cleaning.

[0097] like Figure 3 As shown, a silicon substrate 10 is used, for example, on which a GaN channel layer 11, an AlGaN barrier layer 12, and a p-GaN enhancement structure layer 15 are sequentially formed. The substrate 10 having the GaN channel layer 11, the AlGaN barrier layer 12, and the p-GaN enhancement structure layer 15 sequentially formed thereon is used as a sample, and the sample is cleaned to obtain a clean mesa (base surface) of the p-GaN enhancement structure layer 15.

[0098] Step S32: table isolation.

[0099] like Figure 4 As shown, a mesa isolation intermediate structure 201 is formed on the surface of the cleaned reinforcement structure layer 15 , and the bottom of the mesa isolation intermediate structure 201 is located in the channel layer 11 .

[0100] In this embodiment, two trenches 202 are formed on the surface of the p-GaN enhancement layer 15 through photolithography and etching processes, with the bottoms of the trenches 202 located within the GaN channel layer 11. Furthermore, by filling the trenches 202 with a dielectric such as silicon dioxide and planarizing them, a mesa isolation intermediate structure 201 is formed on the surface of the p-GaN enhancement layer 15, with its bottom located within the GaN channel layer 11. The region between the two mesa isolation intermediate structures 201 defines an active region, which is used to further fabricate a p-GaN HEMT device according to the present invention.

[0101] Step S33: preparing a high-pressure-resistant dense silicon nitride thin film layer 16 based on atomic layer annealing.

[0102] like Figure 5 As shown, the pressure-resistant silicon nitride thin film growth process of the present invention is adopted, and the surface of the p-GaN enhanced structure layer 15 is used as the base surface, and a high-pressure-resistant dense silicon nitride thin film layer 16 is formed on the surface of the p-GaN enhanced structure layer 15, and the mesa isolation intermediate structure 201 is covered.

[0103] In some embodiments, the silicon nitride film layer 16 (SiN x ) has a thickness of 10 to 20 nm. In this embodiment, the thickness of the silicon nitride thin film layer 16 is 15 nm.

[0104] Step S34: gate metal deposition.

[0105] like Figure 6 As shown, a TiN metal gate layer 17 serving as a gate metal is deposited on the surface of the silicon nitride film layer 16 .

[0106] Step S35 : preparing the gate structure 14 .

[0107] like Figure 7 As shown, the TiN metal gate layer 17 , the silicon nitride thin film layer 16 and the p-GaN enhancement structure layer 15 are patterned to form a gate structure 14 on the surface of the AlGaN barrier layer 12 .

[0108] In some embodiments, the TiN metal gate layer 17, the silicon nitride thin film layer 16, and the p-GaN enhancement structure layer 15 are patterned through photolithography and etching processes to form a gate structure 14. Furthermore, when etching the p-GaN enhancement structure layer 15, the redundant mesa isolation intermediate structure 201 located in the p-GaN enhancement structure layer 15 above the surface of the AlGaN barrier layer 12 is removed, thereby forming a new mesa isolation structure 20 on the surface of the AlGaN barrier layer 12. The area between the two mesa isolation structures 20 shown in the figure defines an active region, and during patterning, the formed gate structure 14 is positioned on the surface of the AlGaN barrier layer 12 within the active region. Consequently, a stacked structure of the patterned p-GaN enhancement structure layer 15, the silicon nitride thin film layer 16, and the TiN metal gate layer 17 is formed in the gate structure 14. Using a high-voltage-resistant dense silicon nitride film layer 16 as a dielectric layer between the TiN metal gate layer 17 and the p-GaN enhancement structure layer 15 can improve the device threshold voltage while improving gate reliability under long-term electrical stress and avoiding destructive breakdown of the device.

[0109] Step S36: preparing the ohmic contact 13 .

[0110] like Figure 8 As shown, source and drain (S, D) ohmic contacts 13 protruding from the surface of the AlGaN barrier layer 12 are formed on the surface of the AlGaN barrier layer 12 on both sides of the gate structure 14 within the active area by a metal sputtering process or other applicable process.

[0111] Step S37 : forming a passivation layer 19 and preparing a field plate 18 .

[0112] like Figure 9 As shown, a passivation layer 19 is deposited on the surface of the AlGaN barrier layer 12 to cover the mesa isolation structure 20, the gate structure 14, and the ohmic contact 13. Then, the surface of the passivation layer 19 is planarized so that the metal gate layer 17 in the gate structure 14 and the top of the ohmic contact 13 are exposed on the surface of the passivation layer 19.

[0113] Finally, a field plate 18 metal is deposited on the surface of the passivation layer 19 so that the field plate 18 metal covers the top surface of the metal gate layer 17, and the field plate 18 metal is patterned through photolithography and etching processes to form a field plate 18 (Field Plate) on the surface of the passivation layer 19 that contacts the top surface of the metal gate layer 17.

[0114] In summary, the present invention forms a dense, high-quality, voltage-resistant silicon nitride thin film layer 16 between the metal gate layer 17 and the p-GaN enhancement structure layer 15 in the gate structure 14 of the p-GaN HEMT device using a novel atomic layer deposition process based on in-situ nitrogen plasma annealing treatment. This can improve the device threshold voltage while also enhancing gate reliability under long-term electrical stress. This effectively prevents gate degradation and even destructive breakdown in the device, thereby improving device performance.

[0115] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A process for growing a pressure-resistant silicon nitride film, characterized in that: The following steps are involved: Step S11: providing a substrate; Step S12: introducing the first precursor; Step S13: introducing the first gas for purging; Step S14: introducing a second precursor; Step S15: introducing a second gas for purging; Step S16: performing in-situ third gas plasma treatment to obtain a dense silicon nitride film resistant to high pressure; The steps S12 to S16 constitute a process cycle, which is performed one or more times.

2. The pressure-resistant silicon nitride thin film growth process according to claim 1, characterized in that: The first precursor includes silane, the second precursor includes ammonia plasma, and the first gas to the third gas include nitrogen.

3. The pressure-resistant silicon nitride thin film growth process according to claim 2, characterized in that: The in-situ third gas plasma treatment is an in-situ nitrogen plasma annealing treatment.

4. The pressure-resistant silicon nitride thin film growth process according to claim 3, characterized in that: The in-situ nitrogen plasma annealing has an annealing temperature of 200-400° C., an annealing power of 30-70 W, and an annealing time of 50-70 s.

5. A HEMT device, characterized in that: include: A channel layer and a barrier layer are sequentially provided on the surface of the substrate; a gate structure provided on the surface of the barrier layer, the gate structure comprising an enhancement structure layer, a silicon nitride thin film layer and a metal gate layer stacked in sequence in a direction away from the surface of the barrier layer; The silicon nitride film layer is prepared by the voltage-resistant silicon nitride film growth process according to any one of claims 1 to 4 and with the enhanced structural layer as a substrate, so as to improve the device threshold voltage and gate reliability.

6. The HEMT device according to claim 5, wherein: The channel layer includes a GaN layer, the barrier layer includes an AlGaN layer, and the enhancement structure layer includes a p-GaN layer.

7. The HEMT device according to claim 5, wherein: The thickness of the silicon nitride film layer is 10-20 nm.

8. The HEMT device according to claim 5, wherein: Also includes: An ohmic contact is provided on the surface of the barrier layer on both sides of the gate structure, a passivation layer is provided on the surface of the barrier layer, the gate structure and the ohmic contact are located in the passivation layer, and the top of the metal gate layer and the top of the ohmic contact are exposed on the surface of the passivation layer, and a field plate is provided on the surface of the passivation layer, and the field plate is in contact with the top of the metal gate layer.

9. The HEMT device according to claim 8, wherein: Also includes: A mesa isolation structure is provided on the surface of the barrier layer, the bottom of the mesa isolation structure is located in the channel layer, and the gate structure, the ohmic contact and the field plate are located on the active area defined by the mesa isolation structure.

10. A method for preparing a HEMT device, characterized in that: The following steps are involved: Step S21: providing a substrate; Step S22: forming a channel layer, a barrier layer and an enhancement structure layer in sequence on the surface of the substrate; Step S23: forming a silicon nitride thin film layer and a metal gate layer in sequence on the surface of the enhancement structure layer; Step S24: patterning the metal gate layer, the silicon nitride thin film layer, and the enhanced structure layer to form a gate structure; The voltage-resistant silicon nitride thin film growth process according to any one of claims 1 to 4 is used, and the enhanced structural layer is used as a substrate to prepare the silicon nitride thin film layer, so as to improve the device threshold voltage and gate reliability.

11. The method for preparing a HEMT device according to claim 10, wherein: The channel layer includes a GaN layer, the barrier layer includes an AlGaN layer, and the enhancement structure layer includes a p-GaN layer.

12. The method for preparing a HEMT device according to claim 10, wherein: The thickness of the silicon nitride film layer is 10-20 nm.

13. The method for preparing a HEMT device according to claim 10, wherein: Before forming the silicon nitride thin film layer, the method further includes: cleaning the surface of the enhancement structure layer; After cleaning, the method further includes: forming a mesa isolation intermediate structure on the surface of the enhancement structure layer, so that the bottom of the mesa isolation intermediate structure is located in the channel layer; Then, the silicon nitride thin film layer is formed on the surface of the enhancement structure layer to cover the mesa isolation intermediate structure; When forming the gate structure, the metal gate layer, the silicon nitride thin film layer and the enhancement structure layer are patterned, and the redundant mesa isolation intermediate structure above the surface of the barrier layer is removed to form a mesa isolation structure, the active area is defined by the mesa isolation structure, and the formed gate structure is located on the surface of the barrier layer within the active area.

14. The method for preparing a HEMT device according to claim 13, wherein: After forming the gate structure, the method further includes: Within the active area, ohmic contacts protruding from the surface of the barrier layer are formed on the surface of the barrier layer on both sides of the gate structure; forming a passivation layer on the surface of the barrier layer, covering the mesa isolation structure, the gate structure, and the ohmic contact, and exposing the tops of the gate structure and the ohmic contact to the surface of the passivation layer; A field plate is formed on the surface of the passivation layer, and the field plate is in contact with the top surface of the metal gate layer.

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