Preparation method of addressable silicon-based integrated nanolaser and laser

Abstract

The application relates to the technical field of lasers, in particular to a preparation method of an addressable silicon-based integrated nanometer laser and the laser, which comprises the following steps: sequentially growing a transition layer and an epitaxial layer on a silicon wafer substrate; obtaining a plurality of grooves on a P-face contact layer through photoetching and developing, growing a metal layer in the grooves, and obtaining a P-face electrode; leaving a gap between the P-face electrodes, etching the epitaxial layer downwards along the gap, over-etching to an N-face contact layer, and forming an N-face electrode through hole; and firstly depositing TiN in the N-face electrode through hole, then depositing metal tungsten, and filling the N-face electrode through hole. By growing a laser epitaxial structure on the silicon substrate, combining a process technology route of a 65nm node of a silicon-based integrated circuit, a brand-new process route of a silicon-based nanometer laser is given, and the compatibility of the laser with CMOS front-end and back-end processes is exhibited.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of lasers, in particular to a preparation method of an addressable silicon-based integrated nanolaser and the laser. BACKGROUND

[0002] With the electronic chip process approaching the physical limit, the bandwidth and energy consumption of electrical interconnection are highlighted. The theoretical bandwidth density of optical interconnection is 1000 times that of copper interconnection, and the power consumption is only 1 / 10. Traditional discrete III-V lasers are difficult to meet the density and cost requirements, and the silicon-based integrated scheme can compress the optical engine size to millimeter level.

[0003] Lasers will become the core component of the new generation of information infrastructure. Monolithic integrated laser CPU has entered the consumer electronics and human-computer interface photonization, which has been laid out by many companies, opening up new scene applications, so this technology is not only an engineering problem, but also a deep coupling of basic science and industrial demand.

[0004] The traditional process is to bond III-V wafers to a silicon substrate through plasma activation or low-temperature bonding technology, and then form a laser structure through photolithography and etching, but the disadvantages are that the thermal stress and defects of the bonding interface are not easy to control, resulting in unstable quality of the laser. SUMMARY

[0005] To solve the above problems, the application provides a preparation method of an addressable silicon-based integrated nanolaser and the laser.

[0006] One of the purposes of the application is to provide a preparation method of an addressable silicon-based integrated nanolaser, which adopts the following technical scheme:

[0007] A preparation method of an addressable silicon-based integrated nanolaser, comprising the following steps:

[0008] S1, a transition layer and an epitaxial layer are sequentially grown on a silicon wafer substrate; the epitaxial layer includes an N-face contact layer at the bottom and a P-face contact layer at the top, and a plurality of functional layers between the N-face contact layer and the P-face contact layer;

[0009] S2, a plurality of grooves are obtained on the P-face contact layer through photolithography and development, a metal layer is grown in the grooves, and a P-face electrode is obtained;

[0010] S3, a gap is left between the P-face electrodes, the epitaxial layer is etched downward along the gap, and the N-face electrode through hole is formed by over-etching to the N-face contact layer;

[0011] S4, TiN is first deposited in the N-face electrode through hole, then metal tungsten is deposited, and the N-face electrode through hole is filled, so as to realize the lead-out of the N-face electrode;

[0012] S5, deposit a mask layer of SiO2 on the whole surface of the epitaxial layer, transfer the pattern to the mask layer, and etch the epitaxial structure and the epitaxial transition layer and part of the silicon through the mask layer, so as to isolate different laser units;

[0013] S6, deposit a medium layer of SiCOH above the mask layer, and deposit a layer of SiN above the medium layer, perform photolithography and etching to form a connecting via hole opposite to the P-face electrode and the N-face electrode, and expose the P-face electrode and the N-face electrode;

[0014] S7, electroplate Cu in the connecting via hole to fill the connecting via hole.

[0015] By adopting the technical scheme, the laser is directly prepared on the silicon substrate without bonding heterogeneous materials, the III-V material is directly epitaxially grown on the silicon substrate to grow the laser epitaxial structure on the silicon substrate, a new silicon-based nanometer laser process route is given by combining the process technology route of the 65nm node of the silicon-based integrated circuit, the compatibility of the laser with the CMOS front-end and back-end process is shown, and the stability of the laser quality is improved. The nanometer laser can be designed according to actual requirements to realize addressable work for multiple laser single tubes.

[0016] Preferably, in S3, after the P-face electrode is formed,

[0017] S31, sequentially deposit and grow SiN layer, SiO2 layer and APF layer on the epitaxial layer from bottom to top, transfer the pattern to the APF layer by photolithography to form APF strips, and gaps are left between the APF strips;

[0018] S32, grow SiN on the APF strips as a whole to form a space interval layer, the APF strips are wrapped by SiN to form SiN strips, and gaps are left between the SiN strips;

[0019] S33, etch and remove the SiN on the top of the SiN strips, and etch and remove the APF strips in the SiN together;

[0020] S34, etch downward in the gap between the SiN strips and the SiN strips to remove the SiO2 layer below the gap;

[0021] S35, etch and remove the SiN strips and the SiO2 as a whole, transfer the pattern to the SiN layer to form a plurality of wrapped strips wrapped outside the P-face electrode;

[0022] S36, etch the gap between the wrapped strips and the wrapped strips, and over-etch to the N-face contact layer to form the N-face electrode via hole.

[0023] Preferably, in S33, the distance between the SiN strips is 150 nm, and the interval is controlled by the thickness of the SiN strip.

[0024] By using the above technical solution, the specifications of the SiN strips are controlled by using SiO2 and APF as the intermediate transition sacrificial layer, the distance precision between the SiN strips is ensured, and the etching precision of the electrode via is ensured.

[0025] Preferably, in S4, after the N-face electrode via is formed,

[0026] S41, depositing a layer of SiN in the inner wall of the N-face electrode via to form a space layer;

[0027] S42, and etching and removing the SiN at the bottom of the N-face electrode via to expose the N-face contact layer;

[0028] S43, then depositing TiN and tungsten.

[0029] By using the above technical solution, the SiN layer isolates and protects the sidewall of the electrode via, so that the deposited TiN and tungsten only contact the N-face contact layer at the bottom.

[0030] Preferably, in S43, the TiN and tungsten overfill the N-face electrode via to ensure fullness.

[0031] S44, removing the excess tungsten and TiN by CMP (chemical mechanical planarization), the CMP stop layer is SiN, and the loss amount of tungsten is controlled to be not lower than the upper surface of the P-face contact layer;

[0032] S45, removing the SiN above and around the P-face electrode by wet etching to expose the P-face electrode.

[0033] By using the above technical solution, the upper surface of the tungsten is flattened by CMP to ensure the flatness of the surface.

[0034] Preferably, it further comprises

[0035] S8, flattening by CMP and stopping on SiN, depositing an Al layer on SiN;

[0036] S9, etching the Al layer to form a plurality of Al pieces in contact with the Cu.

[0037] By using the above technical solution, the Al pieces are used as the wire bonding external metal layer in the subsequent process, which is convenient for external wiring.

[0038] Preferably, in S1, the growth process of the transition layer is:

[0039] First, grow 1um thick GaAs on silicon to reduce the lattice mismatch between silicon and the subsequent laser epitaxial structure; then grow 10 periods of 9.3nm In 0.15 GaAs / 12nm GaAs strained superlattice layer to prevent the underlying dislocations from propagating to the upper epitaxial structure; then grow a 0.35um thick GaAs layer to filter the dislocations.

[0040] Another object of the present application is to provide an addressable silicon-based integrated nanolaser, which adopts the following technical solutions:

[0041] An addressable silicon-based integrated nanolaser is prepared by the preparation method of the addressable silicon-based integrated nanolaser.

[0042] In summary, the present application includes at least one of the following beneficial technical effects:

[0043] The present application uses a transition layer to alleviate lattice mismatch, thereby directly epitaxially growing III-V materials on a silicon substrate; and a monolithic silicon-based integrated laser and a preparation route compatible with CMOS front-end and back-end processes are also provided. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a chip structure schematic diagram in step S2 in embodiment one;

[0045] Figure 2(a) is a chip structure schematic diagram in step S31 in the embodiment;

[0046] Figure 2(b) is a chip structure schematic diagram in step S32 in the embodiment;

[0047] Figure 2(c) is a chip structure schematic diagram in step S33 in the embodiment;

[0048] Figure 2(d) is a chip structure schematic diagram in step S36 in the embodiment;

[0049] Figure 3(a) is a chip structure schematic diagram in step S41 in the embodiment;

[0050] Figure 3(b) is a chip structure schematic diagram in step S43 in the embodiment;

[0051] Figure 3(c) is a chip structure schematic diagram in step S44 in the embodiment;

[0052] Figure 3(d) is a chip structure schematic diagram in step S45 in the embodiment;

[0053] Figure 4(a) is a chip structure schematic diagram in step S61 in the embodiment;

[0054] Figure 4(b) is a chip structure schematic diagram in step S62 in the embodiment;

[0055] Fig. 4(c) is a schematic diagram of a chip structure in step S9 in the embodiment.

[0056] Reference signs:

[0057] 1, substrate; 2, transition layer; 3, epitaxial layer; 4, N-face contact layer; 5, P-face contact layer; 6, functional layer; 7, groove; 8, P-face electrode; 9, N-face electrode via hole; 10, mask layer; 11, dielectric layer; 12, connection via hole; 13, APF strip; 14, SiN strip; 15, wrapping strip; 16, spacer layer; 17, lead-out dielectric; 18, Al piece. DETAILED DESCRIPTION

[0058] The application will be further described in detail below in combination with all the drawings.

[0059] Embodiment one:

[0060] The embodiment of the application discloses a preparation method of an addressable silicon-based integrated nanolaser, comprising the following steps,

[0061] S1, referring to Figure 1 A transition layer 2 and an epitaxial layer 3 are sequentially grown on a silicon wafer substrate 1; the epitaxial layer 3 comprises an N-face contact layer 4 located at the lowermost position and a P-face contact layer 5 located at the uppermost position, and a plurality of functional layers 6 located between the N-face contact layer 4 and the P-face contact layer 5. The growth process of the transition layer 2 is as follows:

[0062] First, 1 um thick GaAs is grown on silicon to reduce the lattice mismatch between silicon and the subsequent laser epitaxial structure; then 10 periods of 9.3 nm In 0.15 GaAs / 12 nm GaAs strained superlattice layer is grown to prevent the propagation of dislocations in the lower layer to the epitaxial structure above; then a 0.35 um thick GaAs layer is grown to filter dislocations. Finally, the epitaxial layer 3 is sequentially grown on the above.

[0063] S2, referring to Figure 1 A plurality of grooves 7 with a width of 100 nm and a length of 1 um are obtained on the P-face contact layer 5 by lithography and development, Ti / Pt / Au / TiN is grown in the grooves 7 by magnetron sputtering, and the P-face electrode 8 is obtained by Lift-off process to strip the unnecessary part. Three P-face electrodes 8 are taken as an example for description in the embodiment.

[0064] S31, referring to Fig. 2(a), a SiN layer, a SiO2 layer and an APF layer are sequentially and uniformly deposited and grown on the epitaxial layer 3 from bottom to top, a pattern is transferred to the APF layer by lithography to form APF strips 13, gaps are left between the APF strips 13, and there are three APF strips 13 in total, and the three APF strips 13 are one-to-one opposite to the three P-face electrodes 8.

[0065] S32, referring to Fig. 2(b), SiN is grown on the APF strips 13 to form a space interval layer, and the APF strips 13 are wrapped by SiN to form SiN strips 14, and gaps are left between the SiN strips 14; the distance between the SiN strips 14 is 150 nm, and the interval is controlled by the thickness of the SiN strips 14.

[0066] S33, referring to Fig. 2(c), the SiN on the top of the APF strips 13 and the bottom of the adjacent APF strips 13 is removed by one-step self-aligned etching, and the APF strips 13 are exposed for further etching.

[0067] S34, referring to Fig. 2(d), the gap between the SiN strips 14 is etched downward, and the SiO2 layer below the gap is removed, and the SiO2 layer acts as a transition sacrificial layer.

[0068] S35, referring to Fig. 2(d), the SiN strips 14 and the SiO2 as a sacrificial layer are etched and removed, and the pattern is transferred to the SiN layer to form a plurality of wrapped strips 15 wrapped outside the P-face electrode 8.

[0069] S36, referring to Fig. 2(d), the wrapped strips 15 and the gap between the wrapped strips 15 are etched, and the over-etching is performed to the N-face contact layer 4, and the through hole formed is the N-face electrode through hole 9.

[0070] S41, referring to Fig. 3(a), a layer of SiN is deposited in the inner wall of the N-face electrode through hole 9 to form a space layer 16.

[0071] S42, referring to Fig. 3(b), the SiN at the bottom of the N-face electrode through hole 9 is etched and removed to expose the N-face contact layer 4.

[0072] S43, referring to Fig. 3(b), then TiN and metal tungsten are sequentially deposited as a lead-out medium 17, the lead-out medium 17 overfills the N-face electrode through hole 9 to ensure fullness.

[0073] S44, referring to Fig. 3(c), the excess lead-out medium 17 is removed by CMP chemical mechanical planarization, the CMP stop layer is SiN, and the loss of tungsten cannot be lower than the upper surface of the P-face contact layer 5.

[0074] S45, referring to Fig. 3(d), the SiN on the P-face electrode 8 and around the P-face electrode 8 is removed by wet etching the wrapped strips 15 to expose the P-face electrode 8.

[0075] S5, referring to Fig. 4(a), a layer of SiO2 mask layer 10 is deposited on the entire surface of the epitaxial layer 3, the pattern is transferred to the mask layer 10, and the epitaxial structure and the epitaxial transition layer 2 and part of the silicon are etched away through the mask layer 10, thereby isolating different laser units.

[0076] S61, referring to Fig. 4(a), a SiCOH dielectric layer 11 is deposited above the mask layer 10, and a SiN layer is further deposited above the dielectric layer 11.

[0077] S62, referring to Fig. 4(b), the SiN layer is subjected to photolithography and etching to form a connecting via 12 opposite to the P-face electrode 8 and the N-face electrode, and the P-face electrode 8 and the N-face electrode are exposed. The chemical vapor deposition interlayer dielectric SiCOH mainly functions to isolate different laser units, and serves as an electrical insulator to prevent current interference between adjacent lasers during operation.

[0078] S7, referring to Fig. 4(c), Cu is electroplated in the connecting via 12 to fill the connecting via 12.

[0079] S8, referring to Fig. 4(c), CMP is used for planarization and stopping on the SiN layer, and an Al layer is deposited on the SiN layer.

[0080] S9, referring to Fig. 4(c), the Al layer is etched to form a plurality of Al pieces 18 in contact with the Cu.

[0081] Embodiment two:

[0082] The application discloses a kind of addressable silicon-based integrated nanolaser, which is prepared by the preparation method of the addressable silicon-based integrated nanolaser in the above embodiment.

[0083] The above are preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Therefore, any equivalent changes made according to the structure, shape, principle of the present application should be covered within the protection scope of the present application.

Claims

1. A method for fabricating an addressable silicon-based integrated nanolaser, characterized in that: The method comprises the following steps: S1, growing a transition layer (2) and an epitaxial layer (3) on a silicon wafer substrate (1) in sequence; the epitaxial layer (3) comprises an N-face contact layer (4) at the bottom and a P-face contact layer (5) at the top, and a plurality of functional layers (6) between the N-face contact layer (4) and the P-face contact layer (5); the growth process of the transition layer (2) is as follows: A 1 um thick GaAs is first grown on silicon to reduce the lattice mismatch of silicon and the subsequent laser epitaxial structure; then 10 cycles of 9.3 nm In 0.15 GaAs / 12 nm GaAs strained superlattice layer to prevent the underlying dislocation from propagating to the upper epitaxial structure; 0.35 um of GaAs layer is regrown to filter dislocations; S2, a plurality of grooves (7) are obtained on the P-face contact layer (5) by photoetching and developing, and a metal layer is grown in the grooves (7) to obtain a P-face electrode (8); S3, a gap is left between the P-face electrodes (8), and the epitaxial layer (3) is etched downward along the gap to the N-face contact layer (4) to form an N-face electrode via hole (9); S4, TiN is first deposited in the N-face electrode via hole (9), then metal tungsten is deposited to fill the N-face electrode via hole (9), thereby realizing the lead-out of the N-face electrode; S5, a SiO2 mask layer (10) is deposited on the entire surface of the epitaxial layer (3), the pattern is transferred to the mask layer (10), and the epitaxial structure, the transition layer (2) and part of the silicon of the silicon wafer substrate (1) are etched away through the mask layer (10), thereby isolating different laser units; S6, a SiCOH dielectric layer (11) is deposited above the mask layer (10), and a SiN layer is further deposited above the dielectric layer (11), photoetching and etching are performed to form a connection via hole (12) opposite to the P-face electrode (8) and the N-face electrode, and the P-face electrode (8) and the N-face electrode are exposed; S7, Cu is used for electroplating in the connection via hole (12) to fill the connection via hole (12).

2. The method of claim 1, wherein the method further comprises: In S3, after the P-face electrode (8) is formed, S31, a SiN layer, a SiO2 layer and an APF layer are sequentially deposited and grown on the epitaxial layer (3) from bottom to top, the pattern is transferred to the APF layer by photoetching to form an APF strip (13), and a gap is left between the APF strips (13); S32, SiN is further grown on the outside of the APF strip (13) to form a spatial spacing layer, the APF strip (13) is wrapped by SiN to form a SiN strip (14), and a gap is left between the SiN strips (14); S33, the SiN on the top of the SiN strip (14) is etched away, and the APF strip (13) in the SiN is etched away together; S34, the gap between the SiN strips (14) is etched downward to remove the SiO2 layer below the gap; S35, the SiN strip (14) and the SiO2 are etched away as a whole to transfer the pattern to the SiN layer, thereby forming a plurality of wrapped strips (15) wrapped outside the P-face electrode (8); S36, the gap between the wrapped strips (15) is etched, and the etching is over-etched to the N-face contact layer (4) to form the N-face electrode via hole (9).

3. The method of claim 2, wherein the method further comprises: In S33, the distance between the SiN strips (14) is 150 nm, and the interval is controlled by the thickness of the SiN strip (14).

4. The method of claim 2, wherein the method further comprises: In S4, after the N-face electrode via hole (9) is formed, S41, depositing a layer of SiN in the inner wall of the N-face electrode through hole (9) to form a space layer (16); S42, etching the SiN at the bottom of the N-face electrode through hole (9) to expose the N-face contact layer (4); S43, then depositing TiN and metal tungsten.

5. The method of claim 4, wherein the method further comprises: In S43, the TiN and tungsten overfill the N-face electrode through hole (9) to ensure fullness; S44, removing the excess tungsten and TiN by CMP chemical mechanical planarization, the CMP stop layer is SiN, and the loss of tungsten is controlled to be not lower than the upper surface of the P-face contact layer (5); S45, removing the SiN on and around the P-face electrode (8) by wet etching to expose the P-face electrode (8).

6. The method of claim 1, wherein the method further comprises: Further comprising, S8, planarizing by CMP and stopping on SiN, depositing an Al layer on the SiN; S9, etching the Al layer to form a plurality of Al pieces (18) in contact with the Cu.

7. An addressable silicon-based integrated nanolaser, characterized by: The preparation method is prepared by the preparation method of the addressable silicon-based integrated nanolaser according to any one of claims 1-6.

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