A radio frequency switch chip

Abstract

The application provides a radio frequency switch chip, comprising at least adjacent first and second radio frequency channels, each radio frequency channel comprising a series-parallel switch structure, the series-parallel switch structure comprising: N series-connected first switches, sequentially connected between a radio frequency input end and a radio frequency output end of the radio frequency channel, N being an integer greater than or equal to 1; M parallel-connected second switches, each second switch connected between the radio frequency channel and a standard ground, M being an integer greater than or equal to 1, each second switch having a grounding point for connecting with the standard ground; the radio frequency switch chip having grounding bumps on the surface, each grounding point electrically connected with the standard ground through a corresponding grounding bump, wherein the positions of the grounding bumps are configured such that the sum of the lateral distances from each grounding point to the nearest grounding bump is minimum; and / or, in the adjacent two radio frequency channels, the two grounding points having the greatest impact on the channel isolation have the shortest paths to the corresponding grounding bumps.

Description

Technical Field

[0001] The present application relates to the field of radio frequency chips, and in particular to a radio frequency switch chip. Background Art

[0002] As a key component of the RF front-end in modern communications systems, RF switches play a unique role in Massive Multiple-Input Multiple-Output (Massive MIMO) system architectures. The feedback chain design for digital predistortion (DPD) systems requires a high-isolation RF switch to construct a multi-channel sampling system. First, the nonlinear RF signal output from the power amplifier (PA) is extracted via a directional coupler, digitized by an analog-to-digital converter (ADC), and transmitted to a digital signal processor (DSP). The DSP generates a predistorted waveform through real-time calculations, which is then converted to an analog signal by a digital-to-analog converter (DAC). This signal is then injected into the PA input to compensate for the nonlinear distortion. Because Massive MIMO systems utilize multiple PAs transmitting in parallel, when the DPD system alternately samples each channel, RF signals from adjacent channels can generate crosstalk through common ground lines, spatial radiation, and other channels. In this case, the RF switch's isolation directly determines the purity of the feedback signal. High isolation effectively suppresses interference from leakage from non-sampled channels. Switch isolation (expressed in dB) is defined as the logarithmic absolute value of the ratio of the incident voltage to the output voltage across the signal transmission path in the off state. Under normal circumstances, without special requirements, switch isolation is typically between 20 and 40 dB. 40 to 60 dB is considered high isolation (only 1 / 100 of the signal is transmitted), and a switch isolation greater than 60 dB (1 / 1000 of the signal is transmitted) is considered ultra-high isolation.

[0003] Multi-channel RF switches typically use single-pole four-throw (SP4T) switches. To improve isolation, three high-isolation single-pole double-throw (SPDT) switches can also be used instead of the SP4T. However, with the increasing number of channels and the demand for higher chip integration, replacing multi-channel RF switches with multiple high-isolation SPDTs is no longer a preferred option. Currently, the solution to improve inter-channel isolation is to maximize the number of ground bumps between the chip die and the package substrate. However, with increasing chip integration, the chip die area is shrinking, and the number of channels is increasing. This limits the number of ground bumps that can be installed within a limited space. Therefore, achieving high-isolation multi-channel RF switch chips is a pressing technical challenge. Summary of the Invention

[0004] To solve the above technical problems, the application provides a radio frequency switch chip, which can improve the isolation degree between radio frequency channels of a multi-channel radio frequency switch by optimizing the position distribution of grounding bumps and setting isolation grooves on a limited chip area.

[0005] The application discloses a radio frequency switch chip, which at least includes adjacent first and second radio frequency channels, each radio frequency channel including a series-parallel switch structure, the series-parallel switch structure including: N-stage first switches connected in series between a radio frequency input end and a radio frequency output end of the radio frequency channel, N being an integer greater than or equal to 1; M-stage second switches connected in parallel, each stage of the second switches being connected between the radio frequency channel and a standard ground, M being an integer greater than or equal to 1, each stage of the second switches having a grounding point, the grounding point being used for being connected with the standard ground; a surface of the radio frequency switch chip having grounding bumps, each of the grounding points being electrically connected with the standard ground through a corresponding grounding bump, wherein the positions of the grounding bumps are configured such that the sum of the lateral distances from each of the grounding points to the nearest grounding bump is minimum; and / or, in the adjacent two radio frequency channels, the path from the grounding point having the greatest influence on the channel isolation degree to the corresponding grounding bump is the shortest.

[0006] The radio frequency switch chip according to the application further includes: a device layer, an interconnection layer located on the device layer; the first switches and the second switches include transistors, and the transistors are located on the device layer; the interconnection layer includes: an interconnection line and a conductive plug connected with the interconnection line, and the first switches and the second switches are electrically connected through the interconnection line and the conductive plug; the grounding points include the conductive plug, the interconnection line or the conductive plug and the interconnection line located in the interconnection layer.

[0007] The radio frequency switch chip according to the application, the grounding point having the greatest influence on the channel isolation degree includes: the grounding point corresponding to the last stage of the second switches of the adjacent two radio frequency channels in the radio frequency transmission direction.

[0008] The radio frequency switch chip according to the application, the path from the grounding point having the greatest influence on the channel isolation degree to the corresponding grounding bump being the shortest includes: the grounding point of the last stage of the second switches and the corresponding grounding bump partially overlap in the vertical chip direction.

[0009] The radio frequency switch chip according to the application, each of the grounding points corresponds to a grounding bump, and the grounding bumps are not shared; or, at least two adjacent grounding points share a grounding bump.

[0010] According to the radio frequency switch chip of the present application, at least one of the grounding points has an overlapping part with the corresponding grounding bump in the direction perpendicular to the chip surface, or the grounding point and the corresponding grounding bump have no overlapping part in the direction perpendicular to the chip surface, but the sum of the lateral distances from each grounding point to the grounding bump closest to it is minimum.

[0011] According to the radio frequency switch chip of the present application, by optimizing the position distribution of the grounding bumps, the grounding bumps are as close as possible to the grounding points in the lateral direction, thereby shortening the reflow path length of the SH switch tube on the chip on the ground plane, improving the isolation between adjacent radio frequency channels, and reducing the interference between adjacent radio frequency channels.

[0012] According to the radio frequency switch chip of the present application, a specific area is surrounded by the grounding points between the two adjacent radio frequency channels, and as many grounding bumps as possible are arranged in the specific area to be connected to the standard ground.

[0013] By arranging as many grounding bumps as possible on the ground plane to be electrically connected to the packaging substrate, the isolation between adjacent radio frequency channels can be further improved, and the interference between adjacent radio frequency channels can be reduced.

[0014] According to the radio frequency switch chip of the present application, the radio frequency switch chip includes a chip ground layer or a chip grounding area, and the grounding point is the connection between the second switch and the chip ground layer or the chip grounding area.

[0015] According to the radio frequency switch chip of the present application, the chip ground layer or the chip grounding area is located in one or more interconnection layers.

[0016] According to the radio frequency switch chip of the present application, the standard ground is located on the substrate, and is a ground layer or a grounding area on the substrate.

[0017] According to the radio frequency switch chip of the present application, a first isolation groove is arranged on the interconnection layer, the first isolation groove is used to isolate the grounding points with the greatest influence on the channel isolation between adjacent two radio frequency channels, and the first isolation groove is filled with a non-conductive medium.

[0018] According to the radio frequency switch chip of the present application, the grounding point corresponding to the last-stage second switch has at least one grounding bump closest to it; and the first isolation groove is used to isolate the grounding bump closest to the grounding point corresponding to the last-stage second switch of the two adjacent radio frequency channels.

[0019] According to the radio frequency switch chip of the present application, one end of the first isolation groove extends to the grounding bump closest to the grounding point corresponding to the last-stage second switch.

[0020] According to the radio frequency switch chip, the first isolation groove is in a straight line or a broken line in the vertical chip surface direction.

[0021] According to the radio frequency switch chip, the first isolation groove penetrates the interconnection layer of the radio frequency switch in the vertical chip surface direction.

[0022] By arranging the first isolation groove filled with the non-conductive medium between the two ground points with the greatest influence on the channel isolation, the common ground return path between the two ground points can be cut off, the ground return paths of the two adjacent radio frequency channels at the ground points with the greatest influence on the channel isolation are isolated from each other, and thus the isolation between the adjacent radio frequency channels can be further improved, and the interference between the adjacent radio frequency channels can be reduced.

[0023] According to the radio frequency switch chip, the two ground bumps adjacent to the ground point corresponding to the last-stage second switch of the first radio frequency channel are a first bump and a second bump respectively, the two ground bumps adjacent to the ground point corresponding to the last-stage second switch of the second radio frequency channel are a third bump and a fourth bump respectively, the first bump and the third bump are located on a first side of the ground point corresponding to the last-stage second switch of the adjacent two radio frequency channels, the second bump and the fourth bump are located on a second side of the ground point corresponding to the last-stage second switch of the adjacent two radio frequency channels, an end of the first side of the first isolation groove extends to at least a connection line of edges of the first side of the first bump and the third bump, and an end of the second side of the first isolation groove extends to at least a connection line of edges of the second side of the second bump and the fourth bump.

[0024] By setting the length of the first isolation groove to be longer than the positions of the two ground bumps adjacent to the ground point, the common ground return path between the two last-stage ground points can be better cut off, the isolation between the adjacent radio frequency channels can be further improved, and the interference between the adjacent radio frequency channels can be reduced.

[0025] According to the radio frequency switch chip, the ground bump located on the first side of the ground point corresponding to the first-stage second switch of the first radio frequency channel is a fifth bump, the ground bump located on the first side of the ground point corresponding to the first-stage second switch of the second radio frequency channel is a sixth bump, and an end of the first side of the first isolation groove extends to at least a connection line of edges of the first side of the fifth bump and the sixth bump.

[0026] By setting the length of the first isolation groove to be able to isolate the ground points corresponding to all the second switches of the adjacent two radio frequency channels, the isolation between the adjacent radio frequency channels can be further improved, and the interference between the adjacent radio frequency channels can be reduced.

[0027] According to the radio frequency switch chip of the present application, at least one second isolation groove is further arranged on the interconnection layer, the second isolation groove is filled with non-conductive medium, the extension direction of the first isolation groove is the first direction, the extension direction of the second isolation groove is the second direction, the first direction intersects with the second direction, and the second isolation groove is used for isolating the current path between the ground point with the greatest impact on the channel isolation degree and the ground point with the non-greatest impact on the channel isolation degree.

[0028] According to the radio frequency switch chip of the present application, the ground bump on the second side of the ground point corresponding to the second switch of the second-to-last stage of the first radio frequency channel is the seventh bump, the ground bump on the second side of the ground point corresponding to the second switch of the second-to-last stage of the second radio frequency channel is the eighth bump, the second isolation groove is located on the second side of the seventh bump and the eighth bump and on the first side of the third bump and the fourth bump.

[0029] By arranging the second isolation groove intersecting with the first isolation groove, the last stage ground point and the second-to-last stage ground point of each radio frequency channel are isolated, and the common ground backflow path therebetween is cut off, so that the isolation degree between adjacent radio frequency channels can be further improved, and the interference between adjacent radio frequency channels can be reduced.

[0030] According to the radio frequency switch chip of the present application, a plurality of second isolation grooves parallel to each other are arranged on the interconnection layer and are respectively used for isolating the ground points corresponding to the adjacent two-stage second switches of the first radio frequency channel and the ground points corresponding to the adjacent two-stage second switches of the second radio frequency channel.

[0031] Further, the plurality of second isolation grooves are arranged to isolate the ground points of the adjacent two stages of each radio frequency channel, so that the isolation degree between adjacent radio frequency channels can be further improved, and the interference between adjacent radio frequency channels can be reduced.

[0032] According to the radio frequency switch chip of the present application, the radio frequency switch chip is packaged on a substrate, the substrate includes X metal layers, X is an integer greater than or equal to 2, the metal layers are electrically connected through vias, a third isolation groove corresponding to the first isolation groove is arranged on the first metal layer, and the third isolation groove is filled with non-conductive medium.

[0033] According to the radio frequency switch chip of the present application, a third isolation groove corresponding to the first isolation groove is arranged on the first metal layer to the X-1 metal layer.

[0034] According to the radio frequency switch chip of the present application, the lateral dimension of the third isolation groove is greater than the lateral dimension of the first isolation groove, and the range of the third isolation groove can completely cover the range of the first isolation groove in the vertical chip direction.

[0035] By setting the third isolation groove on the substrate metal layer of the packaging substrate, the backflow path deteriorating the isolation effect can be separated, thereby further improving the isolation degree between adjacent radio frequency channels and reducing the interference between adjacent radio frequency channels. In addition, the size of the packaging substrate is larger than that of the chip die, and the wiring line is simpler, so there is more space for setting the isolation groove, and the wider and longer isolation groove can further ensure the isolation effect. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A simplified circuit schematic diagram of the present radio frequency switch chip;

[0037] Figure 2 A perspective schematic diagram of the radio frequency switch chip;

[0038] Figure 3 A simulation schematic diagram of the isolation degree of the radio frequency switch chip under five conditions of the grounding point to the ideal grounding, non-ideal grounding, and standard grounding;

[0039] Figure 4 A cross-sectional schematic diagram of a partial region of the radio frequency switch chip;

[0040] Figure 5 A cross-sectional schematic diagram of a functional region of the radio frequency switch chip;

[0041] Figure 6 A perspective schematic diagram of a partial structure of the radio frequency switch chip involved in the present application;

[0042] Figure 7 A disassembled perspective schematic diagram of a partial structure of the radio frequency switch chip involved in the present application;

[0043] Figure 8 A top view schematic diagram of a partial structure of a general radio frequency switch chip;

[0044] Figure 9 A top view schematic diagram of a partial structure of the radio frequency switch chip involved in the first embodiment of the present application;

[0045] Figure 10 A Figure 6 and Figure 7 A simulation schematic diagram of the isolation degree between adjacent radio frequency channels of the radio frequency switch chip structure shown in FIGS. 1-3;

[0046] Figure 11 A top view schematic diagram of a partial structure of the radio frequency switch chip involved in the second embodiment of the present application;

[0047] Figure 12 Another top view schematic diagram of a partial structure of the radio frequency switch chip involved in the second embodiment of the present application;

[0048] Figure 13A schematic diagram of a typical four-channel RF switch chip;

[0049] Figure 14 A schematic diagram of a four-channel RF switch chip according to the first embodiment of the present application;

[0050] Figure 15 A schematic diagram of a four-channel RF switch chip according to the third embodiment of the present application;

[0051] Figure 16 Schematic diagrams of two-channel, four-channel, and eight-channel RF switch chips, respectively;

[0052] Figure 17 A schematic diagram of a ground bump layout between two parallel adjacent RF channels of a typical two-stage ground structure;

[0053] Figure 18 A schematic diagram of a ground bump layout between two parallel adjacent RF channels of a two-stage ground structure according to the third embodiment of the present application;

[0054] Figure 19 A schematic diagram of a ground bump layout between two parallel adjacent RF channels of a typical three-stage ground structure;

[0055] Figure 20 A schematic diagram of a ground bump layout between two parallel adjacent RF channels of a three-stage ground structure according to the third embodiment of the present application;

[0056] Figure 21 A schematic diagram of a ground bump layout between two adjacent RF channels of a typical three-stage ground structure in a fan shape;

[0057] Figure 22 A schematic diagram of a ground bump layout between two adjacent RF channels of a three-stage ground structure in a fan shape according to the third embodiment of the present application;

[0058] Figure 23 A top view schematic diagram of a partial structure of an RF switch chip according to the fourth embodiment of the present application;

[0059] Figure 24 An exploded perspective schematic diagram of a partial structure of an RF switch chip according to the fourth embodiment of the present application;

[0060] Figure 25 A top view schematic diagram of a first isolation groove according to the fourth embodiment of the present application;

[0061] Figure 26 Another top view schematic diagram of a first isolation groove according to the fourth embodiment of the present application;

[0062] Figure 271 is a schematic top view of a first isolation trench and a second isolation trench according to a fourth embodiment of the present application;

[0063] Figure 28 for Figure 8 、 Figure 25 and Figure 27 Schematic diagram of the isolation simulation between adjacent RF channels of three different chip structures shown;

[0064] Figure 29 is another schematic top view of the first isolation trench involved in the fourth embodiment of the present application;

[0065] Figure 30 This is another schematic top view of the first isolation trench according to the fourth embodiment of the present application; Figure 31 This is a side structural diagram of a radio frequency switch chip including a substrate involved in the fifth embodiment of the present application;

[0066] Figure 32 This is a disassembled three-dimensional schematic diagram of the radio frequency switch chip including the substrate involved in the fifth embodiment of the present application

[0067] Figure 33 Schematic diagram of the isolation simulation between adjacent RF channels of three different substrates. DETAILED DESCRIPTION

[0068] The present application will be further described below with reference to specific embodiments and accompanying drawings. It should be understood that the illustrative embodiments of the present application are intended only to explain the present application and are not intended to limit the present application. In addition, for ease of description, the accompanying drawings only illustrate some, but not all, structures or processes relevant to the present application.

[0069] The following specific embodiments illustrate the implementation of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Although the description of the present application will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this application are limited to this implementation. On the contrary, the purpose of introducing the application in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of the present application. In order to provide an in-depth understanding of the present application, the following description will contain many specific details. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other unless there is a conflict.

[0070] Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrase "A / B" means "A or B." The phrase "A and / or B" means "(A and B) or (A or B)."

[0071] It should be understood that although the terms "first," "second," etc. may be used herein to describe various components, units, or data, these components, units, or data should not be limited by these terms. These terms are used only to distinguish one feature from another. For example, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature without departing from the scope of the exemplary embodiments.

[0072] It should be understood that although directional terms such as "up", "down", "left" and "right" may be used here to describe the positional relationship of each component, these directional terms are only used to indicate the directions in the drawings for the convenience of understanding and cannot be used to limit the scope of protection of this application.

[0073] It should be noted that in this specification, like reference numerals and letters denote similar items in the drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0074] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0075] Figure 1 This is a simplified circuit diagram of the RF switch chip. Figure 1 As shown, the RF switch chip includes n channels. Each RF channel comprises a series-parallel switch structure, which can be described as an SR-SH switch, where SR (Series Resonant) represents a series switch and SH (Shunt Resonant) represents a shunt switch. The switch (SR switch) connected in series between the RF input and output terminals in an RF channel is defined as the first switch. Along the signal transmission direction, multiple first switches connected in series are referred to as the first-stage first switch, the second-stage first switch, and so on. The switch (SH switch) connected between the parallel RF channel and the standard ground in an RF channel is defined as the second switch. Along the signal transmission direction, multiple second switches connected in parallel are referred to as the first-stage second switch, the second-stage second switch, and so on.

[0076] exist Figure 1 In the example, RFin is the RF input terminal, and RFout is the RF output terminal. Each channel from the RF input terminal to the RF output terminal includes three stages of first switches (SR switches) connected in series and two stages of second switches (SH switches) connected in parallel. Each stage of the second switch has a grounding point connected to the standard ground. By connecting the second switch to the standard ground, a path to the ground is provided when the switch is off, that is, in the isolated state. Figure 1The ground symbol in represents the grounding point of the second switch. The grounding point of the first-stage second switch of the first RF channel is the first grounding point 11, the grounding point of the second-stage second switch of the first RF channel is the second grounding point 12, the grounding point of the first-stage second switch of the second RF channel is the third grounding point 13, and the grounding point of the second-stage second switch of the second RF channel is the fourth grounding point 14.

[0077] For two adjacent RF channels in the RF switch chip, in the series-parallel switch structure, there are several SH switches in each channel, which is usually called a several-level grounding structure. For example, Figure 1 The example in the figure is a two-level grounding structure, but the present application is not limited thereto. It can also be a one-level grounding, three-level grounding, four-level grounding structure, etc. The commonly used structure is a two-level or three-level grounding structure.

[0078] The specific number of grounding levels used is determined by the overall chip design. Generally speaking, more grounding levels result in higher isolation, but this also translates to larger chip area and higher cost. Furthermore, more grounding levels require more ground bumps, which, due to the limited spacing between ground bumps, can hinder miniaturization. In short, the number of grounding levels is determined at the outset of the design, and the location of the SH switch grounding point is also determined for the circuit layout.

[0079] Figure 2 Figure 1 is a three-dimensional schematic diagram of the RF switch chip. Figure 2 As shown, the first to fourth grounding points 11-14 of the RF switch chip are connected to the ground layer of the RF switch chip, and the ground layer of the RF switch chip is connected to the ground layer or ground area on the substrate through the ground bump. The ground layer or ground area on the substrate is the standard ground. Figure 2 The surface of the RF chip shown in the figure can be a solder ball, a copper column bump, a mixed material bump, a gold bump, or any other type of bump in the art that can connect the chip to the substrate. The substrate is the connection between the chip and the PCB board ( Figure 2 The substrate serves as a transition structure between the chip and the PCB board, and the substrate carries the chip and electrically connects the chip to the PCB board.

[0080] The ground bump is equivalent to an inductor to the standard ground. This equivalent inductance (parasitic inductance) increases the impedance between the corresponding second switch ground point and the standard ground at high frequencies, thereby degrading isolation. If the RF switch chip grounding is ideal, the equivalent inductance from the ground bump to the standard ground is zero. However, this is only an ideal case; the connection between the RF switch chip ground point and the standard ground is typically non-ideal.

[0081] Figure 3The isolation simulation diagrams of the ground of the radio frequency switch chip under five conditions of standard ideal ground, non-ideal ground are shown. Combined with the reference Figure 1 and Figure 3 :

[0082] C1 represents that the first ground 11 and the second ground 12 of the first radio frequency channel, and the third ground 13 and the fourth ground 14 of the second radio frequency channel are all independent grounds, and each ground is connected to the standard ideal ground;

[0083] C2 represents that the first ground 11 and the second ground 12 are common grounds, and the third ground 13 and the fourth ground 14 are common grounds, and each ground is connected to the standard ideal ground;

[0084] C3 represents that the first ground 11 and the third ground 13 are common grounds, and each ground is connected to the standard ideal ground;

[0085] C4 represents that the second ground 12 and the fourth ground 14 are common grounds, and each ground is connected to the standard ideal ground;

[0086] C5 represents that each ground is connected to the standard ground which is not ideal, and the equivalent inductance of each ground bump is 30 pH, and the first to fourth grounds 11-14 are grounded through the equivalent inductance.

[0087] As Figure 3 shown, the horizontal axis represents the frequency (Frequency) in GHz, and the vertical axis represents the isolation (Isolation) in dB. In the five cases of C1-5, the isolation between the first radio frequency channel and the second radio frequency channel is best in the C1 case, that is, the isolation between the adjacent two radio frequency channels is highest, and in turn, the isolation in the C2 case is second, the isolation in the C3 case is third, the isolation in the C4 case is fourth, and the isolation in the C5 case is worst.

[0088] According to the isolation curve diagram shown in Figure 3 , the following conclusions can be drawn:

[0089] (1) Since the isolation in the C5 case is the worst, it can be known that when considering the equivalent inductance in the actual situation, a slight increase in inductance will cause serious deterioration of the isolation;

[0090] (2) In the C2 case, the ground points of the same radio frequency channel are common, in the C3 and C4 cases, the ground points of the corresponding stages of the adjacent radio frequency channels are common, the isolation degree of C2 is better than that of C3 and C4, that is, the ground points of the same radio frequency channel have less influence on the isolation degree between adjacent radio frequency channels than the ground points of the corresponding stages of the adjacent radio frequency channels, and have higher isolation degree, so the ground points of the corresponding stages of the adjacent radio frequency channels need to be isolated in order to improve the isolation degree;

[0091] (3) In the C3 case, the first stage ground points of the adjacent radio frequency channels are common, in the C4 case, the second stage ground points of the adjacent radio frequency channels are common, the isolation degree of C3 is better than that of C4, that is, the ground points of the adjacent radio frequency channels closer to the RFout port have greater influence on the isolation degree between adjacent radio frequency channels, and can seriously deteriorate the isolation degree.

[0092] From the above conclusion (1), an important factor affecting the isolation degree between adjacent radio frequency channels is the parasitic inductance from the ground point to the standard ground, that is, case C5. In the conventional ground scheme, the equivalent inductance to the ground is reduced as much as possible by increasing the ground bump, but due to the size limitation of the radio frequency switch chip, this scheme cannot be well implemented.

[0093] The inventors have found various factors affecting the isolation degree through long-term research and demonstration, including the isolation degree caused by parasitic inductance under non-ideal ground conditions, the influence of the ground points between adjacent channels and the ground points between the same channel on the isolation degree, based on which the inventors propose various embodiments of the present application to reduce the isolation degree between adjacent channels of the radio frequency switch.

[0094] In order to reduce the parasitic inductance from the ground point to the standard ground, thereby optimizing the isolation degree between adjacent radio frequency channels of the radio frequency switch chip, the first embodiment of the present application discloses a technical scheme for reasonably and effectively controlling the path from the ground point to the standard ground.

[0095] In combination with reference Figure 1 , Figure 6 , Figure 7 , Figure 9 , in the first embodiment, the radio frequency switch chip includes: a first switch of N levels in series, connected in series between the radio frequency input end and the radio frequency output end of the radio frequency channel, N being an integer greater than or equal to 1; and a second switch of M levels in parallel, each level of the second switch being connected between the radio frequency channel and the standard ground, M being an integer greater than or equal to 1. Figure 1 In the example shown, a three-level SR switch and a two-level SH switch are shown, but this does not constitute a limitation on the technical scheme of the present application. Each level of the second switch has a ground point for connecting with the standard ground, as shown in Figure 1As shown, the first-stage second switch of the first radio frequency channel has a first grounding point 11, the second-stage second switch of the first radio frequency channel has a second grounding point 12, the first-stage second switch of the second radio frequency channel has a third grounding point 13, and the second-stage second switch of the second radio frequency channel has a fourth grounding point 14. The surface of the radio frequency switch chip has grounding bumps 20, and the first to fourth grounding points 11-14 are connected to the standard ground through their corresponding grounding bumps 20 (in combination with reference to Figure 4 ) in which the positions of the grounding bumps 20 are configured such that the sum of the lateral distances from each grounding point to the nearest grounding bump is minimized; and / or, in adjacent two radio frequency channels, the two grounding points that have the greatest impact on the channel isolation degree have the shortest path to the corresponding grounding bump.

[0096] Figure 4 A cross-sectional view of a partial area of a radio frequency switch chip is shown in which: SI represents Silicon, which is the substrate material of the chip; PAD represents a pad, which is used for electrical connection; OXIDE represents an oxide, which is used for an insulation layer; PI represents Polyimide, which is used for insulation and protection; TI / CU represents Titanium / Copper, which is used as a metalized layer for electrical connection; CU represents Copper, which is used as the main body of the grounding bump for electrical connection; SN / AG represents Tin / Silver, which is used as solder; and NI represents Nickel, which is used to prevent copper diffusion. As shown, Figure 4 The radio frequency switch chip includes a substrate 15 and a functional area 16 that implements the circuit functions of the chip. The material of the substrate 15 needs to take into account high-frequency performance, loss control, integration, and cost. In order to improve the isolation degree, the radio frequency switch chip usually uses Silicon-On-Insulator (SOI) as the substrate, but the present application is not limited thereto, and single-crystal silicon, gallium arsenide (GaAs), gallium nitride (GaN), sapphire (Al2O3), etc. can also be used as the substrate. The radio frequency switch chip also includes grounding bumps 20 disposed on the surface of the chip. The grounding bumps 20 are copper pillar bumps, one end of which is electrically connected to a pad (PAD), and the other end is electrically connected to a substrate (not shown) through Tin / Silver (SN / AG) solder. Figure 4

[0097] Figure 5 A cross-sectional view of a functional area of a radio frequency switch chip is shown in which: SI represents Silicon, which is the substrate material of the chip; PAD represents a pad, which is used for electrical connection; OXIDE represents an oxide, which is used for an insulation layer; PI represents Polyimide, which is used for insulation and protection; TI / CU represents Titanium / Copper, which is used as a metalized layer for electrical connection; CU represents Copper, which is used as the main body of the grounding bump for electrical connection; SN / AG represents Tin / Silver, which is used as solder; and NI represents Nickel, which is used to prevent copper diffusion. As shown, Figure 5 ​​As shown, the functional region 16 of the radio frequency switch chip includes a device layer 17 and an interconnection layer 18, wherein: the device layer 17 is an active region, and a first switch and a second switch including NMOS and / or PMOS transistors are formed in the substrate by a photolithography process on the substrate material; the interconnection layer 18 is formed on the device layer 17 and includes a plurality of layers of copper / gold interconnection lines 181 and tungsten / copper conductive plugs 182, the conductive plugs 182 can realize low-impedance connection between layers, and the signal paths between the switches are formed by the interconnection lines 181 and the conductive plugs 182. The ground point of the radio frequency switch chip is located in the interconnection layer, and can be a single conductive plug, an interconnection line, a network of low-impedance ground points, or a combination of an interconnection line and a conductive plug.

[0098] The radio frequency switch chip further includes a chip ground layer or a chip ground region, which can be one or more layers according to actual conditions, for example, one or more layers in the interconnection layer. The ground point of the radio frequency switch chip is the connection between the second switch and the chip ground layer or the chip ground region. Similarly, the ground layer or the ground region of the substrate can also be one or more layers according to actual conditions. The ground layer refers to a substantially whole metal layer as a ground layer, and the ground region refers to a part of a whole metal layer as a ground region. The chip ground layer 10 and the substrate ground layer 30 in the present application Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 11 、 Figure 12 The chip ground layer 10 and the substrate ground layer 30 in the present application are only schematic, and the specific chip ground layer 10 and substrate ground layer 30 need to be determined according to the specific chip structure and substrate structure, such as the number of layers and the location. In the embodiments of the present application, the chip ground layer 10 and the substrate ground layer 30 are described as a whole metal layer.

[0099] Figure 6 is a perspective view of part of the structure of the radio frequency switch chip involved in the present application, Figure 7 is a perspective view of part of the structure of the radio frequency switch chip involved in the present application, which is exploded. Figure 6 and Figure 7 As shown, the reference numeral 10 represents the ground layer of the radio frequency switch chip, the reference numeral 20 represents the ground bump, and the reference numeral 30 represents the ground layer of the substrate. The ground point of the radio frequency switch chip is located in the ground layer 10 of the radio frequency switch chip and is connected to the ground layer 30 of the substrate through the ground bump 20.

[0100] Figure 8 is a top view of part of the structure of a conventional radio frequency switch chip.Figure 8 As shown, when viewed from above, the first to fourth grounding points 11-14 represented by black squares are respectively located between two grounding bumps 20. This relative position setting of the grounding points and the grounding bumps will cause the return path of the SH switch on the interconnect layer to become longer, thereby increasing the parasitic inductance from the grounding points to the standard ground and reducing the isolation between adjacent RF channels.

[0101] Figure 9 This is a schematic top view of a portion of the structure of the RF switch chip involved in the first embodiment of the present application. Compared to conventional RF switch chips, in the first embodiment of the present application, the relative position between the ground point of the RF switch chip and its corresponding ground bump is configured so that the ground bump is as close to the ground point as possible in the lateral direction. In other words, the position of the ground bump is configured so that the sum of the lateral distances from each ground point to the nearest ground bump is minimized. Here, the lateral direction refers to the direction within a plane perpendicular to the top-down angle when viewed from a top-down angle, and the lateral distance between the ground point and the ground bump refers to the distance from the ground point to the geometric center of the ground bump when viewed from a top-down angle. In this embodiment, according to the understanding of those skilled in the art, "the ground bump is as close to the ground point as possible in the lateral direction" is defined as: when the RF switch chip size is fixed, the closer the ground bump is to the ground point in the lateral direction, the better, without affecting other performance and structure of the RF switch chip; if the distance is too close and affects other performance and structure of the RF switch chip, the optimal situation is to have the ground bump close to the ground point at a distance that just does not affect other performance and structure of the RF switch chip. However, those skilled in the art will understand that, under the guidance of the spirit of this embodiment, when the grounding bump is not at the optimal distance from the grounding point, but still utilizes the core essence of this application, it also falls within the definition of the grounding bump being as close to the grounding point as possible in the lateral direction as defined in this application.

[0102] Figure 9 An optional form of the first embodiment is shown. When viewed from above, the first to fourth grounding points 11-14 are located at the geometric center of their corresponding grounding bumps 20, that is, the sum of the lateral distances from each grounding point to the nearest grounding bump corresponding to it is 0. It should be noted that Figure 9 The grounding point of the radio frequency switch chip shown is a grounding point in the form of a conductive plug.

[0103] Figure 10 for Figure 8 and Figure 9 Schematic diagram of the isolation simulation between adjacent RF channels of the RF switch chip structure shown. Figure 10 The horizontal and vertical axes represent the same meaning as Figure 3 The same as above, no further description will be given in this and subsequent similar drawings. Figure 10In the middle, the solid line represents Figure 8 The isolation curve between adjacent RF channels of the RF switch chip structure shown in the figure is shown in the figure. The dotted line indicates the isolation curve between adjacent RF channels of the RF switch chip structure shown in the figure. Figure 9 The isolation curve between adjacent RF channels of the RF switch chip structure is shown in the figure. As shown in the figure, the first embodiment of the present application can improve the isolation between adjacent RF channels by about 10 dB.

[0104] It should be further pointed out that as the requirements for chip integration become higher and higher, there are stricter restrictions on chip size during chip design, which results in a limit on the number of ground bumps that can be set within the limited chip space. Therefore, there may be a situation where different ground points share the same ground bump and are connected to the standard ground. For example, according to Figure 3 The conclusion (2) is that the common grounding point of the same RF channel has little effect on the isolation between adjacent RF channels. In the first embodiment of the present application, Figure 9 Each of the illustrated grounding points 11-14 may correspond to a ground bump, but this application is not limited thereto. Adjacent grounding points within the same RF channel may share the same ground bump. For example, grounding points 11 and 12 may share the same ground bump connected to the standard ground, which contributes to reducing the size of the RF switch chip. In other embodiments, adjacent grounding points within the same RF channel may not share the same ground bump, but may each have its own independent ground bump. The same applies to grounding points 13 and 14.

[0105] according to Figure 3 Conclusion (3) shows that the closer the grounding points of adjacent RF channels are to the RFout port, the greater the impact on the isolation between adjacent RF channels. When the RF channel has M-level second switches, along the RF transmission direction, the grounding point corresponding to the last-level (Mth-level) second switch of the two adjacent RF channels is the grounding point that has the greatest impact on the isolation between the channels. In this application, the last-level second switch of each channel corresponds to one grounding point. Figure 11 FIG2 is a schematic top view of a partial structure of a radio frequency switch chip according to the second embodiment of the present application. Figure 11As shown, in the second embodiment of the present application, the two ground points that have the greatest impact on the isolation between channels in the two adjacent RF channels are the second ground point 12 and the fourth ground point 14. The corresponding ground bumps 20 are arranged to coincide with the geometric centers of the second ground point 12 and the fourth ground point 14, that is, the positions of the ground bumps are configured to ensure that the second ground point 12 and the fourth ground point 14, which have the greatest impact on the isolation between channels, have the shortest path to the standard ground. The first ground point 11 and the third ground point 13 have relatively small impact on the isolation between channels, and the shortest path to the ground can not be set for these two ground points. The relevant description of the RF switch chip in the first embodiment of the present application can be cited here, and will not be repeated here. In the second embodiment of the present application, the main difference from the first embodiment is that "in the two adjacent RF channels, the two ground points that have the greatest impact on the isolation between channels have the shortest path to the corresponding ground bumps". The first embodiment and the second embodiment in the present application are not mutually exclusive, and the first embodiment and the second embodiment can be combined together. That is, in the present application, the positions of the ground bumps are configured to minimize the sum of the lateral distances from each ground point to the nearest ground bump; and / or, in the two adjacent RF channels, the two ground points that have the greatest impact on the isolation between channels have the shortest path to the corresponding ground bumps.

[0106] In the present application, the shortest path from the ground points that have the greatest impact on the isolation between the two adjacent RF channels to the corresponding ground bumps means that the lateral distance from the two ground points to the corresponding ground bumps is the shortest. The shortest lateral distance means that, in the case of a fixed size of the RF switch chip, the distance from the ground point to the corresponding ground bump can reach the minimum value without affecting other performance and structure of the RF switch chip. If the distance is too close to affect other performance and structure of the RF switch chip, the optimal condition is that the distance from the ground point to the corresponding ground bump is just not to affect other performance and structure of the RF switch chip. However, it can be understood by those skilled in the art that, under the guidance of the spirit of the present embodiment, when there is a certain manufacturing / design error or deviation between the distance from the ground point to the corresponding ground bump and the ideal shortest distance, it also belongs to "the shortest lateral distance". In the second embodiment of the present application, for example, the ground point of the second switch of the Mth stage (the last stage) partially overlaps with the corresponding ground bump in the vertical direction of the chip surface, that is, the ground point partially overlaps with the corresponding ground bump from the perspective, that is, the lateral distance between the ground point of the second switch of the Mth stage (the last stage) and the corresponding ground bump is substantially zero, but there is a certain distance or zero distance between the geometric centers of the two. Figure 12 Another top view schematic diagram of part of the structure of the RF switch chip involved in the second embodiment of the present application is shown in FIG. 6. Figure 12As shown, the two ground points 12 and 14, which have the greatest impact on the isolation, partially overlap with the corresponding ground bumps 20, rather than coinciding with the geometric centers, in the case shown Figure 12 In the case shown, it can be considered that the lateral distance between the second ground point 12 and the fourth ground point 14 and the corresponding ground bump 20 is substantially zero, and the path to the ground is still the shortest, which belongs to the case of "shortest lateral distance". The above describes the case that the two ground points 12 and 14, which have the greatest impact on the isolation, partially overlap with the corresponding ground bumps 20, but the present application is not limited thereto, and at least one ground point and the corresponding ground bump can have an overlapping portion in the direction perpendicular to the chip surface, or the ground point and the corresponding ground bump have no overlapping portion in the direction perpendicular to the chip surface, but the sum of the lateral distances from each ground point to the nearest ground bump is the smallest.

[0107] In the second embodiment of the present application, the two ground points that have the greatest impact on the isolation between adjacent radio frequency channels include the ground points of the second switches in the last stage of each radio frequency channel. However, according to the spirit of the present application, the two ground points that have the greatest impact on the isolation between adjacent radio frequency channels can also be the ground points of the second switches in other stages, according to the changes in the specific circuit structure of the radio frequency switch chip.

[0108] According to the first and second embodiments of the present application, on the basis of reasonable and effective control of the path of the ground point to the standard ground, the parasitic inductance of the ground point to the standard ground can also be reduced by increasing the number of ground bumps as much as possible, so as to optimize the isolation between adjacent radio frequency channels of the radio frequency switch chip.

[0109] Since the requirement for chip integration is becoming higher and higher, the area between radio frequency channels is limited, and the lateral spacing between the ground bumps connecting the chip and the substrate structure is required, the radio frequency switch chip of the third embodiment of the present application can arrange the most ground bumps in the area between the radio frequency channels. Figure 13It is a simplified schematic diagram of a four-channel RF switch chip, in which RFC represents the common input port, the black square represents the grounding point of the SH switch, the RF channel is a two-level grounding structure, that is, each RF channel has two-level SH switch grounding points, and the black circle represents the grounding bump. Taking into account the size of the grounding bump itself and the requirements for the lateral distance between the bumps, as many grounding bumps as possible are set in the specific area surrounded by the grounding points between the RF channels. For example, 10 grounding bumps are set between the first RF channel and the second RF channel. In addition to the 4 grounding bumps corresponding to the 4 grounding points shown in the figure, 6 grounding bumps are additionally set; 6 grounding bumps are set between the second RF channel and the third RF channel. In addition to the 4 grounding bumps corresponding to the 4 grounding points shown in the figure, 2 grounding bumps are additionally set. Here, the specific area refers to the area between two adjacent RF channels that is roughly surrounded by the grounding points and is prone to generating a common ground return path. Specifically, Figure 13-22 The area enclosed by the virtual solid lines connecting the grounding points is shown in FIG. Figure 13 The ground bump between the third RF channel and the fourth RF channel is omitted. It should be further explained that in this application, providing as many ground bumps as possible means providing the maximum number of ground bumps within a certain area, taking into account the size of the ground bumps themselves and the minimum safe distance between the ground bumps.

[0110] Figure 14 FIG is a simplified schematic diagram of a four-channel RF switch chip according to the first embodiment of the present application. Figure 14 As shown, the number of grounding points of the SH switch is the same as the number of grounding bumps, and each grounding point at least partially overlaps with its corresponding grounding bump, and is arranged so that the path from the grounding point to the standard ground is the shortest, thereby improving the isolation between adjacent RF channels.

[0111] Figure 15 FIG is a simplified schematic diagram of a four-channel RF switch chip according to the third embodiment of the present application. Figure 15 As shown, the third embodiment is Figure 14 Based on the structure of the RF switch chip shown, it is prioritized to ensure that there is a ground bump at the ground point of the SH switch, and that the ground point and its corresponding ground bump at least partially overlap, and then further arrange as many ground bumps as possible within the specific area surrounded by the solid line connecting the ground points. The traditional matrix arrangement can be abandoned and a honeycomb staggered layout can be adopted. The lateral spacing of the ground bumps can be set using a triangular grid structure. For example, the bumps are distributed according to the vertices of an equilateral triangle, so that 6 fillable spaces are formed around each bump while meeting the minimum spacing requirements. Figure 14 Compared with the first embodiment shown, Figure 15The third embodiment shown makes full use of the space between the two radio frequency channels, and further sets the maximum number of ground bumps that can be accommodated, for example, 4 ground bumps are added between the first radio frequency channel and the second radio frequency channel, and 3 ground bumps are added between the second radio frequency channel and the third radio frequency channel, so that the third embodiment has higher isolation than the first embodiment.

[0112] Figure 16 The schematic diagrams of two-channel, four-channel, and eight-channel radio frequency switch chips are shown respectively. Generally, radio frequency switch chips are divided into SPDT (1 input 2 output), SP4T, SP5T, SP8T, SP10T, etc., as shown in the figure. These switches have a common feature that they are input from a common input port (RFC) and output from one of the radio frequency channels (RFX), and the remaining channels are in an off state. These radio frequency switch chips are characterized in form: the RFC is located at one end of the chip or in the middle of the chip, and the RFX is uniformly distributed at the edge of the chip package. Therefore, in these radio frequency switch chips, there are adjacent radio frequency channels, and the isolation between these adjacent radio frequency channels needs to be guaranteed. Figure 16

[0113] For ease of understanding, only two adjacent radio frequency channels are selected for grounding scheme in the multi-channel switch. For ease of explanation and drawing, a parallel channel structure is first used, i.e., two adjacent channels are in a parallel structure in the circuit layout. Figure 17 The layout diagram of the ground bumps between the two parallel adjacent radio frequency channels of the general two-level grounding structure is shown in the figure, Figure 18 The layout diagram of the ground bumps between the two parallel adjacent radio frequency channels of the two-level grounding structure involved in the third embodiment of the present application is shown in the figure, wherein the gray band part represents the two adjacent radio frequency channels, the arrow represents the transmission direction of the radio frequency signal, the black square represents the grounding point of the SH switch, the black circle represents the ground bump, and the black square represents the specific area surrounded by the grounding point between the two adjacent radio frequency channels, i.e., the area for setting the ground bump. Compared with Figure 17 the general ground bump layout shown in the figure, Figure 18 The key point of the ground bump layout involved in the third embodiment of the present application shown in the figure is that a ground bump is preferentially set at the grounding point, and then as many ground bumps as possible are set in the specific area surrounded by the grounding point, so that better isolation effect can be obtained, which is beneficial to further miniaturization of the chip.

[0114] Figure 19 The layout diagram of the ground bumps between the two parallel adjacent radio frequency channels of the general three-level grounding structure is shown in the figure, Figure 20 ​Fig. 3 is a schematic diagram of the layout of the grounding bumps between two parallel adjacent RF channels of the three-level grounding structure according to the third embodiment of the present application. Figure 19 and Figure 20 respectively, the only difference being that one more grounding point of the SH switch is added, which will not be repeated here. Figure 17 Figure 18 The above

[0115] The above Figure 16-19 illustrates the case of parallel adjacent RF channels, but in fact the area between RF channels of a multi-channel RF switch chip can be a sector structure, but regardless of the shape between channels, the area between RF channels is limited, and the key points to be considered in the layout of the grounding bumps are still the same. Figure 21 Fig. 4 is a schematic diagram of the layout of the grounding bumps between two adjacent RF channels of a general sector three-level grounding structure, Figure 22 Fig. 5 is a schematic diagram of the layout of the grounding bumps between two adjacent RF channels of a sector three-level grounding structure according to the third embodiment of the present application, where θ is the included angle between the two adjacent RF channels, and the ellipsis indicates that part of the grounding bumps between the two adjacent RF channels are omitted, which is not explicitly drawn here because in fact the layout of the grounding bumps can not be regular, and the included angle between the RF channels can also affect the layout of the grounding bumps, only the layout of the grounding bumps in the outermost circle is marked here.

[0116] According to Figure 3 the conclusion (3), the closer the grounding points of adjacent RF channels to the RFout port, the greater the impact on the isolation between adjacent RF channels, which will seriously deteriorate the isolation, therefore in the fourth embodiment of the present application, a first isolation groove is provided on the interconnection layer, the first isolation groove penetrates the interconnection layer of the RF switch in the vertical chip surface direction, and is used to isolate the two grounding points of the two adjacent RF channels closest to the RFout port, thereby cutting off the ground path that has the greatest impact on the isolation, and separating the ground paths of the two adjacent RF channels at this point. The grounding point corresponding to the last stage second switch has at least one grounding bump closest to it, the first isolation groove isolates the grounding bump of the last stage second switch of the two adjacent RF channels closest to the grounding point, and one end of the first isolation groove extends to the grounding bump closest to the grounding point in the planar direction.

[0117] The isolation groove can be processed on the interconnection layer by chip manufacturing processes such as photolithography and etching, and filled with a non-conductive medium in the isolation groove, thereby achieving the effect of isolation. Specifically, first, define the isolation groove pattern on the specified position of the interconnection layer using photolithography technology, protect the non-etching area with a photoresist mask, and then perform selective etching on the interconnection layer by etching process, such as reactive ion etching (RIE), to form an isolation groove with vertical or inclined sidewalls. The non-conductive medium can be selected from​ or , filled into the isolation groove by methods such as plasma enhanced chemical vapor deposition (PECVD) or the like; or a polymer material such as polyimide (PI) can be selected and filled into the isolation groove by a spin coating and curing method; or an air gap can be formed, i.e. the non-conductive medium filled into the isolation groove is air or a low-pressure cavity.

[0118] Figure 23 is a top view schematic diagram of a part of the structure of the radio frequency switch chip involved in the fourth embodiment of the present application, Figure 24 is a split perspective schematic diagram of a part of the structure of the radio frequency switch chip involved in the fourth embodiment of the present application. As shown in Figure 23 and Figure 24 , reference numeral 41 denotes a first isolation groove provided on the radio frequency switch chip, the first isolation groove 41 is provided between the second ground point 12 and the fourth ground point 14 (wherein Figure 24 the ground points are omitted), the second ground point 12 is the ground point corresponding to the second-stage SH switch of the first radio frequency channel, and the fourth ground point 14 is the ground point corresponding to the second-stage SH switch of the second radio frequency channel, that is, the second ground point 12 and the fourth ground point 14 are the two ground points of the adjacent radio frequency channels closest to the RFout port, and the first isolation groove 41 cuts off the common ground path between the second ground point 12 and the fourth ground point 14 which has the greatest impact on the isolation, thereby improving the isolation. The ground points 12 and 14 of the last-stage SH switch are located on the ground layer 10 of the radio frequency switch chip and are connected to the ground layer 30 (standard ground) of the substrate through the ground bumps 20, and the first isolation groove 41 can pull the return path between the ground points 12 and 14 far away, that is, when the signal of the right channel is connected from the ground point 12 to the ground layer 30 of the substrate, if there is no first isolation groove 41, in addition to the signal flowing to the upper and lower two ground bumps 20 adjacent to the ground point 12 to the ground layer of the substrate, the signal will also flow to the upper and lower two ground bumps 20 adjacent to the ground point 14, which may have an impact on the left channel through the ground point 14.

[0119] Figure 25 is a top view schematic diagram of the first isolation groove involved in the fourth embodiment of the present application. The first isolation groove 41 is further described by Figure 25 , the second ground point 12 of the second-stage SH switch of the first radio frequency channel corresponds to two adjacent ground bumps, the first bump 21 and the second bump 22, and the fourth ground point 14 of the second-stage SH switch of the second radio frequency channel corresponds to two adjacent ground bumps, the third bump 23 and the fourth bump 24, the first bump 21 is located on the first side of the second ground point 12, and the third bump 23 is located on the first side of the fourth ground point 14, the first side being Figure 25the upper side in the figure, i.e. the side close to the grounding point of the first-stage SH switch, the second protrusion 22 is located on the second side of the second grounding point 12, and the fourth protrusion 24 is located on the second side of the fourth grounding point 14. The second side is Figure 25 the lower side in the figure, i.e. the side away from the grounding point of the first-stage SH switch. In the illustrated example, the dashed line 43 represents the connection line of the first side edges of the first protrusion 21 and the third protrusion 23, and the dashed line 44 represents the connection line of the second side edges of the second protrusion 22 and the fourth protrusion 24. It should be noted that the dashed line 43 and the dashed line 44 are not real lines, but virtual lines used for illustration. Since the second grounding point 12 can form a ground loop with the adjacent first protrusion 21 and the second protrusion 22, and the fourth grounding point 14 can form a ground loop with the adjacent third protrusion 23 and the fourth protrusion 24, in order to completely cut off the common ground path between the second grounding point 12 and the fourth grounding point 14, the length of the first isolation groove 41 needs to extend at least from the dashed line 43 to the dashed line 44, that is, the length of the first isolation groove 41 needs to extend from the first side edges of the first protrusion 21 and the third protrusion 23 to the first side edges of the first protrusion 21 and the third protrusion 23. In this application, the grounding protrusions corresponding to the second grounding point and the fourth grounding point (the first protrusion 21 and the second protrusion 22, the third protrusion 23 and the fourth protrusion 24) are symmetrically distributed, but the application is not limited to the case of symmetric distribution. The grounding protrusions corresponding to the first grounding point and the second grounding point can also be one; the positional relationship between the first grounding point, the second grounding point and the corresponding grounding protrusions can be the positional relationship between the grounding protrusions and the grounding points that have the greatest impact on the isolation degree in the second embodiment of the application, and the grounding points and the corresponding grounding protrusions partially overlap or the geometric centers coincide.

[0120] In order to further improve the isolation degree, in the fourth embodiment of the application, the length of the first isolation groove can be further extended, for example, to the edge connection line of the first side grounding protrusion of the grounding point of the first-stage SH switch of the adjacent two radio frequency channels, thereby isolating the grounding points corresponding to the first-stage to M-stage second switches of the adjacent two radio frequency channels. Figure 26 Another top view schematic diagram of the first isolation groove involved in the fourth embodiment of the application is shown in FIG. 4B. As shown in FIG. 4B, the length of the first isolation groove 41 is further extended to the edge connection line of the first side grounding protrusion of the grounding point of the first-stage SH switch of the adjacent two radio frequency channels, thereby isolating the grounding points corresponding to the first-stage to M-stage second switches of the adjacent two radio frequency channels. Figure 26As shown, the grounding bump on the first side of the first grounding point 11 is the fifth bump 25, the grounding bump on the first side of the third grounding point 13 is the sixth bump 26, and the end of the first side of the first isolation groove 41 further extends to the connection line 43 of the first side edges of the fifth bump 25 and the sixth bump 26. It needs to be further pointed out that the isolation of the grounding points corresponding to the first to M-level second switches of the two adjacent radio frequency channels here refers to the isolation of the grounding points of the first-level SH switch of the first radio frequency channel and the grounding points of the first-level SH switch of the second radio frequency channel, the isolation of the grounding points of the second-level SH switch of the first radio frequency channel and the grounding points of the second-level SH switch of the second radio frequency channel, and so on, until the isolation of the grounding points of the M-level SH switch of the first radio frequency channel and the grounding points of the M-level SH switch of the second radio frequency channel.

[0121] Figure 23-26 The first isolation groove is shown as a straight line in the vertical chip surface direction, but the application is not limited thereto, and the first isolation groove can also be set as a broken line according to the actual distribution of the grounding points.

[0122] In order to further improve the isolation, in the fourth embodiment of the application, at least one second isolation groove can also be arranged in the interconnection layer of the radio frequency switch chip, for isolating the grounding points of the M-level SH switch and the M-1-level SH switch of the radio frequency channel, for example, in a two-level grounding structure, a second isolation groove is arranged on the interconnection layer, for isolating the grounding points of the second-level SH switch and the first-level SH switch of the radio frequency channel. Figure 27 The top view schematic diagram of the first isolation groove and the second isolation groove involved in the fourth embodiment of the application is shown. As shown in the figure, Figure 27 As shown, the second isolation groove 42 is arranged in the grounding layer 10 of the radio frequency switch chip, the extension direction of the first isolation groove 41 is set as the first direction, the extension direction of the second isolation groove 42 is set as the second direction, the first direction and the second direction intersect with each other, and the second isolation groove isolates the current path between the grounding point with the greatest influence on the isolation between channels and the grounding point with the greatest influence on the non-isolation between channels. The grounding bump on the second side of the first grounding point 11 is the seventh bump 27, the grounding bump on the second side of the third grounding point 13 is the eighth bump 28, the second isolation groove 42 is located on the second side of the seventh bump 27 and the eighth bump 28 and on the first side of the third bump 23 and the fourth bump 24, for isolating the first grounding point 11 and the second grounding point 12, and isolating the third grounding point 13 and the fourth grounding point 14. Figure 27In the preferred embodiment shown, the end of the first side of the first isolation groove 41 just extends to the second isolation groove 42. However, the application is not limited in this regard, and the first isolation groove 41 can also not extend to the second isolation groove 42, as long as it can completely cut off the common ground path between the second ground point 12 and the fourth ground point 14. In addition, the first isolation groove can also extend through the second isolation groove, i.e., the first isolation groove and the second isolation groove are staggered and then continue to extend in the second direction, thereby isolating the ground points corresponding to the first to M-level second switches of the adjacent two radio frequency channels. Figure 27 The first isolation groove and the second isolation groove are shown as straight lines and perpendicular to each other, but the application is not limited in this regard. According to the actual distribution of the ground points, the first isolation groove and the second isolation groove can also be set as broken lines, and the first direction in which the first isolation groove extends and the second direction in which the second isolation groove extends can intersect at any angle. Figure 27 Only one second isolation groove is shown in the two-level ground structure for isolating the ground points of the second-level SH switch and the ground points of the first-level SH switch, but the application is not limited in this regard. The radio frequency switch chip can be a three-level, four-level, or five-level ground structure, and multiple second isolation grooves can be provided for isolating the ground points of the SH switches at each level.

[0123] In combination with reference Figure 5 In the application, the first isolation groove and the second isolation groove can extend from the surface of the radio frequency switch to the bottommost layer of the interconnection layer, stop above the device layer 17 (here, above is not directly above, but only to indicate the relative position relationship between the upper and lower layers), or can penetrate through the bottommost layer of the interconnection layer. The purpose of the first isolation groove and the second isolation groove is to isolate the conduction path between the adjacent two ground points, and as long as the first isolation groove and the second isolation groove can meet this requirement, they belong to the technical solutions protected by the application.

[0124] In order to further improve the isolation, in the fourth embodiment of the application, multiple second isolation grooves parallel to each other can also be provided on the interconnection layer, for isolating the ground points corresponding to the adjacent two-level second switches of the first radio frequency channel, and for isolating the ground points corresponding to the adjacent two-level second switches of the second radio frequency channel.

[0125] Figure 28 For Figure 8 , Figure 25 and Figure 27 The isolation simulation diagrams between the adjacent radio frequency channels of the three different chip structures are shown, wherein the solid line of "Structure 1" represents the isolation curve between the adjacent radio frequency channels in the conventional chip structure shown in Figure 8 The long dashed line of "Structure 2" represents the isolation curve between the adjacent radio frequency channels in the chip structure shown in Figure 25The isolation degree curve between adjacent radio frequency channels in the chip structure provided with the first isolation groove is shown. The short dashed line of "Structure 3" represents Figure 27 The isolation degree curve between adjacent radio frequency channels in the chip structure provided with the first isolation groove and the second isolation groove is shown. The long dashed line of "Structure 4" represents Figure 22 It can be clearly seen that the isolation groove provided on the interconnection of the radio frequency switch chip to isolate the grounding points can effectively improve the isolation degree.

[0126] The above Figure 25-26 The first isolation groove and the second isolation groove provided on the basis of the general grounding structure in the fourth embodiment of the present application are shown, but the present application is not limited thereto. In the fourth embodiment of the present application, the first isolation groove and the second isolation groove can also be provided on the basis of the first embodiment, the second embodiment or the third embodiment. Figure 29 And Figure 30 Another top view schematic diagram of the first isolation groove involved in the fourth embodiment of the present application is shown, wherein: Figure 29 The first isolation groove is provided on the basis of the first embodiment, and the first to fourth grounding points 11-14 are respectively located at the geometric centers of the corresponding grounding bumps 20. The first isolation groove 41 is provided between the two grounding bumps 20 corresponding to the second grounding point 12 and the fourth grounding point 14. Figure 30 The first isolation groove is provided on the basis of the second embodiment. The second grounding point 12 and the fourth grounding point 14 are the two grounding points that have the greatest impact on the isolation degree, and are respectively located at the geometric centers of the corresponding grounding bumps 20. The first grounding point 11 and the third grounding point 13 are located between the two adjacent grounding bumps 20. The first isolation groove 41 is provided between the two grounding bumps 20 corresponding to the second grounding point 12 and the fourth grounding point 14. Based on the above description of each embodiment, those skilled in the art can easily conceive that the fourth embodiment of the present application can provide the first isolation groove and the second isolation groove on the basis of the first to third embodiments.

[0127] The on-chip interconnection layer (together with the grounding bump) isolation process of the high-isolation radio frequency switch chip is analyzed and described above. In the chip product design, the radio frequency switch chip also needs to be jointly packaged, such as FCLGA (Flip Chip Land Grid Array) packaging, etc., as a whole product for design, and therefore the isolation on the packaging substrate is also a key point that needs to be considered in chip design. Figure 31 A side structure schematic diagram of the radio frequency switch chip involving the substrate structure in the fifth embodiment of the present application is shown, Figure 32 A split perspective schematic diagram of the radio frequency switch chip involving the substrate structure in the fifth embodiment of the present application is shown. As Figure 31 And Figure 32As shown, the ground layer 10 of the RF switch chip is connected to the ground layer 30 of the substrate through the ground bumps 20. The ground layer 30 of the substrate includes four metal layers, which are the first metal layer 31, the second metal layer 32, the third metal layer 33 and the fourth metal layer 34 from the side of the ground layer 10 of the RF switch chip. It is easy to think that the number of the metal layers of the substrate structure can be set according to the needs of the chip design, for example, it can be two layers, three layers, five layers, six layers, etc. The metal layers of the substrate are electrically connected through the vias 36, and the third isolation groove 35 corresponding to the first isolation groove 41 is arranged on the first metal layer 31, and the third isolation groove 35 is filled with non-conductive medium. The non-conductive medium filling the third isolation groove 35 can be selected from a polymer material, such as polyimide (PI), which is filled into the third isolation groove by spin coating and curing.

[0128] Further, the third isolation groove 35 corresponding to the first isolation groove 41 can also be arranged on the second metal layer and the third metal layer, so as to further improve the isolation of the RF switch chip. It needs to be further explained that the lateral size of the third isolation groove is greater than that of the first isolation groove, and the range of the third isolation groove in the vertical chip direction can completely cover the range of the first isolation groove.

[0129] Figure 33 The simulation diagrams of the isolation degrees between the adjacent RF channels of the three different substrate structures are shown in the figure, wherein the solid line represents the isolation degree curve when the third isolation groove is not arranged in the substrate structure, the long dashed line represents the isolation degree curve when the third isolation groove is arranged only on the first metal layer in the substrate structure, and the short dashed line represents the isolation degree curve when the third isolation groove is arranged on the first to third metal layers in the substrate structure. It can be seen from the figure that Figure 33 It can be seen that arranging the third isolation groove corresponding to the first isolation groove on the metal layer in the substrate structure can significantly improve the isolation of the RF switch chip, and the more metal layers on which the third isolation groove is arranged, the better the improvement effect of the isolation degree.

[0130] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application; the embodiments of the present application and the features in the embodiments can be combined with each other without conflict. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A radio frequency switch chip, characterized in that: The system comprises at least a first radio frequency channel and a second radio frequency channel adjacent to each other, each radio frequency channel comprising a series-parallel switch structure, wherein the series-parallel switch structure comprises: N stages of first switches connected in series are sequentially connected in series between the RF input terminal and the RF output terminal of the RF channel, where N is an integer ≥ 1; M stages of second switches connected in parallel, each stage of the second switches being connected between the radio frequency channel and a standard ground, where M is an integer ≥ 1, and each stage of the second switches having a grounding point for connection to the standard ground; The surface of the RF switch chip has grounding bumps, each grounding point is electrically connected to a standard ground via its corresponding grounding bump, wherein the positions of the grounding bumps are configured so that the sum of the lateral distances from each grounding point to the grounding bump closest thereto is minimized; And / or, in two adjacent radio frequency channels, the path from the ground point that has the greatest impact on inter-channel isolation to the corresponding ground bump is the shortest.

2. The radio frequency switch chip according to claim 1, wherein: Also includes: a device layer, and an interconnection layer located on the device layer; The first switch and the second switch include transistors, and the transistors are located in the device layer; The interconnection layer includes: an interconnection line and a conductive plug connected to the interconnection line, and the first switch and the second switch are electrically connected through the interconnection line and the conductive plug; The grounding point includes a conductive plug, an interconnection line, or a conductive plug and an interconnection line located in the interconnection layer.

3. The radio frequency switch chip according to claim 1, wherein: The grounding point having the greatest impact on the inter-channel isolation includes: along the RF transmission direction, the grounding points corresponding to the second switches of the last stage of two adjacent RF channels.

4. The radio frequency switch chip according to claim 3, wherein: The shortest path from the grounding point having the greatest impact on inter-channel isolation to the corresponding grounding bump includes: the grounding point of the last-stage second switch partially overlaps with the corresponding grounding bump in a direction perpendicular to the chip.

5. The radio frequency switch chip according to claim 1, wherein: Each of the grounding points corresponds to a grounding bump, and the grounding bumps are not shared; or, at least two adjacent grounding points share a grounding bump.

6. The radio frequency switch chip according to claim 1, wherein: At least one of the grounding points has an overlapping portion with its corresponding grounding bump in a direction perpendicular to the chip surface, or the grounding point has no overlapping portion with its corresponding grounding bump in a direction perpendicular to the chip surface, but the sum of the lateral distances from each grounding point to the grounding bump closest to it is the smallest.

7. The radio frequency switch chip according to claim 1, wherein: Between two adjacent radio frequency channels, a specific area is enclosed by the grounding point. In addition to the grounding bumps corresponding to the grounding point, as many grounding bumps as possible are arranged in the specific area to be electrically connected to the standard ground.

8. The radio frequency switch chip according to claim 1, wherein: The radio frequency switch chip includes a chip ground layer or a chip ground area, and the grounding point is a connection point between the second switch and the chip ground layer or the chip ground area.

9. The radio frequency switch chip according to claim 8, wherein: The chip ground layer or chip ground area is located at one or more layers of the interconnection layer.

10. The radio frequency switch chip according to claim 1, wherein: The standard ground is located on the substrate and is a ground layer or a ground area on the substrate.

11. The radio frequency switch chip according to claim 2, wherein: A first isolation groove is provided on the interconnection layer. The first isolation groove is used to isolate a grounding point having the greatest impact on the inter-channel isolation between two adjacent radio frequency channels. The first isolation groove is filled with a non-conductive medium.

12. The radio frequency switch chip according to claim 11, wherein: The grounding point corresponding to the second switch of the last stage has at least one grounding bump closest to it; The first isolation slot is used to isolate the grounding bumps of two adjacent radio frequency channels that are closest to the grounding point corresponding to the last-stage second switch.

13. The radio frequency switch chip according to claim 11, wherein: One end of the first isolation slot extends to a grounding bump that is closest to a grounding point corresponding to the last-stage second switch.

14. The radio frequency switch chip according to claim 11, wherein: The first isolation trench is a straight line or a broken line in a direction perpendicular to the chip surface.

15. The radio frequency switch chip according to claim 11, wherein: The first isolation trench penetrates the interconnection layer of the radio frequency switch in a direction perpendicular to the chip surface.

16. The radio frequency switch chip according to claim 11, wherein: Two grounding bumps adjacent to a grounding point corresponding to the last-stage second switch of the first radio frequency channel are respectively a first bump and a second bump; Two grounding bumps adjacent to the grounding point corresponding to the last-stage second switch of the second RF channel are respectively a third bump and a fourth bump; The first bump and the third bump are located on a first side of a grounding point corresponding to the last-stage second switch of two adjacent radio frequency channels; The second bump and the fourth bump are located on a second side of a grounding point corresponding to the last-stage second switch of two adjacent radio frequency channels; The end of the first side of the first isolation groove extends at least to the line connecting the edges of the first side of the first bump and the third bump, and the end of the second side of the first isolation groove extends at least to the line connecting the edges of the second side of the second bump and the fourth bump.

17. The radio frequency switch chip according to claim 16, wherein: The ground bump located on the first side of the ground point corresponding to the first-stage second switch of the first RF channel is a fifth bump, the ground bump located on the first side of the ground point corresponding to the first-stage second switch of the second RF channel is a sixth bump, and the end of the first side of the first isolation slot extends at least to a line connecting edges of the first sides of the fifth bump and the sixth bump.

18. The radio frequency switch chip according to claim 16, wherein: At least one second isolation trench is further provided on the interconnection layer. The second isolation trench is filled with a non-conductive medium. The first isolation trench extends in a first direction, and the second isolation trench extends in a second direction. The first direction intersects the second direction. The second isolation slot is used to isolate the current path between the grounding point that has the greatest impact on the inter-channel isolation and the grounding point that does not have the greatest impact on the inter-channel isolation.

19. The radio frequency switch chip according to claim 18, wherein: The ground bump located on the second side of the ground point corresponding to the second switch of the second-to-last stage of the first RF channel is the seventh bump, the ground bump located on the second side of the ground point corresponding to the second switch of the second-to-last stage of the second RF channel is the eighth bump, and the second isolation groove is located on the second sides of the seventh and eighth bumps, and on the first side of the third and fourth bumps.

20. The radio frequency switch chip according to claim 18, wherein: A plurality of mutually parallel second isolation grooves are provided on the interconnection layer, respectively used to isolate the grounding points corresponding to two adjacent stages of the second switches of the first RF channel and the grounding points corresponding to two adjacent stages of the second RF channel.

21. The radio frequency switch chip according to any one of claims 11 to 20, characterized in that: The RF switch chip is packaged on a substrate, which includes X metal layers, where X is an integer ≥ 2. The metal layers are electrically connected through vias. A third isolation groove corresponding to the first isolation groove is provided on the first metal layer, and the third isolation groove is filled with a non-conductive medium.

22. The radio frequency switch chip according to claim 21, wherein: Third isolation trenches corresponding to the first isolation trenches are respectively provided on the first metal layer to the X-1th metal layer.

23. The radio frequency switch chip according to claim 21, wherein: The lateral dimension of the third isolation trench is greater than that of the first isolation trench, and the range of the third isolation trench in the direction perpendicular to the chip can completely cover the range of the first isolation trench.

Images