Non-polar bus isolator and ring bus system

Abstract

A non-polar bus isolator and a ring bus system belong to the technical field of buses, are provided with a first end and a second end, and comprise a control circuit, a first rectification circuit, a switch circuit, a second rectification circuit, a first detection circuit and a second detection circuit; the first end, the first rectifying circuit, the switching circuit, the second rectifying circuit and the second end are sequentially connected in series; the first detection circuit responds to the first end short circuit and outputs a first trigger signal; the second detection circuit responds to the short circuit of the second end and outputs a second trigger signal; the control circuit responds to the first trigger signal or the second trigger signal and controls the switching circuit to be switched off; therefore, non-polar connection is supported while the ring bus system is realized.

Description

Technical Field

[0001] The present application belongs to the field of bus technology, and in particular relates to a non-polarity bus isolator and a ring bus system. Background Art

[0002] In actual engineering applications, the positive and negative poles of the relevant bus isolators must be strictly distinguished during installation, which increases the difficulty of construction and the probability of error. During subsequent maintenance and inspection, it is also easy to cause equipment damage or system failure due to incorrect polarity connection.

[0003] Furthermore, with the development of industrial automation, intelligent buildings and other fields, the demand for system stability is becoming increasingly stringent. In a tree-like wiring method, if a problem occurs at any point in the line, all subsequent equipment will be paralyzed.

[0004] However, the relevant bus isolators cannot meet the requirements of the ring bus. Therefore, it is necessary to develop isolators suitable for ring wiring to ensure that faults can be effectively isolated in the ring bus structure and maintain stable operation of the system.

[0005] Therefore, there is an urgent need to provide a non-polarity bus isolator that can realize a ring bus system. Summary of the Invention

[0006] The purpose of the present application is to provide a non-polarity bus isolator and a ring bus system, aiming to solve the problem that related bus isolators cannot support non-polarity connections while implementing a ring bus system.

[0007] An embodiment of the present application provides a non-polarity bus isolator having a first end and a second end, including a control circuit, a first rectifier circuit, a switch circuit, and a second rectifier circuit;

[0008] The first end, the first rectifier circuit, the switch circuit, the second rectifier circuit and the second end are sequentially connected in series;

[0009] The non-polarity bus isolator further comprises:

[0010] a first detection circuit connected to the first end, configured to output a first trigger signal in response to a short circuit of the first end;

[0011] a second detection circuit connected to the second end, configured to output a second trigger signal in response to a short circuit of the second end;

[0012] The control circuit, the first detection circuit and the second detection circuit are used to control the switch circuit to be disconnected in response to the first trigger signal or the second trigger signal.

[0013] An embodiment of the present invention further provides a ring bus system, characterized in that the ring bus system includes a controller, a plurality of load devices and a plurality of the above-mentioned non-polarity bus isolators;

[0014] A plurality of the non-polarity bus isolators are connected in series between the first input / output terminal of the controller and the second input / output terminal of the controller, and the load device is connected in parallel between every two of the non-polarity bus isolators.

[0015] Compared with the prior art, the embodiments of the present invention have the following advantages: a main loop for bidirectional transmission is formed by sequentially connecting the first end, the first rectifier circuit, the switch circuit, the second rectifier circuit, and the second end in series; since the main loop includes the first rectifier circuit and the second rectifier circuit, non-polarity connection can be performed; since the main loop has a bidirectional transmission function, and the first detection circuit outputs a first trigger signal in response to a short circuit at the first end to disconnect the switch circuit, thereby isolating the short-circuited load connected to the first end in the case of reverse transmission (current passes through the second end, the second rectifier circuit, the switch circuit, the first rectifier circuit to the first end); and the second detection circuit outputs a second trigger signal in response to a short circuit at the second end to disconnect the switch circuit, thereby isolating the short-circuited load connected to the second end in the case of forward transmission (current passes through the first end, the first rectifier circuit, the switch circuit, the second rectifier circuit to the second end); thereby, a ring bus system can be constructed; therefore, while implementing the ring bus system, non-polarity connection is supported. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical inventions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic structural diagram of a non-polarity bus isolator provided in one embodiment of the present application;

[0018] Figure 2 Another structural diagram of a non-polarity bus isolator provided in one embodiment of the present application;

[0019] Figure 3 Another structural diagram of a non-polarity bus isolator provided in one embodiment of the present application;

[0020] Figure 4 A partial exemplary circuit diagram of a non-polarity bus isolator provided in one embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0022] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0023] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0025] Figure 1 The following is a schematic diagram of the structure of a non-polarity bus isolator provided in a preferred embodiment of the present application. For ease of explanation, only the parts related to this embodiment are shown, which are described in detail as follows:

[0026] The non-polarity bus isolator has a first end and a second end, and includes a first rectifier circuit 10, a switch circuit 30 and a second rectifier circuit 20;

[0027] The first end, the first rectifier circuit 10, the switch circuit 30, the second rectifier circuit 20 and the second end are sequentially connected in series;

[0028] The polarity-independent bus isolator further includes a first detection circuit 40 , a second detection circuit 50 and a control circuit 60 .

[0029] A first detection circuit 40 is connected to the first terminal and is configured to output a first trigger signal in response to a short circuit at the first terminal;

[0030] a second detection circuit 50 connected to the second terminal, configured to output a second trigger signal in response to a short circuit at the second terminal;

[0031] The control circuit 60 , together with the first detection circuit 40 and the second detection circuit 50 , is configured to control the switch circuit 30 to be disconnected in response to the first trigger signal or the second trigger signal.

[0032] A main loop for bidirectional transmission is formed by sequentially connecting the first end, the first rectifier circuit 10, the switch circuit 30, the second rectifier circuit 20, and the second end in series. Since the main loop includes the first rectifier circuit 10 and the second rectifier circuit 20, non-polarity connection can be performed.

[0033] Since the main circuit has a bidirectional transmission function, and the first detection circuit 40 outputs a first trigger signal in response to a short circuit at the first end to disconnect the switch circuit 30, thereby isolating the short-circuited load connected to the first end in the case of reverse transmission (current passes through the second end, the second rectifier circuit 20, the switch circuit 30, the first rectifier circuit 10 to the first end).

[0034] Since the main circuit has a bidirectional transmission function, and the second detection circuit 50 outputs a second trigger signal in response to a short circuit at the second end to disconnect the switch circuit 30, thereby achieving isolation of the short-circuited load connected to the second end under forward transmission (current passes through the first end, the first rectifier circuit 10, the switch circuit 30, the second rectifier circuit 20 to the second end).

[0035] This allows the construction of a ring bus system to be realized; thus, while realizing the ring bus system, a non-polarity connection is performed.

[0036] In one embodiment, if Figure 2 As shown, the first rectifier circuit 10 is used to receive a first input voltage from a first end and rectify the first input voltage to output a first direct current; the switching circuit 30 is used to transmit the first direct current in response to a control signal to output a second direct current; the second rectifier circuit 20 is used to rectify the second direct current to output a first output voltage to the second end; the second detection circuit 50 includes a second short-circuit circuit 51 and a second trigger circuit 52.

[0037] a second short-circuit circuit 51 connected to the second terminal, the switch circuit 30 and the second rectifier circuit 20, for short-circuiting the second DC power in response to the second terminal being short-circuited;

[0038] The second trigger circuit 52 is connected to the control circuit 60, the switch circuit 30 and the second rectifier circuit 20, and is configured to output a second trigger signal in response to the second DC short circuit;

[0039] The control circuit 60 is further configured to disconnect the control signal in response to the second trigger signal, so as to enable the switch circuit 30 to disconnect the output of the second direct current and enable the second rectifier circuit 20 to disconnect the output of the first output voltage.

[0040] Through the above technical solution, in the case of forward transmission (current passes through the first end, the first rectifier circuit 10, the switch circuit 30, the second rectifier circuit 20 to the second end), if the load connected to the second end is short-circuited, a second trigger signal is output to disconnect the switch circuit 30, thereby achieving isolation of the short-circuited load connected to the second end.

[0041] In one embodiment, if Figure 3 As shown, the second rectifier circuit 20 is used to receive the second input voltage from the second end and rectify the second input voltage to output a third direct current; the switching circuit 30 is used to transmit the third direct current in response to the control signal to output a fourth direct current; the first rectifier circuit 10 is used to rectify the fourth direct current to output a second output voltage to the first end; the first detection circuit 40 includes a first short-circuit circuit 41 and a first trigger circuit 42.

[0042] a first short-circuit circuit 41 connected to the first end, the switch circuit 30 and the first rectifier circuit 10, and configured to short-circuit the fourth DC power in response to a short circuit at the first end;

[0043] a first trigger circuit 42 connected to the control circuit 60, the switch circuit 30 and the first rectifier circuit 10, and configured to output a first trigger signal in response to a fourth DC short circuit;

[0044] The control circuit 60 is further configured to disconnect the control signal in response to the first trigger signal, so as to enable the switch circuit 30 to disconnect the output of the fourth DC power and enable the first rectifier circuit 10 to disconnect the output of the second output voltage.

[0045] Through the above technical solution, in the case of reverse transmission (current passes through the second end, the second rectifier circuit 20, the switch circuit 30, the first rectifier circuit 10 to the first end), if the load connected to the first end is short-circuited, the first trigger signal is output to disconnect the switch circuit 30, thereby achieving isolation of the short-circuited load connected to the first end.

[0046] In one embodiment, the polarity-free bus isolator further includes a resistor component.

[0047] The resistor element is connected in parallel with the switch circuit 30 and is connected to the first rectifier circuit 10 and the second rectifier circuit 20 .

[0048] At the moment the first end is connected to the first input voltage, the first DC power is converted into a second DC power after current limiting by the resistor component and input into the second rectifier circuit 20. Due to the voltage-reducing effect of the load connected to the second end, the second detection circuit 50 stops outputting the second trigger signal to the control circuit 60. The control circuit 60 stops outputting the control signal to turn on the switch circuit 30, and the switch circuit 30 outputs the second DC power.

[0049] At the moment the second end is connected to the second input voltage, the third DC power is converted into a fourth DC power after current limiting by the resistor component and input into the second rectifier circuit 20. Due to the voltage-reducing effect of the load connected to the first end, the first detection circuit 40 stops outputting the first trigger signal to the control circuit 60. The control circuit 60 stops outputting the control signal to turn on the switch circuit 30, and the switch circuit 30 outputs the fourth DC power.

[0050] Through the above technical solution, the power-on startup of the non-polarity bus isolator is achieved.

[0051] Figure 4 A partial exemplary circuit structure of a non-polarity bus isolator provided by an embodiment of the present invention is shown. For ease of explanation, only the portion related to the embodiment of the present invention is shown, which is described in detail as follows:

[0052] The second short circuit 51 includes a first photorelay U1, a first resistor R1 and a second resistor R2;

[0053] The anode of the light-emitting diode in the first channel of the first photorelay U1 is connected to the first end of the first resistor R1, the anode of the light-emitting diode in the second channel of the first photorelay U1 is connected to the first end of the second resistor R2, and the cathode of the light-emitting diode in the first channel of the first photorelay U1 and the cathode of the light-emitting diode in the second channel of the first photorelay U1 are connected to the power ground;

[0054] The second end of the first resistor R1, the second end of the second resistor R2, and the second end of the light-receiving semiconductor in the second channel of the first photorelay U1 are connected and together constitute a first controlled end of the second short-circuit circuit 51, which is connected to the second trigger circuit 52, the switch circuit 30, and the second rectifier circuit 20 to receive the negative electrode of the second direct current;

[0055] The first end of the light-receiving semiconductor in the first channel of the first photorelay U1 constitutes the second controlled end of the second short-circuit circuit 51, which is connected to the second trigger circuit 52, the switch circuit 30 and the second rectifier circuit 20 to receive the positive electrode of the second direct current;

[0056] The second end of the light-receiving semiconductor in the first channel of the first photorelay U1 constitutes the first control end of the second short-circuit circuit 51, and is connected to the second rectifier circuit 20 and the second end of the non-polarity bus isolator to access the positive electrode of the first output voltage;

[0057] The first end of the light-receiving semiconductor in the second channel of the first photorelay U1 constitutes the second control end of the second short-circuit circuit 51 , which is connected to the second rectifier circuit 20 and the second end of the non-polarity bus isolator to access the negative pole of the first output voltage.

[0058] The second trigger circuit 52 includes a first transistor Q1, a first voltage regulator Z1, a first diode D1, a second diode D2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

[0059] The cathode of the first voltage regulator tube Z1 constitutes the first input terminal of the second trigger circuit 52, which is connected to the second short circuit 51, the switch circuit 30 and the second rectifier circuit 20 to receive the positive electrode of the second direct current;

[0060] The cathode of the first diode D1 constitutes the second input terminal of the second trigger circuit 52, and is connected to the second short circuit 51, the switch circuit 30 and the second rectifier circuit 20 to receive the cathode of the second direct current.

[0061] The anode of the first voltage-stabilizing diode Z1 is connected to the emitter of the first transistor Q1, the base of the first transistor Q1 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the anode of the first diode D1, the collector of the first transistor Q1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the first end of the fourth resistor R4;

[0062] The second end of the fourth resistor R4 and the first end of the fifth resistor R5 are connected to form an output end of the second trigger circuit 52, which is connected to the control circuit 60 to output a second trigger signal;

[0063] A second end of the fifth resistor R5 is connected to the power ground.

[0064] The first short circuit 41 includes a second optical relay U2, a sixth resistor R6 and a seventh resistor R7;

[0065] The anode of the light-emitting diode in the first channel of the second photorelay U2 is connected to the first end of the sixth resistor R6, the anode of the light-emitting diode in the second channel of the second photorelay U2 is connected to the first end of the seventh resistor R7, and the cathode of the light-emitting diode in the first channel of the second photorelay U2 and the cathode of the light-emitting diode in the second channel of the second photorelay U2 are both connected to the power ground;

[0066] The second end of the sixth resistor R6, the second end of the seventh resistor R7, and the second end of the light-receiving semiconductor in the second channel of the second photorelay U2 are connected and together constitute a first controlled end of the first short-circuit circuit 41, which is connected to the first trigger circuit 42, the switch circuit 30, and the first rectifier circuit 10 to receive the negative electrode of the fourth direct current;

[0067] The first end of the light-receiving semiconductor in the first channel of the second photorelay U2 constitutes the second controlled end of the first short-circuit circuit 41, and is connected to the first trigger circuit 42, the switch circuit 30 and the first rectifier circuit 10 to receive the positive electrode of the fourth direct current;

[0068] The second end of the light-receiving semiconductor in the first channel of the second photorelay U2 constitutes the first control end of the first short-circuit circuit 41, and is connected to the first rectifier circuit 10 and the first end of the non-polarity bus isolator to access the positive electrode of the second output voltage;

[0069] The first end of the light-receiving semiconductor in the second channel of the second photorelay U2 constitutes the second control end of the first short-circuit circuit 41 , and is connected to the first rectifier circuit 10 and the first end of the non-polarity bus isolator to access the negative pole of the second output voltage.

[0070] The first trigger circuit 42 includes a second transistor Q2, a second voltage regulator Z2, a third diode D3, a fourth diode D4, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10;

[0071] The cathode of the second voltage-stabilizing tube Z1 constitutes the first input terminal of the first trigger circuit 42, and is connected to the first short-circuit circuit 41, the switch circuit 30 and the first rectifier circuit 10 to receive the positive electrode of the fourth direct current;

[0072] The cathode of the third diode D3 constitutes the second input terminal of the first trigger circuit 42, and is connected to the first short circuit 41, the switch circuit 30 and the first rectifier circuit 10 to receive the negative electrode of the fourth direct current;

[0073] The anode of the second voltage-stabilizing diode Z2 is connected to the emitter of the second triode Q2, the base of the second triode Q2 is connected to the first end of the eighth resistor R8, the second end of the eighth resistor R8 is connected to the anode of the third diode D3, the collector of the second triode Q2 is connected to the anode of the fourth diode D4, and the cathode of the fourth diode D4 is connected to the first end of the ninth resistor R9;

[0074] The second end of the ninth resistor R4 and the first end of the tenth resistor R10 are connected to form an output end of the first trigger circuit 42, which is connected to the control circuit 60 to output a first trigger signal;

[0075] A second end of the tenth resistor R10 is connected to the power ground.

[0076] The first rectifier circuit 10 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a fourth capacitor C4, a fifth capacitor C5, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, and an eighteenth resistor R18;

[0077] The drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the first end of the fifteenth resistor R15, and the first end of the seventeenth resistor R17 are connected to form a first positive input and output end of the first rectifier module, which is connected to the first end of the non-polarity bus isolator to receive the A pole of the first input voltage or output the positive pole of the second output voltage;

[0078] The drain of the second PMOS transistor P2, the drain of the second NMOS transistor N2, the first end of the eleventh resistor R11, and the first end of the thirteenth resistor R13 are connected to form a first negative input and output terminal of the first rectifier module, which is connected to the first end of the non-polarity bus isolator to receive the B pole of the first input voltage or output the negative pole of the second output voltage;

[0079] The source of the first PMOS transistor P1, the source of the second PMOS transistor P2, the first end of the fifth capacitor C5, the first end of the twelfth resistor R12, and the first end of the sixteenth resistor R16 are connected to form a second positive input and output end of the first rectifier module, which is connected to the switch circuit 30 and the first detection circuit 40 to output the positive electrode of the first direct current or to receive the positive electrode of the fourth direct current;

[0080] The source of the first NMOS transistor N1, the source of the second NMOS transistor N2, the first end of the fourth capacitor C4, the first end of the fourteenth resistor R14, and the first end of the eighteenth resistor R18 are connected to form a second negative input and output end of the first rectifier module, which is connected to the switch circuit 30 and the first detection circuit 40 to output the negative electrode of the first direct current or be connected to the negative electrode of the fourth direct current;

[0081] The gate of the first PMOS transistor P1 is connected to the second end of the eleventh resistor R11 and the second end of the twelfth resistor R12. The gate of the second PMOS transistor P2 is connected to the second end of the fifth capacitor C5, the second end of the fifteenth resistor R15, and the second end of the sixteenth resistor R16. The gate of the first NMOS transistor N1 is connected to the second end of the fourth capacitor C4, the second end of the thirteenth resistor R13, and the second end of the fourteenth resistor R14. The gate of the second NMOS transistor N2 is connected to the second end of the seventeenth resistor R17 and the second end of the eighteenth resistor R18.

[0082] The pole A of the first input voltage and the pole B of the first input voltage have opposite polarities and are respectively the positive pole of the first input voltage and the negative pole of the first input voltage.

[0083] It can be understood that the first rectifier circuit 10 may further include a third voltage regulator tube Z3, a fourth voltage regulator tube Z4, a fifth voltage regulator tube Z5 and a sixth voltage regulator tube Z6; the third voltage regulator tube Z3 is connected between the gate and source of the first PMOS tube P1, the fourth voltage regulator tube Z3 is connected between the gate and source of the first NMOS tube N1; the fifth voltage regulator tube Z5 is connected between the gate and source of the second PMOS tube P2, and the sixth voltage regulator tube Z6 is connected between the gate and source of the second NMOS tube N2.

[0084] The first rectifier circuit 10 may further include a third capacitor C3 and a sixth capacitor C6; the third capacitor C3 is connected between the gate and source of the first PMOS transistor P1, and the sixth capacitor C6 is connected between the gate and source of the second NMOS transistor N2. It should be noted that the third capacitor C3 and the sixth capacitor C6 have smaller capacitance than the fourth capacitor C4 and the fifth capacitor C5.

[0085] The second rectifier circuit 20 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, a fourth NMOS transistor N4, an eighth capacitor C8, a ninth capacitor C9, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, and a twenty-sixth resistor R26.

[0086] The drain of the third PMOS transistor P3, the drain of the third NMOS transistor N3, the first end of the twenty-third resistor R23, and the first end of the twenty-fifth resistor R25 are connected to form a first positive input and output terminal of the second rectifier module, and are connected to the second end of the non-polarity bus isolator to receive the A terminal of the second input voltage or output the positive terminal of the first output voltage;

[0087] The drain of the fourth PMOS transistor P4, the drain of the fourth NMOS transistor N4, the first end of the nineteenth resistor R19, and the first end of the twenty-first resistor R21 are connected to form a first negative input and output terminal of the second rectifier module, and are connected to the second end of the non-polarity bus isolator to receive the B terminal of the second input voltage or output the negative terminal of the first output voltage;

[0088] The source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the first end of the ninth capacitor C9, the first end of the twentieth resistor R20, and the first end of the twenty-fourth resistor R24 ​​are connected to form a second positive input and output end of the second rectifier module, which is connected to the switch circuit 30 and the second detection circuit 50 to output the positive electrode of the third direct current or to be connected to the positive electrode of the second direct current;

[0089] The source of the third NMOS transistor N3, the source of the fourth NMOS transistor N4, the first end of the eighth capacitor C8, the first end of the twenty-second resistor R22, and the first end of the twenty-sixth resistor R26 are connected to form a second negative input and output end of the second rectifier module, which is connected to the switch circuit 30 and the second detection circuit 50 to output the negative electrode of the third direct current or be connected to the negative electrode of the second direct current;

[0090] The gate of the third PMOS transistor P3 is connected to the second end of the nineteenth resistor R19 and the second end of the twentieth resistor R20. The gate of the fourth PMOS transistor P4 is connected to the second end of the ninth capacitor C9, the second end of the twenty-third resistor R23, and the second end of the twenty-fourth resistor R24. The gate of the third NMOS transistor N3 is connected to the second end of the eighth capacitor C8, the second end of the twenty-first resistor R21, and the second end of the twenty-second resistor R22. The gate of the fourth NMOS transistor N4 is connected to the second end of the twenty-fifth resistor R25 and the second end of the twenty-sixth resistor R26.

[0091] The pole A of the second input voltage and the pole B of the second input voltage have opposite polarities and are respectively the positive pole of the second input voltage and the negative pole of the second input voltage.

[0092] It can be understood that the second rectifier circuit 20 may further include a seventh voltage regulator tube Z7, an eighth voltage regulator tube Z8, a ninth voltage regulator tube Z9 and a tenth voltage regulator tube Z10; the seventh voltage regulator tube Z7 is connected between the gate and source of the third PMOS tube P3, the eighth voltage regulator tube Z8 is connected between the gate and source of the third NMOS tube N3; the ninth voltage regulator tube Z9 is connected between the gate and source of the fourth PMOS tube P4, and the tenth voltage regulator tube Z10 is connected between the gate and source of the fourth NMOS tube N4.

[0093] The second rectifier circuit 20 may further include a seventh capacitor C7 and a tenth capacitor C10; the seventh capacitor C7 is connected between the gate and source of the third PMOS transistor P3, and the tenth capacitor C10 is connected between the gate and source of the fourth NMOS transistor N2. It should be noted that the seventh capacitor C7 and the tenth capacitor C10 have smaller capacitance than the eighth capacitor C8 and the ninth capacitor C9.

[0094] The switch circuit 30 includes a first field effect transistor M1, a second field effect transistor M2, a fifth diode D5 and a twenty-seventh resistor R27;

[0095] The drain of the first field-effect transistor M1 constitutes the first input / output terminal of the switching circuit 30, and is connected to the first detection circuit 40 and the first rectifier circuit 10 to receive the negative electrode of the first direct current or output the negative electrode of the fourth direct current; the drain of the second field-effect transistor M2 constitutes the second input / output terminal of the switching circuit 30, and is connected to the second detection circuit 50 and the second rectifier circuit 20 to receive the negative electrode of the third direct current or output the negative electrode of the second direct current; the gate of the first field-effect transistor M1 is connected to the gate of the second field-effect transistor M2 and the negative electrode of the fifth diode D5, the anode of the fifth diode D5 is connected to the first end of the twenty-seventh resistor R27, and the second end of the twenty-seventh resistor R27 constitutes the control terminal of the switching circuit 30, and is connected to the control circuit 60 to receive the control signal.

[0096] The control circuit 60 includes a microprocessor U3;

[0097] The first universal input and output terminal P1.0 of the microprocessor U3 constitutes the first trigger signal input terminal of the control circuit 60, and is connected to the first trigger circuit 42 to receive the first trigger signal; the second universal input and output terminal P1.2 of the microprocessor U3 constitutes the second trigger signal input terminal of the control circuit 60, and is connected to the second trigger circuit 52 to receive the second trigger signal; the third universal input and output terminal P1.1 of the microprocessor U3 constitutes the control signal output terminal of the control circuit 60, and is connected to the switch circuit 30 to output the control signal.

[0098] The resistor assembly includes a current limiting resistor Rs. A first end of the non-polarity bus isolator is connected in parallel to a first TVS diode TVS1. A second end of the non-polarity bus isolator is connected in parallel to a second TVS diode TVS2.

[0099] The following is combined with the working principle Figure 4 As shown for further explanation:

[0100] Figure 4 The polarity-insensitive bus isolator shown has two operating states.

[0101] In a first operating state, if the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are connected to the positive electrode of the first input voltage, and the drain of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 are connected to the negative electrode of the first input voltage, the first PMOS transistor P1 and the second NMOS transistor N2 are turned on, the source of the first PMOS transistor P1 outputs the positive electrode of the first direct current, and the source of the second NMOS transistor N2 outputs the negative electrode of the first direct current. If the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are connected to the negative electrode of the first input voltage, and the drain of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 are connected to the positive electrode of the first input voltage, the first NMOS transistor N1 and the second PMOS transistor P2 are turned on, the source of the first NMOS transistor N1 outputs the positive electrode of the first direct current, and the source of the second PMOS transistor P2 outputs the negative electrode of the first direct current.

[0102] The third general-purpose input / output terminal P1.1 of the microprocessor U3 outputs a control signal to the gates of the first field-effect transistor M1 and the second field-effect transistor M2. The first field-effect transistor M1 and the second field-effect transistor M2 are turned on, thereby causing the switch circuit 30 to output a second direct current. The voltage of the second direct current is divided by the nineteenth resistor R19 to the twenty-second resistor R22 and applied to the gate of the third PMOS transistor P3. The voltage of the second direct current is also divided by the twenty-third resistor R23 to the twenty-sixth resistor R26 and applied to the gate of the fourth NMOS transistor N4. The third PMOS transistor P3 and the fourth NMOS transistor N4 are turned on. The drain of the third PMOS transistor P3 outputs the positive electrode of the first output voltage, and the drain of the fourth NMOS transistor N4 outputs the negative electrode of the first output voltage. It is worth noting that due to the delay effect of the eighth capacitor C8 and the ninth capacitor C9, the third NMOS transistor N3 and the fourth PMOS transistor P4 are turned off. As a result, the second terminal of the non-polarity bus isolator outputs the first output voltage.

[0103] It can be understood that at the moment the first input voltage is connected, the first direct current is converted into the second direct current after being limited by the current-limiting resistor Rs and input into the second rectifier circuit 20. Due to the voltage-reducing effect of the load connected to the second end, the first transistor Q1 is turned on, so that the second end of the fourth resistor R4 and the first end of the fifth resistor R5 stop outputting the low-level second trigger signal to the second universal input and output terminal P1.2 of the microprocessor U3, and the microprocessor U3 stops outputting the high-level control signal to turn on the first field effect transistor M1 and the second field effect transistor M2, and the switching circuit 30 outputs the second direct current.

[0104] When the load connected to the second end is short-circuited, the second end of the light-receiving semiconductor in the first channel of the first photorelay U1 and the first end of the light-receiving semiconductor in the second channel of the first photorelay U1 are short-circuited, so that the first end of the light-receiving semiconductor in the first channel of the first photorelay U1, the second end of the first resistor R1, and the second end of the second resistor R2 are connected, that is, the second DC power is short-circuited, so that the voltage between the base of the first transistor Q1 and the emitter of the first transistor Q1 is 0, the first transistor Q1 is turned off, the second end of the fourth resistor R4 and the first end of the fifth resistor R5 output a low-level second trigger signal to the second general-purpose input / output terminal P1.2 of the microprocessor U3, and the microprocessor U3 outputs a high-level control signal to turn off the first field-effect transistor M1 and the second field-effect transistor M2. The switch circuit 30 disconnects the output of the second DC power, and the second rectifier circuit 20 stops working and disconnects the first output voltage.

[0105] In the second operating state, if the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3 are connected to the positive electrode of the second input voltage, and the drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 are connected to the negative electrode of the second input voltage, the third PMOS transistor P3 and the fourth NMOS transistor N4 are turned on, the source of the third PMOS transistor P3 outputs the positive electrode of the third direct current, and the source of the fourth NMOS transistor N4 outputs the negative electrode of the third direct current. If the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3 are connected to the negative electrode of the second input voltage, and the drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 are connected to the positive electrode of the second input voltage, the third NMOS transistor N3 and the fourth PMOS transistor P4 are turned on, the source of the third NMOS transistor N3 outputs the positive electrode of the third direct current, and the source of the fourth PMOS transistor P4 outputs the negative electrode of the third direct current.

[0106] The third general-purpose input / output terminal P1.1 of the microprocessor U3 outputs a control signal to the gates of the first field-effect transistor M1 and the second field-effect transistor M2. The first field-effect transistor M1 and the second field-effect transistor M2 are turned on, thereby causing the switch circuit 30 to output a fourth direct current. The voltage of the fourth direct current is applied to the gate of the first PMOS transistor P3 after voltage division by the eleventh resistor R11 to the fourteenth resistor R14. The voltage of the second direct current is also applied to the gate of the second NMOS transistor N2 after voltage division by the fifteenth resistor R15 to the eighteenth resistor R18. The first PMOS transistor P1 and the second NMOS transistor N2 are turned on. The drain of the first PMOS transistor P1 outputs the positive electrode of the second output voltage, and the drain of the second NMOS transistor N2 outputs the negative electrode of the second output voltage. It is worth noting that due to the delay effect of the fourth capacitor C4 and the fifth capacitor C5, the first NMOS transistor N1 and the second PMOS transistor P2 are turned off. As a result, the first terminal of the non-polarity bus isolator outputs the second output voltage.

[0107] It can be understood that at the moment the second input voltage is connected, the third DC power is converted into the fourth DC power after being limited by the current-limiting resistor Rs and input into the first rectifier circuit 10. Due to the voltage-reducing effect of the load connected to the first end, the second transistor Q2 is turned on, so that the second end of the ninth resistor R9 and the first end of the tenth resistor R10 stop outputting the low-level first trigger signal to the second universal input and output terminal P1.2 of the microprocessor U3, and the microprocessor U3 stops outputting the high-level control signal to turn on the first field-effect transistor M1 and the second field-effect transistor M2, and the switching circuit 30 outputs the fourth DC power.

[0108] When the load connected to the first end is short-circuited, the second end of the light-receiving semiconductor in the first channel of the second photorelay U2 and the first end of the light-receiving semiconductor in the second channel of the second photorelay U2 are short-circuited, so that the first end of the light-receiving semiconductor in the first channel of the second photorelay U2, the second end of the sixth resistor R6 and the second end of the seventh resistor R7 are connected, that is, the fourth direct current is short-circuited, so that the voltage between the base of the second transistor Q2 and the emitter of the second transistor Q2 is 0, the second transistor Q2 is turned off, the second end of the ninth resistor R9 and the first end of the tenth resistor R10 output a low-level first trigger signal to the first general input and output terminal P1.0 of the microprocessor U3, and the microprocessor U3 outputs a high-level control signal to turn off the first field-effect transistor M1 and the second field-effect transistor M2. The switch circuit 30 disconnects the output of the fourth direct current, the first rectifier circuit 10 stops working and disconnects the second output voltage.

[0109] An embodiment of the present invention further provides a ring bus system, the ring bus system comprising a controller, a plurality of load devices and a plurality of the above-mentioned non-polarity bus isolators;

[0110] A plurality of the non-polarity bus isolators are connected in series between the first input / output terminal of the controller and the second input / output terminal of the controller, and the load device is connected in parallel between every two of the non-polarity bus isolators.

[0111] It should be noted that n non-polarity bus isolators are connected in series between the first input / output terminal of the controller and the second input / output terminal of the controller. The first input / output terminal of the controller outputs a voltage to the first non-polarity bus isolator. When all load devices are not short-circuited, the second input / output terminal of the controller receives the voltage output by the nth non-polarity bus isolator. In the event of a short circuit in the load between the i-th and i+1-th non-polarity bus isolators, the i-th non-polarity bus isolator stops outputting voltage to the load between the i-th and i+1-th non-polarity bus isolators, thereby preventing the second input / output terminal of the controller from receiving the voltage output by the n-th non-polarity bus isolator. The second input / output terminal of the controller then outputs voltage to the n-th non-polarity bus isolator to power the load between the i+1-th and n-th non-polarity bus isolators. Due to the short circuit in the load between the i-th and i+1-th non-polarity bus isolators, the i+1-th non-polarity bus isolator disconnects the output voltage to the short-circuited load, thereby isolating the short-circuited load (the load between the i-th and i+1-th non-polarity bus isolators). Where n is a positive integer and i is a positive integer less than n.

[0112] The ring bus wiring structure uses bidirectional power supply, with each end connected to the system power supply. This maximizes system operation. Even if a line failure occurs in one direction, current can still flow through the other direction to power the equipment, preventing system failure. The non-polarity design eliminates the need to consider positive and negative line polarity, making installation and wiring more convenient for construction workers and maintenance personnel more convenient for troubleshooting and equipment replacement, effectively reducing construction and maintenance costs and improving work efficiency.

[0113] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0114] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A non-polarity bus isolator, characterized in that: It has a first end and a second end, and includes a first rectifier circuit, a switch circuit, and a second rectifier circuit; The first end, the first rectifier circuit, the switch circuit, the second rectifier circuit and the second end are sequentially connected in series; The non-polarity bus isolator further comprises: a first detection circuit connected to the first end, configured to output a first trigger signal in response to a short circuit of the first end; a second detection circuit connected to the second end, configured to output a second trigger signal in response to a short circuit of the second end; The control circuit, the first detection circuit and the second detection circuit are used to control the switch circuit to be disconnected in response to the first trigger signal or the second trigger signal.

2. The non-polarity bus isolator according to claim 1, wherein: The first rectifier circuit is configured to receive a first input voltage from the first end and rectify the first input voltage to output a first direct current; The switch circuit is configured to transmit the first direct current in response to a control signal to output a second direct current; The second rectifier circuit is used to rectify the second direct current to output a first output voltage to the second end; The second detection circuit includes: a second short-circuit circuit connected to the second end, the switch circuit, and the second rectifier circuit, for short-circuiting the second DC power in response to the second end being short-circuited; a second trigger circuit connected to the control circuit, the switch circuit and the second rectifier circuit, and configured to output the second trigger signal in response to the second DC power being short-circuited; The control circuit is further configured to disconnect the control signal in response to the second trigger signal, so as to cause the switch circuit to disconnect the output of the second direct current and the second rectifier circuit to disconnect the output of the first output voltage.

3. The non-polarity bus isolator according to claim 2, characterized in that: The second short circuit includes a first photorelay, a first resistor and a second resistor; The anode of the light-emitting diode in the first channel of the first photorelay is connected to the first end of the first resistor, the anode of the light-emitting diode in the second channel of the first photorelay is connected to the first end of the second resistor, and the cathode of the light-emitting diode in the first channel of the first photorelay and the cathode of the light-emitting diode in the second channel of the first photorelay are connected to a power ground. The second end of the first resistor, the second end of the second resistor, and the second end of the light-receiving semiconductor in the second channel of the first photorelay are connected and together constitute a first controlled end of the second short-circuit circuit, which is connected to the second trigger circuit, the switch circuit, and the second rectifier circuit to be connected to the negative electrode of the second direct current; The first end of the light-receiving semiconductor in the first channel of the first photorelay constitutes the second controlled end of the second short-circuit circuit, and is connected to the second trigger circuit, the switch circuit and the second rectifier circuit to be connected to the positive electrode of the second direct current; The second end of the light-receiving semiconductor in the first channel of the first photorelay constitutes the first control end of the second short-circuit circuit, and is connected to the second rectifier circuit and the second end of the non-polarity bus isolator to access the positive electrode of the first output voltage; The first end of the light-receiving semiconductor in the second channel of the first photorelay constitutes the second control end of the second short-circuit circuit, which is connected to the second rectifier circuit and the second end of the polarity-free bus isolator to access the negative electrode of the first output voltage.

4. The non-polarity bus isolator according to claim 2, wherein: The second trigger circuit includes a first triode, a first voltage regulator, a first diode, a second diode, a third resistor, a fourth resistor and a fifth resistor; The negative electrode of the first voltage regulator tube constitutes the first input end of the second trigger circuit, and is connected to the second short circuit, the switch circuit and the second rectifier circuit to receive the positive electrode of the second direct current; The cathode of the first diode constitutes the second input end of the second trigger circuit, and is connected to the second short circuit, the switch circuit and the second rectifier circuit to be connected to the cathode of the second direct current; The anode of the first voltage regulator is connected to the emitter of the first transistor, the base of the first transistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the anode of the first diode, the collector of the first transistor is connected to the anode of the second diode, and the cathode of the second diode is connected to the first end of the fourth resistor; The second end of the fourth resistor and the first end of the fifth resistor are connected to form an output end of the second trigger circuit, which is connected to the control circuit to output the second trigger signal; The second end of the fifth resistor is connected to the power ground.

5. The non-polarity bus isolator according to claim 1, wherein: The second rectifier circuit is configured to receive a second input voltage from the second end and rectify the second input voltage to output a third direct current; The switch circuit is configured to transmit the third direct current in response to a control signal to output a fourth direct current; The first rectifier circuit is used to rectify the fourth direct current to output a second output voltage to the first end; The first detection circuit includes: a first short-circuit circuit connected to the first end, the switch circuit, and the first rectifier circuit, configured to short-circuit the fourth direct current in response to the first end being short-circuited; a first trigger circuit connected to the control circuit, the switch circuit, and the first rectifier circuit, and configured to output the first trigger signal in response to the fourth DC power being short-circuited; The control circuit is further configured to disconnect the control signal in response to the first trigger signal, so as to cause the switch circuit to disconnect the output of the fourth direct current and cause the first rectifier circuit to disconnect the output of the second output voltage.

6. The non-polarity bus isolator according to claim 5, characterized in that: The first short circuit includes a second photorelay, a sixth resistor and a seventh resistor; The anode of the light-emitting diode in the first channel of the second photorelay is connected to the first end of the sixth resistor, the anode of the light-emitting diode in the second channel of the second photorelay is connected to the first end of the seventh resistor, and the cathode of the light-emitting diode in the first channel of the second photorelay and the cathode of the light-emitting diode in the second channel of the second photorelay are connected to the power ground. The second end of the sixth resistor, the second end of the seventh resistor, and the second end of the light-receiving semiconductor in the second channel of the second photorelay are connected and together constitute a first controlled end of the first short-circuit circuit, which is connected to the first trigger circuit, the switch circuit, and the first rectifier circuit to be connected to the negative electrode of the fourth direct current; The first end of the light-receiving semiconductor in the first channel of the second photorelay constitutes the second controlled end of the first short-circuit circuit, and is connected to the first trigger circuit, the switch circuit and the first rectifier circuit to be connected to the positive electrode of the fourth direct current; The second end of the light-receiving semiconductor in the first channel of the second photorelay constitutes the first control end of the first short-circuit circuit, and is connected to the first rectifier circuit and the first end of the non-polarity bus isolator to access the positive electrode of the second output voltage; The first end of the light-receiving semiconductor in the second channel of the second photorelay constitutes the second control end of the first short-circuit circuit, and is connected to the first rectifier circuit and the first end of the non-polarity bus isolator to access the negative electrode of the second output voltage.

7. The non-polarity bus isolator according to claim 5, characterized in that: The first trigger circuit includes a second triode, a second voltage-stabilizing diode, a third diode, a fourth diode, an eighth resistor, a ninth resistor, and a tenth resistor; The negative electrode of the second voltage regulator tube constitutes the first input end of the first trigger circuit, is connected to the first short circuit, the switch circuit and the first rectifier circuit, and is connected to the positive electrode of the fourth direct current; The cathode of the third diode constitutes the second input end of the first trigger circuit, is connected to the first short circuit, the switch circuit and the first rectifier circuit, and is connected to the cathode of the fourth direct current; The anode of the second voltage-stabilizing diode is connected to the emitter of the second transistor, the base of the second transistor is connected to the first end of the eighth resistor, the second end of the eighth resistor is connected to the anode of the third diode, the collector of the second transistor is connected to the anode of the fourth diode, and the cathode of the fourth diode is connected to the first end of the ninth resistor; The second end of the ninth resistor and the first end of the tenth resistor are connected to form an output end of the first trigger circuit, and are connected to the control circuit to output the first trigger signal; The second end of the tenth resistor is connected to the power ground.

8. The non-polarity bus isolator according to claim 1, wherein: Also includes: A resistor component is connected in parallel with the switch circuit and is connected to the first rectifier circuit and the second rectifier circuit.

9. The non-polarity bus isolator according to claim 1, wherein: The first rectifier circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a fourth capacitor, a fifth capacitor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and an eighteenth resistor; The drain of the first PMOS transistor, the drain of the first NMOS transistor, the first end of the fifteenth resistor, and the first end of the seventeenth resistor are connected to form a first positive input and output end of the first rectifier module, which is connected to the first end of the non-polarity bus isolator to access the A pole of the first input voltage or output the positive pole of the second output voltage; The drain of the second PMOS transistor, the drain of the second NMOS transistor, the first end of the eleventh resistor, and the first end of the thirteenth resistor are connected to form a first negative input and output end of the first rectifier module, and are connected to the first end of the non-polarity bus isolator to access the B pole of the first input voltage or output the negative pole of the second output voltage; The source of the first PMOS transistor, the source of the second PMOS transistor, the first end of the fifth capacitor, the first end of the twelfth resistor, and the first end of the sixteenth resistor are connected to form a second positive input and output end of the first rectifier module, which is connected to the switch circuit and the first detection circuit to output the positive electrode of the first direct current or be connected to the positive electrode of the fourth direct current; The source of the first NMOS transistor, the source of the second NMOS transistor, the first end of the fourth capacitor, the first end of the fourteenth resistor, and the first end of the eighteenth resistor are connected to form a second negative input and output end of the first rectifier module, which is connected to the switching circuit and the first detection circuit to output the negative electrode of the first direct current or be connected to the negative electrode of the fourth direct current; The gate of the first PMOS transistor is connected to the second end of the eleventh resistor and the second end of the twelfth resistor, the gate of the second PMOS transistor is connected to the second end of the fifth capacitor, the second end of the fifteenth resistor, and the second end of the sixteenth resistor, the gate of the first NMOS transistor is connected to the second end of the fourth capacitor, the second end of the thirteenth resistor, and the second end of the fourteenth resistor, and the gate of the second NMOS transistor is connected to the second end of the seventeenth resistor and the second end of the eighteenth resistor; The pole A of the first input voltage and the pole B of the first input voltage have opposite polarities and are respectively the positive pole of the first input voltage and the negative pole of the first input voltage.

10. The non-polarity bus isolator according to claim 1, wherein: The second rectifier circuit includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, an eighth capacitor, a ninth capacitor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, and a twenty-sixth resistor; The drain of the third PMOS transistor, the drain of the third NMOS transistor, the first end of the twenty-third resistor, and the first end of the twenty-fifth resistor are connected to form a first positive input and output end of the second rectifier module, and are connected to the second end of the non-polarity bus isolator to access the A pole of the second input voltage or output the positive pole of the first output voltage; The drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, the first end of the nineteenth resistor, and the first end of the twenty-first resistor are connected to form a first negative input and output end of the second rectifier module, and are connected to the second end of the non-polarity bus isolator to access the B pole of the second input voltage or output the negative pole of the first output voltage; The source of the third PMOS transistor, the source of the fourth PMOS transistor, the first end of the ninth capacitor, the first end of the twentieth resistor, and the first end of the twenty-fourth resistor are connected to form a second positive input and output end of the second rectifier module, which is connected to the switch circuit and the second detection circuit to output the positive electrode of the third direct current or be connected to the positive electrode of the second direct current; The source of the third NMOS transistor, the source of the fourth NMOS transistor, the first end of the eighth capacitor, the first end of the twenty-second resistor, and the first end of the twenty-sixth resistor are connected to form a second negative input and output end of the second rectifier module, which is connected to the switching circuit and the second detection circuit to output the negative electrode of the third direct current or be connected to the negative electrode of the second direct current; The gate of the third PMOS transistor is connected to the second end of the nineteenth resistor and the second end of the twentieth resistor, the gate of the fourth PMOS transistor is connected to the second end of the ninth capacitor, the second end of the twenty-third resistor, and the second end of the twenty-fourth resistor, the gate of the third NMOS transistor is connected to the second end of the eighth capacitor, the second end of the twenty-first resistor, and the second end of the twenty-second resistor, and the gate of the fourth NMOS transistor is connected to the second end of the twenty-fifth resistor and the second end of the twenty-sixth resistor; The pole A of the second input voltage and the pole B of the second input voltage have opposite polarities and are respectively the positive pole of the second input voltage and the negative pole of the second input voltage.

11. A ring bus system, characterized in that: The ring bus system comprises a controller, a plurality of load devices and a plurality of polarity-free bus isolators according to any one of claims 1 to 10; A plurality of the non-polarity bus isolators are connected in series between the first input / output terminal of the controller and the second input / output terminal of the controller, and the load device is connected in parallel between every two of the non-polarity bus isolators.

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