Photoelectric packaging structure

Abstract

The invention provides a photoelectric packaging structure, and relates to the field of semiconductor packaging, the photoelectric packaging structure comprises an organic substrate with a groove and a glass substrate, a glass plate is inserted in the groove and is electrically connected with the organic substrate, the glass substrate is also electrically connected with a PIC chip, a first EIC chip, a second EIC chip and an ASIC chip, and the first EIC chip, the second EIC chip and the ASIC chip are electrically connected with the glass substrate. The first EIC chip, the second EIC chip, the PIC chip and the ASIC chip are arranged on the glass substrate, a heat dissipation enclosure is fixed on the organic substrate, the heat dissipation enclosure is arranged on the periphery of the glass substrate in a surrounding mode, and the first EIC chip, the second EIC chip, the PIC chip and the ASIC chip abut against the glass substrate. Therefore, the wiring space of the organic substrate on the XY plane is saved, the technical advantages of low loss and narrow line width of the glass substrate in high-frequency signal transmission are brought into full play, and the packaging size under the same signal density is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a photoelectric packaging structure. Background Art

[0002] In the current field of optoelectronic integrated packaging technology, the system-level packaging architecture generally includes three functional modules: photonic integrated circuits (PICs), electronic integrated circuits (EICs), and application-specific integrated circuits (ASICs). The PIC module completes the conversion and processing of optical signals into electrical signals, the EIC module implements signal preamplification and drive control, and the ASIC module is responsible for terminal functions. However, existing technologies still have the following technical bottlenecks in three-dimensional heterogeneous integrated packaging:

[0003] First, traditional organic substrate interconnect solutions have significant system scalability defects: the planar wiring architecture causes the XY plane size of the package to continue to expand, which not only lengthens the signal transmission path and causes signal integrity degradation, but also the ultra-large silicon interposer used to compensate for signal integrity has a nonlinear growth in manufacturing cost and process complexity, and yield control faces severe challenges.

[0004] Second, the existing chip stacking solution leads to a significant increase in heat flux density, while the traditional vertical interconnect structure has a limited heat conduction path, resulting in a significant heat accumulation effect. Under continuous operation, the chip junction temperature rise exceeds the design threshold, which not only accelerates the aging process of materials but also leads to an aggravation of electromigration effects, putting system reliability under severe test. Summary of the Invention

[0005] The present invention provides an optoelectronic packaging structure, the purpose of which is to solve the problem of increased XY plane size and deteriorated signal integrity caused by a wiring architecture in optoelectronic integrated packaging.

[0006] In order to achieve the above-mentioned object, an embodiment of the present invention provides an optoelectronic packaging structure, comprising:

[0007] An organic substrate, wherein a groove is provided in the middle of the organic substrate;

[0008] A glass substrate is inserted into the groove, and the organic substrate and the glass substrate are electrically connected in the groove;

[0009] A PIC chip, used for connecting to an optical fiber, wherein the PIC chip is electrically connected to a side surface of the glass substrate;

[0010] A first EIC chip and a second EIC chip are electrically connected to the other side surface of the glass substrate respectively;

[0011] an ASIC chip, electrically connected to the organic substrate;

[0012] A heat dissipation enclosure is fixed on the organic substrate and is arranged around the glass substrate, and presses the first EIC chip, the second EIC chip, the PIC chip and the ASIC chip against the glass substrate.

[0013] Preferably, a first gold finger is provided on the sidewall of the groove, and a second gold finger is provided on the glass substrate, and the first gold finger contacts the second gold finger to achieve electrical connection between the organic substrate and the glass substrate.

[0014] Preferably, the organic substrate is grooved to form the groove, and the groove is metallized to form a copper layer, and the copper layer is nickel-plated and gold-plated to form the first gold finger.

[0015] Preferably, the glass substrate is metallized to form a second gold finger, and a gold layer is deposited on the second gold finger.

[0016] Preferably, a copper layer is deposited on the seed layer of the glass substrate by electroplating or sputtering, a photoresist is coated on the surface of the copper layer and patterned by photolithography, the copper layer is etched to form a second gold finger, and the gold layer is formed on the second gold finger by electroplating or chemical plating.

[0017] Preferably, the PIC chip, the first EIC chip and the second EIC chip are electrically connected to the glass substrate respectively through bumps.

[0018] Preferably, heat-conducting materials are filled between the PIC chip, the first EIC chip, the second EIC chip and the ASIC chip and the heat dissipation enclosure to form a heat-conducting layer.

[0019] Preferably, springs are provided on both sides of the glass substrate, the other ends of the springs are connected to the heat dissipation enclosure, and the springs are in a stretched state.

[0020] Preferably, the heat dissipation enclosure is made of copper.

[0021] Preferably, the grooves of the organic substrate and the glass substrate are filled with underfill to fix the mechanical connection between the organic substrate and the glass substrate.

[0022] The above solution of the present invention has the following beneficial effects:

[0023] This application effectively achieves three-dimensional integration through a vertical interconnection architecture between the organic and glass substrates. This not only saves wiring space on the organic substrate in the XY plane, but also fully leverages the glass substrate's technical advantages of low loss and narrow linewidth in high-frequency signal transmission, significantly reducing the package size for the same signal density. Furthermore, the composite structure formed by the glass and organic substrates, combined with the heat dissipation enclosure and thermal conductive layer design, not only improves high-frequency signal integrity, but also enhances heat dissipation efficiency and structural reliability.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a longitudinal sectional view of the present invention;

[0026] Figure 2 yes Figure 1 A magnified schematic diagram of part A;

[0027] Figure 3 This is a top view of the present invention (with chips omitted).

[0028] [Description of Reference Numerals]

[0029] 10-Organic substrate, 11-First gold finger, 12-Underfill,

[0030] 20-glass substrate, 21-second gold finger, 22-spring,

[0031] 30-PIC chip, 31-optical fiber,

[0032] 40-first EIC chip, 41-bump, 42-thermal conductive material,

[0033] 50-Second EIC chip,

[0034] 60-ASIC chip,

[0035] 70-Heat dissipation enclosure. DETAILED DESCRIPTION

[0036] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 1-Figure 3 As shown, an embodiment of the present invention provides an optoelectronic packaging structure, including an organic substrate 10 and a glass substrate 20, wherein a groove is provided in the middle of the organic substrate 10 and a solder ball is provided at the bottom. The aforementioned glass substrate 20 is inserted into the groove, and the glass substrate 20 and the organic substrate 10 are electrically connected in the groove to transmit signals.

[0038] The present application also includes a PIC chip 30, a first EIC chip 40, a second EIC chip 50, and an ASIC chip 60, wherein the PIC chip 30 is used to connect to the optical fiber 31 to obtain an optical signal. The PIC chip 30 is electrically connected to one side of the glass substrate 20, so that the PIC chip 30 converts the optical signal into an electrical signal and transmits it to the glass substrate 20. The first EIC chip 40 and the second EIC chip 50 are arranged on the other side of the glass substrate 20, and the first EIC chip 40 and the second EIC chip 50 are located on the same side of the glass substrate 20. The first EIC chip 40 and the second EIC chip 50 are respectively electrically connected to the glass substrate 20. The ASIC chip 60 is electrically connected to the organic substrate 10, and the ASIC chip 60 and the PIC chip 30 are located on the same side of the glass substrate 20.

[0039] A heat dissipation enclosure 70 is further provided on the upper surface of the glass substrate 20 and is fixed to the organic substrate 10. The heat dissipation enclosure 70 surrounds the glass substrate 20. Under the action of the heat dissipation enclosure 70, the PIC chip 30, the first EIC chip 40, the second EIC chip 50, and the ASIC chip 60 are tightly abutted against the glass substrate 20.

[0040] In the present application, the Z-direction space is utilized to realize the vertical interconnection architecture of the organic substrate 10 and the glass substrate 20, which not only reduces the size requirements of the substrate in the XY plane, but also utilizes the advantages of the narrow line width and loss resistance of the glass substrate 20, so that the present application has a smaller package size under the same signal density. The heat dissipation enclosure 70 is arranged around the glass substrate 20 and realizes surface contact with each chip, making full use of the heat dissipation area of ​​the heat dissipation enclosure 70. At the same time, the heat dissipation enclosure 70 plays a certain fixing and limiting role, which is conducive to each chip maintaining the corresponding position, reducing the strength requirements of the mechanical connection between each chip and the glass substrate 20 or the organic substrate 10.

[0041] Furthermore, first gold fingers 11 are provided on opposing sidewalls of the groove, and second gold fingers 21 are provided on the glass substrate 20. The first and second gold fingers 11, 21 contact each other within the groove to achieve electrical connection between the organic substrate 10 and the glass substrate 20. In this technical solution, the first and second gold fingers 11, 21 are interconnected within the groove, fully utilizing the height of the organic substrate 10 and further reducing the package height in the Z direction.

[0042] Specifically, the first gold finger 11 is manufactured in the following manner: the organic substrate 10 is grooved to form the aforementioned groove, the depth of which is less than the thickness of the organic substrate 10 , the groove is metallized to form a copper layer, and the copper layer is nickel-plated and gold-plated to form the first gold finger 11 .

[0043] In this embodiment, the metallization process is carried out using conventional techniques, such as electroplating copper or chemical copper plating. The purpose of nickel plating is to serve as a barrier between the gold layer and the copper layer, effectively preventing the migration of copper ions and improving the stability of the gold finger. The purpose of gold plating is to improve the conductivity and wear resistance of the gold finger.

[0044] The aforementioned second gold finger 21 is formed by metallizing the glass substrate 20, and a gold layer is also deposited on the second gold finger 21. Specifically, a copper layer is deposited on the seed layer of the glass substrate 20 by electroplating or sputtering, and a photoresist is applied to the surface of the copper layer and patterned by photolithography. The copper layer is then etched to form the second gold finger 21. After the second gold finger 21 is cleaned, a gold layer is formed on the second gold finger 21 by electroplating or chemical plating.

[0045] Preferably, after the glass substrate 20 is inserted into the organic substrate 10 , an underfill is filled in the groove to enhance the mechanical connection between the organic substrate 10 and the glass substrate 20 .

[0046] The aforementioned PIC chip 30, first EIC chip 40, and second EIC chip 50 are electrically connected to the glass substrate 20 via bumps 41. Bumps 41 provide both electrical connection and reliable mechanical support. The aforementioned ASIC chip 60 is electrically connected to the organic substrate 10 via a flip-chip arrangement. Preferably, the ASIC chip 60 is also electrically connected via bumps 41.

[0047] Preferably, a thermally conductive material 42 is applied to the surfaces of the PIC chip 30, the first EIC chip 40, the second EIC chip 50, and the ASIC chip 60 that contact the heat dissipation enclosure 70, thereby forming a thermally conductive layer between each chip and the heat dissipation enclosure 70. The thermally conductive layer can transfer heat generated by each chip during operation to the heat dissipation enclosure 70, eliminating air gaps between the heat dissipation enclosure 70 and each chip, thereby further optimizing the heat dissipation effect of the packaging structure.

[0048] In this application, springs 22 are also provided. These springs 22 are positioned on both sides of the glass substrate 20, and the number of springs 22 is equal to provide equal elastic force on both sides of the glass substrate 20. In this application, two springs 22 are provided, located on the same side of the glass as the chip. One end of the spring 22 is fixedly connected to the glass substrate 20, and the other end is fixedly connected to the heat dissipation enclosure 70. Both springs 22 are in a stretched state. When the springs 22 are installed, they tend to contract. The adaptive alignment of the two springs 22 helps maintain the glass substrate 20 in an upright position, thereby preventing poor contact between the first and second gold fingers 11, 21. This allows the resulting package structure to adapt to various vibration environments, significantly increasing the package's applicability. Furthermore, since traditional molding compounds are prone to delamination during temperature cycling, the redundant fixing mechanism of the underfill 12 and the springs 22 complement each other, reducing the negative effects of thermal stress. Even when the underfill 12 ages, the force of the springs 22 can still maintain the reliability of the gold finger contact.

[0049] Preferably, in the present application, the heat dissipation enclosure 70 and the organic substrate 10 are bonded together by adhesive, the heat dissipation enclosure 70 is made of copper material, and the height of the heat dissipation enclosure 70 is higher than the height of the glass substrate 20 .

[0050] In another embodiment of the present application, a window is opened on the surface of the organic substrate 10 in a local area connected to the heat dissipation enclosure 70. The heat dissipation enclosure 70 is soldered to the organic substrate 10 using solder paste, so that the heat dissipation enclosure 70 is connected to the GND of the organic substrate 10, thereby achieving the effect of grounding the heat dissipation enclosure; at the same time, a metal mesh is installed on the upper surface of the heat dissipation enclosure 70, so that the heat dissipation enclosure 70 produces a Faraday cage effect, which has a good electromagnetic shielding effect.

[0051] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. An optoelectronic packaging structure, characterized in that: include: An organic substrate (10), wherein a groove is provided in the middle of the organic substrate (10); A glass substrate (20) is inserted into the groove, and the organic substrate (10) and the glass substrate (20) are electrically connected in the groove; A PIC chip (30) for connecting to an optical fiber (31), wherein the PIC chip (30) is electrically connected to a side surface of the glass substrate (20); A first EIC chip (40) and a second EIC chip (50) are electrically connected to the other side surface of the glass substrate (20), respectively; An ASIC chip (60) electrically connected to the organic substrate (10); A heat dissipation enclosure (70) is fixed on the organic substrate (10), and the heat dissipation enclosure (70) is arranged around the glass substrate (20) and presses the first EIC chip (40), the second EIC chip (50), the PIC chip (30) and the ASIC chip (60) against the glass substrate (20).

2. The optoelectronic packaging structure according to claim 1, wherein: A first gold finger (11) is provided on the side wall of the groove, a second gold finger (21) is provided on the glass substrate (20), and the first gold finger (11) contacts the second gold finger (21) to achieve electrical connection between the organic substrate (10) and the glass substrate (20).

3. The optoelectronic packaging structure according to claim 2, wherein: The organic substrate (10) is grooved to form the groove, and a metallization process is performed on the groove to form a copper layer. The copper layer is subjected to nickel plating and gold plating processes to form a first gold finger (11).

4. The optoelectronic packaging structure according to claim 2, wherein: The glass substrate (20) is metallized to form a second gold finger (21), and a gold layer is deposited on the second gold finger (21).

5. The optoelectronic packaging structure according to claim 4, wherein: A copper layer is deposited on the seed layer of the glass substrate (20) by electroplating or sputtering, a photoresist is coated on the surface of the copper layer and photolithographic patterning is performed, the copper layer is etched to form a second gold finger (21), and the gold layer is formed on the second gold finger (21) by electroplating or chemical plating.

6. The optoelectronic packaging structure according to claim 1, wherein: The PIC chip (30), the first EIC chip (40) and the second EIC chip (50) are electrically connected to the glass substrate (20) via bumps (41).

7. The optoelectronic packaging structure according to claim 1, wherein: A heat-conducting material (42) is filled between the PIC chip (30), the first EIC chip (40), the second EIC chip (50), and the ASIC chip (60) and the heat dissipation enclosure (70) to form a heat-conducting layer.

8. The optoelectronic packaging structure according to claim 1, wherein: Springs (22) are also provided on both sides of the glass substrate (20), and the other ends of the springs (22) are connected to the heat dissipation enclosure (70), and the springs (22) are in a stretched state.

9. The optoelectronic packaging structure according to claim 1, wherein: The heat dissipation enclosure (70) is made of red copper.

10. The optoelectronic packaging structure according to claim 1, wherein: The organic substrate (10) and the glass substrate (20) are filled with an underfill (12) at the groove to fix the mechanical connection between the organic substrate (10) and the glass substrate (20).

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