Backside sealing of semiconductor substrate

Abstract

Methods and apparatus for backside sealing of a semiconductor substrate are provided. In some embodiments, such techniques may include delivering a first set of one or more processing gases to a first processing chamber of a deposition apparatus, the first processing chamber having a semiconductor substrate placed therein; applying a first processing temperature in the presence of the plasma to form a first material layer on the back side of the semiconductor substrate; delivering a second set of one or more process gases to the first process chamber; and applying a first processing temperature in the presence of plasma to form a second material layer on the first material layer on the back side of the semiconductor substrate; and applying a second process temperature to cause an annealing process to occur to collectively form a material stack sealing the back side of the semiconductor substrate.

Description

Background Art

[0001] In semiconductor processing, auto-doping is a serious problem that arises during epitaxial deposition processes. During this process, doping heteroatoms can diffuse out of the backside of the substrate and migrate around the edge of the substrate, resulting in unintentional over-doping on the edge and front side of the substrate. Current solutions for mitigating auto-doping include extensive procedures through various temperatures, processes, and substrate positions, involving complex procedures that require repositioning (including flipping), resulting in high costs and low efficiency. It would be desirable to use a new solution for mitigating auto-doping using a tool that eliminates many of the complexities and even improves other aspects of using the tool.

[0002] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. To the extent described in this background section, the work of the inventors, as well as aspects of the description that may not qualify as prior art at the time of filing, are neither explicitly nor implicitly admitted to be prior art against the present disclosure. Summary of the Invention

[0003] In one aspect of the present disclosure, an apparatus configured for sealing the backside of a semiconductor substrate is disclosed. In some embodiments, the apparatus may include: one or more process chambers; a showerhead configured to deliver one or more process gases to the backside of a semiconductor substrate in at least one of the one or more process chambers; and a controller coupled to the showerhead and the one or more process chambers and configured to: deliver a first set of one or more process gases to a first process chamber having a semiconductor substrate; apply a first process temperature of 200-400° C. in the presence of plasma to form a silicon oxide (SiO2) layer on the backside of the semiconductor substrate; deliver a second set of one or more process gases to the first process chamber; apply a first process temperature of 200-400° C. in the presence of plasma to form an amorphous silicon layer on the SiO2 layer on the backside of the semiconductor substrate; and after forming the amorphous silicon layer, apply a second process temperature of at least 700° C. to cause an annealing process to occur, the annealing process comprising crystallizing the amorphous silicon layer to form a polycrystalline silicon layer to collectively form a material stack that seals the backside of the semiconductor substrate.

[0004] In another aspect of the present disclosure, an apparatus is disclosed. In some embodiments, the apparatus may include: a first process chamber configured to receive a semiconductor substrate; a showerhead configured to deliver one or more process gases to a backside of the semiconductor substrate in the first process chamber; and a controller coupled to at least the showerhead and the first process chamber and configured to: deliver a first set of one or more process gases to the first process chamber having the semiconductor substrate; apply a first process temperature of 200-400° C. in the presence of plasma to form an amorphous silicon layer on the backside of the semiconductor substrate; deliver a second set of one or more process gases to the first process chamber; apply a first process temperature of 200-400° C. in the presence of plasma to form a silicon oxide (SiO2) layer on the amorphous silicon layer on the backside of the semiconductor substrate; and, after forming the SiO2 layer, apply a second process temperature of at least 700° C. to cause an annealing process to occur, the annealing process comprising crystallizing the amorphous silicon layer to form a polycrystalline silicon layer to collectively form a material stack that seals the backside of the semiconductor substrate.

[0005] In another aspect of the present disclosure, a method for sealing the backside of a semiconductor substrate is disclosed. In some embodiments, the method may include: delivering a first set of one or more process gases to a first process chamber of a deposition apparatus, wherein a semiconductor substrate is disposed in the first process chamber; applying a first process temperature in the presence of a plasma to form a first material layer on the backside of the semiconductor substrate; delivering a second set of one or more process gases to the first process chamber; applying the first process temperature in the presence of a plasma to form a second material layer on the first material layer on the backside of the semiconductor substrate; and, after forming the second material layer, applying a second process temperature to cause an annealing process to occur, wherein the annealing process includes causing crystallization of the first material layer or the second material layer to collectively form a material stack that seals the backside of the semiconductor substrate.

[0006] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B An exemplary doping profile is shown, wherein an epitaxial process is applied to a semiconductor substrate to epitaxially grow a film.

[0008] Figure 2 An exemplary process flow for a conventional method of depositing a backside sealing layer without backside deposition is shown.

[0009] Figure 3 An exemplary process flow for a method of depositing a backside sealing layer using backside deposition according to certain embodiments is shown.

[0010] Figure 4Depicted are examples of an enhanced backside sealing layer formed on a surface of a semiconductor substrate according to certain embodiments.

[0011] Figure 5 Another exemplary process flow for a method of depositing a backside sealing layer using backside deposition according to certain embodiments is shown.

[0012] Figure 6 is a flow chart of an example of a method for backside sealing of a semiconductor substrate according to certain embodiments.

[0013] Figure 7 and Figure 8 A block diagram of an exemplary substrate processing system according to certain embodiments herein is shown.

[0014] Figure 9A An exemplary cross section of the edge of a spray-base is shown.

[0015] Figure 9B A top view of an exemplary carrier ring is shown.

[0016] Figure 10 is a schematic illustration of a cross-section of a processing system for depositing a film on the backside of a semiconductor substrate according to certain embodiments herein.

[0017] Figure 11 is a schematic diagram of an exemplary processing system that can be used to perform the methods described herein. DETAILED DESCRIPTION

[0018] The following terms are used throughout this manual:

[0019] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. One of ordinary skill in the art understands that the term "partially fabricated integrated circuit" can refer to a semiconductor wafer on which any of the many stages of fabricating an integrated circuit are performed. Wafers or substrates used in the semiconductor device industry are typically 200 mm, 300 mm, or 450 mm in diameter. Examples of wafer materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various items such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components, such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, and the like. The workpieces can be of various shapes, sizes, and materials.

[0020] As used herein, a “semiconductor device manufacturing operation” is an operation performed during the semiconductor device manufacturing process. Typically, the entire manufacturing process includes multiple semiconductor device manufacturing operations, each of which is performed in its own semiconductor manufacturing tool, such as a plasma reactor, an electroplating cell, a chemical mechanical planarization tool, a wet etching tool, etc. Categories of semiconductor device manufacturing operations include subtractive processes, such as etching processes and planarization processes, and material additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of an etching process, a substrate etching process includes a process for etching a mask layer, or more generally, a process for etching any material layer previously deposited on and / or otherwise present on the substrate surface. Such etching processes can etch layer stacks in a substrate.

[0021] In the context of this disclosure, "epitaxial" or "epitaxial" may refer to a method of fabrication to create a crystalline layer upon which a semiconductor device is built. An "epitaxial process," "epitaxial deposition process," or "epitaxial growth process" may refer to a process that involves forming a layer of material (e.g., a film) at high temperatures and may be an example of the semiconductor device fabrication operations described above.

[0022] "Fabrication equipment" refers to equipment in which a manufacturing process is performed. Fabrication equipment typically has a processing chamber in which a workpiece is located during processing. Typically, when used, the fabrication equipment performs one or more semiconductor device fabrication operations. Examples of production equipment used in semiconductor device fabrication include deposition reactors, such as electroplating cells, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive process reactors, such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0023] "Silicon oxide" herein refers to any and all stoichiometric possibilities including SixOy, including integer values ​​of x and y as well as non-integer values ​​of x and y. For example, "silicon oxide" includes silicon oxide having the formula SiO n where 1≤n≤2, where n can be an integer or non-integer value. "Silicon oxide" may include substoichiometric compounds such as SiO 1.8 "Silicon oxide" also includes silicon dioxide (SiO2) and silicon monoxide (SiO). "Silicon oxide" also includes both natural and synthetic variants and any and all crystalline and molecular structures including tetrahedral coordination of oxygen atoms around a central silicon atom. "Silicon oxide" also includes amorphous silicon oxide and silicates.

[0024] Among various approaches, the materials (e.g., thin films) in the layer stack can be deposited by chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or by direct metal deposition (DMD). These examples are not intended to be limiting. Different deposition techniques can be used for different ends. For example, deposition may be useful whenever wafer stress and / or bowing is caused by the presence of material on the front side of the wafer. Note that different deposition techniques may be associated with or affected by different temperatures, pressures, precursors, or other deposition processes, conditions, or recipes. For example, certain deposition techniques may overlap in the temperature range that can be used, which may be advantageously used to strategically deposit multiple layers simultaneously or only certain layers.

[0025] Semiconductor substrates can be doped with elements (such as phosphorus atoms) to increase the substrate's electrical conductivity. More specifically, the use of such dopants can improve the conductivity of silicon in silicon-based wafers. Many downstream applications or uses of the wafers may involve high temperatures, such as the formation of epitaxial layers on the wafer surface. However, high temperatures can cause dopants to diffuse out of the wafer. This is a problem that the semiconductor industry is well aware of and is known as "autodoping."

[0026] One way to prevent dopant release is to deposit a backside sealing layer on the backside of the wafer. Typically, a silicon-based film, such as silicon oxide (SiO2), silicon nitride (SiN), or a polysilicon film, can be deposited to seal the backside of the wafer. However, conventional processes for depositing a backside sealing layer are expensive, complex, lengthy, and inefficient. In particular, multiple deposition techniques requiring different temperatures and wafer orientations (with the wafer facing down or facing up) increase complexity and inefficiency.

[0027] To address this issue in conventional methods, methods and apparatus for depositing an enhanced backside sealing layer directly on the backside of a wafer are described herein. These methods do not require flipping the wafer between different deposition techniques. In fact, the wafer can remain stationary in a processing environment (e.g., a processing chamber or station of a deposition apparatus). In certain embodiments, the enhanced backside sealing layer can include a stack of SiO2 and amorphous silicon (a-Si), which can be formed in a single process using a deposition apparatus configured for backside deposition, for example, using PECVD at the same processing temperature, which will be described in more detail herein. This simplified approach effectively reduces the cost and time involved and improves the efficiency of providing a backside sealing layer to the wafer. Wafer backside sealing

[0028] Figure 1AAn exemplary doping profile 100 is shown, in which an epitaxial process is applied to a semiconductor substrate 102 to achieve epitaxial growth of a film 104. In some examples, the semiconductor substrate 102 can be a doped silicon-based wafer, and as a result of the epitaxial deposition process, the film 104 can be formed or in the process of being formed on the front side of the semiconductor substrate 102. However, during this epitaxial deposition process, dopants 106 (e.g., dopant heteroatoms) may diffuse from the back side (i.e., the surface opposite the front side) of the semiconductor substrate 102. This diffusion may migrate along and affect the edges and inclined surfaces of the semiconductor substrate 102, resulting in unintentional overdoping 108 (also known as auto-doping) on ​​the wafer edge and front side. Therefore, the exemplary doping profile 100 is an unfavorable doping profile that requires backside sealing to mitigate auto-doping, which is typically performed prior to the epitaxial process.

[0029] To this end, in some methods, a silicon-based film can be deposited on the back side of the semiconductor substrate 102. Examples of silicon-based films can include silicon oxide (e.g., SiO2), low-temperature oxide (LTO, SiO2 can also be referred to as LTO), silicon nitride (e.g., SiN), or polycrystalline silicon (also known as poly-Si, poly-Si, or semi-crystalline silicon). In addition, the deposited material can be a combination of different films, thereby forming a stack of layers or materials. An exemplary stack can be a stack of SiO2 and poly-Si. The deposited film or stack can seal the dopant 106 in the semiconductor substrate 102 and prevent the dopant 106 from excessive diffusion and migration.

[0030] Figure 1B Another exemplary doping profile 120 is shown, in which an epitaxial process is applied to the semiconductor substrate 102 to achieve epitaxial growth of the film 104. In this example, a backside sealing layer 124 is deposited on the backside of the semiconductor substrate 102. A stack of SiO2 and poly-Si films deposited on the backside of the semiconductor substrate 102 can be an example of a backside sealing layer 124. This mitigates auto-doping issues by preventing diffusion and migration of the dopant 106.

[0031] However, current techniques for depositing the backside sealing layer 124 are complex, costly, and inefficient. Figure 2 In one example of such prior art shown, a five-step process flow is required to deposit the backside sealing layer 124 onto the backside.

[0032] Figure 2An exemplary process flow 200 for a conventional method of depositing a backside sealing layer without backside deposition is shown. In step 202, a semiconductor substrate 201 may be provided with its front side facing upward. In step 204, the semiconductor substrate 201 may be flipped over so that its front side faces downward. In step 206, a deposition process may be applied to the semiconductor substrate 201 to deposit a silicon oxide layer on the backside of the semiconductor substrate 201 from above (since it faces downward).

[0033] Back to Figure 2 An example of a deposition process that can be used in step 206 is APCVD, where a silicon oxide precursor is introduced into an atmospheric pressure processing environment (e.g., a processing chamber) at a uniform rate and a first processing temperature (e.g., 250-400° C.) is applied to the environment, resulting in the deposition of a first layer. Another example of a deposition process that can be used in step 206 is PECVD, where a silicon oxide precursor is introduced. The first layer can be a silicon oxide (SiO2) layer deposited on the back side of the semiconductor substrate 201, such as Figure 2 shown.

[0034] In step 208, another deposition process may be performed to deposit layers on both sides of the semiconductor substrate 201. For example, LPCVD may be used with a silicon-based precursor at a second processing temperature (e.g., 600-700° C.) to deposit polycrystalline silicon (poly-Si) layers on the front and back sides.

[0035] In step 210, the semiconductor substrate 201 can be flipped over again so that the front side is facing up again. In step 212, the front side of the semiconductor substrate 201 can be polished to remove the poly-Si layer from the front side. Thus, the exemplary process flow 200 can produce a wafer with a backside sealing layer, wherein the backside sealing layer includes a silicon oxide layer and a poly-Si layer. Having both layers can improve the sealing ability of the backside sealing layer, rather than having only one layer, although in some cases (for example, when the epitaxial layer is not thick and the dopant diffusion from the back side is small) having only one layer can also be acceptable.

[0036] However, the above-mentioned traditional method also has disadvantages. This complex procedure involving flipping and multiple steps is costly and time-consuming, and leads to low efficiency. Part of the complexity of the traditional method is that the deposition of the two silicon oxide and polysilicon layers requires different processing temperatures (such as 250-400°C and 600-700°C). In addition, two different deposition tools are required to deposit the two layers, which increases the complexity of the process flow and its cost and processing time. In addition, the poly-Si layer deposited via LPCVD may undergo over-crystallization in any subsequent epitaxial step at high processing temperatures (such as above 1000°C), resulting in large grain size and rough surface.

[0037] While the resulting backside sealing layer can mitigate autodoping, it is clear that significant improvements can be made to reduce complexity, reduce costs, shorten processing time, and thus improve efficiency. The techniques and equipment described below can improve each of the above issues. In addition, different types of layers (besides SiO2 and poly-Si) can be deposited in different configurations to avoid some of the above issues.

[0038] Figure 3 An exemplary process flow 300 of a method for depositing a backside sealing layer using backside deposition according to certain embodiments is shown. In step 302, a semiconductor substrate 301 may be provided with its front side facing up.

[0039] In step 304, a deposition process may be applied to the semiconductor substrate 301 without flipping the semiconductor substrate 301. In some embodiments, the deposition process may include PECVD using a backside deposition apparatus (described below). This eliminates the need to flip or otherwise move the semiconductor substrate 301, as it allows one or more layers to be deposited directly onto the backside of the semiconductor substrate 301.

[0040] In some methods, the deposition process may include two consecutive deposition steps. In the first deposition step, the first layer 312 may be deposited on the back side of the semiconductor substrate 301 in an environment suitable for PECVD (e.g., a process chamber of a backside deposition apparatus). In some examples, the first layer 312 may include a silicon oxide (SiO2) film. This deposition step may involve a lower process temperature (e.g., 200-400°C) than that used in LPCVD, which is applied to a set of first process gases (reactive gases, such as silane gas (SiH4) and nitrous oxide gas (N2O)) and plasma introduced into the environment to form the SiO2 film.

[0041] In the second deposition step, after depositing the first layer 312, while the front side is still facing upward, the second layer 314 can be deposited on the back side of the semiconductor substrate 301, directly above the first layer 312. The second deposition step can be performed immediately or substantially immediately (e.g., within 5 seconds) after the first deposition step. The deposition step can use the same processing temperature as the first deposition step (e.g., 200-400°C) and introduce a carrier gas and plasma into the environment. In some examples, the second layer 314 can include a high-quality amorphous silicon (a-Si) film. The SiO2 film and the a-Si film can each have a specified thickness. For example, the thickness of the SiO2 film can be The thickness of a-Si film can be as high as In certain embodiments, the thickness of either or both of the SiO2 film and the a-Si film may be as high as When forming a-Si, the chemical reaction involves the decomposition of SiH4, so only carrier gas can be introduced, and no other process gases or reactive gases can be introduced. The carrier gas used in the second deposition step can be an inert gas such as argon (Ar), nitrogen (N2) or helium (He).

[0042] While the above description is made with reference to the first and second deposition steps, it will be appreciated that these steps are part of a single process for producing two films. That is, the process temperature can be kept constant (e.g., 200-400°C), the substrate can remain stationary, and the only change in process conditions is the switching of the reactant gases to form the two layers on the back side of the substrate. As discussed below with respect to Figure 5 As described above, the reaction gases can be changed to change the order of layers formed on the back side of the substrate.

[0043] This is a prominent advantage of the present disclosure. The two deposition steps of silicon oxide and a-Si can be performed in the same environment or process chamber at the same process temperature without breaking the vacuum or transferring or otherwise moving the semiconductor substrate 301. Only the process gas needs to be changed between the deposition steps. Compared with traditional methods (such as Figure 2 Compared to the example process flow 200 in FIG. 2 , no flipping is required because deposition occurs directly on the back side of the wafer, without any front side deposition, and no removal or polishing of the front side is required or performed. In addition, there is good adhesion between the silicon oxide layer and the a-Si layer, which prevents peeling or flaking of the a-Si film, which in some cases may be relatively thicker than the silicon oxide film.

[0044] Additionally, in some cases, a-Si can be used as a conductive layer to improve wafer clamping, such as electrostatic clamping. Thus, depositing a-Si on the semiconductor substrate 301 helps further stabilize or fix it in the environment, such as the susceptor of the processing chamber (or ShoPed as described below).

[0045] In step 306, an annealing process may be performed. In some embodiments, the annealing may be performed at a temperature different from the temperature used for the deposition step, for example, 700-1100°C. That is, the semiconductor substrate 301 having the first layer 312 and the second layer 314 may be exposed to a high temperature (for example, 700-1100°C) and allowed to cool over time. The annealing may be performed in different environments or processing chambers. Through this annealing process, the second layer 314 (such as an a-Si film) may crystallize and transform into a different material. In some examples, the resulting crystalline layer 316 (such as a poly-Si film) may be formed on the SiO2 film, thereby forming an enhanced back sealing layer 320 on the back of the semiconductor substrate 301, and the semiconductor substrate 301 does not move during the process of forming the enhanced back sealing layer 320. Therefore, the enhanced back sealing layer 320 may include a SiO2+poly-Si stack. Compared with conventional methods (such as Figure 2 Compared to the exemplary process flow 200 of the present disclosure, the poly-Si film can have a smaller grain size and a smoother surface, which is another advantage of the present disclosure. In wafer processing, it is generally desirable to have a smooth surface rather than a rough surface, which may otherwise affect wafer clamping in other tools and downstream processes (including lithography and etching processes).

[0046] Brief Reference Figure 4 , depicts an example of an enhanced backside sealing layer 400 formed on the surface of a semiconductor substrate 401 according to certain embodiments. According to the single-step deposition method described above with respect to step 304, a first material layer (e.g., SiO2 film 404) may be deposited on the surface of the semiconductor substrate 401, and a second material layer (e.g., a-Si film 406) may be deposited on the first material layer. The SiO2 film 404 may have a thickness T1 (e.g., in this example, within the above parameter range), which is less than the thickness T2 of a-Si (for example, Within the above parameter range). However, the function of the SiO2 film 404 includes promoting the adhesion of a-Si to the semiconductor substrate 401. Therefore, the thicker T2 does not cause peeling or flaking problems of the a-Si film 406. The SiO2 film 404 can further prevent the leakage or diffusion of dopants from the semiconductor substrate 401 and improve the stability of the a-Si film 406 during high temperature processes by absorbing hydrogen released by a-Si. In addition, compared with poly-Si produced using LPCVD in traditional methods, the outer surface 408 of the a-Si film 406 produced according to the disclosed embodiment after annealing (due to the smaller grain size) is smoother.

[0047] Optionally, after the annealing treatment in step 306, other processes may be performed, such as (i) removing the semiconductor substrate 301 with the enhanced backside sealing layer 320, (ii) downstream processes related to the environment (e.g., the processing chamber), such as process diagnostics, process control, chamber cleaning, hazard purging, gas (e.g., N2 from the processing chamber) purging, or (iii) collecting data related to the semiconductor substrate 301 and / or the environment via one or more sensors such as a spatial sensor (e.g., a camera), a spectral sensor (e.g., an optical emission spectroscopy (OES) sensor), and / or a temporal sensor (e.g., a photodiode).

[0048] Furthermore, the above processes can be performed simultaneously on multiple semiconductor substrates in a single process chamber or multiple process chambers of a multi-chamber deposition apparatus, as will be further described below.

[0049] However, in some embodiments, the first layer 312 may include a-Si and the second layer 314 may include SiO2. That is, the materials of the first layer 312 and the second layer 314 may be reversed, rather than Figure 3 shown.

[0050] Figure 5 Another exemplary process flow 500 of a method for depositing a backside sealing layer using backside deposition according to certain embodiments is shown. Here, the process begins at step 502 where a semiconductor substrate 501 is provided with its front side facing up, similar to step 302.

[0051] In step 504, a deposition process can be applied to the semiconductor substrate 501 without flipping the semiconductor substrate 501. In some embodiments, the deposition process can include PECVD using a backside deposition apparatus (described below). This eliminates the need to flip or otherwise move the semiconductor substrate 501, as it allows one or more layers to be deposited directly on the backside of the semiconductor substrate 501.

[0052] In some methods, the deposition process may include two consecutive deposition steps. In the first deposition step, a first layer 512 may be deposited on the back side of the semiconductor substrate 501 in an environment suitable for PECVD (e.g., a process chamber of a backside deposition apparatus). In some examples, the first layer 512 may include an a-Si film. This deposition step may involve a lower process temperature (e.g., 200-400° C.) than that used in LPCVD, which is applied to a set of first process gases (e.g., a reactive gas SiH) introduced into the environment. 4) and plasma to form an a-Si film.

[0053] In a second deposition step, after the first layer 512 is deposited, a second layer 514 may be deposited on the back side of the semiconductor substrate 501 directly above the first layer 512 while the front side is still facing upward. The second deposition step may be performed immediately or substantially immediately (e.g., within 5 seconds) after the first deposition step. The deposition step may involve the same process temperature (e.g., 200-400° C.) as the first deposition step, and a second set of process gases (e.g., reactant gases SiH 4 and N 2 O) and plasma introduced into the environment. In some examples, the second layer 514 may include a SiO 2 film. The SiO 2 film and the a-Si film may each have a specified thickness, for example, the thickness of the a-Si film may be up to 1000 nm. The thickness of SiO2 is as high as

[0054] It is also advantageous that the two deposition steps of silicon oxide and a-Si can be performed in the same environment or process chamber at the same process temperature without breaking the vacuum or transferring or otherwise moving the semiconductor substrate 501. Only the process gas needs to be changed between the deposition steps. Figure 2 Unlike the exemplary process flow 200 in FIG. 1 , no flipping is required because deposition occurs directly on the back side of the wafer without any front side deposition and without any removal or polishing of the front side.

[0055] In step 506, an annealing process may be performed, similar to step 306. In some embodiments, the annealing may be performed at a temperature different from that used for the deposition step, for example, 700-1100°C, in the same environment or processing chamber, and allowed to cool over time. Through this annealing process, the first layer 512 (e.g., an a-Si film) may crystallize and transform into a different material. In some examples, a crystalline layer 516 (e.g., a poly-Si film) may be formed under the SiO2 film, thereby forming an enhanced back sealing layer 520 on the back side of the semiconductor substrate 501, and the semiconductor substrate 301 does not move during the formation of the enhanced back sealing layer 520. Therefore, the enhanced back sealing layer 520 may include a poly-Si+SiO2 stack. In the exemplary process flow 500, the surface smoothness of the enhanced back sealing layer 520 depends on the smoothness of the outer layer, which is the second layer 514 (e.g., a SiO2 film).

[0056] Optionally, after the annealing process of step 506, other downstream processes, such as those described, may be performed.

[0057] Furthermore, the above-described processes may be performed simultaneously on multiple semiconductor substrates in a single process chamber or multiple process chambers of a multi-chamber deposition apparatus, as further described below. method

[0058] Figure 6is a flow chart of an example of a method 600 for backside sealing of a semiconductor substrate according to certain embodiments. One or more functions of the method 600 may be performed or caused by a computerized device or system. Figure 6 The structure of the functions shown in one or more blocks shown may be performed by hardware and / or software components of such a computerized device or system, such as, for example, a controller device, a computerized system, or a computer-readable device including a storage medium storing computer-readable and / or computer-executable instructions, which instructions are configured to cause at least one processor device or computerized device to perform operations when executed by a processor device. A controller may be one example of a computerized device or system. A processing chamber may be another example of a computerized device or system. Exemplary components of the above devices are as follows: Figures 7 to 11 and described in more detail elsewhere in this document.

[0059] It should also be noted that Figure 6 The operations in can be performed in any suitable order, not necessarily Figure 6 In the order depicted in . In addition, Figure 6 The process shown may include Figure 6 The operations depicted may be more or less than those described.

[0060] At block 610, method 600 may include delivering a first set of one or more process gases to a first process chamber of a deposition apparatus, wherein the first process chamber has a semiconductor substrate positioned therein. In certain embodiments, the first process chamber may be one of a plurality of process chambers or stations of the deposition apparatus, as further described below.

[0061] At block 620 , the method 600 may include applying a first processing temperature in the presence of a plasma to form a first material layer on the back side of the semiconductor substrate.

[0062] In some embodiments, the first material layer may include silicon oxide (SiO 2 ).

[0063] In certain embodiments, the first material layer may include amorphous silicon.

[0064] In some embodiments, the first processing temperature may include a temperature of 200-400°C.

[0065] At block 630, the method 600 may include delivering a second set of one or more process gases to the first process chamber.

[0066] In some embodiments, the first set of one or more process gases may include silane (SiH4) and nitrous oxide (N2O), and the second set of one or more process gases may include a carrier gas. For example, these sets of gases may be used with the exemplary process flow 300.

[0067] In some embodiments, the first set of one or more process gases may include silane (SiH 4 ) and the second set of one or more process gases may include SiH 4 and nitrous oxide (N 2 O). For example, these sets of gases may be used with the exemplary process flow 500 .

[0068] At block 640 , method 600 may include applying a first processing temperature in the presence of plasma to form a second material layer on the first material layer on the back side of the semiconductor substrate. The first processing temperature may be the same first processing temperature as block 620 (eg, 200-400° C.).

[0069] In some embodiments, the second material layer may include amorphous silicon. In certain embodiments, the second material layer may include silicon oxide (SiO2).

[0070] At block 650 , the method 600 may include, after forming the second material layer, applying a second processing temperature to cause an annealing process to occur, including causing the first material layer or the second material layer to crystallize to collectively form a material stack that seals the backside of the semiconductor substrate.

[0071] In some embodiments, the first material layer may include a silicon oxide (SiO2) layer or film; the second material layer may include an amorphous silicon layer or film formed on the SiO2 film; the crystallization of the first material layer or the second material layer may include crystallizing the amorphous silicon film into a polycrystalline silicon layer or film; the polycrystalline silicon film and the SiO2 film may together form a material stack that seals the back side of the semiconductor substrate, thereby reducing the diffusion of dopants from the semiconductor substrate.

[0072] In some embodiments, the first material layer may include an amorphous silicon layer or film; the second material layer may include a silicon oxide (SiO2) layer or film formed on the amorphous silicon film; the crystallization of the first material layer or the second material layer may include crystallizing the amorphous silicon film into a polycrystalline silicon layer or film; the polycrystalline silicon film and the SiO2 film may together form a material stack that seals the back side of the semiconductor substrate, thereby reducing the diffusion of dopants from the semiconductor substrate.

[0073] In certain embodiments, the silicon oxide (SiO 2 ) layer may be up to 5,000 angstroms thick, while the amorphous silicon layer may be up to 12,000 angstroms thick.

[0074] In some embodiments, the semiconductor substrate can be placed in at least one of one or more processing chambers (e.g., a first processing chamber) such that the back side of the semiconductor substrate faces downward and the front side of the semiconductor substrate faces upward during the formation of the first material layer on the back side of the semiconductor substrate and the formation of the second material layer on the back side of the semiconductor substrate.

[0075] In some embodiments, the semiconductor substrate does not move between applying the first processing temperature and applying the second processing temperature. In some embodiments, during the application of the first processing temperature, the first material layer and the second material layer may be formed only on the back side of the semiconductor substrate, and not on the front side of the semiconductor substrate.

[0076] In some embodiments, method 600 may further include performing an epitaxial process after forming the second material layer. In some implementations, the material stack may reduce diffusion of dopants from the semiconductor substrate during the epitaxial process. Device

[0077] In some embodiments, Figure 7 is a block diagram illustrating a substrate processing system 700 for performing processing on a semiconductor substrate 702 (also referred to herein as a wafer) in accordance with some embodiments. As shown, the substrate processing system 700 can include a chamber 734. A central column can be configured to support a pedestal while the upper surface of the semiconductor substrate 702 is being processed, for example, while a film is being formed on the upper surface of the semiconductor substrate 702 or on the backside of the semiconductor substrate 702. According to some embodiments disclosed herein, the pedestal can be referred to as a showerhead-pedestal ("ShoPed") 706. A showerhead 736 can be disposed above the ShoPed 706.

[0078] In some embodiments, the showerhead 736 can be electrically coupled to a power source 738 via a matching network 740. The power source 738 can be controlled by a control module 742 (e.g., a controller). In certain embodiments, power can be supplied to the ShoPed 706 instead of the showerhead 736. The control module 742 can be configured to operate the substrate processing system 700 by executing process inputs and controls for a particular process recipe. Depending on whether the upper surface of the semiconductor substrate 702 receives a deposited layer or layer stack or whether the lower surface of the semiconductor substrate 702 receives a deposited layer or layer stack, the controller module 742 can set various operational inputs for the process recipe, such as power levels, timing parameters, process gases, mechanical movement of the semiconductor substrate 702, and / or the height of the semiconductor substrate 702 relative to the ShoPed 706.

[0079] In some embodiments, the center column may further include lift pins that are controlled by a lift pin controller. Such lift pins may be used to lift the semiconductor substrate 702 from the ShoPed 706 so that the end effector (not shown) can pick up the wafer and place the semiconductor substrate 702 down after the end effector is placed. The end effector may also place the semiconductor substrate 702 on the spacer 744. As described below, the spacer 744 may be sized to provide a controlled separation of the semiconductor substrate 702 between the top surface of the showerhead 736 (facing the wafer) and the top surface of the ShoPed 706 (facing the wafer).

[0080] In some embodiments, the substrate processing system 732 can further include a first gas manifold 746 connected to a first gas source 748 (e.g., a gas chemical supply and / or an inert gas from a facility). The control module 742 can control the delivery of the first gas source 748 via the first gas manifold 746, depending on the process being performed on the upper surface of the semiconductor substrate 702. The selected gas can then flow into the showerhead 736 and be distributed in the volume of space defined between the faces of the showerhead 736 that face the semiconductor substrate 702 when the wafer rests on the susceptor.

[0081] In some embodiments, the substrate processing system 732 can further include a second gas manifold 750 connected to a second gas source 752 (e.g., a gas chemical supply and / or an inert gas from a facility). The control module 742 can control the delivery of the second gas source 752 via the second gas manifold 750 based on the process being performed on the bottom surface of the semiconductor substrate 702. The selected gas can then flow into the showerhead 736 and be distributed in the volume of space defined between the sides of the ShoPed 706 facing the bottom or bottom surface (e.g., backside) of the semiconductor substrate 702 when the wafer rests on the spacer 744. The spacer 744 can provide a spacing that optimizes deposition on the bottom surface of the semiconductor substrate 702 while reducing deposition above the top surface of the semiconductor substrate 702. In some embodiments, when deposition is directed toward the lower surface of the semiconductor substrate 702, an inert gas may flow over the upper surface of the semiconductor substrate 702 via the showerhead 736, which may push the reactant gas away from the upper surface and direct the reactant gas provided from the ShoPed 706 toward the lower surface of the semiconductor substrate 702.

[0082] In some embodiments, showerhead 736 or ShoPed 706 can employ a zoned deposition design. For example, second gas manifold 750 can be fluidically coupled to control the delivery of gas to different regions of the wafer. By controlling the flow of gas to different regions, different films can be deposited on the wafer as desired.

[0083] In addition, the gases may or may not be premixed. Appropriate valve settings and mass flow control mechanisms may be used to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. The process gases may be exhausted from the chamber 734 via an outlet. A vacuum pump (e.g., a single or two-stage mechanical dry pump and / or a turbomolecular pump) may extract the process gases and maintain an appropriate low pressure within the reactor through a closed-loop controlled flow limiting device (e.g., a throttle valve or a swing valve).

[0084] In certain embodiments, a carrier ring 754 can surround an outer region of the ShoPed 706. When the top surface of the semiconductor substrate 702 is being processed (e.g., material is being deposited thereon), the carrier ring 754 can be configured to rest above a carrier ring support region that is a step down from the wafer support region in the center of the ShoPed 706. The top surface of the carrier ring 754 is generally coplanar with the top surface of the semiconductor substrate 702. The carrier ring 754 can include an outer edge side (e.g., an outer radius) of its disk structure and a wafer edge side (e.g., an inner radius) of its disk structure, the latter being closest to where the semiconductor substrate 702 is located. The carrier ring 754 can be associated with an inner diameter (ID). The ID can extend to the inner perimeter of the carrier ring, generally surrounding a substrate (e.g., semiconductor substrate 702) in the processing chamber. The wafer edge side of the carrier ring 754 can also include a plurality of contact support structures or "tabs" that can be configured to elevate the semiconductor substrate 702 when the carrier ring 754 is held by the spacers 744. The carrier ring 754 can include a plurality of tabs, the number of which can be selected from a range to support the semiconductor substrate 702 during processing. Additional details regarding tab embodiments are provided below.

[0085] Figure 8 is a block diagram illustrating another substrate handling system 800 for performing processing on a semiconductor substrate 802 (also referred to herein as a wafer) according to some embodiments. In some embodiments, a crossbar 856 can be used to lift and maintain a carrier ring 854 at a processing height, for example, to allow deposition on the lower surface (backside) of the semiconductor substrate 802. Thus, the carrier ring 854 can be lifted along with the semiconductor substrate 802. In some embodiments, the carrier ring 854 can be rotated to another station (e.g., in a multi-station system).

[0086] In summary, embodiments disclosed herein are directed to systems for depositing PECVD films on selected sides (front and / or back) of a wafer with dynamic control. Some embodiments may include dual gas flow electrodes for defining a capacitively coupled PECVD system. The system may include a gas flow showerhead (e.g., showerhead 836) and a ShoPed 806. In certain embodiments, the gas flow base (i.e., ShoPed) is a combination of a showerhead and a base that enables deposition on the back side of the wafer. The electrode geometry combines features of the showerhead (e.g., gas mixing boost chamber, holes, hole patterns, baffles to prevent gas injection) and features of the base. Examples of base features include embedded controlled heaters, wafer lifting mechanisms, the ability to accommodate plasma suppression rings, and movability. This allows for the transfer of wafers and process gases with or without RF power being provided by the base.

[0087] In some embodiments, the system may include a wafer lift mechanism that tightly controls the parallelism of the substrate to the electrodes. In one example, this can be achieved by positioning the lift mechanism parallel to the two electrodes and controlling manufacturing tolerances (e.g., a spindle or lift pin mechanism). In another example, the lift can be achieved by elevating the wafer lift assembly. This approach may not allow for dynamic control of the deposition side.

[0088] In certain configurations, the lift mechanism can allow for dynamic control of substrate position during processing (before, during, and after plasma) to control the deposition side, deposition profile, and deposited film properties. The system can also allow for selective activation / disable of one side for reactant flow. One side can be used for reactant flow, while the other side can be used for inert gas flow to suppress deposition and plasma.

[0089] In certain embodiments, the gap between the sides of the wafer where plasma / deposition is not desired can be tightly controlled. This distance can be controlled to suppress the plasma. Without this distance control, the wafer can be susceptible to plasma damage. For example, the system can allow a minimum gap of about 2 mm to about 0.5 mm, and in another embodiment, a minimum gap of about 1 mm to about 0.05 mm (limited by wafer curvature), and this gap can be controlled. The gap can be controlled based on process conditions.

[0090] In certain embodiments, the gas flow base (i.e., ShoPed) can achieve, but is not limited to, the following: (a) thermal stabilization of the wafer to the processing temperature before processing; (b) selective design of the hole pattern on the ShoPed to selectively deposit films in different areas on the back side of the wafer; (c) interchangeable rings can be attached to achieve appropriate plasma confinement and hole pattern; (d) stabilization of the wafer transfer mechanism within the chamber and transfer of the wafer outward to another chamber or box - such as lift pins, RF coupling features, minimum contact arrays; (e) implementation of gas mixing features such as, for example, internal booster chambers, baffles, and manifold line openings; and (f) addition of compartments in the gas flow base (i.e., ShoPed) to allow gas to flow selectively to different areas on the back side of the wafer and control the flow rate via flow controllers and / or multiple booster chambers.

[0091] In another embodiment, dynamic gap control of the wafer lift mechanism is used to achieve the following: (a) control the distance from the deposition or reactant flow electrode to the side or middle of the wafer where deposition is desired so that deposition can occur on both sides; and (b) the lift mechanism dynamically controls the distance during processing (before plasma, during plasma, after plasma) to control the deposition side, the profile of the deposition, and the deposited film properties. In another embodiment, for deposition modes for deposition on the back side of the wafer, film edge exclusion control is very desirable to avoid stacking issues associated with lithography. The lift mechanism used in this system is implemented via a carrier ring 854, which has design features that shield deposition on the edge. This determines the edge exclusion control via the design and shape of the carrier ring.

[0092] Figure 9A A cross-sectional view of an edge region of a ShoPed 906 (e.g., 706, 806) is shown. This view provides a cross-sectional illustration of a carrier ring 954 (e.g., 754, 854) having a carrier ring inner radius 954a and a carrier ring outer radius 954b. In certain embodiments, the carrier ring 954 includes a support extension 954c that extends below the substantially planar surface of the carrier ring 954.

[0093] The support extensions 954c are configured to mate with and reside within support surfaces defined in the top surface of the spacers 944. The support surfaces provide complementary mating surfaces for the support extensions 954c, thereby preventing the carrier ring 954 from sliding or moving when supported by the spacers 944. Although three spacers are shown as the spacers 944 in FIG9 , it is contemplated that any number of spacers may be provided so long as the carrier ring can be supported substantially parallel to the surface of the ShoPed 906 and the spacers are defined to support the semiconductor substrate 902 in a spaced relationship from the top surface of the ShoPed 906.

[0094] As further shown, the top surface of the ShoPed 906 will include a hole pattern 906a distributed across the entire surface to provide uniform gas distribution and output during operation. In one embodiment, the hole pattern 906a is distributed in a plurality of concentric rings that begin at the center of the top surface of the ShoPed 906 and extend to the periphery of the ShoPed 906. At least one hole pattern 906a is disposed in an edge hole region 907 of the hole pattern, and the orifices defined in the edge hole region 907 are preferably angled to provide gas that is not perpendicular to the surface of the ShoPed 906.

[0095] In one example, the angle or tilt at which the orifices defining the edge hole region 907 are located is defined as being tilted or angled away from the center of the ShoPed 906. In one embodiment, the angle is approximately 45° from horizontal. In other embodiments, the angle can vary from 20° from horizontal to approximately 80° from horizontal. In one embodiment, by providing angled orifices in the edge hole region 907, additional process gas distribution can be provided during backside deposition on the semiconductor substrate 902. In one embodiment, the remaining orifices 906d of the hole pattern 906a are oriented substantially perpendicular to the surface of the ShoPed 906 and toward the bottom surface of the semiconductor substrate 902.

[0096] Figure 9B It is shown that when the semiconductor substrate 902 is held by the carrier ring 954, the edge of the semiconductor substrate 902 will be located on an edge region closer to the carrier ring inner radius 954a of the carrier ring 954. When positioned using the spacer 944, the surface of the showerhead 936 facing the top surface of the semiconductor substrate 902 can be substantially close to prevent deposition during a mode of depositing onto the back side of the semiconductor substrate 902.

[0097] For example, the distance between the top of the semiconductor substrate 902 and the surface of the showerhead 936 is preferably between about 2 mm and about 0.5 mm, and in some embodiments, about 1 mm to about 0.5 mm, depending on the degree of wafer curvature. That is, if the wafer is significantly curved, the spacing will be about 0.5 mm or greater. If the wafer is not significantly curved, the spacing can be less than about 0.5 mm. In one embodiment, it is preferred to minimize the spacing to prevent deposition on the top surface of the substrate when depositing a layer of material on the back side of the substrate. In some embodiments, the showerhead 936 is configured to provide an inert gas flow above the top surface of the semiconductor substrate 902 while the back side of the substrate is being deposited and the deposition gas is being provided by the ShoPed 906.

[0098] Any suitable chamber may be used to implement the disclosed embodiments. Exemplary deposition equipment includes various systems, such as the Lam Research Corp., of Fremont, California. and Max, or any of a variety of other commercially available processing systems.

[0099] Figure 101 is a cross-sectional view of a processing system 1000 for depositing a film on the backside of a semiconductor substrate according to some embodiments herein. In some embodiments, the processing system 1000 may include a showerhead 1002, a shower-pedestal (ShoPed) 1004, and one or more support structures 1006 (e.g., carrier rings 754, 854, 954 and / or protrusions of the carrier ring, or cross 856). The one or more support structures 1006 may be configured to support a semiconductor substrate 1020. In some embodiments, the one or more support structures 1006 may be coupled to the ShoPed 1004 and / or other structures associated with the processing system 1000, such as one or more process chamber walls. In some embodiments, an electrostatic chuck (e.g., a bipolar chuck or a monopolar chuck) may be used to further secure the semiconductor substrate 1020 (electrostatic chuck not shown). In some embodiments, depositing SiO2 on the semiconductor substrate 1020 may improve the clamping of the semiconductor substrate 1020, as described above.

[0100] In some embodiments, the showerhead 1002 may include an electrode 1010 operable by providing RF power to multiple zones. For example, there may be two different zones configured to receive different amounts of RF power at different times or substantially simultaneously. In another example, there may be three different zones. In other examples, there may be four or more zones. The RF power provided to two or more (or in some cases, all) zones may be the same amount.

[0101] In some embodiments, the electrode 1010 can be integrated or embedded into the showerhead 1002. The electrode 1010 can have a specific zone configuration based on wafer curvature and / or other requirements. Examples of zones are discussed above. However, in some embodiments, the electrode 1010 can be a separate component that can be replaced and installed in the showerhead 1002 without destroying the showerhead 1002. Such a replaceable electrode can facilitate performing different customized backside film depositions of the type discussed in this disclosure. For example, an electrode with three zones can be replaced with an electrode with two zones to correct for different types of wafer curvature.

[0102] In some embodiments, the ShoPed 1004 can have one or more gas inlets 1005 configured to deliver and exhaust a process gas 1007. Examples of process gases 1007 can include silane (SiH4), nitrous oxide (N2O), and / or ammonia (NH3). An inert carrier gas (e.g., argon, nitrogen, neon, or helium) can also be delivered and exhausted through the ShoPed 1004. In some cases, a mixture of process gas and carrier gas can be delivered through and exhausted from the showerhead 1002. Depending on the type of process gas, different types of film materials can be deposited on the semiconductor substrate 1020. The showerhead 1002 can have one or more gas inlets 1003 configured to receive and disperse a purge gas 1008 (e.g., nitrogen). The purge gas 1008 flowing along the top or front surface of the semiconductor substrate 1020 can be used to prevent the process gas 1007 or impurities from the ShoPed 1004 from reaching the top or front surface of the semiconductor substrate 1020.

[0103] In some embodiments, the semiconductor substrate 1020 can be positioned and supported closer to the showerhead 1002 than the ShoPed 1004. In an exemplary embodiment, the gap 1012 between the showerhead 1002 and the semiconductor substrate 1020 can be approximately 1 mm, while the gap 1014 between the ShoPed 1004 and the semiconductor substrate 1020 can be approximately 12 mm. Various distances can be used. However, it is noteworthy and useful that the gap 1012 is small (e.g., small enough to prevent plasma formation), and can be much smaller than the gap 1014. This is to prevent the formation of plasma 1015 between the showerhead 1002 and the semiconductor substrate 1020 (where the front surface of the semiconductor substrate 1020 is located). In other words, the plasma 1015 is encouraged to form on the back surface 1025 of the semiconductor substrate 1020, where the back surface faces away from the showerhead 1002 and the electrode 1010, and toward the ShoPed 1004 and / or the support structure 1006. The front side may have sensitive and expensive features (transistors, memory cells, wiring, etc.) In some embodiments, the purge gas flowing from the holes of the showerhead 1002 can push away any process gases or precursors that may remain or be delivered to the front side.

[0104] As discussed herein, by specifying the amount of RF power provided to different regions of the electrode 1010, and in some embodiments at different times, a film material having spatially varying properties can be formed on the semiconductor substrate 1020. Some examples of film properties include intrinsic stress (e.g., tensile stress or compressive stress) and film thickness.

[0105] Figure 111 is a schematic diagram of a processing system suitable for performing deposition processing (e.g., front-side deposition processing) in accordance with embodiments. System 1100 includes a transport module 1103. Transport module 1103 provides a clean, pressurized environment to minimize the risk of contamination of processed substrates as they move between different reactor modules. A multi-station reactor 1109 mounted on transport module 1103 is capable of performing ALD, treatment, and CVD in accordance with various embodiments. Multi-station reactor 1109 may include a plurality of stations 1111, 1113, 1115, and 1117 that may sequentially perform operations in accordance with disclosed embodiments. A station may include a heated susceptor or substrate support, one or more gas inlets or showerheads, or a dispersion plate.

[0106] One or more single-station or multi-station modules 1107 can be mounted on the transport module 1103, which can perform plasma or chemical (non-plasma) pre-cleaning, other deposition operations, or etching operations. The modules can also be used for various processes, such as preparing substrates for deposition processes. The system 1100 also includes one or more wafer source modules 1101 that store wafers before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 1119 can first move the wafers from the wafer source module 1101 to the load lock 1121. The wafer transfer device (typically a robot arm unit) in the transport module 1103 moves the wafers from the load lock 1121 to the modules mounted on the transport module 1103 and moves them between the modules.

[0107] In various embodiments, a system controller 1142 is used to control process conditions during the deposition process. The system controller 1142 typically includes one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0108] The system controller 1142 controls all activities of the deposition apparatus. The system controller 1142 executes system control software, which includes a set of instructions for controlling timing, gas mixtures, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or susceptor position, and other parameters of a particular process. In certain embodiments, other computer programs stored on a storage device associated with the system controller 1142 may also be used.

[0109] The depicted embodiment includes a user interface associated with the system controller 1142. The user interface may include a display screen, graphical software displays of device and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, and the like.

[0110] The computer program code for controlling the processes in the processing sequence can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by the processor to perform the tasks identified in the program. As also indicated, the program code can be hard-coded.

[0111] Controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be input using a user interface.

[0112] Signals used to monitor the process may be provided through analog and / or digital input connections of the system controller 1142. Signals used to control the process may be output through analog and digital output connections of the system 1100.

[0113] The system software can be designed or configured in various ways. For example, a plurality of chamber component subroutines or control objects can be written to control the operation of the chamber components required to perform deposition processes according to the disclosed embodiments. Examples of programs or program segments used for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0114] In some embodiments, the system controller 1142 is part of a system, which can be part of the examples described above. Such systems include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics to control their operation before, during, or after processing of semiconductor wafers or substrates. The electronics can be referred to as a "controller" and can control various components or sub-parts of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 1142 can be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer access tools and other transfer tools, and / or load locks connected to or interfaced with a particular system. System Controller

[0115] In a broad sense, a controller can be defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurement, etc. Such a controller can be used in any device described herein or used together with the device. Integrated circuits can include a chip, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software) in the form of firmware. Program instructions can be instructions that are transferred to a controller or system in the form of various individual settings (or program files), which define operating parameters for specific processing on or for a semiconductor wafer or to a system. In some embodiments, operating parameters can be a part of a recipe for one or more processing steps in the manufacturing process of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or bare chips of a wafer, as defined by a process engineer.

[0116] The system controller can be part of or coupled to a computer that is integrated with, coupled to, or otherwise connected to the system via a network, or a combination thereof. For example, the system controller can be in the "cloud" or all or part of a main computer system in a wafer fab, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review trends or performance metrics of multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that enables input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each process step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool with which the controller is configured to interface or control. Thus, as described above, the controller can be distributed, for example, by including one or more discrete controllers that are connected together via a network and work toward a common goal (e.g., the processing and control described herein). An example of a distributed controller for these purposes would be one or more integrated circuits on the chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer), which combine to control the processing on the chamber.

[0117] Exemplary systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel etch chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or fabrication of semiconductor wafers.

[0118] As described above, depending on the one or more processing steps to be performed by the tool, the controller can communicate with: one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to transport containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0119] The system controller may include various programs. A substrate positioning program may include program code for controlling chamber components used to load a substrate onto a susceptor or chuck and to control the spacing between the substrate and other components of the chamber, such as a gas inlet and / or a target. A process gas control program may include code for controlling gas composition, flow rate, pulse timing, and optionally, for flowing gas into the chamber to stabilize the pressure in the chamber prior to deposition. A pressure control program may include code for controlling the pressure in the chamber by adjusting, for example, a throttle valve in an exhaust system in the chamber. A heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to the wafer chuck.

[0120] Examples of chamber sensors that can be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the susceptor or chuck. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain desired process conditions.

[0121] The foregoing describes implementation of the embodiments herein in a single-chamber or multi-chamber semiconductor processing tool. The apparatus and processes described herein can be used in conjunction with photolithographic patterning tools or processes, for example, for preparing or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of films typically includes some or all of the following steps, each of which is provided by a number of feasible tools: (1) applying a photoresist to a workpiece, i.e., a substrate, using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible light or UV light or x-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern to an underlying film or workpiece using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. in conclusion

[0122] Although the above-described embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain variations and modifications may be implemented within the scope of the appended claims. The embodiments disclosed herein may be implemented without some or all of these specific details. In other cases, well-known processing operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. Furthermore, although the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that the specific embodiments are not intended to limit the disclosed embodiments. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the embodiments of the present invention. Accordingly, the embodiments of the present invention should be considered illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. An apparatus configured for backside sealing of a semiconductor substrate, the apparatus comprising: one or more processing chambers; a showerhead configured to deliver one or more process gases to a backside of the semiconductor substrate in at least one of the one or more process chambers; as well as a controller coupled to the showerhead and the one or more process chambers and configured to: delivering a first set of one or more process gases to a first processing chamber having the semiconductor substrate; applying a first processing temperature of 200-400° C. in the presence of plasma to form a silicon oxide (SiO 2 ) layer on the back side of the semiconductor substrate; delivering a second set of one or more process gases to the first process chamber; applying the first processing temperature of 200-400° C. in the presence of plasma to form an amorphous silicon layer on the SiO 2 layer on the back side of the semiconductor substrate; as well as After forming the amorphous silicon layer, a second process temperature of at least 700° C. is applied, causing an annealing process to occur, the annealing process including crystallizing the amorphous silicon layer to form a polysilicon layer to together form a material stack sealing the back side of the semiconductor substrate.

2. The apparatus according to claim 1 , wherein the semiconductor substrate is placed in at least one of the one or more processing chambers such that during the formation of the SiO 2 layer on the back side of the semiconductor substrate and the formation of the amorphous silicon layer on the back side of the semiconductor substrate, the back side of the semiconductor substrate faces downward and the front side of the semiconductor substrate faces upward.

3. The apparatus of claim 1 , wherein the first set of one or more process gases comprises silane (SiH 4 ) and nitrous oxide (N 2 O), and the second set of one or more process gases comprises a carrier gas.

4. The apparatus according to claim 1, wherein: The controller is further configured to perform an epitaxial process after forming the amorphous silicon layer; and The material stack reduces diffusion of dopants from the semiconductor substrate during the epitaxial growth process.

5. The apparatus of claim 1, wherein the silicon oxide (SiO2) layer comprises a thickness of up to 5,000 angstroms and the amorphous silicon layer comprises a thickness of up to 12,000 angstroms.

6. The apparatus of claim 1, wherein the semiconductor substrate does not move between applying the first process temperature and applying the second process temperature.

7. The apparatus according to claim 1, wherein During application of the first process temperature, the amorphous silicon and the polycrystalline silicon are formed only on the back side of the semiconductor substrate, and are not formed on the front side of the semiconductor substrate.

8. A device comprising: a first processing chamber configured to receive a semiconductor substrate; a showerhead configured to deliver one or more process gases to a backside of the semiconductor substrate in the first process chamber; as well as a controller coupled to at least the showerhead and the first process chamber and configured to: delivering a first set of one or more process gases to the first process chamber having the semiconductor substrate; applying a first processing temperature of 200-400° C. in the presence of plasma to form an amorphous silicon layer on the back side of the semiconductor substrate; delivering a second set of one or more process gases to the first process chamber; applying the first processing temperature of 200-400° C. in the presence of plasma to form a silicon oxide (SiO 2 ) layer on the amorphous silicon layer on the back side of the semiconductor substrate; as well as After the SiO2 layer is formed, a second process temperature of at least 700°C is applied to cause an annealing process to occur, which includes crystallizing the amorphous silicon layer to form a polysilicon layer to together form a material stack sealing the back side of the semiconductor substrate.

9. The apparatus of claim 8, wherein the first set of one or more process gases comprises silane (SiH4), and the second set of one or more process gases comprises SiH4 and nitrous oxide (N2O).

10. A method for backside sealing of a semiconductor substrate, the method comprising: delivering a first set of one or more process gases to a first process chamber of a deposition apparatus, wherein the first process chamber has a semiconductor substrate disposed therein; applying a first processing temperature in the presence of plasma to form a first material layer on the back side of the semiconductor substrate; delivering the second set of one or more process gases to the first process chamber; applying the first processing temperature in the presence of plasma to form a second material layer on the first material layer on the back side of the semiconductor substrate; as well as After forming the second material layer, a second processing temperature is applied to cause an annealing process to occur, the annealing process including crystallizing the first material layer or the second material layer to collectively form a material stack that seals the back side of the semiconductor substrate. The method according to claim 10 , wherein the first material layer comprises silicon oxide (SiO 2 ). The method according to claim 10 , wherein the first material layer comprises amorphous silicon. The method according to claim 10 , wherein the second material layer comprises amorphous silicon. The method according to claim 10 , wherein the second material layer comprises silicon oxide (SiO 2 ).

15. The method of claim 10, wherein the first processing temperature comprises a temperature of 200-400°C.

16. The method of claim 10, wherein the first set of one or more process gases comprises silane (SiH4) and nitrous oxide (N2O), and the second set of one or more process gases comprises a carrier gas.

17. The method of claim 10, wherein the first set of one or more process gases comprises silane (SiH4), and the second set of one or more process gases comprises SiH4 and nitrous oxide (N2O).

18. The method of claim 10, wherein: The first material layer includes a silicon oxide (SiO2) film; The second material layer includes an amorphous silicon film formed on the SiO2 film; The crystallization of the first material layer or the second material layer includes crystallizing the amorphous silicon film into a polycrystalline silicon film; as well as The polysilicon film and the SiO 2 film together form the material stack, which seals the back side of the semiconductor substrate, thereby reducing diffusion of dopants from the semiconductor substrate.

19. The method of claim 10, wherein: The first material layer includes an amorphous silicon film; The second material layer includes a silicon oxide (SiO2) film formed on the amorphous silicon film; The crystallization of the first material layer or the second material layer includes crystallizing the amorphous silicon film into a polycrystalline silicon film; and The polysilicon film and the SiO 2 film together form the material stack, which seals the back side of the semiconductor substrate, thereby reducing diffusion of dopants from the semiconductor substrate.

20. The method according to claim 10, further comprising performing an epitaxial process after forming the second material layer; in, The material stack reduces diffusion of dopants from the semiconductor substrate during the epitaxial growth process.

21. The method of claim 10, wherein no movement of the semiconductor substrate occurs between applying the first process temperature and applying the second process temperature.

22. The method according to claim 10, wherein During application of the first process temperature, the first material layer and the second material layer are formed only on the back side of the semiconductor substrate, but not on the front side of the semiconductor substrate.

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