Subthreshold standard cell circuit optimization method, device and equipment

Abstract

The invention discloses a sub-threshold standard cell circuit optimization method, device and equipment, relates to the technical field of digital integrated circuits, and is used for solving the problem that a standard cell circuit is in non-Gaussian distribution in time delay under sub-threshold voltage in the prior art. Comprising the following steps: extracting common parameters of a subthreshold standard unit and analyzing the common parameters to obtain analysis data; selecting a subthreshold standard unit type according to the analysis data and carrying out structural design to obtain a subthreshold standard unit structure; determining a target size corresponding to the subthreshold standard unit structure to obtain a target subthreshold standard unit; and analyzing and optimizing the target sub-threshold standard unit to obtain an optimized sub-threshold standard unit circuit. According to the technical scheme provided by the invention, the problem that in the prior art, the time delay of a standard unit circuit is in non-Gaussian distribution under the subthreshold voltage can be solved. A large-scale circuit is closer to Gaussian distribution, and a guarantee is provided for realizing high-energy-efficiency design of a digital system.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuits, and in particular to a sub-threshold standard cell circuit optimization method, device and equipment. Background Art

[0002] As modern semiconductor process sizes continue to shrink and chip integration continues to increase, power consumption per unit area is rising exponentially. Consequently, power consumption has become a key factor limiting chip reliability, scalability, and endurance. Research on low-power technologies is particularly important in power-sensitive applications such as wearable devices, Internet of Things (IoT) sensors, and implantable medical devices. Subthreshold circuit design can significantly reduce the dynamic energy consumption of circuits by lowering the power supply voltage to a level below the threshold voltage of MOS transistors, thereby guiding the design of low-power digital circuits. Because standard cell libraries are the foundation of large-scale integrated circuit design, the industry typically uses commercial standard cell libraries for low-power design at subthreshold voltages.

[0003] However, under subthreshold operating voltage, the CMOS mismatch coefficient increases, resulting in a reduction in the static noise margin of the original commercial standard unit, timing degradation, and even functional failure; in addition, process fluctuations under subthreshold voltage make the transistor current and threshold voltage exponentially related, resulting in a non-Gaussian distribution of unit circuit delay, making it difficult to converge the timing of circuits implemented based on standard units.

[0004] Therefore, the existing commercial advanced process standard cell library no longer meets the design requirements, and there is an urgent need to optimize the standard cell circuits under subthreshold conditions. Summary of the Invention

[0005] The object of the present invention is to provide a subthreshold standard cell circuit optimization method, device and equipment for solving the problem in the prior art that the delay of the standard cell circuit at the subthreshold voltage is non-Gaussian.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a subthreshold standard cell circuit optimization method, the method comprising:

[0008] Extracting and analyzing the common parameters of subthreshold standard cells to obtain analytical data;

[0009] Selecting a subthreshold standard cell type and performing structural design based on the analysis data to obtain a subthreshold standard cell structure;

[0010] determining a target size corresponding to a subthreshold standard cell structure, and obtaining a target subthreshold standard cell;

[0011] The target subthreshold standard cell is analyzed and optimized to obtain an optimized subthreshold standard cell circuit.

[0012] Optionally, common parameters of the subthreshold standard cell are extracted and analyzed to obtain analysis data, including:

[0013] Determine the gate length of the transistor based on the short channel and anti-short channel effect of the transistor at subthreshold voltage;

[0014] Construct the optimal energy consumption circuit and determine the optimal energy consumption point voltage;

[0015] Analyze the characteristic structure in the basic logical structure unit to make a preliminary judgment on the stability.

[0016] Optionally, selecting a subthreshold standard cell type and performing structural design based on the analysis data to obtain a subthreshold standard cell structure includes:

[0017] Select basic logic structure units that meet preset conditions based on fan-in type, unit structure, and power consumption;

[0018] It uses static complementary CMOS structure as the basic logic structure and preset transmission gate as the structure of complex unit;

[0019] The subthreshold standard cell structure is determined based on the basic logic structure units and complex cells that meet the preset conditions.

[0020] Optionally, determining a target size corresponding to a subthreshold standard cell structure to obtain a target subthreshold standard cell includes:

[0021] Analyze the most vulnerable working state of each type of cell in the subthreshold standard cell structure, and select the working state with the weakest driving capability and the largest delay based on the charge and discharge current analysis results;

[0022] Adjust transistor size, optimize the matching of pull-up and pull-down networks, and determine the optimal size range of unit transistors;

[0023] Using the formula:

[0024] f(I, D) = I*D

[0025] Within the optimal size range of the unit transistor, the target size corresponding to the subthreshold standard unit structure is determined by the objective function; wherein, I is the unit current, the circuit energy consumption E=I*V, V is the power supply voltage, the unit current is proportional to the circuit energy consumption, and the circuit energy consumption is proportional to the unit area; D is the unit delay, the unit delay is the average of the rise delay and the fall delay, the unit current and the unit delay are inversely proportional, and the minimum value is determined based on the objective function by adjusting the channel width of the transistor.

[0026] Optionally, analyzing and optimizing the target subthreshold standard cell to obtain an optimized subthreshold standard cell circuit includes:

[0027] Based on the static noise margin, the voltage transfer characteristic curve of the target subthreshold standard cell in the most vulnerable operating state is simulated. Under the first preset error input and second preset error output, Monte Carlo analysis is performed on different operating modes of the library cell, taking into account process deviation, temperature variation, and voltage jitter. The simulation results are then judged based on the 3σ principle to determine whether they meet the functional correctness evaluation criteria.

[0028] If the noise tolerance simulation and stability simulation of the unit meet the requirements, the modified unit size is the optimal value;

[0029] The delay distribution data is obtained through Monte Carlo simulation, and the fitting curve of the delay distribution data is analyzed. The unit size is fine-tuned so that the rising transmission delay and the falling transmission delay are close to the preset optimal value, and the delay distribution is closer to the Gaussian distribution. The simulation is iterated until the unit with the optimal size meets the noise tolerance and delay distribution evaluation criteria, and the optimized sub-threshold standard unit circuit is obtained.

[0030] Optionally, determining the gate length of the transistor based on the short channel and anti-short channel effect of the transistor at a subthreshold voltage includes:

[0031] Determine the subthreshold voltage of the library unit, simulate the threshold voltage of the PMOS transistor and the NMOS transistor, and determine the trend of the threshold being affected by the change of transistor size and the threshold voltage range;

[0032] Scan the influence of transistor gate width and gate length on threshold voltage respectively, and determine the adjustment range of gate length and gate width;

[0033] The gate length of the transistor is determined based on the short channel and anti-short channel effects of the transistor at subthreshold voltage.

[0034] Optionally, construct an optimal energy consumption circuit and determine the optimal energy consumption point voltage, including:

[0035] Build an optimal energy consumption circuit through multiple sets of preset level ring oscillator circuits;

[0036] Performing simulation based on the optimal energy consumption circuit, and determining the optimal energy consumption point voltage based on the simulation result;

[0037] Analyze the characteristic structure of the basic logical structure unit to make a preliminary judgment on the stability, including:

[0038] A static complementary CMOS structure is adopted as the basic logic structure. According to the circuit structure of the pull-up network and the pull-down network, the characteristic structure of the basic logic structure is divided into multiple circuit structure types. The circuit structure types include at least NMOS transistors, PMOS transistors, and multiple stages of NMOS transistors and PMOS transistors connected in series.

[0039] Compared with the prior art, the present invention provides a subthreshold standard cell circuit optimization method. The method extracts and analyzes common parameters of subthreshold standard cells to obtain analysis data; selects a subthreshold standard cell type based on the analysis data and performs structural design to obtain a subthreshold standard cell structure; determines a target size corresponding to the subthreshold standard cell structure to obtain a target subthreshold standard cell; and analyzes and optimizes the target subthreshold standard cell to obtain an optimized subthreshold standard cell circuit. This method improves the non-Gaussian distribution of delay in standard cell circuits at subthreshold voltages. Advanced processes increase the CMOS mismatch coefficient at subthreshold voltages, and process fluctuations cause random variations in the physical and electrical parameters of the chip. This reduces the noise margin of standard cell circuits suitable for normal operating voltages, worsens the delay, and results in a non-Gaussian distribution. This makes subsequent timing analysis difficult to converge, and causes large-scale circuits implemented based on the cell to also exhibit a non-Gaussian distribution. By improving the stability and timing characteristics of the cell circuit, the cell delay tends to be Gaussian, providing technical reserves for advanced process low-power integrated circuit technology. Therefore, in the design of sub-threshold standard cell circuits, while ensuring sufficient driving capability and low power consumption of the cell, it is necessary to improve the non-Gaussian problem of the cell delay distribution, solve the subsequent design timing convergence problem, and make large-scale circuits closer to the Gaussian distribution, so as to provide a guarantee for the high-energy-efficiency design of digital systems.

[0040] In a second aspect, the present invention provides a subthreshold standard cell circuit optimization device, comprising:

[0041] A common parameter analysis module is used to extract and analyze the common parameters of sub-threshold standard cells to obtain analysis data;

[0042] a subthreshold standard cell structure design module, configured to select a subthreshold standard cell type and perform structural design based on the analysis data to obtain a subthreshold standard cell structure;

[0043] a target size determination module, configured to determine a target size corresponding to a subthreshold standard cell structure and obtain a target subthreshold standard cell;

[0044] The sub-threshold standard cell circuit optimization module is used to analyze and optimize the target sub-threshold standard cell to obtain an optimized sub-threshold standard cell circuit.

[0045] In a third aspect, the present invention provides a subthreshold standard cell circuit optimization device, comprising:

[0046] A memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be run by the processor; when the processor runs the computer program, it executes the above-mentioned sub-threshold standard cell circuit optimization method.

[0047] In a fourth aspect, the present invention provides a computer storage medium having instructions stored therein. When the instructions are executed, the above-mentioned sub-threshold standard cell circuit optimization method is implemented.

[0048] The technical effects achieved by the device-type solution provided in the second aspect, the equipment-type solution provided in the third aspect, and the computer storage medium solution provided in the fourth aspect are the same as those of the method-type solution provided in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0050] Figure 1 A schematic diagram of the steps of a sub-threshold standard cell circuit optimization method provided by the present invention;

[0051] Figure 2 A design flow chart of a sub-threshold standard cell circuit optimization method provided by the present invention;

[0052] Figure 3 Schematic diagram of the current-voltage characteristics of a transistor in the subthreshold region;

[0053] Figure 4 This is the schematic diagram of the voltage evaluation circuit for the optimal energy consumption point;

[0054] Figure 5 Schematic diagram of preliminary analysis of six unit characteristic structures;

[0055] Figure 6 Schematic diagram of SNM transfer characteristic curve;

[0056] Figure 7 This is a schematic diagram for gate-level unit delay distribution evaluation;

[0057] Figure 8 A schematic structural diagram of a sub-threshold standard cell circuit optimization device provided by the present invention;

[0058] Figure 9 This is a schematic structural diagram of a sub-threshold standard cell circuit optimization device provided by the present invention. DETAILED DESCRIPTION

[0059] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0060] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0061] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0062] First, some abbreviations, English and key terms used in the specification of the present invention are explained:

[0063] PVT (Process Voltage Temperature): process, voltage, temperature;

[0064] SCE: short channel effect;

[0065] RSCE: reverse short channel effect;

[0066] Propagation Delay: transmission delay distribution;

[0067] Transition Delay: Transition delay distribution;

[0068] NAND4: Four-input NAND gate;

[0069] NOR4: Four-input NOR gate;

[0070] INV: NAND gate;

[0071] NAND2: Two-input NAND gate;

[0072] NOR2: Two-input NOR gate;

[0073] XOR2: Two-input exclusive-OR gate;

[0074] DFF: trigger;

[0075] MUX2: two-to-one multiplexer;

[0076] SNM: static noise margin.

[0077] Prior art 1 proposes a technique that sets all transistors to a minimum channel width and adjusts the transistor current by scaling the transistor size to match the pull-up and pull-down networks. The theory behind this technique is that transistors exhibit a significant inverse narrow channel effect at subthreshold voltages. This effect occurs when the transistor width increases within a small range, causing the transistor threshold to increase, the current to decrease, and the drive capability to decline. Therefore, when the transistor is at its minimum width, its threshold voltage is lowest, resulting in the maximum device current. Furthermore, this design approach results in lower power consumption and a smaller area compared to conventionally sized designs.

[0078] However, the technical solution of the prior art only considers the inverse narrow channel effect, ignoring other secondary effects, such as the narrow channel effect, that is, when the width of the transistor is reduced, its threshold voltage increases and the driving capability is weakened. Transistors of different processes have different secondary effects that dominate under the same PVT conditions. Therefore, considering only the inverse narrow channel effect is too one-sided. In addition, the minimum width of the transistor does not necessarily mean that its threshold voltage is the minimum. The threshold voltage is affected by multiple factors, including the material of the transistor, the doping concentration, the process parameters, and the geometric dimensions of the device (such as length and width). In addition, this method cannot solve the problem of non-Gaussian distribution of circuit delay.

[0079] The second prior art proposes a method based on the inverse short channel effect, which assumes that as gate length increases, current first increases and then decreases, and that an optimal gate length exists. The method then adjusts the matching of the pull-up and pull-down networks based on traditional gate width adjustment strategies to determine the gate width range of the transistors in the cell. Finally, the transistor gate width is determined based on the optimization objective function f(P,D) = Pi*D. By adjusting the gate widths of each transistor in the cell to optimize the objective function, the target cell size is determined. P represents the cell power consumption, D represents the cell delay, and i represents the adjustment coefficient, which is used to adjust the ratio of cell power consumption to cell delay.

[0080] In the second prior art, although the solution takes into account the effects of the inverse narrow channel effect and the inverse short channel effect on the transistor threshold voltage under the process used, and integrates the optimal objective function to determine the gate width and gate length values ​​of the transistor in the unit. However, through experimental simulation, it was found that only considering the above factors to adjust the size of the transistor in the unit has limited improvement on the non-Gaussian delay distribution of the standard unit operating at the subthreshold. Under normal voltage, the delay distribution of the transistor is Gaussian, but because the transistor current and threshold voltage at the subthreshold are nonlinear, even if it is assumed that the process parameters are Gaussian, the unit delay is no longer Gaussian. Therefore, the problem of non-Gaussian distribution of unit delay needs to be considered in the design of standard units at the subthreshold.

[0081] The existing commercial advanced process standard cell library no longer meets the design requirements. It is necessary to optimize the design of standard cell circuits under subthreshold conditions, thereby improving the stability and timing characteristics of the cell circuits, making the cell delay tend to Gaussian distribution, and providing technical reserves for advanced process low-power integrated circuit technology. Therefore, in order to solve the problems in the above-mentioned prior art, the present invention provides a subthreshold standard cell circuit optimization method, device and equipment. Next, the solution provided in the embodiment of this specification is described in conjunction with the accompanying drawings:

[0082] like Figure 1 As shown, the process may include the following steps:

[0083] Step 110: extracting and analyzing common parameters of the sub-threshold standard cell to obtain analysis data.

[0084] Common parameters may include electrical characteristic parameters (such as threshold voltage, subthreshold swing, etc.) and size parameters (such as transistor size, unit area, etc.).

[0085] The analysis data may include the gate length of the transistor, the voltage at the optimal energy consumption point, and other reliability and stability data.

[0086] Step 120: selecting a subthreshold standard cell type according to the analysis data and performing structural design to obtain a subthreshold standard cell structure.

[0087] Step 130: Determine a target size corresponding to the sub-threshold standard cell structure to obtain a target sub-threshold standard cell.

[0088] In standard cell library design, a rich variety and quantity of cells provide more options for logic synthesis, helping to optimize circuit performance and achieve greater design refinement and flexibility. However, not all cells exhibit good electrical performance and functionality at subthreshold voltages, so library cells need to be screened to ensure strong stability and reliability.

[0089] Step 140: Analyze and optimize the target subthreshold standard cell to obtain an optimized subthreshold standard cell circuit.

[0090] This step may mainly include gate-level unit noise margin and stability analysis, and gate-level unit delay distribution evaluation and optimization.

[0091] Figure 1 The proposed method extracts and analyzes the common parameters of subthreshold standard cells to obtain analysis data. Based on the analysis data, a subthreshold standard cell type is selected and structurally designed to obtain a subthreshold standard cell structure. The target size corresponding to the subthreshold standard cell structure is determined to obtain a target subthreshold standard cell. The target subthreshold standard cell is analyzed and optimized to obtain an optimized subthreshold standard cell circuit. This method improves the non-Gaussian distribution of delay in standard cell circuits at subthreshold voltages. Advanced processes increase CMOS mismatch coefficients at subthreshold voltages, and process fluctuations cause random variations in the chip's physical and electrical parameters. This reduces the noise margin of standard cell circuits suitable for normal operating voltages, worsens delay, and results in a non-Gaussian distribution. This makes subsequent timing analysis difficult to converge, and results in non-Gaussian distributions in large-scale circuits implemented based on the cell. By improving the stability and timing characteristics of the cell circuit, the cell delay approaches a Gaussian distribution, providing technical support for advanced process low-power integrated circuit technology. Therefore, in the design of sub-threshold standard cell circuits, while ensuring sufficient driving capability and low power consumption of the cell, it is necessary to improve the non-Gaussian problem of the cell delay distribution, solve the subsequent design timing convergence problem, and make large-scale circuits closer to the Gaussian distribution, so as to provide a guarantee for the high-energy-efficiency design of digital systems.

[0092] based on Figure 1 The present specification also provides some specific implementation methods of the method, which are described below.

[0093] The solution proposed in this invention is mainly aimed at improving the design of commercial advanced process standard cell libraries at sub-threshold voltages, which can improve cell stability and make gate-level circuits tend to Gaussian distribution; it is achieved through comprehensive extraction of common technologies such as transistor gate length, optimal energy consumption point voltage, characteristic structure pre-analysis, cell type and structure, optimal size design, stability evaluation, delay distribution evaluation and optimization, etc. Figure 2 It is the design flow chart of the present invention, such as Figure 2 As shown, the process begins with the analysis and extraction of common parameters of sub-threshold units, followed by sub-threshold unit type screening and structural design, and sub-threshold unit optimal size design, and then sub-threshold unit stability analysis. If the stability does not meet the requirements, the sub-threshold optimal size design is readjusted until the stability meets the requirements; when the stability meets the requirements, the sub-threshold unit delay distribution evaluation and optimization are continued. When the optimization does not meet the conditions, the sub-threshold optimal size design is readjusted until the optimization meets the conditions and the process ends.

[0094] Next, combine Figure 1 as well as Figure 2 The specific implementation means of each implementation step are further explained:

[0095] In step 110, common parameters of the sub-threshold standard cell are extracted and analyzed to obtain analysis data, which may specifically include:

[0096] Determine the gate length of the transistor based on the short channel and anti-short channel effect of the transistor at subthreshold voltage;

[0097] Construct the optimal energy consumption circuit and determine the optimal energy consumption point voltage;

[0098] Analyze the characteristic structure in the basic logical structure unit to make a preliminary judgment on the stability.

[0099] For the above steps, the gate length of the transistor is determined based on the short channel and anti-short channel effect of the transistor at the subthreshold voltage. The specific implementation process is as follows:

[0100] Determine the subthreshold voltage of the library unit, simulate the threshold voltage of the PMOS transistor and the NMOS transistor, and determine the trend of the threshold being affected by the change of transistor size and the threshold voltage range;

[0101] Scan the influence of transistor gate width and gate length on threshold voltage respectively, and determine the adjustment range of gate length and gate width;

[0102] The gate length of the transistor is determined based on the short channel and anti-short channel effects of the transistor at subthreshold voltage.

[0103] Specifically, one of the most effective ways to reduce chip power consumption is to lower the circuit operating voltage. To determine the subthreshold voltage of the library unit, it is first necessary to simulate the threshold voltage of the PMOS transistor and the NMOS transistor to determine the trend of their threshold being affected by changes in transistor size and the threshold voltage range. The influence of the transistor gate width and gate length on its threshold voltage is scanned separately to determine the adjustment range of the gate length and gate width, thereby ensuring that its threshold voltage variation is within a certain range. Next, the gate length of the transistor is determined based on the short channel and anti-short channel effect of the transistor at the subthreshold voltage.

[0104] Short Channel Effect (SCE): When the channel length of a transistor is shortened to near or below a certain threshold, its electrical characteristics will change significantly. For example, it may cause the threshold voltage to decrease, which in turn increases leakage current and negatively affects power consumption.

[0105] Reverse Short Channel Effect (RSCE): This phenomenon occurs when a transistor's channel length decreases, but the threshold voltage (Vth) increases. This increase in threshold voltage reduces leakage current, potentially reducing power consumption. The specific variation in transistor threshold voltage with channel length is the result of both the short channel effect and the reverse short channel effect. Therefore, it is necessary to determine the relationship between transistor threshold voltage and channel length at low voltages, thereby deriving the transistor gate length for a high-drive capability.

[0106] Because the mobility of electrons is twice that of holes, the driving capability of an NMOS transistor of the same size is approximately twice that of a PMOS transistor at standard voltage. As the power supply voltage decreases, the transistor's operating state gradually transitions from the saturation region to the linear region, causing its output current to change significantly. When the power supply voltage is lower than the transistor's threshold voltage, the transistor's current will vary exponentially with the power supply voltage, as shown in Equation (1).

[0107]

[0108] Among them, Weff is the effective channel width of the transistor, Leff is the effective channel length of the transistor, Ncheff is the effective channel doping, μ is the carrier mobility, ε si is the dielectric constant, Φs is the surface potential, m is the body bias effect coefficient, Vgs is the gate-source voltage, Vds is the drain-source voltage, V T is the thermal voltage.

[0109] The subthreshold region transistor current decreases as the power supply voltage decreases. When the power supply voltage is lower than the transistor threshold voltage, the current will decrease exponentially. At the subthreshold voltage, the driving capability of the transistor is significantly weakened. Therefore, in order to ensure the normal performance of the unit, it is necessary to simulate the transfer curve of the transistor in the subthreshold region, such as Figure 3, and reasonably design its structure and size.

[0110] In the above steps, the optimal energy consumption circuit is constructed and the optimal energy consumption point voltage is determined. The specific implementation process is as follows:

[0111] Construct an optimal energy consumption circuit and determine the optimal energy consumption point voltage, including:

[0112] Build an optimal energy consumption circuit through multiple sets of preset level ring oscillator circuits;

[0113] Simulation is performed based on the optimal energy consumption circuit, and the optimal energy consumption point voltage is determined based on the simulation result.

[0114] More specifically, there is an optimal power supply voltage in the optimal energy consumption point theory, which minimizes the total energy consumption of the circuit. The optimal power supply voltage of the system is usually lower than the threshold voltage of the transistor. This design can not only minimize the energy consumption of the circuit, but also provide an effective solution for modern low-power integrated circuits. After determining the gate length of the transistor, the optimal energy consumption point circuit is constructed by 10 groups of 101-level ring oscillator circuits (NAND gates / NOR gates), such as Figure 4 By inputting different signals into the ring oscillator circuit, we can effectively control the switching activity factor, change the circuit's flip-flop rate, and influence the ratio of dynamic to static energy consumption. By estimating circuit energy consumption using different switching activity factors, we can find the optimal power supply voltage range.

[0115] It should be noted that since the optimal energy consumption point is affected by many factors, such as the circuit's output load, duty cycle, circuit structure, input signal, and temperature, a certain voltage margin needs to be retained to improve circuit performance.

[0116] In the above steps, the characteristic structure in the basic logical structure unit is analyzed to achieve a preliminary judgment on stability. The specific implementation process is as follows:

[0117] A static complementary CMOS structure is adopted as the basic logic structure. According to the circuit structure of the pull-up network and the pull-down network, the characteristic structure of the basic logic structure is divided into multiple circuit structure types. The circuit structure types include at least NMOS transistors, PMOS transistors, and multiple stages of NMOS transistors and PMOS transistors connected in series.

[0118] More specifically, the basic logic structure unit usually uses a static complementary CMOS structure due to its simple structure; in order to reduce the number of simulations for the optimal size design of the unit circuit, the structure of the unit can be deeply analyzed.

[0119] According to the circuit structure of the pull-up network and the pull-down network, the characteristic structure of the unit is divided into 6 types: NMOS, PMOS, two-stage series NMOS, two-stage series PMOS, three-stage series NMOS and three-stage series PMOS. The structure is shown in the figure below. Figure 5 The stability of the library cell depends on the matching of the driving capabilities between the PMOS pull-up network and the pull-down network. Analyzing the relative driving capabilities of these structures allows for a preliminary assessment of the library cell's stability and guides subsequent optimization of the library cell circuit size.

[0120] Step 120 may specifically include:

[0121] Select basic logic structure units that meet preset conditions based on fan-in type, unit structure, and power consumption;

[0122] It uses static complementary CMOS structure as the basic logic structure and preset transmission gate as the structure of complex unit;

[0123] The subthreshold standard cell structure is determined based on the basic logic structure units and complex cells that meet the preset conditions.

[0124] More specifically, the principles for screening subthreshold standard cell structures include at least:

[0125] Basic logic structure units should be of 1 to 2 fan-in type, and units with large fan-in such as NAND4 and NOR4 should be eliminated; complex logic units should be appropriately selected, and overly complex and power-intensive sequential units should be eliminated. For example, sequential units such as triggers should be of a type with fewer enable signals.

[0126] For simple basic logic structures such as INV, NAND2, and NOR2, a traditional static complementary CMOS structure is directly used. For more complex units such as XOR2, DFF, and MUX2, to ensure high stability at subthreshold voltages, a transmission gate structure with better performance at low voltages is used. Furthermore, transmission gates are less sensitive to process variations, allowing for smaller sizes, thereby reducing circuit load and power consumption.

[0127] Step 130, when implemented specifically, may include:

[0128] Analyze the most vulnerable working state of each type of cell in the subthreshold standard cell structure, and select the working state with the weakest driving capability and the largest delay based on the charge and discharge current analysis results;

[0129] Adjust transistor size, optimize the matching of pull-up and pull-down networks, and determine the optimal size range of unit transistors;

[0130] Within the optimal size range of the unit transistor, the target size corresponding to the sub-threshold standard cell structure is determined by the objective function.

[0131] More specifically, first, because the threshold of the transistor is affected by the anti-short channel effect at low voltage, there is a certain gate length condition under which the driving current of the transistor is larger. Therefore, this gate length can be determined as the uniform channel length of the transistor. The steps for designing the optimal unit size are as follows:

[0132] First, it's necessary to determine the unit's most vulnerable operating state. Analyze the most vulnerable operating state for each unit type and, based on the charge / discharge current analysis results, select the operating state with the weakest drive capability and the greatest delay. Analyze the unit's circuit structure under this most vulnerable operating state. If the unit's most vulnerable operating state exhibits good stability, it can be inferred that the other states will also be stable.

[0133] Next, the driving capabilities of the pull-up and pull-down networks are matched. Based on the six characteristic structures mentioned above, the designed unit is structurally analyzed to evaluate whether it meets the defined characteristic structures. By adjusting the channel width of the transistor, the driving capabilities of the pull-up and pull-down networks are balanced to ensure the normal function of the unit. In this process, by adjusting the transistor size and optimizing the matching of the pull-up and pull-down networks, the optimal size range of the unit transistor is determined to ensure the performance stability of the circuit under different operating conditions.

[0134] Finally, the unit objective function analysis is performed. The unit design needs to comprehensively consider factors such as stability, energy consumption, delay, and area. After completing the above steps, the size of the unit transistor can be determined by the objective function. The objective function is shown in formula (2):

[0135] f(I, D)=I*D (2)

[0136] Here, I is the unit current, circuit energy consumption E = I * V, and V is the power supply voltage, indicating that the current I is proportional to the energy consumption E. Furthermore, the circuit energy consumption is also proportional to the unit area. D is the unit delay, which is the average of the rise delay and fall delay. Since the unit current and unit delay are inversely proportional, the objective function can be minimized by adjusting the transistor channel width, which is the optimal objective function.

[0137] Finally, considering the three steps of optimal unit size design discussed above, a compromise is made to select the unit size with equivalent pull-up / pull-down network driving capability and smaller objective function as the optimal unit size at this time when the unit is most prone to failure. The stability evaluation and delay distribution evaluation are then performed.

[0138] When step 140 is specifically implemented, it may include:

[0139] Based on the static noise margin, the voltage transfer characteristic curve of the target subthreshold standard cell in the most vulnerable operating state is simulated. Under the first preset error input and second preset error output, Monte Carlo analysis is performed on different operating modes of the library cell, taking into account process deviation, temperature variation, and voltage jitter. The simulation results are then judged based on the 3σ principle to determine whether they meet the functional correctness evaluation criteria.

[0140] If the noise tolerance simulation and stability simulation of the unit meet the requirements, the modified unit size is the optimal value;

[0141] The delay distribution data is obtained through Monte Carlo simulation, and the fitting curve of the delay distribution data is analyzed. The unit size is fine-tuned so that the rising transmission delay and the falling transmission delay are close to the preset optimal value, and the delay distribution is closer to the Gaussian distribution. The simulation is iterated until the unit with the optimal size meets the noise tolerance and delay distribution evaluation criteria, and the optimized sub-threshold standard unit circuit is obtained.

[0142] Next, the gate-level unit noise tolerance and stability analysis, as well as the gate-level unit delay distribution evaluation and optimization implementation are described in detail:

[0143] For gate-level unit noise margin and stability analysis: Static noise margin (SNM) is a measure of the ability of a digital circuit to maintain correct output under the worst input conditions and is an important parameter for evaluating unit stability. The voltage transfer characteristic curve of the unit's most vulnerable working state is simulated to evaluate the unit noise, such as Figure 6 The larger the noise tolerance, the stronger the unit's resistance to external noise and the higher the stability. After the unit circuit design is completed, the stability of the unit needs to be evaluated. The standard for stability evaluation is: when the input error is 20%, the output error shall not exceed 10%. Taking into account process deviations, temperature changes, and voltage jitter, Monte Carlo analysis is performed on different working modes of the library unit, and the simulation results are judged based on the 3σ principle to determine whether they meet the evaluation criteria for functional correctness. [6] If the noise tolerance simulation and stability simulation of the unit meet the requirements, the modified unit size is the optimal value.

[0144] Evaluation and optimization of gate-level unit delay distribution: The rise delay and fall delay of the unit are determined by the driving capabilities of its pull-up network and pull-down network respectively. The delay distribution curve of the unit can be presented through Monte Carlo simulation. Therefore, after completing the above evaluation of the unit, its delay distribution data can be obtained through Monte Carlo simulation, and the mean, standard deviation (3σ), and +3σ / -3σ values ​​of its fitting curve can be analyzed. By fine-tuning the unit size, its rise transmission delay and fall transmission delay reach the optimal value, and the delay distribution is closer to the Gaussian distribution. Figure 7If the designed unit size does not meet the above standards, the unit needs to be re-simulated and iterated until the unit with the optimal size meets the noise tolerance and delay distribution evaluation standards.

[0145] The technical solution provided by the present invention improves the delay distribution of commercial advanced process standard cell circuits to a Gaussian distribution, while ensuring sufficient driving capability and low power consumption of subthreshold standard cell structure circuits, thereby resolving the problem of difficult timing convergence of subthreshold circuits. The present invention proposes a method for extracting common technologies, optimizing structure and transistor size design for commercial advanced process standard cell libraries under subthreshold voltages, improving cell circuit stability and making gate-level cell circuit delays tend to a Gaussian distribution. This method is achieved through the extraction of common technologies such as transistor gate length, optimal energy consumption point voltage, and characteristic structure pre-analysis, as well as cell type selection and structural design, and optimal size design.

[0146] The present invention proposes a delay distribution evaluation and optimization method for gate-level standard cells based on advanced processes, which includes stability evaluation, delay distribution evaluation and optimization, and ensures that the cell delay distribution tends to Gaussian distribution.

[0147] Based on the same idea, the present invention also provides a sub-threshold standard unit circuit optimization device, such as Figure 8 As shown, the device may include:

[0148] A common parameter analysis module 810 is used to extract and analyze common parameters of sub-threshold standard cells to obtain analysis data;

[0149] A subthreshold standard cell structure design module 820 is configured to select a subthreshold standard cell type based on the analysis data and perform structural design to obtain a subthreshold standard cell structure;

[0150] A target size determination module 830 is configured to determine a target size corresponding to a subthreshold standard cell structure and obtain a target subthreshold standard cell;

[0151] The sub-threshold standard cell circuit optimization module 840 is configured to analyze and optimize the target sub-threshold standard cell to obtain an optimized sub-threshold standard cell circuit.

[0152] based on Figure 8 The device may further include some specific implementation units:

[0153] Optionally, the common parameter analysis module 810 may include:

[0154] A transistor gate length determining unit, configured to determine the gate length of the transistor according to the short channel and anti-short channel effects of the transistor at a subthreshold voltage;

[0155] An optimal energy consumption point voltage determination unit, used to construct an optimal energy consumption circuit and determine the optimal energy consumption point voltage;

[0156] The preliminary stability judgment unit is used to analyze the characteristic structure in the basic logical structure unit to achieve preliminary stability judgment.

[0157] Optionally, the sub-threshold standard cell structure design module 820 may include:

[0158] A basic logic structure unit selection unit is used to select a basic logic structure unit that meets preset conditions according to fan-in type, unit structure, and power consumption;

[0159] A structure setting unit for adopting a static complementary CMOS structure as a basic logic structure and a preset transmission gate as a structure of a complex unit;

[0160] The sub-threshold standard cell structure determining unit is used to determine the sub-threshold standard cell structure based on the basic logic structure unit and the complex cell that meet the preset conditions.

[0161] Optionally, the target size determination module 830 may include:

[0162] Analyze the most vulnerable working state of each type of cell in the subthreshold standard cell structure, and select the working state with the weakest driving capability and the largest delay based on the charge and discharge current analysis results;

[0163] Adjust transistor size, optimize the matching of pull-up and pull-down networks, and determine the optimal size range of unit transistors;

[0164] Using the formula:

[0165] f(I, D) = I*D

[0166] Within the optimal size range of the unit transistor, the target size corresponding to the subthreshold standard unit structure is determined by the objective function; wherein, I is the unit current, the circuit energy consumption E=I*V, V is the power supply voltage, the unit current is proportional to the circuit energy consumption, and the circuit energy consumption is proportional to the unit area; D is the unit delay, the unit delay is the average of the rise delay and the fall delay, the unit current and the unit delay are inversely proportional, and the minimum value is determined based on the objective function by adjusting the channel width of the transistor.

[0167] Optionally, the sub-threshold standard cell circuit optimization module 840 may be used to:

[0168] Based on the static noise margin, the voltage transfer characteristic curve of the target subthreshold standard cell in the most vulnerable operating state is simulated. Under the first preset error input and second preset error output, Monte Carlo analysis is performed on different operating modes of the library cell, taking into account process deviation, temperature variation, and voltage jitter. The simulation results are then judged based on the 3σ principle to determine whether they meet the functional correctness evaluation criteria.

[0169] If the noise tolerance simulation and stability simulation of the unit meet the requirements, the modified unit size is the optimal value;

[0170] The delay distribution data is obtained through Monte Carlo simulation, and the fitting curve of the delay distribution data is analyzed. The unit size is fine-tuned so that the rising transmission delay and the falling transmission delay are close to the preset optimal value, and the delay distribution is closer to the Gaussian distribution. The simulation is iterated until the unit with the optimal size meets the noise tolerance and delay distribution evaluation criteria, and the optimized sub-threshold standard unit circuit is obtained.

[0171] Optionally, the transistor gate length determining unit may be used to:

[0172] Determine the subthreshold voltage of the library unit, simulate the threshold voltage of the PMOS transistor and the NMOS transistor, and determine the trend of the threshold being affected by the change of transistor size and the threshold voltage range;

[0173] Scan the influence of transistor gate width and gate length on threshold voltage respectively, and determine the adjustment range of gate length and gate width;

[0174] The gate length of the transistor is determined based on the short channel and anti-short channel effects of the transistor at subthreshold voltage.

[0175] Optionally, the optimal energy consumption point voltage determination unit may be used to:

[0176] Build an optimal energy consumption circuit through multiple sets of preset level ring oscillator circuits;

[0177] Performing simulation based on the optimal energy consumption circuit, and determining the optimal energy consumption point voltage based on the simulation result;

[0178] Analyze the characteristic structure of the basic logical structure unit to make a preliminary judgment on the stability, including:

[0179] A static complementary CMOS structure is adopted as the basic logic structure. According to the circuit structure of the pull-up network and the pull-down network, the characteristic structure of the basic logic structure is divided into multiple circuit structure types. The circuit structure types include at least NMOS transistors, PMOS transistors, and multiple stages of NMOS transistors and PMOS transistors connected in series.

[0180] Based on the same idea, the embodiment of this specification also provides a sub-threshold standard cell circuit optimization device. Figure 9 As shown, the device includes:

[0181] A memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be run by the processor; when the processor runs the computer program, it executes the aforementioned sub-threshold standard cell circuit optimization method.

[0182] like Figure 9 As shown, the processor can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. There can be one or more communication interfaces. The communication interface can use any device such as a transceiver for communicating with other devices or a communication network.

[0183] like Figure 9 As shown, the terminal device may further include a communication line. The communication line may include a path for transmitting information between the components.

[0184] Optional, such as Figure 9 As shown, the terminal device may further include a memory. The memory stores a computer program executable by the processor; when the processor executes the computer program, the method provided by the embodiment of the present invention is implemented.

[0185] like Figure 9As shown, the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a communication line. The memory can also be integrated with the processor.

[0186] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0187] In a specific implementation, as an embodiment, Figure 9 As shown, the processor may include one or more CPUs, such as Figure 9 CPU0 and CPU1 in.

[0188] In a specific implementation, as an embodiment, Figure 9 As shown, the terminal device may include multiple processors, such as Figure 9 Each of these processors can be a single-core processor or a multi-core processor.

[0189] Based on the same idea, the embodiments of this specification also provide a computer storage medium corresponding to the above embodiments. The computer storage medium stores instructions, and when the instructions are executed, the method in the above embodiments is implemented.

[0190] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the interaction between the various modules. It can be understood that, in order to realize the above functions, each module includes a hardware structure and / or software unit corresponding to the execution of each function. It should be easy for those skilled in the art to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0191] The embodiments of the present invention can be divided into functional modules according to the above-mentioned method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into a single processing module. The above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present invention is illustrative and is only a logical functional division. In actual implementation, other division methods may be used.

[0192] The processor in this specification may also function as a memory. The memory is used to store computer-executable instructions for implementing the solutions of the present invention, and the processor controls the execution of the instructions. The processor is used to execute the computer-executable instructions stored in the memory, thereby implementing the methods provided in the embodiments of the present invention.

[0193] The memory may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a communication line. The memory may also be integrated with the processor.

[0194] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0195] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor or by software instructions. The above processor may be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The methods, steps, and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in conjunction with the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor or by a combination of hardware and software modules in the decoding processor. The software modules can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in a memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0196] Although the present invention has been described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0197] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A subthreshold standard cell circuit optimization method, characterized in that the method include: Extracting and analyzing the common parameters of subthreshold standard cells to obtain analytical data; Selecting a subthreshold standard cell type and performing structural design based on the analysis data to obtain a subthreshold standard cell structure; determining a target size corresponding to a subthreshold standard cell structure, and obtaining a target subthreshold standard cell; The target subthreshold standard cell is analyzed and optimized to obtain an optimized subthreshold standard cell circuit.

2. The subthreshold standard cell circuit optimization method according to claim 1, characterized in that: Extract and analyze the common parameters of subthreshold standard cells to obtain analytical data, including: Determine the gate length of the transistor based on the short channel and anti-short channel effect of the transistor at subthreshold voltage; Construct the optimal energy consumption circuit and determine the optimal energy consumption point voltage; Analyze the characteristic structure in the basic logical structure unit to make a preliminary judgment on the stability.

3. The subthreshold standard cell circuit optimization method according to claim 2, characterized in that: Selecting a subthreshold standard cell type and performing structural design based on the analysis data to obtain a subthreshold standard cell structure includes: Select basic logic structure units that meet preset conditions based on fan-in type, unit structure, and power consumption; It uses static complementary CMOS structure as the basic logic structure and preset transmission gate as the structure of complex unit; The subthreshold standard cell structure is determined based on the basic logic structure units and complex cells that meet the preset conditions.

4. The subthreshold standard cell circuit optimization method according to claim 1, characterized in that: Determining a target size corresponding to a subthreshold standard cell structure to obtain a target subthreshold standard cell includes: Analyze the most vulnerable working state of each type of cell in the subthreshold standard cell structure, and select the working state with the weakest driving capability and the largest delay based on the charge and discharge current analysis results; Adjust transistor size, optimize the matching of pull-up and pull-down networks, and determine the optimal size range of unit transistors; Using the formula: f(I, D) = I*D Within the optimal size range of the unit transistor, the target size corresponding to the subthreshold standard unit structure is determined by the objective function; wherein, I is the unit current, the circuit energy consumption E=I*V, V is the power supply voltage, the unit current is proportional to the circuit energy consumption, and the circuit energy consumption is proportional to the unit area; D is the unit delay, the unit delay is the average of the rise delay and the fall delay, the unit current and the unit delay are inversely proportional, and the minimum value is determined based on the objective function by adjusting the channel width of the transistor.

5. The subthreshold standard cell circuit optimization method according to claim 2, characterized in that: Analyzing and optimizing the target subthreshold standard cell to obtain an optimized subthreshold standard cell circuit includes: Based on the static noise margin, the voltage transfer characteristic curve of the target subthreshold standard cell in the most vulnerable operating state is simulated. Under the first preset error input and second preset error output, Monte Carlo analysis is performed on different operating modes of the library cell, taking into account process deviation, temperature variation, and voltage jitter. The simulation results are then judged based on the 3σ principle to determine whether they meet the functional correctness evaluation criteria. If the noise tolerance simulation and stability simulation of the unit meet the requirements, the modified unit size is the optimal value; The delay distribution data is obtained through Monte Carlo simulation, and the fitting curve of the delay distribution data is analyzed. The unit size is fine-tuned so that the rising transmission delay and the falling transmission delay are close to the preset optimal value, and the delay distribution is closer to the Gaussian distribution. The simulation is iterated until the unit with the optimal size meets the noise tolerance and delay distribution evaluation criteria, and the optimized sub-threshold standard unit circuit is obtained.

6. The subthreshold standard cell circuit optimization method according to claim 5, characterized in that: The gate length of the transistor is determined based on the short channel and anti-short channel effect of the transistor at subthreshold voltage, including: Determine the subthreshold voltage of the library unit, simulate the threshold voltage of the PMOS transistor and the NMOS transistor, and determine the trend of the threshold being affected by the change of transistor size and the threshold voltage range; Scan the influence of transistor gate width and gate length on threshold voltage respectively, and determine the adjustment range of gate length and gate width; The gate length of the transistor is determined based on the short channel and anti-short channel effects of the transistor at subthreshold voltage.

7. The subthreshold standard cell circuit optimization method according to claim 2, characterized in that: Construct an optimal energy consumption circuit and determine the optimal energy consumption point voltage, including: Build an optimal energy consumption circuit through multiple sets of preset level ring oscillator circuits; Performing simulation based on the optimal energy consumption circuit, and determining the optimal energy consumption point voltage based on the simulation result; Analyze the characteristic structure of the basic logical structure unit to make a preliminary judgment on the stability, including: A static complementary CMOS structure is adopted as the basic logic structure. According to the circuit structure of the pull-up network and the pull-down network, the characteristic structure of the basic logic structure is divided into multiple circuit structure types. The multiple circuit structure types include at least NMOS transistors, PMOS transistors, and multiple stages of NMOS transistors and PMOS transistors connected in series.

8. A subthreshold standard cell circuit optimization device, characterized in that: The device includes: A common parameter analysis module is used to extract and analyze the common parameters of sub-threshold standard cells to obtain analysis data; a subthreshold standard cell structure design module, configured to select a subthreshold standard cell type and perform structural design based on the analysis data to obtain a subthreshold standard cell structure; a target size determination module, configured to determine a target size corresponding to a subthreshold standard cell structure and obtain a target subthreshold standard cell; The sub-threshold standard cell circuit optimization module is used to analyze and optimize the target sub-threshold standard cell to obtain an optimized sub-threshold standard cell circuit.

9. A subthreshold standard cell circuit optimization device, characterized in that the device include: a memory, a processor, and a communication interface coupled to the processor; The memory stores a computer program executable by the processor; When the processor runs the computer program, it executes the sub-threshold standard cell circuit optimization method according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that The computer storage medium stores instructions, and when the instructions are executed by the processor, the sub-threshold standard cell circuit optimization method according to any one of claims 1 to 7 is implemented.

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