Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display, and the display panel comprises an array substrate and a conductive isolation layer. The conductive isolation layer is located on one side of the array substrate and comprises an isolation structure and a touch electrode which are arranged on the same layer, and the isolation structure is insulated from the adjacent touch electrode; the touch electrodes are configured as self-capacitance detection electrodes. According to the display panel, the isolation structure and the touch control electrode are arranged on the same layer of one side of the array substrate, the isolation structure does not need to be reused, touch control of the display panel can be completed through the touch control electrode, the cost of the display panel can be reduced, the thickness of the display panel can be reduced, and the purpose that the display panel is light and thin can be achieved more easily.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing a display panel, and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display panels.

[0003] However, there are still some problems with display panels that need to be solved urgently. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel, wherein the display panel includes:

[0005] array substrate;

[0006] a conductive isolation layer located on one side of the array substrate, the conductive isolation layer including an isolation structure and touch electrodes arranged on the same layer, the isolation structure being insulated from adjacent touch electrodes;

[0007] The touch electrodes are configured as self-capacitance detection electrodes.

[0008] In some possible implementations, at least some of the touch electrodes include first touch trace segments extending along a first direction, a plurality of the first touch trace segments arranged along a second direction are electrically connected via jumper traces, the jumper traces and the first touch trace segments are located in different film layers of the display panel, and the first direction intersects the second direction;

[0009] Preferably, the orthographic projections of the first touch sensing trace segments and the jumper traces on the array substrate are in a mesh structure;

[0010] Preferably, the isolation structure comprises a plurality of isolation units arranged at intervals, and the isolation units extend along the first direction;

[0011] Preferably, the orthographic projection of the first touch trace segment on the array substrate is located between the orthographic projections of two adjacent isolation units on the array substrate;

[0012] Preferably, the jumper trace extends along the second direction;

[0013] Preferably, the first direction is perpendicular to the second direction.

[0014] In some possible implementations, along the second direction, the width of the orthographic projection of the first touch trace segment on the array substrate ranges from 5 μm to 15 μm;

[0015] Preferably, the minimum distance between the first touch sensing trace segment and the isolation structure is 10 μm-30 μm.

[0016] In some possible implementations, at least some of the touch electrodes include a first touch trace segment extending along a first direction and a second touch trace segment extending along a second direction, and the second touch trace segment is electrically connected to the first touch trace segment.

[0017] In some possible implementations, the orthographic projections of the first touch trace segment and the second touch trace segment on the array substrate intersect crosswise;

[0018] Preferably, the orthographic projections of the same first touch trace segment and a plurality of second touch trace segments arranged along the second direction on the array substrate intersect crosswise;

[0019] The orthographic projections of the first touch trace segment and the second touch trace segment on the array substrate are in a mesh structure;

[0020] Along the first direction, the width of the orthographic projection of the second touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm;

[0021] Preferably, the minimum distance between the second touch sensing trace segment and the isolation structure is 10 μm-30 μm.

[0022] In some possible embodiments, the isolation structure includes a plurality of isolation units arranged at intervals, at least some of the second touch trace segments are arranged at intervals, and adjacent second touch trace segments arranged along the second direction are electrically connected via jumper traces; along the first direction, at least some of the adjacent isolation units are electrically connected via first connecting traces, the jumper traces and the second touch trace segments are located in different film layers in the display panel, and the orthographic projection of the jumper traces on the array substrate at least partially overlaps with the orthographic projection of the first connecting traces on the array substrate; and / or

[0023] Along the first direction, at least some of the adjacent isolation units are electrically connected via a jumper wire, the jumper wire and the isolation structure are located in different film layers in the display panel, and an orthographic projection of the second touch sensing wire segment on the array substrate at least partially overlaps with an orthographic projection of the jumper wire on the array substrate;

[0024] Preferably, along the first direction, the width of the first connecting trace on the array substrate is in a range of 3 μm to 10 μm;

[0025] Preferably, the display panel further includes second connecting wires extending along the second direction, and the second connecting wires are electrically connected to the isolation units arranged along the second direction.

[0026] In some possible implementations, the display panel further includes a light-emitting pixel located on one side of the array substrate, and the orthographic projections of at least part of the first touch trace segments and / or at least part of the second touch trace segments on the array substrate surround the orthographic projections of the light-emitting pixel on the array substrate;

[0027] Preferably, the light-emitting pixel includes at least one light-emitting sub-pixel;

[0028] Preferably, the light-emitting sub-pixel includes a red light-emitting sub-pixel, a blue light-emitting sub-pixel, or a green light-emitting sub-pixel.

[0029] In some possible implementations, the array substrate includes a substrate, the array substrate includes a substrate and a conductive layer located on one side of the substrate, and the jumper trace is located on the conductive layer;

[0030] Preferably, along a direction away from the substrate, the conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence;

[0031] Preferably, the jumper traces are respectively located in the same film layer or different film layers among the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer; and / or, the display panel further includes a first electrode layer located on one side of the array substrate, and the jumper traces are located in the first electrode layer;

[0032] Preferably, an insulating layer is provided between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, between the third conductive layer and the fourth conductive layer, and between the fourth conductive layer and the first electrode layer;

[0033] Preferably, a via is formed on the insulating layer in a direction away from the substrate, and the via exposes at least a portion of the jumper trace.

[0034] In some possible embodiments, the display panel further includes a light-emitting functional layer and a second electrode layer located on a side of the first electrode layer away from the array substrate and stacked sequentially in a direction away from the array substrate, and the second electrode layer is electrically connected to the isolation structure;

[0035] Preferably, the isolation structure encloses an isolation opening, the first electrode layer includes a first electrode at least partially located within the isolation opening, the light-emitting functional layer includes a light-emitting portion located within the isolation opening, the second electrode layer includes a second electrode at least partially located within the isolation opening, and the second electrode is electrically connected to the isolation structure.

[0036] In some possible embodiments, the display panel further includes a pixel defining layer located on one side of the array substrate, the conductive isolation layer is located on a side of the pixel defining layer away from the array substrate, the pixel defining layer includes a pixel opening exposing at least a portion of the first electrode, and an orthographic projection of the isolation structure on the array substrate is located between orthographic projections of two adjacent pixel openings on the array substrate;

[0037] Preferably, the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate;

[0038] Preferably, the first electrode comprises an anode;

[0039] Preferably, the second electrode comprises a cathode.

[0040] In some possible implementations, the display panel further includes a first encapsulation layer located on a side of the second electrode layer away from the array substrate, the first encapsulation layer including a plurality of encapsulation units spaced apart from each other, the encapsulation units extending from a side of the isolation structure to a side of the isolation structure away from the array substrate;

[0041] Preferably, two adjacent packaging units are spaced apart on a side of the isolation structure away from the array substrate;

[0042] Preferably, a distance exists between a side of the packaging unit close to the isolation structure and a side of the isolation structure away from the array substrate;

[0043] Preferably, the material of the first encapsulation layer includes an inorganic material.

[0044] In some possible embodiments, the isolation structure includes a plurality of isolation units spaced apart, each isolation unit including a first isolation portion and a second isolation portion stacked in sequence in a direction away from the array substrate, wherein the orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate.

[0045] In some possible implementations, the second electrode is electrically connected to the first isolation portion; and / or the isolation unit further includes a third isolation portion located on a side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion;

[0046] Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

[0047] In some possible implementations, the present application further provides a method for preparing a display panel, the method comprising:

[0048] providing an array substrate;

[0049] forming a conductive isolation layer on one side of the array substrate, the conductive isolation layer including an isolation structure and touch electrodes arranged on the same layer, and the isolation structure and the adjacent touch electrodes being insulated from each other;

[0050] The touch electrodes are configured as self-capacitance detection electrodes.

[0051] In some possible implementations, the present application further provides an electronic device, which includes the display panel described in the present application.

[0052] Compared with the prior art, this application has the following beneficial effects:

[0053] The present application provides a display panel, a method for preparing a display panel, and an electronic device. By arranging an isolation structure and a touch electrode in the same layer on one side of an array substrate, there is no need to reuse the isolation structure. The touch control of the display panel can be completed through the touch electrode, which not only reduces the cost of the display panel, but also reduces the thickness of the display panel, thereby making it easier to achieve the goal of making the display panel lighter and thinner. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0055] Figure 1 A schematic cross-sectional view of a display panel in the related art provided in an embodiment of the present application;

[0056] Figure 2 This is one of the schematic top views of the conductive isolation layer provided in an embodiment of the present application;

[0057] Figure 3 This is one of the cross-sectional schematic diagrams of a display panel provided in an embodiment of the present application;

[0058] Figure 4The second cross-sectional schematic diagram of the display panel provided in the embodiment of the present application;

[0059] Figure 5 Provided in the embodiments of this application Figure 2 A magnified schematic diagram of point A in the middle;

[0060] Figure 6 Provided in the embodiments of this application Figure 5 One of the cross-sectional diagrams at AA in the middle;

[0061] Figure 7 Provided in the embodiments of this application Figure 5 The second cross-sectional diagram at AA in the middle;

[0062] Figure 8 Provided in the embodiments of this application Figure 5 The third cross-sectional diagram at AA in the middle;

[0063] Figure 9 Provided in the embodiments of this application Figure 5 The fourth cross-sectional diagram at AA in the middle;

[0064] Figure 10 Provided in the embodiments of this application Figure 5 The fifth cross-sectional diagram at AA in the middle;

[0065] Figure 11 A second schematic top view of a conductive isolation layer provided in an embodiment of the present application;

[0066] Figure 12 Provided in the embodiments of this application Figure 11 A magnified schematic diagram of point B in the middle;

[0067] Figure 13 Provided in the embodiments of this application Figure 12 One of the cross-sectional diagrams at the middle BB;

[0068] Figure 14 Provided in the embodiments of this application Figure 12 The second cross-sectional diagram at the middle BB;

[0069] Figure 15 Provided in the embodiments of this application Figure 12 The third cross-sectional diagram at the middle BB;

[0070] Figure 16 Provided in the embodiments of this application Figure 12 The fourth cross-sectional diagram at the middle BB;

[0071] Figure 17 Provided in the embodiments of this application Figure 12 The fifth cross-sectional diagram at the middle BB;

[0072] Figure 18 Provided in the embodiments of this application Figure 11 The enlarged schematic diagram of point C in the middle;

[0073] Figure 19 Provided in the embodiments of this application Figure 18 One of the cross-sectional diagrams at CC;

[0074] Figure 20 Provided in the embodiments of this application Figure 18 The second cross-sectional diagram at CC;

[0075] Figure 21 Provided in the embodiments of this application Figure 18 The third cross-sectional diagram at CC;

[0076] Figure 22 Provided in the embodiments of this application Figure 18 The fourth cross-sectional diagram at CC;

[0077] Figure 23 Provided in the embodiments of this application Figure 18 Sectional diagram of CC in the middle part 5;

[0078] Figure 24 The display panel provided in the embodiment of the present application includes a cross-sectional schematic diagram of a first encapsulation layer;

[0079] Figure 25 A schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present application.

[0080] Reference numerals: 1, array substrate; 101, substrate; 102, buffer layer; 103, gate insulating layer; 104, capacitor dielectric layer; 105, interlayer insulating layer; 106, first planarizing layer; 107, second planarizing layer; 108, semiconductor layer; 109, first conductive layer; 110, second conductive layer; 111, third conductive layer; 112, fourth conductive layer; 2, touch emitting electrode; 3, touch receiving electrode; 4, touch insulating layer; 5, optical adhesive layer; 6, conductive isolation layer; 7, isolation unit element; 71. first isolation portion; 72. second isolation portion; 73. third isolation portion; 8. touch electrode; 81. first touch trace segment; 82. second touch trace segment; 9. jumper trace; 10. light-emitting sub-pixel; 11. second connection trace; 12. pixel defining layer; 13. isolation opening; 14. first electrode; 15. light-emitting portion; 16. second electrode; 17. pixel opening; 18. isolation structure; 19. via; 20. first connection trace; 21. first packaging layer; 211. packaging unit. DETAILED DESCRIPTION

[0081] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0082] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without making any creative efforts shall fall within the scope of protection of the present application.

[0083] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0084] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0085] It should be noted that, in the absence of conflict, different features in the embodiments of the present application can be combined with each other.

[0086] See Figure 1 The display panel in the related art includes an array substrate 1, an encapsulation layer located on one side of the array substrate 1, a touch emitting electrode 2 located on the side of the encapsulation layer away from the array substrate 1, a touch insulating layer 4 located on the side of the touch emitting electrode 2 away from the array substrate 1, a touch receiving electrode 3 located on the side of the touch insulating layer 4 away from the array substrate 1, and an optical adhesive layer 5 located on the side of the touch receiving electrode 3 away from the array substrate 1. Forming the touch emitting electrode 2, the touch insulating layer 4, the touch receiving electrode 3, and the optical adhesive layer 5 each requires a mask. Therefore, at least four masks are required to form the touch film layer of the display panel. This not only increases the cost of the display panel but also makes it thicker, making it difficult to achieve the goal of making the display panel thinner and lighter.

[0087] In view of this, this embodiment provides a solution that can improve the reliability of the display panel. The solution provided by this embodiment is described in detail below.

[0088] See Figure 2-Figure 3 This embodiment provides a display panel, which includes an array substrate 1 and a conductive isolation layer 6.

[0089] The array substrate 1 may include a substrate and multiple drive units located on one side of the substrate. Each drive unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the cooperation of multiple film layers in the array substrate 1. For example, the semiconductor switching devices may be thin film transistors formed by the cooperation of multiple film layers.

[0090] The conductive isolation layer 6 is located on one side of the array substrate 1 . The conductive isolation layer 6 includes an isolation structure 18 and touch electrodes 8 arranged on the same layer. The isolation structure 18 is insulated from adjacent touch electrodes 8 . The touch electrodes 8 are configured as self-capacitance detection electrodes.

[0091] The composition, preparation, etc. of the isolation structure 18 are further described in patents PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 for reference.

[0092] At the same time as the isolation structure 18 is formed, the touch electrode 8 is formed, and the touch electrode 8 is configured as a self-capacitance detection electrode. In this way, compared with the solution in the related art that requires at least four masks to set the touch film layer, the present embodiment can reduce the number of masks for setting the touch film layer, thereby reducing the manufacturing cost of the display panel. In addition, compared with the solution in the related art where the touch electrodes 8 are located on different layers and a touch insulating layer 4 is required to separate the touch electrodes 8 of different layers, thereby resulting in a relatively thick display panel in the related art, the touch electrodes 8 in the present embodiment can be self-capacitance electrodes, and all touch electrodes 8 are set on the same layer, thereby greatly reducing the thickness of the display panel.

[0093] In addition, in this embodiment, the isolation structure 18 does not need to be reused, and the touch function of the display panel can be completed through the touch electrodes 8. Therefore, overly complicated driving and timing coordination are not required.

[0094] Based on the above design, in this embodiment, by setting the isolation structure 18 and the touch electrode 8 on the same layer on one side of the array substrate 1, there is no need to reuse the isolation structure 18. The touch control of the display panel can be completed through the touch electrode 8, which not only reduces the cost of the display panel, but also reduces the thickness of the display panel, thereby making it easier to achieve the goal of making the display panel lighter and thinner.

[0095] For some possible implementations, see again Figure 3 The display panel further includes light-emitting pixels located on one side of the array substrate 1 , and the orthographic projections of at least part of the touch electrodes 8 on the array substrate 1 surround the orthographic projections of the light-emitting pixels on the array substrate 1 .

[0096] Preferably, the luminous pixel includes at least one luminous sub-pixel 10; the luminous sub-pixel 10 includes a red luminous sub-pixel, a blue luminous sub-pixel, or a green luminous sub-pixel. For example, Figure 2 A luminous pixel includes a red luminous sub-pixel, a blue luminous sub-pixel, and a green luminous sub-pixel. Thus, with a luminous pixel as the minimum division unit, at least part of the touch electrode 8 surrounds the luminous pixel.

[0097] For some possible implementations, see again Figure 3 The display panel also includes a first electrode layer, a light-emitting functional layer located on a side of the first electrode layer away from the array substrate 1 and stacked in sequence along a direction away from the array substrate 1, and a second electrode layer, the second electrode layer is electrically connected to the isolation structure 18; the isolation structure 18 encloses to form an isolation opening 13, the first electrode layer includes a first electrode 14 at least partially located in the isolation opening 13, the light-emitting functional layer includes a light-emitting portion 15 located in the isolation opening 13, the second electrode layer includes a second electrode 16 at least partially located in the isolation opening 13, and the second electrode 16 is electrically connected to the isolation structure 18.

[0098] The display panel also includes a pixel defining layer 12 located on one side of the array substrate 1, the conductive isolation layer 6 is located on the side of the pixel defining layer 12 away from the array substrate 1, the pixel defining layer 12 includes a pixel opening 17 exposing at least a portion of the first electrode 14, the orthographic projection of the isolation structure 18 on the array substrate 1 is located between the orthographic projections of two adjacent pixel openings 17 on the array substrate 1; the orthographic projection of the pixel opening 17 on the array substrate 1 is located within the orthographic projection of the isolation opening 13 on the array substrate 1.

[0099] When forming the light-emitting functional layer, the light-emitting functional layer is partitioned by the isolation structure 18 to form a plurality of spaced light-emitting portions 15. When forming the second electrode layer, the second electrode layer is partitioned by the isolation structure 18 to form a plurality of spaced second electrodes 16. The isolation structure 18 includes a conductive material, and the second electrodes 16 are electrically connected to the isolation structure 18. A first electrode 14, a light-emitting portion 15, and a second electrode 16 form a light-emitting sub-pixel 10, wherein the first electrode 14 is an anode and the second electrode 16 is a cathode.

[0100] For some possible implementations, see again Figure 2At least some of the touch electrodes 8 include first touch trace segments 81 extending along the first direction X. Multiple first touch trace segments 81 arranged along the second direction Y are electrically connected via jumper traces 9. The jumper traces 9 and the first touch trace segments 81 are located in different film layers of the display panel. The first direction X intersects the second direction Y. Preferably, the first direction X is perpendicular to the second direction Y.

[0101] The first direction X can be the direction in which the light-emitting pixels are arranged in rows, and the second direction Y can be the direction in which the light-emitting pixels are arranged in columns. The first touch trace segment 81 can extend along the row direction of the light-emitting pixels, with the orthographic projection of the first touch trace segment 81 on the array substrate 1 located between the orthographic projections of two rows of light-emitting pixels on the array substrate 1. The jumper trace 9 extends along the second direction Y and electrically connects multiple rows of first touch trace segments 81 extending along the first direction X. This increases the touch area of ​​the touch electrode 8 and the touch capacitance, thereby improving the touch accuracy of the display panel.

[0102] Preferably, see again Figure 2 The orthographic projections of the first touch trace segments 81 and the jumper traces 9 on the array substrate 1 form a mesh structure. This not only increases the effective touch area of ​​the touch electrodes 8, but also enables direct connection between the touch electrodes 8, significantly improving capacitance.

[0103] Preferably, see again Figure 2 The isolation structure 18 includes a plurality of isolation units 7 spaced apart from each other, each extending along a first direction X. The orthographic projection of the first touch trace segment 81 on the array substrate 1 is located between the orthographic projections of two adjacent isolation units 7 on the array substrate 1. The jumper trace 9 extends along a second direction Y. This further increases the effective touch area of ​​the touch electrode 8.

[0104] For some possible implementations, see Figure 4 The array substrate 1 includes a substrate 101 , and in a direction away from the substrate 101 , the array substrate 1 further includes a first conductive layer 109 , a second conductive layer 110 , a third conductive layer 111 and a fourth conductive layer 112 in sequence.

[0105] The first conductive layer 109, the second conductive layer 110, the third conductive layer 111 and the fourth conductive layer 112 are all metal layers. The array substrate 1 also includes a buffer layer 102 located on one side of the substrate 101 and a semiconductor layer 108 located on the side of the buffer layer 102 away from the substrate 101. The semiconductor layer 108 includes a source region, a drain region and a channel region. The first conductive layer 109 includes a gate and a first capacitor plate. The second conductive layer 110 includes a second capacitor plate. The first capacitor plate and the second capacitor plate form a capacitor. The third conductive layer 111 includes a drain and a source. The drain is electrically connected to the drain region, and the source is electrically connected to the source region. The semiconductor layer, gate, source and drain form a switching device. The metal trace of the fourth conductive layer 112 is connected to the drain, and the metal trace of the fourth conductive layer 112 is further electrically connected to the first electrode 14.

[0106] Preferably, see again Figure 4 Insulating layers are provided between the first conductive layer 109 and the second conductive layer 110 , between the second conductive layer 110 and the third conductive layer 111 , between the third conductive layer 111 and the fourth conductive layer 112 , and between the fourth conductive layer 112 and the first electrode layer.

[0107] The insulating layer includes a gate insulating layer 103, a capacitor dielectric layer 104, an interlayer insulating layer 105 and a first planarizing layer 106. The gate insulating layer 103 is located between the buffer layer 102 and the first conductive layer 109. The capacitor dielectric layer 104 is located between the first conductive layer 109 and the second conductive layer 110. The interlayer insulating layer 105 is located between the second conductive layer 110 and the third conductive layer 111. The first planarizing layer 106 is located between the third conductive layer 111 and the fourth conductive layer 112. The semiconductor layer 108 is located between the buffer layer 102 and the gate insulating layer 103. A second planarizing layer 107 is also provided between the fourth conductive layer 112 and the first electrode layer.

[0108] Preferably, the jumper trace 9 is respectively located in the same film layer or different film layers among the first conductive layer 109, the second conductive layer 110, the third conductive layer 111, the fourth conductive layer 112 and the first electrode layer; and / or, the display panel also includes a first electrode layer located on one side of the array substrate 1, and the jumper trace 9 is located in the first electrode layer; in the direction away from the substrate 101, a via 19 is opened on the insulating layer, and the via 19 exposes at least part of the jumper trace 9.

[0109] In the first example, see Figure 2 、 Figure 5 and Figure 6The first conductive layer 109 includes jumper traces 9. When forming the first conductive layer 109, jumper traces 9 are formed, and vias 19 are opened in the pixel defining layer 12, the second planarizing layer 107, the first planarizing layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. The first touch-sensing trace segments 81 arranged along the second direction Y are electrically connected via the jumper traces 9 located in the first conductive layer 109. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0110] In the second embodiment, see Figure 7 The second conductive layer 110 includes jumper traces 9. When forming the second conductive layer 110, the jumper traces 9 are formed, and vias 19 are opened in the pixel defining layer 12, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. The first touch trace segments 81 arranged along the second direction Y are electrically connected via the jumper traces 9 located in the second conductive layer 110. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0111] In the third embodiment, see Figure 8 The third conductive layer 111 includes jumper traces 9. When forming the third conductive layer 111, jumper traces 9 are formed, and vias 19 are opened in the pixel definition layer 12, the second planarization layer 107, and the first planarization layer 106. The first touch trace segments 81 arranged along the second direction Y are electrically connected via the jumper traces 9 located in the third conductive layer 111. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of installing jumper traces 9.

[0112] In the fourth embodiment, see Figure 9 The fourth conductive layer 112 includes jumper traces 9. When forming the fourth conductive layer 112, jumper traces 9 are formed, and vias 19 are opened in the pixel definition layer 12 and the second planarization layer 107. The first touch trace segments 81 arranged along the second direction Y are electrically connected via the jumper traces 9 located in the fourth conductive layer 112. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0113] In the fifth embodiment, see Figure 10 The first electrode layer includes jumper traces 9. When forming the first electrode layer, jumper traces 9 are formed, and vias 19 are opened in the pixel defining layer 12. The first touch sensing trace segments 81 arranged along the second direction Y are electrically connected via the jumper traces 9 located in the first electrode layer. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0114] For some possible implementations, see again Figure 2Along the second direction Y, the width W1 of the orthographic projection of the first touch trace segment 81 on the array substrate 1 ranges from 5μm to 15μm. For example, the width W1 can be 5μm, 7μm, 10μm, 13μm, or 15μm. If the width W1 is set too large, the spacing between the first touch trace segment 81 and the isolation structure 18 will be reduced, thereby increasing the difficulty of etching the first touch trace segment 81 and the isolation structure 18. If the width W1 is set too small, the touch sensitivity of the display panel will be reduced. Therefore, a reasonable setting of the width W1 can make it easier to etch the first touch trace segment 81 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0115] Preferably, see again Figure 2 The minimum distance D1 between the orthographic projection of the side of the first touch trace segment 81 close to the isolation structure 18 on the array substrate 1 and the orthographic projection of the isolation structure 18 on the array substrate 1 is 10μm-30μm. For example, the minimum distance D1 can be 10μm, 12μm, 15μm, 20μm, 25μm, 28μm, or 30μm. If the minimum distance D1 is set too small, it will increase the difficulty of etching the first touch trace segment 81 and even increase the risk of short circuiting between the first touch trace segment 81 and the isolation structure 18. If the minimum distance D1 is set too large, the area of ​​the first touch trace segment 81 will be reduced, thereby reducing the touch sensitivity of the display panel. Therefore, a reasonable setting of the minimum distance D1 can make it easier to etch the first touch trace segment 81 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0116] For some possible implementations, see Figure 11 At least part of the touch electrodes 8 includes a first touch trace segment 81 extending along the first direction X and a second touch trace segment 82 extending along the second direction Y. The second touch trace segment 82 is electrically connected to the first touch trace segment 81 .

[0117] A second touch trace segment 82 is also provided in the second direction Y, located between the isolation structures 18. The second touch trace segment 82 and the first touch trace segment 81 together form a touch electrode 8. This greatly increases the overlap area between the finger and the touch electrode 8, thereby increasing the capacitance. For example, the finger touch capacitance can be increased from 67fF to 240fF, thereby improving the touch accuracy of the display panel's self-capacitance. Furthermore, the use of underlying circuits as touch electrodes can be reduced, thereby significantly reducing the load on the touch electrodes and, in turn, alleviating the IC driver load.

[0118] For some possible implementations, see again Figure 11The isolation structure 18 includes a plurality of isolation units 7 arranged at intervals, at least some of the second touch trace segments 82 are arranged at intervals, and two adjacent second touch trace segments 82 arranged at intervals are electrically connected via a jumper trace 9; along the first direction X, at least some of the adjacent isolation units 7 are electrically connected via a first connecting trace 20, the jumper trace 9 and the second touch trace segments 82 are located in different film layers in the display panel, and the orthographic projection of the jumper trace 9 on the array substrate 1 at least partially overlaps with the orthographic projection of the first connecting trace 20 on the array substrate 1.

[0119] In the first example, see Figure 12 and Figure 13 The first conductive layer 109 includes a jumper trace 9. When forming the first conductive layer 109, the jumper trace 9 is formed, and vias 19 are opened in the pixel defining layer 12, the second planarizing layer 107, the first planarizing layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. The two spaced-apart second touch trace segments 82 are electrically connected via the jumper trace 9 located in the first conductive layer 109. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of installing jumper traces 9.

[0120] In the second embodiment, see Figure 14 The second conductive layer 110 includes a jumper trace 9. When forming the second conductive layer 110, the jumper trace 9 is formed, and vias 19 are opened in the pixel defining layer 12, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. The two spaced-apart second touch trace segments 82 are electrically connected via the jumper trace 9 located in the second conductive layer 110. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of installing jumper traces 9.

[0121] In the third embodiment, see Figure 15 The third conductive layer 111 includes a jumper trace 9. When forming the third conductive layer 111, the jumper trace 9 is formed, and vias 19 are opened in the pixel definition layer 12, the second planarization layer 107, and the first planarization layer 106. The two spaced-apart second touch trace segments 82 are electrically connected via the jumper trace 9 located in the third conductive layer 111. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of installing jumper traces 9.

[0122] In the fourth embodiment, see Figure 16 The fourth conductive layer 112 includes a jumper trace 9. When forming the fourth conductive layer 112, the jumper trace 9 is formed, and vias 19 are opened in the pixel definition layer 12 and the second planarization layer 107. The two spaced-apart second touch trace segments 82 are electrically connected via the jumper trace 9 located in the fourth conductive layer 112. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0123] In the fifth embodiment, see Figure 17 The first electrode layer includes a jumper trace 9. When forming the first electrode layer, the jumper trace 9 is formed, and a via 19 is opened in the pixel definition layer 12. The two spaced-apart second touch trace segments 82 are electrically connected via the jumper trace 9 located in the first electrode layer. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0124] In some other possible implementations, please refer again to Figure 11 Along the first direction X, at least some adjacent isolation units 7 are electrically connected via jumper traces 9. The jumper traces 9 and the isolation units 7 are located in different film layers in the display panel. The orthographic projection of the second touch trace segment 82 on the array substrate 1 at least partially overlaps with the orthographic projection of the jumper trace 9 on the array substrate 1.

[0125] In the first example, see Figure 18 and Figure 19 The first conductive layer 109 includes a jumper wire 9. When forming the first conductive layer 109, the jumper wire 9 is formed, and vias 19 are opened in the pixel defining layer 12, the second planarizing layer 107, the first planarizing layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. The two spaced-apart isolation units 7 are electrically connected via the jumper wire 9 located in the first conductive layer 109. This eliminates the need for dedicated jumper wires 9, thereby reducing the cost of providing jumper wires 9.

[0126] In the second embodiment, see Figure 20 The second conductive layer 110 includes a jumper trace 9. When forming the second conductive layer 110, the jumper trace 9 is formed, and vias 19 are opened in the pixel defining layer 12, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. The two spaced-apart isolation units 7 are electrically connected via the jumper trace 9 located in the second conductive layer 110. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0127] In the third embodiment, see Figure 21 The third conductive layer 111 includes a jumper trace 9. When forming the third conductive layer 111, the jumper trace 9 is formed, and vias 19 are opened in the pixel defining layer 12, the second planarization layer 107, and the first planarization layer 106. The two spaced-apart isolation units 7 are electrically connected via the jumper trace 9 located in the third conductive layer 111. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0128] In the fourth embodiment, see Figure 22The fourth conductive layer 112 includes a jumper trace 9. When forming the fourth conductive layer 112, the jumper trace 9 is formed, and vias 19 are opened in the pixel definition layer 12 and the second planarization layer 107. The two spaced-apart isolation units 7 are electrically connected via the jumper trace 9 located in the fourth conductive layer 112. This eliminates the need for dedicated jumper traces 9, thereby reducing the cost of providing jumper traces 9.

[0129] In the fifth embodiment, see Figure 23 The first electrode layer includes a jumper trace 9. When forming the first electrode layer, the jumper trace 9 is formed, and a via 19 is opened in the pixel defining layer 12. The two spaced-apart isolation units 7 are electrically connected via the jumper trace 9 located in the first electrode layer. This eliminates the need for a dedicated jumper trace 9, thereby reducing the cost of providing the jumper trace 9.

[0130] For some possible implementations, see again Figure 11 The orthographic projections of the first touch trace segment 81 and the second touch trace segment 82 on the array substrate 1 intersect each other. Furthermore, the orthographic projections of the same first touch trace segment 81 and the plurality of second touch trace segments 82 arranged along the second direction Y on the array substrate 1 intersect each other. In this way, the effective touch area of ​​the touch electrode 8 can be increased.

[0131] Please see again Figure 11 The orthographic projections of the first touch trace segment 81 and the second touch trace segment 82 on the array substrate 1 are in a mesh structure. The first touch trace segment 81 and the second touch trace segment 82 are interspersed between the isolation units 7 and surround the light-emitting pixels, thereby further increasing the effective touch area of ​​the touch electrode 8.

[0132] Along the first direction X, see again Figure 11 The width W2 of the orthographic projection of the second touch trace segment 82 on the array substrate 1 ranges from 5μm to 15μm. For example, width W2 can be 5μm, 7μm, 10μm, 13μm, or 15μm. Setting width W2 too large reduces the spacing between the second touch trace segment 82 and the isolation structure 18, thereby increasing the difficulty of etching the second touch trace segment 82 and the isolation structure 18. Setting width W2 too small reduces the touch sensitivity of the display panel. Therefore, properly setting width W2 makes it easier to etch the second touch trace segment 82 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0133] Preferably, see again Figure 11The minimum distance D2 between the second touch trace segment 82 and the isolation structure 18 is 10μm-30μm. For example, the minimum distance D2 can be 10μm, 12μm, 15μm, 20μm, 25μm, 28μm, or 30μm. If the minimum distance D2 is set too small, it will increase the difficulty of etching the second touch trace segment 82, and even easily cause the risk of short circuit between the second touch trace segment 82 and the isolation structure 18; if the minimum distance D2 is set too large, it will reduce the area of ​​the second touch trace segment 82, thereby reducing the touch sensitivity of the display panel. Therefore, a reasonable setting of the minimum distance D2 can make it easier to etch the second touch trace segment 82 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0134] Preferably, see again Figure 11 Along the first direction X, the width of the first connecting trace 20 on the array substrate 1 ranges from 3 μm to 10 μm, and the width W3 can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc. If the width W3 is set too large, it will affect the area occupied by the second touch trace segment 82. If the width W3 is set too small, it may affect the reliability of the electrical connection between adjacent isolation units 7. Therefore, a reasonable setting of W3 will not affect the area occupied by the second touch trace segment 82, but can also improve the reliability of the electrical connection between adjacent isolation units 7.

[0135] Preferably, see again Figure 11 The display panel further includes second connecting traces 11 extending along the second direction Y. The second connecting traces 11 are electrically connected to the isolation units 7 arranged along the second direction Y. In this way, the second electrodes 16 between the light-emitting sub-pixels 10 can be electrically connected as a whole through the first connecting traces 20 and the second connecting traces 11.

[0136] For some possible implementations, see again Figure 24 The display panel also includes a first encapsulation layer 21 located on the side of the second electrode layer away from the array substrate 1. The first encapsulation layer 21 includes a plurality of spaced-apart encapsulation units 211. The encapsulation units 211 extend from the side of the isolation unit 7 to the side of the isolation unit 7 away from the array substrate 1. Adjacent encapsulation units 211 are spaced apart on the side of the isolation unit 7 away from the array substrate 1. A gap exists between the side of the encapsulation unit 211 near the isolation unit 7 and the side of the isolation unit 7 away from the array substrate 1. The material of the first encapsulation layer 21 includes an inorganic material. The encapsulation units 211 can independently encapsulate the light-emitting sub-pixels 10, thereby improving the display characteristics of the display panel.

[0137] For some possible implementations, see again Figure 23The isolation unit 7 includes a first isolation portion 71 and a second isolation portion 72 stacked in sequence in a direction away from the array substrate 1 , and the orthographic projection of the first isolation portion 71 on the array substrate 1 is located within the orthographic projection of the second isolation portion 72 on the array substrate 1 .

[0138] Because the second isolation portion 72 is located on the side of the first isolation portion 71 away from the array substrate 1, and the lateral width of the second isolation portion 72 is greater than the lateral width of the first isolation portion 71, the second isolation portion 72 disconnects the light-emitting functional layer and the second electrode layer at the isolation unit 7. In this way, the isolation unit 7 formed by the first isolation portion 71 and the second isolation portion 72 can more easily enable the independent packaging of each light-emitting sub-pixel 10.

[0139] For some possible implementations, see again Figure 23 , the second electrode 16 is electrically connected to the first isolation portion 71; see again Figure 24 , and / or the isolation unit 7 further includes a third isolation portion 73 located on the side of the first isolation portion 71 facing the array substrate 1, and the second electrode 16 is electrically connected to the third isolation portion 73; the third isolation portion 73 is made of molybdenum; and / or the first isolation portion 71 is made of aluminum; and / or the second isolation portion 72 is made of titanium. In this way, when the isolation unit 7 separates the second electrode layer into the second electrode 16, the second electrode 16 is more easily electrically connected to the first isolation portion 71 and / or the third isolation portion 73.

[0140] In summary, in the present application, by setting the isolation structure 18 and the touch electrode 8 on the same layer on one side of the array substrate 1, there is no need to reuse the isolation structure 18, and the touch control of the display panel can be completed through the touch electrode 8, which not only reduces the cost of the display panel, but also reduces the thickness of the display panel, thereby making it easier to achieve the goal of making the display panel lighter and thinner.

[0141] For some possible implementations, see Figure 25 , the present application also provides a method for preparing a display panel, the method comprising:

[0142] S10: providing an array substrate 1.

[0143] The array substrate 1 may include a substrate 101 and multiple driving units located on one side of the substrate 101. Each driving unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the cooperation of multiple film layers in the array substrate 1. For example, the semiconductor switching devices may be thin film transistors formed by the cooperation of multiple film layers.

[0144] S11: forming a conductive isolation layer 6 on one side of the array substrate 1, the conductive isolation layer 6 including an isolation structure 18 and touch electrodes 8 arranged on the same layer, the isolation structure 18 and adjacent touch electrodes 8 being insulated; the touch electrodes 8 being configured as self-capacitance detection electrodes.

[0145] At the same time as the isolation structure 18 is formed, the touch electrode 8 is formed, and the touch electrode 8 is configured as a self-capacitance detection electrode. In this way, compared with the solution in the related art that requires at least four masks to set the touch film layer, the mask plates for setting the touch film layer can be reduced in this embodiment, thereby reducing the manufacturing cost of the display panel. In addition, compared with the solution in the related art where the touch electrodes 8 are located on different layers and a touch insulation layer 4 is required to separate the touch electrodes 8 of different layers, resulting in a relatively thick display panel in the related art, the touch electrodes 8 in this embodiment can be self-capacitance electrodes, and all touch electrodes 8 are set on the same layer, thereby greatly reducing the thickness of the display panel.

[0146] In addition, in this embodiment, the isolation structure 18 does not need to be reused, and the touch function of the display panel can be completed through the touch electrodes 8. Therefore, overly complicated driving and timing coordination are not required.

[0147] In some possible implementations, the present application further provides an electronic device including the display panel described herein. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, or a laptop computer. Because the electronic device includes the display panel described herein, the electronic device has lower cost, is thinner, and has better touch performance.

[0148] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0149] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes: array substrate; a conductive isolation layer located on one side of the array substrate, the conductive isolation layer including an isolation structure and touch electrodes arranged on the same layer, the isolation structure being insulated from adjacent touch electrodes; The touch electrodes are configured as self-capacitance detection electrodes.

2. The display panel according to claim 1, wherein: At least some of the touch electrodes include first touch trace segments extending along a first direction, a plurality of the first touch trace segments arranged along a second direction are electrically connected via jumper traces, the jumper traces and the first touch trace segments are located in different film layers of the display panel, and the first direction intersects the second direction; Preferably, the orthographic projections of the first touch sensing trace segments and the jumper traces on the array substrate are in a mesh structure; Preferably, the isolation structure comprises a plurality of isolation units arranged at intervals, and the isolation units extend along the first direction; Preferably, the orthographic projection of the first touch trace segment on the array substrate is located between the orthographic projections of two adjacent isolation units on the array substrate; Preferably, the jumper trace extends along the second direction; Preferably, the first direction is perpendicular to the second direction.

3. The display panel according to claim 2, wherein: Along the second direction, the width of the orthographic projection of the first touch trace segment on the array substrate is in a range of 5 μm to 15 μm; Preferably, the minimum distance between the first touch sensing trace segment and the isolation structure is 10 μm-30 μm.

4. The display panel according to claim 1, wherein: At least part of the touch electrodes include a first touch trace segment extending along a first direction and a second touch trace segment extending along a second direction, and the second touch trace segment is electrically connected to the first touch trace segment.

5. The display panel according to claim 4, wherein: The orthographic projections of the first touch trace segment and the second touch trace segment on the array substrate intersect crosswise; Preferably, the orthographic projections of the same first touch trace segment and a plurality of second touch trace segments arranged along the second direction on the array substrate intersect crosswise; Preferably, the orthographic projections of the first touch trace segment and the second touch trace segment on the array substrate are in a mesh structure; Along the first direction, the width of the orthographic projection of the second touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm; Preferably, the minimum distance between the second touch sensing trace segment and the isolation structure is 10 μm-30 μm.

6. The display panel according to claim 4, wherein: The isolation structure includes a plurality of isolation units arranged at intervals, at least some of the second touch trace segments are arranged at intervals, and adjacent second touch trace segments arranged along the second direction are electrically connected via jumper traces; Along a first direction, at least some of the adjacent isolation units are electrically connected via a first connecting trace, the jumper trace and the second touch trace segment are located in different film layers of the display panel, and an orthographic projection of the jumper trace on the array substrate at least partially overlaps with an orthographic projection of the first connecting trace on the array substrate; and / or Along the first direction, at least some of the adjacent isolation units are electrically connected via a jumper wire, the jumper wire and the isolation structure are located in different film layers in the display panel, and an orthographic projection of the second touch sensing wire segment on the array substrate at least partially overlaps with an orthographic projection of the jumper wire on the array substrate; Preferably, along the first direction, the width of the first connecting trace on the array substrate is in a range of 3 μm to 10 μm; Preferably, the display panel further includes second connecting wires extending along the second direction, and the second connecting wires are electrically connected to the isolation units arranged along the second direction.

7. The display panel according to claim 4, wherein: The display panel further includes a light-emitting pixel located on one side of the array substrate, and the orthographic projections of at least part of the first touch trace segments and / or at least part of the second touch trace segments on the array substrate surround the orthographic projections of the light-emitting pixel on the array substrate; Preferably, the light-emitting pixel includes at least one light-emitting sub-pixel; Preferably, the light-emitting sub-pixel includes a red light-emitting sub-pixel, a blue light-emitting sub-pixel, or a green light-emitting sub-pixel.

8. The display panel according to claim 2 or 6, characterized in that: The array substrate includes a substrate and a conductive layer located on one side of the substrate, and the jumper trace is located on the conductive layer; Preferably, along a direction away from the substrate, the conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; Preferably, the jumper traces are respectively located in the same film layer or different film layers among the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer; and / or, the display panel further includes a first electrode layer located on one side of the array substrate, and the jumper traces are located in the first electrode layer; Preferably, an insulating layer is provided between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, between the third conductive layer and the fourth conductive layer, and between the fourth conductive layer and the first electrode layer; Preferably, a via is formed on the insulating layer in a direction away from the substrate, and the via exposes at least a portion of the jumper trace.

9. The display panel according to any one of claims 1 to 6, wherein: The display panel further includes a first electrode layer, a light-emitting functional layer and a second electrode layer located on a side of the first electrode layer away from the array substrate and stacked in sequence in a direction away from the array substrate, wherein the second electrode layer is electrically connected to the isolation structure; Preferably, the isolation structure encloses an isolation opening, the first electrode layer includes a first electrode at least partially located within the isolation opening, the light-emitting functional layer includes a light-emitting portion located within the isolation opening, the second electrode layer includes a second electrode at least partially located within the isolation opening, and the second electrode is electrically connected to the isolation structure.

10. The display panel according to claim 9, wherein: The display panel further includes a pixel defining layer located on one side of the array substrate, the conductive isolation layer is located on a side of the pixel defining layer away from the array substrate, the pixel defining layer includes a pixel opening exposing at least a portion of the first electrode, and the orthographic projection of the isolation structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate; Preferably, the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate; Preferably, the first electrode comprises an anode; Preferably, the second electrode comprises a cathode.

11. The display panel according to claim 9, wherein The display panel further includes a first encapsulation layer located on a side of the second electrode layer away from the array substrate, the first encapsulation layer including a plurality of encapsulation units spaced apart from each other, the encapsulation units extending from a side of the isolation structure to a side of the isolation structure away from the array substrate; Preferably, two adjacent packaging units are spaced apart on a side of the isolation structure away from the array substrate; Preferably, a distance exists between a side of the packaging unit close to the isolation structure and a side of the isolation structure away from the array substrate; Preferably, the material of the first encapsulation layer includes an inorganic material.

12. The display panel according to claim 9, wherein: The isolation structure includes a plurality of isolation units arranged at intervals, and the isolation unit includes a first isolation portion and a second isolation portion stacked in sequence in a direction away from the array substrate, and the orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate.

13. The display panel according to claim 12, wherein: The second electrode is electrically connected to the first isolation portion; and / or the isolation unit further includes a third isolation portion located on a side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

14. A method for preparing a display panel, characterized in that: The method comprises: providing an array substrate; forming a conductive isolation layer on one side of the array substrate, the conductive isolation layer including an isolation structure and touch electrodes arranged on the same layer, and the isolation structure and the adjacent touch electrodes being insulated from each other; The touch electrodes are configured as self-capacitance detection electrodes.

15. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 13.

Images