An instruction processing method, apparatus and related device

Abstract

Embodiments of the present application provide an instruction processing method, device and related equipment, the method comprises: in slow mode, obtaining an instruction to be executed, the instruction to be executed is an instruction corresponding to an exception triggering instruction execution mode to switch from fast mode to slow mode; based on a first bit width, the instruction to be executed is decoded to determine the corresponding operation information and the address to be accessed, the address to be accessed is used to access target data with a first bit width; based on a second bit width, the address to be accessed is split into multiple sub access addresses, and the sub target data is accessed based on the sub access addresses, and the judgment of whether the access exception is an error suppression exception exists; after all the sub target data corresponding to all the sub access addresses are accessed, the target data formed by the accessed sub target data is executed according to the operation information. The scheme simplifies the instruction processing flow and reduces the instruction overhead.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, specifically to an instruction processing method, apparatus, and related equipment. Background Technology

[0002] During instruction execution, the processor uses an error suppression mechanism to handle memory access exceptions. However, the instruction processing flow under this error suppression mechanism is relatively complex and has a large instruction overhead.

[0003] Therefore, how to provide technical solutions to reduce instruction overhead has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This invention provides an instruction processing method, apparatus, and related equipment to reduce instruction overhead.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, embodiments of the present invention provide an instruction processing method, including:

[0007] In slow mode, obtain the instruction to be executed, which is the instruction corresponding to the exception that triggers the switch of instruction execution mode from fast mode to slow mode;

[0008] The instruction to be executed is decoded based on the first bit width to determine the corresponding operation information and the address to be accessed; the address to be accessed is used to access target data with the first bit width, where the first bit width is the data bit width corresponding to the instruction to be executed in fast mode.

[0009] The address to be accessed is split into multiple sub-access addresses based on the second bit width, and the sub-target data is accessed based on the sub-access addresses. In addition, when there is an access exception, it is determined whether the access exception is an error suppression exception.

[0010] After all the sub-target data corresponding to all sub-access addresses have been accessed and stored, the target data formed by the accessed sub-target data is processed according to the operation information.

[0011] Optionally, the slow mode is triggered based on a resynchronization failure, and when the resynchronization failure occurs, the slow mode flag is configured to be valid.

[0012] After decoding the instruction to be executed based on the first bit width and before splitting the address to be accessed into multiple sub-access addresses based on the second bit width, the method further includes:

[0013] Determine whether the slow mode flag is valid;

[0014] If yes, execute the step of splitting the address to be accessed into multiple sub-access addresses based on the second bit width; otherwise, enter the scheduling process of fast mode.

[0015] Configure the slow mode flag as invalid after decoding the first instruction in slow mode.

[0016] Optionally, the step of obtaining the instruction to be executed is performed based on the instruction fetch unit, which is used to execute the instruction fetch process in fast mode;

[0017] The step of decoding the instruction to be executed based on the first bit width is performed by a decoding unit, which is used to perform the decoding process in fast mode;

[0018] The step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information is executed based on the computing unit, which is used to execute the computing process in fast mode.

[0019] Optionally, the step of splitting the address to be accessed into multiple sub-access addresses based on the second bit width, and performing memory access on the sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error suppression exception when an exception occurs, includes:

[0020] Based on the second bit width and the target start address, the target sub-access address is determined; the target sub-access address is used to indicate the currently determined sub-access address; wherein, the target start address is the start address of the target sub-access address; during the first execution, the target start address is the start address of the target access address, and during subsequent executions, the target start address is the address after the end address of the target sub-access address of the previous memory access process;

[0021] Based on the target sub-access address, the sub-target data corresponding to the target sub-access address is accessed and stored; wherein, the accessed sub-target data is used to store in the data cache.

[0022] When a memory access exception occurs, it is determined whether the memory access exception is an error-suppressed exception; the error suppression is used to indicate exceptions that can be ignored.

[0023] If so, determine whether the current sub-target data is the last data of the target data; the last data is used to indicate the target data containing the termination address of the corresponding address to be accessed;

[0024] If yes, execute the step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information; if no, execute the step of determining the target sub-access address based on the second bit width and the target starting address.

[0025] Optionally, determining whether the memory access exception is an error-suppressed exception includes:

[0026] Based on the error suppression information under the first bit width, calculate the target error suppression information under the second bit width;

[0027] Based on the target error suppression information corresponding to the target sub-access address, determine whether the memory access exception is an error suppression exception.

[0028] Optionally, determining whether the current sub-target data is the end data of the target data specifically involves determining whether the target sub-access address contains the termination address of the address to be accessed; if yes, then the current sub-target data is the end data of the target data; if no, then the current sub-target data is not the end data of the target data.

[0029] Optionally, the bit width of the data cache is a second bit width, and there are multiple data caches; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is stored sequentially in each data cache according to a preset order; the preset order corresponds to the data position of the sub-target data in the target data;

[0030] The step of performing corresponding processing on the target data formed from the accessed sub-target data according to the operation information includes: concatenating the target data based on the data position of the sub-target data; and performing corresponding processing based on the target data.

[0031] Optionally, the bit width of the data cache is the first bit width; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is stored sequentially in different data bits of the data cache according to a preset order, the preset order corresponding to the data position of the sub-target data in the target data;

[0032] The step of performing corresponding processing on the target data formed from the accessed sub-target data according to the operation information specifically involves performing corresponding processing based on the target data stored in the data cache.

[0033] Optionally, the step of decoding the instruction to be executed based on the first bit width to determine the corresponding operation information and the address to be accessed further includes: storing the operation information corresponding to the decoding into a transmission queue, and configuring the operation information stored in the transmission queue into a sleep state;

[0034] In the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, the operation information corresponding to the access is obtained after the launch queue is woken up, so as to perform the access to the corresponding target sub-access address.

[0035] Optionally, the steps of splitting the address to be accessed into multiple sub-access addresses based on the second bit width, and performing sub-target data access based on the sub-access addresses, as well as determining whether the access exception is an error suppression exception when an access exception exists, are executed based on the scheduling unit and the access unit.

[0036] The scheduling unit is equipped with a slow-mode state machine, which contains an address storage unit for storing the target starting address. The slow-mode state machine is started based on a slow-mode flag.

[0037] Optionally, the slow-mode state machine is configured with the following states:

[0038] The waiting initialization state indicates that the current slow mode state machine is in a waiting initialization state. The initialization is to obtain the operation information of the instruction to be executed from the self-emission queue and configure the address information in the address storage unit as the starting address of the target access address.

[0039] The waiting-to-wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be woken up. In multiple sub-memory access loop processes, the waiting-to-wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information.

[0040] Address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein, the address generation port is used to enable the address generator to generate the target sub-access address;

[0041] One of the sub-memory access loop processes is used to perform a memory access to a target sub-access address. After entering the sub-memory access loop process, the slow mode state machine executes multiple sub-memory access loop processes based on the switching between the waiting wake-up state and the address preemption state.

[0042] In a second aspect, embodiments of the present invention provide an instruction processing apparatus, comprising:

[0043] The instruction acquisition module is used to acquire the instruction to be executed in slow mode. The instruction to be executed is the instruction corresponding to the exception that triggers the switch of instruction execution mode from fast mode to slow mode.

[0044] The decoding module is used to decode the instruction to be executed based on the first bit width to determine the corresponding operation information and the address to be accessed; the address to be accessed is used to access target data with the first bit width, where the first bit width is the data bit width corresponding to the instruction to be executed in fast mode;

[0045] The memory access scheduling module is used to split the address to be accessed into multiple sub-access addresses based on the second bit width, and to perform memory access on the sub-target data based on the sub-access addresses, as well as to determine whether the memory access exception is an error suppression exception when there is a memory access exception.

[0046] The processing module is used to perform corresponding processing on the target data formed by the accessed sub-target data according to the operation information after all the sub-target data corresponding to all sub-access addresses have been accessed and stored.

[0047] Optionally, the instruction acquisition module is an instruction fetching unit, which is used to execute the instruction fetching process in fast mode;

[0048] The decoding module is a decoding unit, which is used to execute the decoding process in fast mode;

[0049] The processing module is a computing unit, which is used to execute the computing process in fast mode.

[0050] Optionally, the scheduling and memory access module includes a scheduling unit and a memory access unit; wherein, the scheduling unit is configured with a slow mode state machine; the slow mode state machine is configured with an address storage unit, the address storage unit is used to store the target starting address, the target starting address is the starting address of the target sub-access address, the target sub-access address is used to indicate the currently executed sub-access address; the slow mode state machine is triggered to start based on a slow mode flag.

[0051] Optionally, the slow-mode state machine is configured with the following states:

[0052] The waiting initialization state indicates that the current slow mode state machine is in a waiting initialization state. The initialization is to obtain the operation information of the instruction to be executed from the self-emission queue and configure the address information in the address storage unit as the starting address of the target access address.

[0053] The waiting-to-wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be woken up. In multiple sub-memory access loop processes, the waiting-to-wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information.

[0054] Address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein, the address generation port is used to enable the address generator to generate the target sub-access address;

[0055] One of the sub-memory access loop processes is used to perform a memory access to a target sub-access address. After entering the sub-memory access loop process, the slow mode state machine executes multiple sub-memory access loop processes based on the switching between the waiting wake-up state and the address preemption state.

[0056] Thirdly, embodiments of the present invention provide a processor including the instruction processing apparatus as described in the second aspect.

[0057] Fourthly, embodiments of the present invention provide an electronic device including the processor described in the third aspect.

[0058] This invention provides an instruction processing method, apparatus, and related devices. The instruction processing method includes: in slow mode, acquiring an instruction to be executed, the instruction to be executed being the instruction corresponding to an exception that triggers the instruction execution mode to switch from fast mode to slow mode; decoding the instruction to be executed based on a first bit width to determine corresponding operation information and an address to be accessed, the address to be accessed being used to access target data with a first bit width; the first bit width being the data bit width corresponding to the instruction that executed the exception in fast mode; splitting the address to be accessed into multiple sub-access addresses based on a second bit width, and performing memory access on the sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error suppression exception when a memory access exception exists; after the sub-target data corresponding to all sub-access addresses has been accessed, performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information.

[0059] As can be seen, in this embodiment of the invention, in slow mode, the data bit width corresponding to the instruction to be executed, i.e. the first bit width, is still executed based on fast mode to decode the instruction. Only during the memory access process, the address to be accessed for accessing the target data with the first bit width is split into multiple sub-access addresses to achieve small-granularity sub-target data access and corresponding error suppression judgment. That is, by reusing the instruction processing flow of fast mode, the processing flow of slow mode using ucode is avoided, simplifying the instruction processing flow and reducing instruction overhead. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0061] Figure 1 This is an example diagram of an optional mode switching method;

[0062] Figure 2 An optional flowchart of the instruction processing method provided in the embodiments of this application;

[0063] Figure 3 An optional flowchart of step S120 provided in an embodiment of this application;

[0064] Figure 4 Another optional flowchart for step S120 provided in the embodiments of this application;

[0065] Figure 5 This is an optional block diagram of an instruction processing apparatus provided in an embodiment of the present invention;

[0066] Figure 6 Another optional example diagram of the instruction processing apparatus provided in the embodiments of the present invention. Detailed Implementation

[0067] As described in the background section, the instruction execution process of existing processors consumes a lot of hardware resources, which affects the processor's performance and scalability.

[0068] refer to Figure 1 The diagram illustrates an example of optional mode switching. To improve processor instruction execution performance, for some complex instructions, such as those supporting error suppression, the execution flow includes two instruction processing modes: Fast mode and Slow mode. In Fast mode, instructions are executed based on a larger bit width, and the data to be processed corresponding to the instruction is processed according to the granularity defined by that bit width (the data to be processed corresponding to that bit width can be called the first data block, such as...). Figure 1 The solid-line data block in the instruction (with a relatively fast data processing speed) will enter Slow mode when an exception occurs during the execution of an instruction. In this mode, the instruction that caused the exception (also known as the exception instruction) will be executed based on a smaller bit width (the data to be processed corresponding to this bit width can be called the second data block, such as...). Figure 1 The system uses dashed data blocks (where the first data block is an integer multiple of the second data block) to identify abnormal data one by one at a smaller granularity. It then checks whether the abnormal data to be processed is suppressed based on error suppression information. If so, the abnormality is ignored; otherwise, an exception handling process, such as interruption or instruction jump, is executed. Afterward, it can switch from Slow mode to Fast mode and continue executing subsequent instructions based on Fast mode.

[0069] In one optional implementation, Slow mode is executed based on a specific ucode (program sequence). This ucode can obtain instruction information corresponding to the exception instruction and, based on the corresponding instruction information, decode the exception instruction into multiple uops (micro-operations) with elements (items, corresponding to the second data block) as independent processing units. Furthermore, it performs scheduling, memory access and writing to specific registers (e.g., the ft register) on an element-by-element basis, as well as error suppression judgment. After determining that there is no need to execute the exception handling process, it jumps out of the ucode, switches to Fast mode, and performs subsequent processing based on the data written in the specific register.

[0070] The inventors believe that the processing flow for slow mode execution using ucode requires configuring a corresponding ucode interface and splitting, scheduling, and accessing memory in ucode mode. In other words, a complete instruction processing flow under ucode mode is needed, making the instruction processing flow under existing error suppression mechanisms quite complex and resulting in excessive instruction overhead. In particular, in one alternative implementation, different ucodes may need to be configured for different types of instructions, further complicating mode switching and instruction processing, and increasing the corresponding instruction overhead.

[0071] In view of this, embodiments of the present invention provide an instruction processing method, apparatus, and related devices. The instruction processing method includes: in slow mode, acquiring an instruction to be executed, the instruction to be executed being the instruction corresponding to an exception that triggers the instruction execution mode to switch from fast mode to slow mode; decoding the instruction to be executed based on a first bit width to determine corresponding operation information and an address to be accessed, the address to be accessed being used to access target data having a first bit width; the first bit width being the data bit width corresponding to the instruction that executed the exception in fast mode; splitting the address to be accessed into multiple sub-access addresses based on a second bit width, and performing memory access on the sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error suppression exception when a memory access exception exists; after the sub-target data corresponding to all sub-access addresses has been accessed, performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information.

[0072] As can be seen, in this embodiment of the invention, in slow mode, the data bit width corresponding to the instruction to be executed, i.e. the first bit width, is still executed based on fast mode to decode the instruction. Only during the memory access process, the address to be accessed for accessing the target data with the first bit width is split into multiple sub-access addresses to achieve small-granularity sub-target data access and corresponding error suppression judgment. That is, by reusing the instruction processing flow of fast mode, the processing flow of slow mode using ucode is avoided, simplifying the instruction processing flow and reducing instruction overhead.

[0073] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] Figure 2 This is an optional flowchart of the instruction processing method provided in an embodiment of the present invention. (See reference) Figure 2 The instruction processing method provided in this embodiment of the invention includes the following steps.

[0075] Step S100: In slow mode, obtain the instruction to be executed, which is the instruction corresponding to the exception that triggers the switch of instruction execution mode from fast mode to slow mode;

[0076] When an exception occurs in fast mode, it can trigger a switch in instruction processing mode from fast to slow. The exception can be one arising during the access process to the data being processed, such as an exception encountered when accessing an avx512Kmask instruction, such as memory access out of bounds, data access mismatch, ECC check failure, etc., or other types of exceptions. The instruction corresponding to the exception that triggers the switch from fast to slow mode, i.e., the instruction processed by the instruction processing flow at the time the exception occurred, is used as the instruction to be executed.

[0077] This step can be performed based on the instruction fetch unit, that is, using the instruction fetch unit to obtain the instruction to be executed. It can be understood that when an exception occurs, slow mode can re-fetch the instruction, thereby obtaining the instruction that was not fully executed before, that is, the instruction processed by the instruction handling flow corresponding to the exception in fast mode, and thus using the re-fetched instruction as the instruction to be executed.

[0078] The fetching of instructions to be executed is based on the instruction fetching unit. This can be achieved by reusing the hardware and software in fast mode. That is, the instruction fetching unit is used to execute the instruction fetching process in fast mode without configuring the program sequence (ucode) for obtaining the corresponding instruction information and the corresponding hardware resources, thereby reducing the hardware and software overhead of the instructions.

[0079] In an optional implementation, when an exception occurs in fast mode, it cannot be determined whether it is a true fault (i.e., an error that is not suppressed under the error suppression mechanism). In this case, a Resync Fault will be generated. This Resync Fault is used to indicate that the instruction fetch should be restarted from the current PC (Program Counter), thereby indicating the instruction fetch process in slow mode.

[0080] In a specific example, the slow mode in this embodiment of the invention can perform instruction fetching and decoding based on the instruction fetching and decoding process in the fast mode. Using a resynchronization fault to trigger the slow mode can appropriately adapt to the processing flow of the slow mode.

[0081] Furthermore, in the example of fetching and decoding in the fast mode, to distinguish the mode of the processing flow and select the corresponding subsequent steps, this application also configures a slow mode (also known as MultiAgen) flag. In a specific example, the resynchronization failure is also used to trigger the configuration of the slow mode flag. That is, when the resynchronization failure occurs, the slow mode flag (e.g., the MultiAgen flag) is configured to be valid, so that the first instruction after the resynchronization failure, under the indication of the slow mode flag, enters the slow mode scheduling flow after fetching and decoding.

[0082] Understandably, in fast mode, after instruction fetching and decoding, the scheduling process can be further initiated based on the indication of the slow mode flag.

[0083] It should be noted that, in a further optional example, the slow mode flag can also be configured to be invalid after the first instruction in slow mode is decoded (e.g., the slow mode flag can be cleared) to avoid affecting subsequent instructions and other instructions running in parallel.

[0084] Step S110: Decode the instruction to be executed based on the first bit width to determine the corresponding operation information and the address to be accessed;

[0085] The address to be accessed is used to access target data with a first bit width, where the first bit width is the data bit width corresponding to the instruction to be executed in fast mode. That is, the decoding stage in this step is still based on the fast mode approach, thus avoiding the need to decode into multiple small-granularity operation information, thereby reducing instruction overhead. Specifically, the decoding is typically used to indicate that the instruction to be executed is decoded into a micro-operation (uop), and correspondingly, the operation information is used to indicate the instruction information for the micro-operation.

[0086] This step decodes the instruction to be executed based on the first bit width. This can be performed using a decoding unit, which is used to execute the decoding process in fast mode. That is, this step can reuse the decoding unit used for executing the decoding process in fast mode. Furthermore, this step can also store the corresponding operation information in the issue queue (issueQ), thereby executing subsequent processes based on the operation information in the issue queue. It is understood that the operation information stored in the issue queue can be configured to a sleep state, i.e., configured to be awakened in subsequent processes. Moreover, the operation information may include identification information indicating entry into slow mode.

[0087] It is understandable that obtaining the instruction to be executed based on the decoding unit can be achieved by reusing the hardware and software in the fast mode, without configuring the program sequence (ucode) for decoding the instruction to be executed and the corresponding hardware resources, thereby reducing the hardware and software overhead of the instruction.

[0088] Step S120: Split the address to be accessed into multiple sub-access addresses based on the second bit width, and perform memory access on the sub-target data based on the sub-access addresses, and determine whether the memory access exception is an error suppression exception when there is a memory access exception.

[0089] The address to be accessed is divided based on a second bit width. For example, starting from the starting address of the address to be accessed, it can be sequentially divided into sub-access addresses with a capacity of the second bit width, thereby performing memory access based on the divided sub-access addresses. In the process of accessing sub-target data based on the sub-access addresses, the memory access of the corresponding sub-access addresses can be executed sequentially according to the order of the sub-access addresses. The obtained sub-target data can be stored in a data buffer, that is, the obtained sub-target data is stored in the data buffer. The data buffer can be set in the memory access unit.

[0090] In the specific implementation, Figure 3 This is an optional flowchart of step S120 provided in the embodiments of this application. Step S120 can achieve memory access to each sub-target data by repeatedly executing the following sub-memory access process. Specifically, the sub-memory access process includes:

[0091] Step S121: Determine the target sub-access address based on the second bit width and the target starting address;

[0092] Here, the target starting address is the starting address of the target sub-access address. The target starting address can be the starting address of the target access address, or it can be the address following the ending address of the target sub-access address of the previous memory access process; that is, the sum of the target starting address of the target sub-access address of the previous memory access process and the second bit width. It can be understood that when step S121 is the first execution, the target starting address can be the starting address of the target access address; when step S121 is not the first execution, the target starting address can be the sum of the target starting address of the target sub-access address of the previous memory access process and the second bit width.

[0093] The target sub-access address is used to indicate the currently determined sub-access address, that is, one of the multiple sub-access addresses after the address to be accessed is split. Access to the sub-target data is achieved based on the target sub-access address.

[0094] The step of determining the target sub-access address can be performed by a scheduling unit. The scheduling unit can be configured with an address storage unit (Payload), which can be used to store the target starting address, and then the target sub-access address can be calculated based on the target starting address.

[0095] Step S122: Based on the target sub-access address, access the sub-target data corresponding to the target sub-access address;

[0096] After determining the target sub-access address, a memory access to that target sub-access address can be performed to obtain the sub-target data corresponding to that target sub-access address, thereby determining whether there is any abnormality in the corresponding memory access process.

[0097] In the specific implementation, the operation information corresponding to step S122 can be obtained after the self-emission queue is woken up, so as to execute the access to the corresponding target sub-access address.

[0098] Understandably, if the memory access process does not encounter any memory access exceptions, the corresponding memory access operation will be executed normally, and step S124 will proceed. In a specific implementation, this step can further store the sub-target data after the memory access into a data buffer. The data buffer is a pre-defined storage device for storing sub-target data, thereby determining the corresponding target data based on the respective target data stored in the data buffer.

[0099] The data buffer can have a first or second bit width. If the data buffer has a second bit width, and there can be multiple data buffers, then in this step, each sub-target data can be stored sequentially in each data buffer according to a preset order. In subsequent steps, the target data can be obtained by concatenating the data based on the data positions of the sub-target data. If the data buffer has a first bit width, then each sub-target data can be stored sequentially in different data positions of the data buffer according to a preset order, where the preset order corresponds to the data position of the sub-target data in the target data. This allows the target data to be determined directly based on the data stored in the data buffer, without having to concatenate the sub-target data to obtain the target data.

[0100] It is understandable that if there is a memory access exception in the memory access process, the corresponding exception information will be generated to indicate the exception type, context information, etc. Accordingly, when there is a memory access exception, step S123 is executed so as to determine whether the memory access exception is an error suppression.

[0101] Step S123: Determine whether the memory access anomaly is an error suppression anomaly;

[0102] In the error suppression mechanism, the error suppression is used to indicate exceptions that can be ignored. In a specific example, the error suppression mechanism can be configured with error suppression information, which can be stored, for example, in the K register. In a specific implementation, the error suppression information may include the type of memory access exception and whether the sub-target data that caused the exception is a suppressed target. If so, the exception is ignored, and step S124 continues; otherwise, the exception handling process is executed.

[0103] In the specific implementation, the error suppression information under the first width is recorded based on the first width. Accordingly, in this step, the target error suppression information under the second width can be calculated first based on the error suppression information under the first width. Then, based on the target error suppression information corresponding to the target sub-access address, it is determined whether the memory access exception is an error suppression exception.

[0104] In an optional example, the calculation of the target error suppression information (i.e., the calculation of the target error suppression information under the second bit width based on the error suppression information under the first bit width) can be performed during the initialization process or in this step.

[0105] Step S124: Determine whether the current sub-target data is the last data of the target data;

[0106] It is understood that sub-target data is accessed sequentially from the start address to the end address, and the end data is used to indicate target data containing the end address of the corresponding address to be accessed. Accordingly, this step can specifically be to determine whether the target sub-access address contains the end address of the address to be accessed; if yes, then the current sub-target data is the end data of the target data; if no, then the current sub-target data is the end data of the non-target data.

[0107] By determining whether the current sub-target data is the last data of the target data, it is determined whether to continuously execute the sub-memory access process in which this step is located. Specifically, if the current sub-target data is the last data of the target data, step S130 is executed; if the current sub-target data is not the last data of the target data, step S121 is executed, and a new round of the sub-memory access process is started.

[0108] In further optional implementations, refer to Figure 4 The illustrated embodiment of this application provides another optional flowchart for step S120. Step S120 can also be executed based on the scheduling unit and the memory access unit. In a specific implementation, the scheduling unit can be configured with a slow-mode state machine, wherein the address storage unit can be configured within the slow-mode state machine, so that the slow-mode state machine sends the address to the memory access unit based on the second bit width. Thus, based on the control of the slow-mode state machine, the memory access unit is used to realize the memory access control of each sub-target data.

[0109] In a specific implementation, the slow-mode state machine can be started based on a slow-mode flag.

[0110] The slow-mode state machine can be configured with the following states:

[0111] Idle state (IDLE): Indicates that the slow-mode state machine is not currently being used by any thread. The idle state can enter a waiting-for-initialization state based on trigger information used to initiate initialization.

[0112] Waiting for Initialization (WAIT_SQ): This indicates that the current slow-mode state machine is in a state of waiting for initialization to complete. Initialization refers to retrieving operation information for instructions to be executed from the emit queue and configuring the address information in the address storage unit as the starting address of the target access address. This ensures that the target sub-access address corresponds to the first sub-target data (first element) accessing the target data, starting from the starting address of the target access address. After initialization is complete, the machine enters a waiting-to-wake-up state.

[0113] Waiting to be woken up (WAIT_LS): This state indicates that the current slow mode state machine is waiting for the operation information of the instruction to be executed to be woken up. In multiple sub-memory access loops, the machine enters the waiting to be woken up state after the memory access unit obtains the target sub-access address and the corresponding operation information. When the memory access unit starts a new loop of the sub-memory access process, it enters the address preemption state. When the memory access unit determines that the current sub-target data is the last data of the target data, it enters the idle state.

[0114] Address Preemption State (JAM): This indicates that the current slow-mode state machine is ready to preempt the address generation port (AgPort). In the sub-memory access loop, a target sub-access address needs to be generated based on the address generator (AGU). By preempting the address generation port, the address generator can generate the target sub-access address (Agen, Address Generation, which is the valid memory access address calculated by memory access instructions such as load / store instructions) based on the current target starting address. It can be understood that while generating the target sub-access address, the next target starting address can also be determined, thus further determining the corresponding target sub-access address in the next sub-memory access loop. Once the address generation port is successfully preempted, the machine enters a waiting-to-wake-up state.

[0115] It is understandable that a sub-memory access loop is used to perform a memory access to a target sub-access address. After entering the sub-memory access loop, the slow mode state machine executes multiple sub-memory access loops based on the switching between the waiting wake-up state and the address preemption state.

[0116] In the specific sub-memory access loop process, the decoded operation information can be stored in the transmit queue and enter a sleep state. Simultaneously, the slow mode state machine is initialized based on the slow mode flag, causing the slow mode state machine to enter a waiting-for-initialization state. In an optional example, the calculation of target error suppression information can be completed during the initialization phase.

[0117] After the initialization process is completed, the system can enter a wait-to-wake-up state to wake up the operation information corresponding to the instruction to be executed in the issue queue. After waking up the operation information corresponding to the instruction to be executed in the issue queue, the system can enter an address preemption state until the generated target sub-access address is determined. In this state, after the operation information (uop) corresponding to the first sub-target data (firstelement) is selected (pick) from the issue queue (issueQ), the address information of the target sub-access address will be stored in the address storage unit (Payload) in the slow mode state machine (MultiAgenEngine). After successfully preempting the address generation port, the system enters a wait-to-wake-up state.

[0118] Step S130: Perform corresponding processing on the target data formed from the accessed sub-target data according to the operation information;

[0119] After all the sub-target data corresponding to all sub-access addresses have been accessed and stored, subsequent processing can be performed based on the accessed data to complete the task corresponding to the instruction to be processed.

[0120] In a specific implementation, if the bit width of the data buffer is the second bit width, and there are multiple data buffers, each sub-target data is stored sequentially in each data buffer according to a preset order. Accordingly, in this step, the target data can be obtained by concatenating the data positions of the sub-target data; then, the corresponding processing is performed based on the target data.

[0121] In another implementation, if the bit width of the data buffer is the first bit width, each sub-target data is stored sequentially in different data bits of the data buffer according to a preset order. Accordingly, the data stored in the data buffer is the concatenated target data. Accordingly, this step can perform corresponding processing based on the target data stored in the data buffer.

[0122] The corresponding processing is determined based on the instruction information of the instruction to be executed. The instruction to be executed may be, for example, stored in a preset memory, or added to data in a preset memory and then stored in the preset memory, etc., and the present invention does not make specific limitations.

[0123] It is understandable that, since the target data has been fully accessed, the corresponding instruction processing in this step can be executed based on the arithmetic unit, which is used to execute the arithmetic process in fast mode. That is, this step can reuse the arithmetic unit used to execute the arithmetic process in fast mode.

[0124] It can be seen that the acquisition of instructions to be executed based on the arithmetic unit can be achieved by reusing the hardware and software in the fast mode, without configuring the program sequence (ucode) for the operation of the instructions to be executed and the corresponding hardware resources, thereby reducing the hardware and software overhead of the instructions.

[0125] In the optional implementation, where a slow mode flag is present, refer to [reference needed]. Figure 4 After step S110 and before step S120, the following is also included:

[0126] Step S115: Determine whether the slow mode flag is valid;

[0127] If yes, execute the step of splitting the address to be accessed into multiple sub-access addresses based on the second bit width; otherwise, enter the fast mode scheduling process.

[0128] The instruction processing apparatus provided in the embodiments of the present invention will be described below. The instruction processing apparatus described below can be considered as a functional module required to implement the instruction processing method provided in the embodiments of the present invention. This functional module can be a software module or a hardware module (such as a hardware logic unit or a hardware logic circuit module). The content of the instruction processing apparatus described below can be referred to in correspondence with the content of the method described above.

[0129] In the optional implementation, Figure 5 An optional block diagram of the instruction processing apparatus provided in an embodiment of the present invention is shown, such as... Figure 5 As shown, the instruction processing device may include:

[0130] The instruction acquisition module 200 is used to acquire an instruction to be executed in slow mode, wherein the instruction to be executed is the instruction corresponding to the exception that triggers the instruction execution mode to switch from fast mode to slow mode;

[0131] Decoding module 210 is used to decode the instruction to be executed based on the first bit width to determine the corresponding operation information and the address to be accessed; the address to be accessed is used to access target data with the first bit width, where the first bit width is the data bit width corresponding to the instruction to be executed in fast mode;

[0132] The memory access scheduling module 220 is used to split the address to be accessed into multiple sub-access addresses based on the second bit width, and to perform memory access on the sub-target data based on the sub-access addresses, and to determine whether the memory access exception is an error suppression exception when there is a memory access exception.

[0133] The processing module 230 is used to perform corresponding processing on the target data formed by the accessed sub-target data according to the operation information after all the sub-target data corresponding to all sub-access addresses have been accessed.

[0134] In an optional implementation, the instruction acquisition module 200 is an instruction fetching unit, which is used to execute the instruction fetching process in fast mode;

[0135] The decoding module 210 is a decoding unit, which is used to execute the decoding process in fast mode;

[0136] The processing module 230 is a computing unit, which is used to execute the computing process in fast mode.

[0137] For further optional implementations, refer to Figure 6Another optional example diagram of the instruction processing apparatus shown includes a scheduling memory access module (not shown) comprising a scheduling unit and a memory access unit; wherein the scheduling unit is configured with a slow-mode state machine; the slow-mode state machine is configured with an address storage unit, the address storage unit being used to store a target starting address, the target starting address being the starting address of a target sub-access address, the target sub-access address being used to indicate the currently executed sub-access address; the slow-mode state machine is triggered to start based on a slow-mode flag.

[0138] In a specific implementation, the scheduling unit may further include a transmit queue, an error suppression calculation unit, a multiplexer, and an address generation port.

[0139] The decoding module can store the operation information corresponding to the decoding into the transmission queue and configure the operation information stored in the transmission queue to a sleep state. Furthermore, when the memory access unit accesses the sub-target data corresponding to the target sub-access address based on the target sub-access address, the operation information corresponding to the memory access is obtained after the transmission queue is woken up to execute the access to the corresponding target sub-access address.

[0140] The error suppression calculation unit is used to calculate the target error suppression information under the second bit width based on the error suppression information under the first bit width, so that subsequent steps can determine whether the memory access anomaly is an error suppression anomaly based on the target error suppression information corresponding to the target sub-access address.

[0141] The multiplexer is used to select address information from the transmit queue and the address storage unit, and the address generation port is used to enable the address generator to generate a target sub-access address based on the selected address information.

[0142] The slow-mode state machine is configured with the following states:

[0143] The waiting initialization state indicates that the current slow mode state machine is in a waiting initialization state. The initialization is to obtain the operation information of the instruction to be executed from the self-emission queue and configure the address information in the address storage unit as the starting address of the target access address.

[0144] The waiting-to-wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be woken up. In multiple sub-memory access loop processes, the waiting-to-wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information.

[0145] Address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein, the address generation port is used to enable the address generator to generate the target sub-access address;

[0146] One of the sub-memory access loop processes is used to perform a memory access to a target sub-access address. After entering the sub-memory access loop process, the slow mode state machine executes multiple sub-memory access loop processes based on the switching between the waiting wake-up state and the address preemption state.

[0147] Optionally, the slow mode is triggered based on a resynchronization failure, and when the resynchronization failure occurs, the slow mode flag is configured to be valid.

[0148] The instruction processing device further includes an identifier bit determination module, which is used to determine whether the slow mode identifier bit is valid; if so, the step of splitting the address to be accessed into multiple sub-access addresses based on the second bit width is executed; if not, the scheduling process of fast mode is entered.

[0149] Specifically, the slow mode flag is configured to be invalid after the first instruction in slow mode is decoded.

[0150] Optionally, the scheduling memory access module is configured to split the address to be accessed into multiple sub-access addresses based on the second bit width, and perform memory access on the sub-target data based on the sub-access addresses, and, when a memory access exception exists, determine whether the memory access exception is an error suppression exception, including:

[0151] Based on the second bit width and the target start address, the target sub-access address is determined; the target sub-access address is used to indicate the currently determined sub-access address; wherein, the target start address is the start address of the target sub-access address; during the first execution, the target start address is the start address of the target access address, and during subsequent executions, the target start address is the address after the end address of the target sub-access address of the previous memory access process;

[0152] Based on the target sub-access address, the sub-target data corresponding to the target sub-access address is accessed and stored; wherein, the accessed sub-target data is used to store in the data cache.

[0153] When a memory access exception occurs, it is determined whether the memory access exception is an error-suppressed exception; the error suppression is used to indicate exceptions that can be ignored.

[0154] If so, determine whether the current sub-target data is the last data of the target data; the last data is used to indicate the target data containing the termination address of the corresponding address to be accessed;

[0155] If yes, execute the step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information; if no, execute the step of determining the target sub-access address based on the second bit width and the target starting address.

[0156] Optionally, the scheduling memory access module, used to determine whether the memory access exception is an error-suppressed exception, includes:

[0157] Based on the error suppression information under the first bit width, calculate the target error suppression information under the second bit width;

[0158] Based on the target error suppression information corresponding to the target sub-access address, determine whether the memory access exception is an error suppression exception.

[0159] Optionally, the scheduling memory access module is used to determine whether the current sub-target data is the end data of the target data. Specifically, it determines whether the target sub-access address contains the termination address of the address to be accessed. If yes, the current sub-target data is the end data of the target data; if no, the current sub-target data is not the end data of the target data.

[0160] Optionally, the bit width of the data cache is a second bit width, and there are multiple data caches; in the step of the scheduling memory access module accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is stored sequentially in each data cache according to a preset order; the preset order corresponds to the data position of the sub-target data in the target data;

[0161] The processing module is used to perform corresponding processing on the target data formed from the accessed sub-target data according to the operation information, including: concatenating the target data based on the data position of the sub-target data; and performing corresponding processing based on the target data.

[0162] Optionally, the bit width of the data cache is the first bit width; in the step of the scheduling memory access module accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is stored sequentially in different data bits of the data cache according to a preset order, the preset order corresponding to the data position of the sub-target data in the target data;

[0163] The processing module is used to perform corresponding processing on the target data formed by the accessed sub-target data according to the operation information, specifically, to perform corresponding processing based on the target data stored in the data cache.

[0164] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0165] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An instruction processing method, characterized in that, include: In slow mode, obtain the instruction to be executed, which is the instruction corresponding to the exception that triggers the switch of instruction execution mode from fast mode to slow mode; The instruction to be executed is decoded based on the first bit width to determine the corresponding operation information and the address to be accessed; the address to be accessed is used to access target data with the first bit width, where the first bit width is the data bit width corresponding to the instruction to be executed in fast mode. The address to be accessed is split into multiple sub-access addresses based on the second bit width, and the sub-target data is accessed based on the sub-access addresses. In addition, when there is an access exception, it is determined whether the access exception is an error suppression exception. After all the sub-target data corresponding to all sub-access addresses have been accessed and stored, the target data formed by the accessed sub-target data is processed according to the operation information.

2. The instruction processing method as described in claim 1, characterized in that, The slow mode is triggered by a resynchronization fault. The resynchronization fault is used to indicate that the instruction is fetched again from the current program counter, thereby indicating the instruction fetch process in slow mode. When the resynchronization fault occurs, the slow mode flag is configured to be valid, so that the first instruction after the resynchronization fault enters the slow mode scheduling process after instruction fetching and decoding under the indication of the slow mode flag. After decoding the instruction to be executed based on the first bit width and before splitting the address to be accessed into multiple sub-access addresses based on the second bit width, the method further includes: Determine whether the slow mode flag is valid; If yes, execute the step of splitting the address to be accessed into multiple sub-access addresses based on the second bit width; otherwise, enter the scheduling process of fast mode. Configure the slow mode flag as invalid after decoding the first instruction in slow mode.

3. The instruction processing method as described in claim 1, characterized in that, The step of obtaining the instruction to be executed is performed based on the instruction fetch unit, which is used to execute the instruction fetch process in fast mode; The step of decoding the instruction to be executed based on the first bit width is performed by a decoding unit, which is used to perform the decoding process in fast mode; The step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information is executed based on the computing unit, which is used to execute the computing process in fast mode.

4. The instruction processing method as described in claim 1, characterized in that, The process of splitting the address to be accessed into multiple sub-access addresses based on the second bit width, performing memory access on the sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error-suppressed exception when an exception occurs, includes: Based on the second bit width and the target start address, the target sub-access address is determined; the target sub-access address is used to indicate the currently determined sub-access address; wherein, the target start address is the starting address of the target sub-access address; during the first execution, the target start address is the starting address of the address to be accessed, and during subsequent executions, the target start address is the address after the end address of the target sub-access address of the previous memory access process; Based on the target sub-access address, the sub-target data corresponding to the target sub-access address is accessed and stored; wherein, the accessed sub-target data is used to store in the data cache. When a memory access exception occurs, it is determined whether the memory access exception is an error-suppressed exception; the error suppression is used to indicate exceptions that can be ignored. If so, determine whether the current sub-target data is the last data of the target data; the last data is used to indicate the target data containing the termination address of the corresponding address to be accessed; If yes, execute the step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information; if no, execute the step of determining the target sub-access address based on the second bit width and the target starting address.

5. The instruction processing method as described in claim 4, characterized in that, The determination of whether the memory access exception is an error-suppressed exception includes: Based on the error suppression information under the first bit width, calculate the target error suppression information under the second bit width; Based on the target error suppression information corresponding to the target sub-access address, determine whether the memory access exception is an error suppression exception.

6. The instruction processing method as described in claim 4, characterized in that, The step of determining whether the current sub-target data is the end data of the target data specifically involves determining whether the target sub-access address contains the termination address of the address to be accessed; if yes, then the current sub-target data is the end data of the target data; if no, then the current sub-target data is not the end data of the target data.

7. The instruction processing method as described in claim 4, characterized in that, The data cache has a second bit width, and there are multiple data caches; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is stored sequentially in each data cache according to a preset order; the preset order corresponds to the data position of the sub-target data in the target data; The step of performing corresponding processing on the target data formed from the accessed sub-target data according to the operation information includes: concatenating the target data based on the data position of the sub-target data; Based on the target data, perform the corresponding processing.

8. The instruction processing method as described in claim 4, characterized in that, The bit width of the data cache is the first bit width; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is stored sequentially in different data bits of the data cache according to a preset order, and the preset order corresponds to the data position of the sub-target data in the target data; The step of performing corresponding processing on the target data formed from the accessed sub-target data according to the operation information specifically involves performing corresponding processing based on the target data stored in the data cache.

9. The instruction processing method as described in claim 4, characterized in that, The step of decoding the instruction to be executed based on the first bit width to determine the corresponding operation information and the address to be accessed further includes: storing the operation information corresponding to the decoding into the transmission queue, and configuring the operation information stored in the transmission queue to a sleep state; In the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, the operation information corresponding to the access is obtained after the launch queue is woken up, so as to perform the access to the corresponding target sub-access address.

10. The instruction processing method as described in claim 4, characterized in that, The steps of splitting the address to be accessed into multiple sub-access addresses based on the second bit width, accessing the sub-target data based on the sub-access addresses, and determining whether the access exception is an error suppression exception when an access exception exists, are executed based on the scheduling unit and the access unit. The scheduling unit is equipped with a slow-mode state machine, which contains an address storage unit for storing the target starting address. The slow-mode state machine is started based on a slow-mode flag.

11. The instruction processing method as described in claim 10, characterized in that, The slow-mode state machine is configured with the following states: The waiting initialization state indicates that the current slow mode state machine is in a waiting initialization state. The initialization is to obtain the operation information of the instruction to be executed from the self-emission queue and configure the address information in the address storage unit as the starting address of the address to be accessed. The waiting-to-wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be woken up. In multiple sub-memory access loop processes, the waiting-to-wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information. Address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein, the address generation port is used to enable the address generator to generate the target sub-access address; One of the sub-memory access loop processes is used to perform a memory access to a target sub-access address. After entering the sub-memory access loop process, the slow mode state machine executes multiple sub-memory access loop processes based on the switching between the waiting wake-up state and the address preemption state.

12. An instruction processing device, characterized in that, include: The instruction acquisition module is used to acquire the instruction to be executed in slow mode. The instruction to be executed is the instruction corresponding to the exception that triggers the switch of instruction execution mode from fast mode to slow mode. The decoding module is used to decode the instruction to be executed based on the first bit width to determine the corresponding operation information and the address to be accessed; the address to be accessed is used to access target data with the first bit width, where the first bit width is the data bit width corresponding to the instruction to be executed in fast mode; The memory access scheduling module is used to split the address to be accessed into multiple sub-access addresses based on the second bit width, and to perform memory access on the sub-target data based on the sub-access addresses, as well as to determine whether the memory access exception is an error suppression exception when there is a memory access exception. The processing module is used to perform corresponding processing on the target data formed by the accessed sub-target data according to the operation information after all the sub-target data corresponding to all sub-access addresses have been accessed and stored.

13. The instruction processing apparatus as claimed in claim 12, characterized in that, The instruction acquisition module is an instruction fetching unit, which is used to execute the instruction fetching process in fast mode. The decoding module is a decoding unit, which is used to execute the decoding process in fast mode; The processing module is a computing unit, which is used to execute the computing process in fast mode.

14. The instruction processing apparatus as claimed in claim 12, characterized in that, The scheduling and memory access module includes a scheduling unit and a memory access unit; wherein, the scheduling unit is configured with a slow mode state machine; the slow mode state machine is configured with an address storage unit, the address storage unit is used to store the target starting address, the target starting address is the starting address of the target sub-access address, the target sub-access address is used to indicate the currently executed sub-access address; the slow mode state machine is triggered to start based on a slow mode flag.

15. The instruction processing apparatus as claimed in claim 14, characterized in that, The slow-mode state machine is configured with the following states: The waiting initialization state indicates that the current slow mode state machine is in a waiting initialization state. The initialization is to obtain the operation information of the instruction to be executed from the self-emission queue and configure the address information in the address storage unit as the starting address of the address to be accessed. The waiting-to-wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be woken up. In multiple sub-memory access loop processes, the waiting-to-wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information. Address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein, the address generation port is used to enable the address generator to generate the target sub-access address; One of the sub-memory access loop processes is used to perform a memory access to a target sub-access address. After entering the sub-memory access loop process, the slow mode state machine executes multiple sub-memory access loop processes based on the switching between the waiting wake-up state and the address preemption state.

16. A processor, characterized in that, Includes the instruction processing apparatus as described in any one of claims 12-15.

17. An electronic device, characterized in that, Includes the processor as described in claim 16.

Images