Data storage system comprising interface device

Abstract

A data storage system including an interface device is disclosed. In some embodiments, a data storage system includes: a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication paths; and an interface device configured to include N communication paths to connect to M communication paths of the controller and a host device including the N communication paths, in which the interface device includes: a connector configured to connect the N communication paths of the host device to the N communication paths of the interface device; and a selector configured to selectively activate M communication paths of the N communication paths of the interface device to transmit data to or receive data from the M communication paths of the controller in response to a host port type identification signal received from the host device.

Description

Technical Field

[0001] This patent document relates to an interface device for a data storage system. Background Art

[0002] A data storage system, such as a hard disk drive (HDD) or solid-state drive (SSD), is a computer component or electronic system that stores data, such as operating systems, applications, and user files. Data storage systems can have different types of interfaces that define how data is transferred between the data storage system and other devices, such as a host device. Summary of the Invention

[0003] In some embodiments, the disclosed technology can be implemented to connect a data storage system whose PCIe lane port type is different from that of a host device by using a switching circuit and a switching algorithm.

[0004] In some embodiments of the disclosed technology, a data storage system may include: a controller connected to multiple memory devices to control memory operations of the multiple memory devices and including M communication paths; and an interface device configured to include N communication paths to connect to a host device including the N communication paths and the M communication paths of the controller, wherein the interface device includes: a connector configured to connect the N communication paths of the host device to the N communication paths of the interface device; and a selector configured to selectively activate M of the N communication paths of the interface device in response to a host port type identification signal received from the host device to send data to or receive data from the M communication paths of the controller.

[0005] In some embodiments of the disclosed technology, a method of operating a data storage system may include: receiving data from a host device having N communication paths through N communication paths of the data storage system, where N is a natural number; receiving a host port type identification signal from the host device; activating M of the N communication paths of the data storage system in response to the host port type identification signal to perform data communication in the data storage system, where N is a natural number greater than M; and performing data communication between the host device and a controller in the data storage system using the activated M communication paths.

[0006] In some embodiments of the disclosed technology, a data storage system may include: a memory device including multiple memory areas configured to store data; a controller connected to the memory device and including M communication paths, where M is a natural number; and an interface device including N communication paths and configured to perform a method including: receiving data from a host device having N communication paths through the N communication paths of the interface device, where N is a natural number greater than M; receiving a host port type identification signal from the host device; activating M of the N communication paths of the interface device in response to the host port type identification signal to perform data communication in the data storage system; and performing data communication between the host device and the controller in the data storage system using the activated M communication paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An example of a memory system that may be used to implement some embodiments of the disclosed technology is shown.

[0008] Figure 2 An example configuration of a host system and a data storage system in communication with the host system that can be used to implement some embodiments of the disclosed technology is shown.

[0009] Figure 3A An example configuration of a host and a data storage system including an interface device based on some embodiments of the disclosed technology is shown. Figure 3B Another example configuration of a host and a data storage system including a PCIe U3 / U2 combo connector, a PCIe switch, and a controller is shown.

[0010] Figure 4 is a flow chart illustrating an example interface algorithm based on some embodiments of the disclosed technology. DETAILED DESCRIPTION

[0011] An interface is a standard that defines how data is transferred between a storage device and other devices, such as a host device. Among them, the PCIe (Peripheral Component Interconnect Express) interface is a high-speed interface standard for connecting various internal components in computer systems. Data storage systems, such as solid-state drives (SSDs), have widely adopted the PCIe interface to communicate with the host. In the example of PCIe, which includes four lanes of the PCIe interface for sending and receiving data, two types of physical connections can be used: U.2 and U.3. U.2 and U.3 can share the same two PCIe lanes, but each can have two dedicated PCIe lanes. Therefore, U.2- and U.3-compatible SSDs require the use of six PCIe lanes in the system-on-chip (SoC) controller, increasing the design complexity and cost of the SoC controller.

[0012] A PCIe host may have a host port type such as U.2 or U.3, and U.2 and U.3 compatible SSDs may connect to the PCIe host and operate by auto-detection between the host and the SSD drive via a device identification (ID) and a host port type ID.

[0013] The U.3 interface was added to the PCIe interface standard after the U.2 interface, so previous SoC controllers used U.2's four PCIe lanes, and PCIe U.2 and U.3 compatible SSDs that required six PCIe lanes could not be used.

[0014] The disclosed technology can be implemented in certain embodiments to provide a printed circuit board (PCB)-level architecture and design methodology for a PCIe U.2 and U.3-compatible SSD that uses only four PCIe lanes of a SoC, simplifying next-generation SoC design and saving overall SSD development time. Additionally, the disclosed technology can be implemented in certain embodiments to leverage previously developed SoCs with four PCIe U.2 lanes for PCIe U.2 and U.3-compatible SSDs.

[0015] Figure 1 An example of a memory system 100 that can be used to implement some embodiments of the disclosed technology is shown. Memory system 100 includes a memory module 110, which can be used to store information for use by other electronic devices or systems. Memory system 100 can be incorporated into other electronic devices and systems (e.g., located on a circuit board). Alternatively, memory system 100 can be implemented as an external storage device, such as a USB flash drive or a solid-state drive (SSD).

[0016] Memory module 110 included in memory system 100 may include memory regions (e.g., memory arrays) 102, 104, 106, and 108. Each of memory regions 102, 104, 106, and 108 may be included in a single memory die or multiple memory dies. The memory dies may be included in an integrated circuit (IC) chip.

[0017] Each of the memory regions 102, 104, 106, and 108 includes a plurality of memory cells. A read operation, a program operation, or an erase operation can be performed in units of memory cells. Thus, each memory cell can include a predetermined number of memory cells. The memory cells in the memory regions 102, 104, 106, or 108 can be included in a single memory die or in multiple memory dies.

[0018] The memory cells in each of the memory regions 102, 104, 106, and 108 may be arranged in rows and columns within a memory unit. Each of the memory units may be a physical unit. For example, a group of multiple memory cells may form a memory unit. Each of the memory units may also be a logical unit. For example, a memory unit may be a bank, block, or page, which may be identified by a unique address such as a bank address, a block address, or a page base address. During a read operation or a write operation, a unique address associated with a particular memory unit may be used to access the particular memory unit. Based on the unique address, information may be written to or retrieved from one or more memory cells within the particular memory unit.

[0019] The memory cells in memory regions 102, 104, 106, and 108 may include nonvolatile memory cells. Examples of nonvolatile memory cells include flash memory cells, phase-change random access memory (PRAM) cells, magnetoresistive random access memory (MRAM) cells, or other types of nonvolatile memory cells. In an example embodiment where the memory cells are configured as NAND flash memory cells, read operations or write operations may be performed in units of pages. However, erase operations in NAND flash memory are performed in units of blocks.

[0020] Each of the non-volatile memory cells can be configured as a single-level cell (SLC) or a multi-level memory cell. A single-level cell can store one bit of information per cell. A multi-level memory cell can store more than one bit of information per cell. For example, each memory cell in memory regions 102, 104, 106, and 108 can be configured as a multi-level cell (MLC) storing two bits of information per cell, a triple-level cell (TLC) storing three bits of information per cell, or a quad-level cell (QLC) storing four bits of information per cell. In another example, each memory cell in memory region 111 can be configured to store at least one bit of information (e.g., one bit of information or multiple bits of information), and each memory cell in memory region 112 can be configured to store more than one bit of information.

[0021] like Figure 1As shown, the memory system 100 includes a controller module 120. The controller module 120 includes a memory interface 121 for communicating with the memory module 110, a host interface 126 for communicating with a host (not shown), a processor 124 for running firmware-level code, and a buffer / cache 123 and system memory 122 for temporarily or permanently storing executable firmware / instructions and related information. In some embodiments, the controller module 120 may include an error correction engine 125 for performing error correction operations on information stored in the memory module 110. The error correction engine 125 may be configured to detect / correct single-bit errors or multiple-bit errors. In another embodiment, the error correction engine 125 may be located in the memory module 110.

[0022] In some embodiments, the controller module 120 may further include a host interface 126 for communicating with a host. The host interface 126 may include a component that complies with at least one host interface specification, including but not limited to Serial Advanced Technology Attachment (SATA), Serial Small Computer System Interface (SAS), and Peripheral Component Interconnect Express (PCIe).

[0023] The controller module 120 may include an error correction code (ECC) engine 125 configured to receive data to be written to the plurality of memory regions 102, 104, 106, 108 and generate codewords. For example, the ECC engine 125 may include an encoder, such as a low-density parity check (LDPC) encoder, configured to encode the data using an error correction code.

[0024] The ECC engine 125 may also be configured to receive data and process the received data using an error correction code (e.g., an LDPC decoder). The LDPC decoder may be configured to decode data read from the plurality of memory regions 102, 104, 106, 108 to detect and correct one or more erroneous bits present in the data until the error correction capability of the ECC scheme is reached.

[0025] Figure 2 An example configuration of a host 210 and a data storage system 220 in communication with the host 210 is shown that can be used to implement some embodiments of the disclosed technology.

[0026] Host 210 may be a device or system including one or more processors 212 that are operable to retrieve data from, store or write data to, a data storage system 220. In some embodiments, examples of hosts may include personal computers (PCs), portable digital devices, digital cameras, digital multimedia players, televisions, and wireless communication devices. In some embodiments, host 210 may include interface circuitry 214 to communicate with data storage system 220 via communication path 230.

[0027] The data storage system 220 includes a memory device 220 that can be used to store information used by the host 210. In some embodiments, the data storage system 220 may include the memory system 100. The memory system 100 includes Figure 1 108. In some embodiments, the memory regions 102, 104, 106, 108 may include a memory cell array comprising a NAND flash memory array divided into a number of blocks, with each block containing a certain number of pages. Each block includes a plurality of memory cell strings, and each memory cell string includes a plurality of memory cells.

[0028] Some examples of data storage system 220 include solid-state drives (SSDs), which are data storage devices that utilize non-volatile memory (e.g., flash memory) and / or volatile memory (e.g., synchronous dynamic random access memory; SDRAM) to store data. For example, data storage system 220 may include multiple flash memory devices using multi-level cell (MLC) technology. Each memory device includes multiple memory blocks, and each of the multiple memory blocks includes multiple memory cells. Each memory cell can be programmed to one of multiple programming states. The data stored in each memory cell can be read using multiple read thresholds.

[0029] In some embodiments where the memory cell array is a NAND flash memory array, read operations and write (program) operations are performed in units of pages, and erase operations are performed in units of blocks. Before performing a programming operation on any page included in a block, all memory cells within the same block must be erased simultaneously. In an embodiment, the NAND flash memory may use an even / odd bit line structure. In another embodiment, the NAND flash memory may use an all-bit line structure. In the even / odd bit line structure, even bit lines and odd bit lines are interleaved along each word line and are accessed alternately so that each pair of even bit lines and odd bit lines can share peripheral circuits such as page buffers. In the all-bit line structure, all bit lines are accessed simultaneously.

[0030] In some embodiments, the data storage system 220 may further include an interface device 226 configured to provide communication between the data storage system 220 and the host 210. In one example, the data storage system 220 may include Figure 1 In some embodiments, the data storage system 220 may further include a controller 224 for controlling the operation of the memory device 222 and / or the interface device 226. In one example, the controller 224 may include any type of controller or processor capable of providing the functionality described herein.

[0031] As mentioned above, a specific SoC controller using four PCIe lanes of U.2 cannot be used by PCIe U.2 and U.3 compatible SSDs that require six PCIe lanes. In some embodiments, the disclosed technology can be implemented to address these issues by providing a PCB-level design to implement a U.2 and U.3 compatible SSD using four PCIe lanes of the SoC controller.

[0032] Figure 3A An example configuration of a host 310 based on some embodiments of the disclosed technology and a data storage system 320 including an interface device 321 is shown. In some embodiments, based on some embodiments of the disclosed technology, the interface device 321 may include a connector (e.g., a PCIe U3 / U2 combo connector) 322, a selector (e.g., a PCIe switch) 324, and a system-on-chip (SoC) controller 326 including multiple PCIe lanes. Figure 3B Another example configuration of a host 310 and a data storage system 320 is shown. The data storage system 320 includes a PCIe U3 / U2 combo connector 322 , a PCIe switch 324 , and a controller 326 .

[0033] like Figure 3AAs shown, host 310 may include interface circuitry 312, which includes a host port type selector 314. In some embodiments, host port type selector 314 is coupled to or communicates with data storage system 320 to select one of multiple types of physical connections, allowing data storage system 320 to transmit data and signals according to the selected physical connection type. For example, host 310 having N PCIe lanes may connect to data storage system 320 including SoC 326 having M PCIe lanes using interface device 321. Interface device 321 includes N PCIe lanes and activates M of the N PCIe lanes of data storage system 320 in response to a selected physical connection type. In one example, N and M are natural numbers, and N is greater than M. In some embodiments, interface device 321 selectively activates PCIe lanes in response to the selected physical connection type. For example, the interface device 321 selectively activates M PCIe lanes among N PCIe lanes of the data storage system 320 and deactivates NM PCIe lanes in response to a selected physical connection type (eg, a host port type identification signal).

[0034] In some embodiments of the disclosed technology, the interface device 321 may include a connector 322 configured to connect a communication path 330 (e.g., N PCIe lanes) from the host 310 to a selector 324, the selector 324 configured to selectively activate M of the N PCIe lanes 332 of the interface device 321 in response to a host port type identification signal 315 from a host port type selector 316 to perform communication between the host 310 configured to include N PCIe lanes and the SoC 326 configured to include M PCIe lanes 334.

[0035] In some embodiments, one of two port types, U.2 and U.3, can be used for a host and a data storage system that includes a PCIe interface that uses a certain number of lanes to send and receive data between the host and a SoC controller in the data storage system. In some embodiments, U.2 and U.3 can share the same two PCIe lanes, but U.2 and U.3 can each have two dedicated PCIe lanes. In some embodiments of the disclosed technology, such as Figure 3BAs shown, at the PCB design level, multiple PCIe switches 324 can be used to activate four of the six PCIe lanes of a PCIe connector 322, which interfaces between a host (PCIe host) 310 and a data storage device 320 to send or receive data to or from a SoC (system on chip) controller 326 that includes four PCIe lanes. In this way, a host running on U.2 or U.3 can connect to a data storage system that includes a SoC controller with fewer PCIe lanes than the host.

[0036] In some embodiments of the disclosed technology, the data storage system (e.g., SSD) 320 may include a PCIe connector (e.g., a PCIe U3 / U2 combo connector) 322 to connect the communication path of the data storage system to the communication path of the host 310. In some embodiments, as Figure 3B As shown, the PCIe U3 / U2 combination connector 322 may include 6 PCIe lanes, and each lane includes a pair of transmitter differential signal lines TXp / n and receiver differential signal lines RXp / n.

[0037] Figure 3BIn the specification, the terms "U3 L0," "U3 L1," "U3 L2," and "U3 L3" represent lane 0, lane 1, lane 2, and lane 3 of the U.3 port type, respectively. The terms "U2 L0," "U2 L1," "U2 L2," and "U2 L3" represent lane 0, lane 1, lane 2, and lane 3 of the U.2 port type, respectively. The term "TXp / n: S2, S3" represents the PCIe differential signals TXp and TXn transmitted to the connector physical pins S2 and S3, respectively, and the term "RXn / p: S5, S6" represents the PCIe differential signals RXn and RXp transmitted to the connector physical pins S5 and S6, respectively. The term "TXp / n: E10, E11" indicates PCIe differential signals TXp and TXn transmitted to connector physical pins E10 and E11, respectively, and the term "RXn / p: E13, E14" indicates PCIe differential signals RXn and RXp transmitted to connector physical pins E13 and E14, respectively. The term "TXp / n: S9, S10" indicates PCIe differential signals TXp and TXn transmitted to connector physical pins S9 and S10, respectively, and the term "RXn / p: S12, S13" indicates PCIe differential signals RXn and RXp transmitted to connector physical pins S12 and S13, respectively. The term "TXp / n: S17, S18" indicates PCIe differential signals TXp and TXn transmitted to connector physical pins S17 and S18, respectively, and the term "RXn / p: S20, S21" indicates PCIe differential signals RXn and RXp transmitted to connector physical pins S20 and S21, respectively. The term "TXp / n: S23, S24" indicates PCIe differential signals TXp and TXn transmitted to connector physical pins S23 and S24, respectively, and the term "RXn / p: S26, S27" indicates PCIe differential signals RXn and RXp transmitted to connector physical pins S26 and S27, respectively. The term “TXp / n: E17, E18” represents PCIe differential signals TXp and TXn transmitted to connector physical pins E17 and E18, respectively, and the term “RXn / p: E20, E21” represents PCIe differential signals RXn and RXp transmitted to connector physical pins E20 and E21, respectively.

[0038] In some embodiments of the disclosed technology, a U.3 port uses four lanes, a U.2 port uses four lanes, and the U.2 port and the U.3 port share one or more lanes.

[0039] In some embodiments, a U.3 port uses four lanes: U3 L0, U3 L1, U3 L2, and U3 L3, and a U.2 port uses four lanes: U2 L0, U2 L1, U2 L2, and U2 L3, with U2 L1 and U3 L2 sharing the same lane, and U2 L2 and U3 L3 sharing the same lane. In some embodiments, U2 L0, U2 L3, U3 L0, and U3 L1 are dedicated lanes.

[0040] In some embodiments of the disclosed technology, Figure 3B As shown, the host 310 includes a total of six PCIe lanes and operates using either a U.2 port or a U.3 port at a time.

[0041] In some embodiments of the disclosed technology, the host 310 outputs one or more host port type ID signals to connect to specific PCIe connector physical pins. In one example, the host 310 outputs a first host port type ID signal HPT0 and a second host port type ID signal HPT1 to connect to PCIe connector physical pins S15 and E16, respectively. In some embodiments, when the first host port type ID signal HPT0 is "open" or at a logic high level ("1"), the host 310 can be determined to be a U.2 host, and when the host port type ID signal HPT0 is "grounded" or at a logic low level ("0"), the host 310 can be determined to be a U.3 host. In some embodiments, when the second host port type ID signal HPT1 is "open" or at a logic high level ("1"), the host interface can be determined to be a PCIe interface.

[0042] In some embodiments of the disclosed technology, SoC 326 may be an SSD SoC controller that includes four PCIe lanes. In some implementations, all four PCIe lanes are always active.

[0043] In some embodiments of the disclosed technology, reference is made to Figure 3A , the connector 322 and the selector may include N PCIe lanes connected to the N PCIe lanes of the host 310, and the selector 324 may activate M of its N PCIe lanes to communicate with the M PCIe lanes of the SoC 326 in response to the host port type identification signal 315. In one example, Figure 3B As shown, the PCIe switch 324 can be used to connect the four PCIe lanes of the SoC to the U.2 port or U.3 port of the host 310 by activating four of the six PCIe lanes in response to the HPTO signal from the host 310.

[0044] In some embodiments of the disclosed technology, the PCIe switch 224 may include one or more switching circuits, such as a multiplexer and a demultiplexer. Figure 3B The PCIe switch 224 may include one or more multiplexers and one or more demultiplexers. In some embodiments, when the HPT0 signal is at a logic low level ("0"), the select pins of one or more multiplexers and one or more demultiplexers in the PCIe switch 224 are at a logic low level ("0"), and the PCIe switch 224 connects the four PCIe lanes of the SoC to the U.3 port of the host 310. When the PCIe switch 224 connects the four PCIe lanes of the SoC to the U.3 port of the host 310, the transmit signal (TX) and the receive signal (RX) move between the "A" pin and the "B" pin. In some embodiments, when the HPT0 signal is at a logic high level ("1"), the select pins of one or more multiplexers and one or more demultiplexers in the PCIe switch 224 are at a logic high level ("1"), and the PCIe switch 224 connects the four PCIe lanes of the SoC to the U.2 port of the host 310. When the PCIe switch 224 connects the four PCIe lanes of the SoC to the U.2 port of the host 310 , transmit signals (TX) and receive signals (RX) move between the “A” pin and the “C” pin.

[0045] In some embodiments of the disclosed technology, Figure 3B As shown, the PCIe connector 322 may include: one or more public PCIe lanes (e.g., U3L2 / U2L1, U3L3 / U2 / L2) connected to the input ports of one or more demultiplexers in the PCIe switch 224; and one or more dedicated PCIe lanes (e.g., U3L0, U3L1 dedicated to U3 port type, U2L0, U2L3 dedicated to U2 port type) connected to the input ports of one or more multiplexers in the PCIe switch 224.

[0046] In some embodiments of the disclosed technology, PCIe switch 224 may include one or more cascaded switch circuits. For example, PCIe switch 224 may include a first switch circuit column and a second switch circuit column connected to the first switch circuit column, such that an input of the first switch circuit column is coupled to a PCIe lane of the host 310, an output of the first switch circuit column is coupled to an input of the second switch circuit column, and an output of the second switch circuit column is coupled to a PCIe lane of the SoC. In some embodiments, the first switch circuit column and the second switch circuit column are activated in response to the same select signal (e.g., an HPTO signal) from the host 310. In this manner, by activating M of the N PCIe lanes of the interface device, the N PCIe lanes of the host 310 can communicate with the M PCIe lanes of the SoC 326 via the N PCIe lanes of the interface device.

[0047] Table 1 shows an example of the PCIe combo connector pinout of the SFF-TA-1001 specification based on the generic x4 link definition of SFF-8639 and PCIe lane assignments between the SoC lane and the host lane for U.2 and U.3.

[0048] Table 1 PCIe combo connector pin assignment

[0049] S15 (HPT0) SoC L0 SoC L1 SoC L2 SoC L3 "0" for U.3 L0 (S2, S3) (S5, S6) L1 (S9, S10) (S12, S13) L2 (S17, S18) (S20, S21) L3 (S23, S24) (S26, S27) "1" for U.2 L0 (E10, E11) (E13, E14) L1 (S17, S18) (S20, S21) L2 (S23, S24) (S26, S27) L3 (E17, E18) (E20, E21)

[0050] As shown in Table 1, each PCIe lane can be logically associated or mapped to a SoC lane and host port type ID signal S15. For example, U3.L0 corresponds to / S15·SoC.L0, U2.L0 corresponds to S15·SoC.L0, U3.L1 corresponds to / S15·SoC.L1, [U3.L2, U2.L1] corresponds to / S15·SoC.L2+S15·SoC.L1, [U3.L3, U2.L2] corresponds to / S15·SoC.L3+S15·SoC.L2, and U2.L3 corresponds to S15·SoC.L3.

[0051] In some embodiments of the disclosed technology, the PCIe switch 324 may be configured to implement the above logical relationship. Figure 3BAs shown, PCIe switch 324 may include multiple switches, such as four multiplexers U1, U2, U3, and U4, and two demultiplexers U5 and U6, which are controlled by the HPT (Host Port Type) signal S15. When S15 is "0," both the A and B terminals of all switches (all multiplexers and demultiplexers) are in the "on" state, selecting the U.3 port of host 310. When S15 is "1," both the A and C terminals of all switches (all multiplexers and demultiplexers) are in the "on" state, selecting the U.2 port of host 310. In this way, the four lanes of the SoC can be automatically connected to either a U.3 port or a U.2 port based on the (HPT) host port type signal.

[0052] In some embodiments, the disclosed technology can be implemented to provide a PCB-level solution for U.3 and U.2 compatible SSD designs by activating some of the PCIe lanes of the interface device to communicate with the SoC controller, where the SoC controller has a smaller number of PCIe lanes than the host.

[0053] Figure 4 is a flow chart illustrating a set of example operations for implementing a PCIe switch method based on some embodiments of the disclosed technology.

[0054] The method includes: at 410, receiving data from a host device having N communication paths through N communication paths of an interface device of a data storage system, where N is a natural number; at 420, receiving a host port type identification signal from the host device; at 430, activating M communication paths of the N communication paths of the interface device in response to the host port type identification signal to perform data communication in the data storage system, where N is a natural number greater than M; at 440, performing data communication between the host device and a controller in the data storage system using the activated M communication paths.

[0055] Thus, various embodiments of the features of the disclosed technology can be implemented based on the above disclosure, including the examples listed below.

[0056] Example 1 A data storage system includes: a controller connected to multiple memory devices to control memory operations of the multiple memory devices, and including M communication paths, where M is a natural number; and an interface device configured to include N communication paths to connect to a host device including N communication paths and the M communication paths of the controller, where N is a natural number greater than M, wherein the interface device includes: a connector configured to connect the N communication paths of the host device to the N communication paths of the interface device; and a selector configured to activate M of the N communication paths of the interface device in response to a host port type identification signal received from the host device to send data to or receive data from the M communication paths of the controller.

[0057] Example 2 A system according to Example 1, wherein the selector includes: one or more second switch circuits configured to receive input from a connector; and one or more first switch circuits configured to receive input from the connector or at least one of the one or more second switch circuits, wherein the output ends of the one or more second switch circuits and the input ends of the one or more first switch circuits are selected in response to a host port type identification signal received from a host device.

[0058] Example 3: The system of Example 2, wherein the one or more first switching circuits include a multiplexer and the one or more second switching circuits include a demultiplexer.

[0059] Example 4 A system according to Example 2, wherein the connector includes: one or more shared input terminals capable of connecting to one or more shared paths used by multiple host port types; and one or more dedicated input terminals capable of connecting to one or more dedicated paths used by specific host port types among the multiple host port types, wherein the input terminals of the one or more second switching circuits are configured to receive inputs from the one or more shared paths, and the input terminals of the one or more first switching circuits are configured to receive inputs from at least one of the one or more shared paths or the one or more dedicated paths.

[0060] Example 5 A system according to Example 4, wherein the one or more second switching circuits configured to receive inputs from one or more shared paths include a demultiplexer, and the one or more first switching circuits configured to receive inputs from at least one of the one or more shared paths or the one or more dedicated paths include a multiplexer.

[0061] Example 6: The system of Example 2, wherein the one or more first switching circuits include first to fourth multiplexers, and the one or more second switching circuits include a first demultiplexer and a second demultiplexer.

[0062] Example 7 A system according to Example 6, wherein the first demultiplexer and the second demultiplexer are configured to receive input from a connector, the first multiplexer is configured to receive input from the connector, the second multiplexer is configured to receive input from the connector and the first demultiplexer, the third multiplexer is configured to receive input from the first demultiplexer and the second demultiplexer, and the fourth multiplexer is configured to receive input from the connector and the second demultiplexer.

[0063] Example 8. The system of Example 7, wherein the output of the one or more demultiplexers and the input of the one or more multiplexers are selected in response to a host port type identification signal received from the host device.

[0064] Example 9 A system according to Example 7, wherein the connector includes: a first shared input terminal and a second shared input terminal, capable of connecting to a first shared path and a second shared path used by multiple host port types; and first to fourth dedicated input terminals, capable of connecting to first to fourth dedicated paths used by a specific host port type among the multiple host port types.

[0065] Example 10 A system according to Example 9, wherein the input ends of the first demultiplexer and the second demultiplexer are configured to receive inputs from the first shared path and the second shared path, and the input ends of the first to fourth multiplexers are configured to receive inputs from the first shared path and the second shared path or at least one of the first to fourth dedicated paths.

[0066] Example 11 A method for operating a data storage system, the method comprising: receiving data from a host device having N communication paths through N communication paths of an interface device of the data storage system, where N is a natural number; receiving a host port type identification signal from the host device; selectively activating M of the N communication paths of the interface device in response to the host port type identification signal to perform data communication in the data storage system, where N is a natural number greater than M; and performing data communication between the host device and a controller in the data storage system using the activated M communication paths.

[0067] Example 12 A method according to Example 11, wherein activating M of the N communication paths of the interface device includes: activating one of a first input end and a second input end of a first switch circuit in response to a host port type identification signal, wherein the first input end of the first switch circuit is connected to a first dedicated path dedicated to the first host port type, and the second input end of the first switch circuit is connected to a second dedicated path dedicated to the second host port type.

[0068] Example 13 A method according to Example 11, wherein activating M of the N communication paths of the interface device includes: activating one of a first output terminal and a second output terminal of a second switch circuit in response to a host port type identification signal, wherein an input terminal of the second switch circuit is connected to a shared path shared by the first port type and the second port type.

[0069] Example 14 The method according to Example 13, wherein activating M communication paths out of N communication paths of the interface device further includes: activating one of the first input terminal and the second input terminal of the first switching circuit in response to the host port type identification signal, wherein one of the first input terminal and the second input terminal is connected to the activated output terminal out of the first output terminal and the second output terminal of the second switching circuit.

[0070] Example 15 The method of Example 11, wherein activating M of the N communication paths of the interface device comprises selecting one of the plurality of inputs of the first switching circuit and selecting one of the plurality of outputs of the second switching circuit.

[0071] Example 16 A data storage system includes: a memory device including a plurality of memory areas configured to store data; a controller connected to the memory device and including M communication paths, where M is a natural number; and an interface device including N communication paths and configured to perform a method including: receiving data from a host device having N communication paths through the N communication paths of the interface device, where N is a natural number greater than M; receiving a host port type identification signal from the host device; activating M of the N communication paths of the interface device in response to the host port type identification signal to perform data communication in the data storage system; and performing data communication between the host device and the controller in the data storage system using the activated M communication paths.

[0072] Example 17 A system according to Example 16, wherein activating M of the N communication paths of the interface device includes: activating one of a first input terminal and a second input terminal of a first switch circuit in response to a host port type identification signal, wherein the first input terminal of the first switch circuit is connected to a first dedicated path dedicated to the first host port type, and the second input terminal of the first switch circuit is connected to a second dedicated path dedicated to the second host port type.

[0073] Example 18 A system according to Example 16, wherein activating M of the N communication paths of the interface device includes: activating one of a first output terminal and a second output terminal of a second switch circuit in response to a host port type identification signal, wherein an input terminal of the second switch circuit is connected to a shared path shared by the first port type and the second port type.

[0074] Example 19 A system according to Example 18, wherein activating M of the N communication paths of the interface device further includes: activating one of the first input terminal and the second input terminal of the first switching circuit in response to a host port type identification signal, wherein one of the first input terminal and the second input terminal is connected to the activated output terminal of the first output terminal and the second output terminal of the second switching circuit.

[0075] Example 20: The system of Example 16, wherein activating M of the N communication paths of the interface device comprises selecting one of the plurality of inputs of the first switching circuit and selecting one of the plurality of outputs of the second switching circuit.

[0076] The embodiments of the subject matter and functional operations described in this patent document can be implemented in various systems, digital electronic circuits or computer software, firmware or hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The embodiments of the subject matter described in this specification can be implemented as one or more computer program products, that is, modules of one or more computer program instructions encoded on a tangible and non-transitory computer-readable medium for being run by a data processing device or controlling the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material composition that affects a machine-readable propagation signal, or a combination of one or more of them. The term "processor" covers all devices, devices and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the device can include code that creates an operating environment for the computer program in question, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system or a combination of one or more of them.

[0077] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored as part of a file that contains other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of code). A computer program can be deployed to run on a single computer or on multiple computers located at a single site or distributed across multiple sites and interconnected by a communications network.

[0078] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0079] Processors suitable for running computer programs include, for example, general-purpose and special-purpose microprocessors, as well as any one or more processors of any type of digital computer. Typically, a processor will receive instructions and data from read-only memory or random access memory, or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include or be operatively coupled to receive data from or transfer data to one or more mass storage devices (e.g., magnetic, magneto-optical, or optical disks) for storing data. However, a computer need not include such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media, and storage devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices. The processor and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0080] This specification and the accompanying drawings should be regarded as exemplary only, where exemplary refers to examples. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of "or" is intended to include "and / or" unless the context clearly indicates otherwise.

[0081] Although this patent document contains many details, these should not be construed as limitations on the scope of any invention or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Specific features described in this patent document in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, individual features described in the context of a single embodiment may also be implemented in a variety of embodiments, alone or in any suitable subcombination. Furthermore, although the above-mentioned features may be described as, or even initially claimed to work in, a particular combination, in some cases one or more features in a claimed combination may be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of subcombinations.

[0082] Similarly, while operations may be depicted in a particular order in the drawings, this should not be understood as requiring that these operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desired results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0083] Only a few embodiments and examples are described, and other embodiments, enhancements, and variations can be made based on what is described and illustrated in this patent document.

Claims

1. A data storage system, comprising: a controller coupled to the plurality of memory devices to control memory operations of the plurality of memory devices and comprising M communication paths, where M is a natural number; as well as An interface device comprising N communication paths for connecting to a host device comprising N communication paths and M communication paths of the controller, wherein N is a natural number greater than M, and the interface device comprises: a connector to connect the N communication paths of the host device to the N communication paths of the interface device; as well as The selector selectively activates M communication paths of the N communication paths of the interface device in response to a host port type identification signal received from the host device to send data to or receive data from the M communication paths of the controller.

2. The system according to claim 1, wherein: The selector includes: one or more second switch circuits that receive input from the connector; and one or more first switch circuits that receive input from the connector or at least one of the one or more second switch circuits, wherein the output ends of the one or more second switch circuits and the input ends of the one or more first switch circuits are selected in response to a host port type identification signal received from the host device.

3. The system according to claim 2, wherein: The one or more first switching circuits include a multiplexer, and the one or more second switching circuits include a demultiplexer.

4. The system according to claim 2, wherein: The connector includes: one or more shared input ends, capable of connecting to one or more shared paths used by multiple host port types; and one or more dedicated input ends, capable of connecting to one or more dedicated paths used by specific host port types among the multiple host port types, wherein the input ends of the one or more second switching circuits receive inputs from the one or more shared paths, and the input ends of the one or more first switching circuits receive inputs from at least one of the one or more shared paths or the one or more dedicated paths.

5. The system according to claim 4, wherein: The one or more second switching circuits receiving input from the one or more shared pathways include a demultiplexer, and the one or more first switching circuits receiving input from at least one of the one or more shared pathways or the one or more dedicated pathways include a multiplexer.

6. The system according to claim 2, wherein: The one or more first switching circuits include a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer, and the one or more second switching circuits include a first demultiplexer and a second demultiplexer.

7. The system according to claim 6, wherein: The first demultiplexer and the second demultiplexer receive input from the connector, the first multiplexer receives input from the connector, the second multiplexer receives input from the connector and the first demultiplexer, the third multiplexer receives input from the first demultiplexer and the second demultiplexer, and the fourth multiplexer receives input from the connector and the second demultiplexer.

8. The system according to claim 7, wherein: One or more demultiplexer outputs and one or more multiplexer inputs are selected in response to a host port type identification signal received from the host device.

9. The system according to claim 7, wherein: The connector includes: a first shared input terminal and a second shared input terminal, which can be connected to a first shared path and a second shared path used by multiple host port types; and a first dedicated input terminal to a fourth dedicated input terminal, which can be connected to a first dedicated path to a fourth dedicated path used by a specific host port type among the multiple host port types.

10. The system according to claim 9, wherein: Input ends of the first demultiplexer and the second demultiplexer receive inputs from the first shared path and the second shared path, and input ends of the first multiplexer to the fourth multiplexer receive inputs from at least one of the first shared path and the second shared path or the first dedicated path to the fourth dedicated path.

11. A method of operating a data storage system, comprising: receiving data from a host device having N communication paths through N communication paths of an interface device of the data storage system, wherein N is a natural number; receiving a host port type identification signal from the host device; selectively activating M communication paths of N communication paths of the interface device in response to the host port type identification signal to perform data communication in the data storage system, where N is a natural number greater than M; as well as Data communication is performed between the host device and a controller in the data storage system using the activated M communication paths.

12. The method according to claim 11, wherein Activating M of the N communication paths of the interface device includes: activating one of a first input end and a second input end of a first switch circuit in response to the host port type identification signal, wherein the first input end of the first switch circuit is connected to a first dedicated path dedicated to a first host port type, and the second input end of the first switch circuit is connected to a second dedicated path dedicated to a second host port type.

13. The method according to claim 11, wherein Activating M of the N communication paths of the interface device includes: activating one of a first output terminal and a second output terminal of a second switch circuit in response to the host port type identification signal, wherein an input terminal of the second switch circuit is connected to a shared path shared by the first port type and the second port type.

14. The method according to claim 13, wherein Activating M of the N communication paths of the interface device further includes: activating one of the first input terminal and the second input terminal of the first switch circuit in response to the host port type identification signal, wherein one of the first input terminal and the second input terminal is connected to the activated output terminal of the first output terminal and the second output terminal of the second switch circuit.

15. The method according to claim 11, wherein Activating M communication paths among the N communication paths of the interface device includes selecting one of the plurality of input terminals of the first switch circuit and selecting one of the plurality of output terminals of the second switch circuit.

16. A data storage system comprising: a memory device comprising a plurality of memory areas for storing data; a controller coupled to the memory device and comprising M communication paths, where M is a natural number; as well as An interface device includes N communication paths and performs a method including the following: receiving data from a host device having N communication channels through the N communication channels of the interface device, where N is a natural number greater than M; receiving a host port type identification signal from the host device; activating M of the N communication paths of the interface device in response to the host port type identification signal to perform data communication in the data storage system; as well as Data communication is performed between the host device and a controller in the data storage system using the activated M communication paths.

17. The system according to claim 16, wherein: Activating M of the N communication paths of the interface device includes: activating one of a first input end and a second input end of a first switch circuit in response to the host port type identification signal, wherein the first input end of the first switch circuit is connected to a first dedicated path dedicated to a first host port type, and the second input end of the first switch circuit is connected to a second dedicated path dedicated to a second host port type.

18. The system according to claim 16, wherein: Activating M of the N communication paths of the interface device includes: activating one of a first output terminal and a second output terminal of a second switch circuit in response to the host port type identification signal, wherein an input terminal of the second switch circuit is connected to a shared path shared by the first port type and the second port type.

19. The system according to claim 18, wherein: Activating M of the N communication paths of the interface device further includes: activating one of the first input terminal and the second input terminal of the first switch circuit in response to the host port type identification signal, wherein one of the first input terminal and the second input terminal is connected to the activated output terminal of the first output terminal and the second output terminal of the second switch circuit.

20. The system of claim 16, wherein: Activating M communication paths among the N communication paths of the interface device includes selecting one of the plurality of input terminals of the first switch circuit and selecting one of the plurality of output terminals of the second switch circuit.

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