Calculation circuit and calculation method for integer frequency pulse signal step length

Abstract

The invention relates to the field of internal structure design of processors, and discloses a calculation circuit and a calculation method for integer frequency pulse signal step length. The circuit comprises a user configuration module, an NAND gate, a delay unit, a system counter, a comparator, a latch, a step length counter, an inverter, an AND gate 1, an AND gate 2, a step length latch L1, a step length latch L2, a step length calculation module and a user reading module. By configuring different delay series N, step length clocks with different frequencies are generated for counting of the step length counter, and when the count value of the system counter is equal to the period value of the period register, the count value of the step length counter is latched to the step length latch for calculating the step length. The problem that step length errors are caused by temperature and voltage changes is solved.

Description

Technical Field

[0001] The present invention relates to the field of processor internal structure design, and in particular to a calculation circuit and a calculation method for integer frequency pulse signal step length. Background Art

[0002] In power electronic equipment systems, integer frequency pulse signals are often required. The circuit of integer frequency pulse signals requires a delay unit to work. The delay time of the delay unit does not depend on the clock, but is only related to the process. After the step length is calculated by the delay time of the delay unit, it is used to generate the integer frequency pulse signal. The step length is the delay of the delay module B contained in one system clock cycle. Therefore, the conventional method for calculating the step length S is , T is the system clock period, and M is the delay time of delay module B. After calculating the step length S, it is rounded to an integer to obtain the final step length. Therefore, the existing step length calculation premise requires the known value of the system clock period T and the delay time M of delay module B.

[0003] However, when the chip is operating, the temperature and voltage change, and the value of the system clock period T and the delay time M of the delay module B will change. At the current temperature and voltage, their specific values ​​cannot be accurately known, which will cause deviations in the step length calculation, resulting in errors in the frequency of the integer frequency pulse signal, which is no longer an integer frequency. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a calculation circuit and calculation method for the step length of an integer frequency pulse signal, so that the step length can be calculated without obtaining the value of the system clock period T and the value of the delay time M of the delay module B, thereby solving the problem of step length errors caused by temperature and voltage changes.

[0005] To achieve the above object, the technical solution of the present invention is as follows: A circuit for calculating the step length of an integer frequency pulse signal, comprising a user configuration module, a NAND gate, a delay unit, a system counter, a comparator, a latch, a step length counter, an inverter, an AND gate 1, an AND gate 2, a step length latch L1, a step length latch L2, a step length calculation module, and a user reading module; The user configuration module is used for the user to configure the period value, work enable, delay level N, step latch L1 enable, step latch L2 enable and step calculation enable of the period register; The NAND gate is used to generate a clock signal to the delay unit according to the work enable configured by the user and the step clock returned by the delay unit; The delay unit is used to generate a step clock according to the delay level N configured by the user and the clock signal output by the NAND gate, and send it to the step counter and feed it back to the NAND gate input at the same time; The system counter is used to count according to the system clock and the counting enable, generate a count value and send it to the comparator; The comparator is used to compare the count value of the system counter with the period value of the period register configured by the user to generate a trigger signal. When the two are equal, the trigger signal is valid and sent to the latch, AND gate 1 and AND gate 2; The latch is used to turn on the counting enable according to the work enable configured by the user, turn off the counting enable when the trigger signal is valid, and send it to the system counter, step counter and user reading module; The step counter is used to count according to the step clock generated by the delay unit and the counting enable to generate a count value; The inverter is used to invert the work enable configured by the user and clear the control system counter and the step counter; The AND gate 1 is used to generate a latch enable 1 for the step latch L1 according to the trigger signal and the step latch L1 enabled by the user; The AND gate 2 is used to generate a latch enable 2 for the step latch L2 according to the trigger signal and the step latch L2 enabled by the user; The step latch L1 and the step latch L2 are used to respectively latch the step counter count values ​​under two different frequency step clocks according to latch enable 1 and latch enable 2; The step length calculation module is used to calculate the step length according to the step length counter count values ​​latched by the step length latch L1 and the step length latch L2 under the step length calculation enable control configured by the user, and send it to the step length register of the user reading module; The user reading module is used for allowing the user to read the counting enable and step value.

[0006] In the above solution, the delay unit includes 256 delay modules B connected in series and a 256-to-1 selector; The delay module B is used to delay the clock signal. The input of the first delay module B is the clock signal output by the NAND gate. Except for the first delay module B, the input of the i-th delay module B is A i , the output is Z i The output of each delay module B simultaneously enters the next level delay module B and the 256 to 1 selector; The 256-to-1 selector is used to select the clock signal of a delay module B to be output according to the delay level N, that is, to obtain a step clock. When the delay level N is x, the output Z of the x-th delay module B is output. xOutput, that is, the step clock is Z x .

[0007] A method for calculating the step length of an integer frequency pulse signal, using the above-mentioned calculation circuit for the step length of an integer frequency pulse signal, comprises the following steps: Step 1: Configure the user configuration module: Turn off the work enable, automatically clear the system counter and step counter, and turn off the step clock; configure the period register period value; configure the level value of the delay level N for the first time; turn on the step latch L1 enable, turn off the step latch L2 enable and the step calculation enable; Step 2: Configure the user configuration module: Turn on the work enable, control the NAND gate and delay unit to generate the step clock, turn on the count enable in the latch, and the system counter and step counter start the first count; Step 3: Read the user reading module: Read count enable cyclically. When the system counter value is equal to the period register value, a trigger signal is generated and the latch turns off the count enable. At this time, the user reads that the count enable is off, which means that the system counter and step counter have completed the first count. The trigger signal and the step latch L1 enable are both valid. After passing through AND gate 1, latch enable 1 is generated to latch the step counter value into the step latch L1. Step 4: Configure the user configuration module: Turn off the work enable, the system counter and step counter are automatically cleared, the trigger signal is invalid, the second configuration delay count N level value is different from the first configuration delay level value N level value, turn off the step latch L1 enable, turn on the step latch L2 enable; Step 5: Configure the user configuration module: Turn on the work enable, control the NAND gate and delay unit to generate the step clock, turn on the count enable in the latch, and the system counter and step counter start the second count; Step 6: Read the user reading module: Read count enable cyclically. When the system counter value is equal to the period register value, a trigger signal is generated and the latch turns off the count enable. At this time, the user reads that the count enable is off, which means that the system counter and step counter have completed the second count. The trigger signal and the step latch L2 enable are both valid. After passing through AND gate 2, latch enable 2 is generated to latch the step counter value into the step latch L2. Step 7: Configure the user configuration module: Turn off the work enable, control the NAND gate and delay unit to turn off the step clock, the system counter and step counter are automatically cleared, and the step latch L2 is turned off; Step 8: Configure the user configuration module: Turn on the step length calculation enable, the step length calculation module starts working, calculates the step length according to the step length counter count value latched by the step length latch L1 and the step length latch L2, and inputs it to the step length register of the user reading module for the user to read and use.

[0008] In the above solution, the delay level N is configured so that the step clock frequency is less than the system clock frequency.

[0009] In the above solution, in step eight, the step length calculation method is as follows: Assume that the period value of the period register is D, the delay level N is configured with two different level values, namely C1 and C2, the latch value of the step latch L1 is V1, and the latch value of the step latch L2 is V2; The calculation formula of step length S is as follows: ; After the step length S is calculated, S is rounded off to an integer value, which is the final step length.

[0010] Through the above technical solution, the present invention provides a circuit and method for calculating the step length of an integer frequency pulse signal, which has the following beneficial effects: The step length calculation circuit disclosed in the present invention generates two step length clocks with different frequencies by configuring two different delay levels N, without the user having to know the system clock cycle and the delay time of the delay module B, and without changing the period value of the period register. After two identical working times, the latch values ​​of the step length latch L1 and the latch values ​​of the step length latch L2 are obtained, and the step length calculation module is used to automatically calculate the step length, thereby solving the problem of step length errors caused by temperature and voltage changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0012] Figure 1 A schematic diagram of a circuit for calculating the step length of an integer frequency pulse signal disclosed in an embodiment of the present invention; Figure 2 It is a structural diagram of the delay unit; Figure 3 This is a schematic diagram of a step clock. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0014] The present invention provides a circuit for calculating the step length of an integer frequency pulse signal. Figure 1 As shown, the system includes a user configuration module, a NAND gate, a delay unit, a system counter, a comparator, a latch, a step counter, an inverter, AND gates 1 and 2, step latches L1 and L2, a step calculation module, and a user read module. The system counter operates based on the system clock, while the step counter operates based on the step clock. When the system counter value equals the period register value, the step counter value is latched into the step latch for step calculation. Figure 1 A black dot indicates that the lines cross, and no black dot indicates that the lines do not cross. The functions of each module are as follows: 1. User configuration module The user configuration module is used for users to configure the period value, work enable, delay level N, step latch L1 enable, step latch L2 enable and step calculation enable of the period register; the above configuration is used to control whether the entire circuit works and the number of times it works.

[0015] The period register is used to configure the period value, which is used to compare with the system counter count value. When the system counter count value is equal to the period register period value, the comparator outputs a trigger signal to turn off the counting enable. At the same time, the step latch L1 and the step latch L2 are enabled, and the step counter count value is latched into the step latch L1 and the step latch L2 respectively.

[0016] The work enable is used for the NAND gate and delay unit to generate the step clock and the control latch to generate the count enable. When the work enable is turned on, first, the step clock is generated, and second, the control latch turns on the count enable. After the count enable is turned on, the system counter and the step counter start counting; when the work enable is turned off, first, the step clock is turned off, and second, the system counter and the step counter are cleared.

[0017] The delay level N is used to control the output step clock of the 256-to-1 selector in the delay unit. The delay count N is configured with different level values. The 256-to-1 selector in the delay unit selects the output Z of different delay modules B as the step clock. The frequency of the step clock is different. Note that the step clock frequency must be less than the system clock frequency, so there are requirements for the configuration of the delay level N.

[0018] The step latch L1 enable and the step latch L2 enable are used to latch the step counter count value. When the system counter count value is equal to the period register period value for the first time, the trigger signal is valid. At this time, the step latch L1 enable is opened. After passing through AND gate 1, latch enable 1 is valid, and the step counter count value is latched into the step latch L1; when the system counter count value is equal to the period register period value for the second time, the trigger signal is valid again. At this time, the step latch L2 enable is opened. After passing through AND gate 2, latch enable 2 is valid, and the step counter count value is latched into the step latch L2.

[0019] The step length calculation enable is used for step length calculation. When the step length latch L1 and the step length latch L2 obtain the latch value, the step length calculation enable is turned on and the step length calculation module automatically calculates the step length.

[0020] 2. NAND Gate The NAND gate is used to generate a clock signal for the delay unit based on the user-configured work enable and the step clock returned by the delay unit. The output logic of the NAND gate is: when any input is 0, the NAND gate output is 1, and when all inputs are 1, the NAND gate output is 0. Therefore, when the work enable is off, one input of the NAND gate is 0, the NAND gate output is 1, the input of the delay unit is 1, the step clock is always 1, and the step clock is off; when the work enable is on, one input of the NAND gate is 1. At this time, the NAND gate logically functions as an inverter. In this way, the input A of the first-stage delay module B in the delay unit is the inverted signal of the step clock, so the step clock is a pulse that changes between high and low, and the step clock is on.

[0021] 3. Delay unit The delay unit is used to generate a step clock based on the delay level N configured by the user and the clock signal output by the NAND gate, and send it to the step counter and feed it back to the NAND gate input at the same time; like Figure 2 As shown, the delay unit includes 256 delay modules B connected in series and a 256-to-1 selector; The delay module B is used to delay the clock signal. The input of the first delay module B is the clock signal output by the NAND gate. Except for the first delay module B, the input of the i-th delay module B is A i , the output is Z i ; The output of each delay module B simultaneously enters the next-level delay module B and the 256-to-1 selector; 256 delay modules B are connected in series, that is, the clock signal output of the previous-level delay module B is the clock signal input of the current-level delay module B, and the clock signal output of the current-level delay module B is the clock signal input of the next-level delay module B.

[0022] The 256-to-1 selector is used to select the clock signal output of a delay module B according to the delay level N, that is, to obtain the step clock. When the delay level N is x, the output Z of the x-th delay module B is output. x Output, that is, the step clock is Z x The relationship is as follows: When N=1, the step clock is the clock signal output of the first delay module B, which means that there is one delay module B participating in the delay calculation, namely Z1; When N=2, the step clock is the clock signal output of the second delay module B, which means that there are two delay modules B participating in the delay calculation, namely Z2; When N=255, the step clock is the clock signal output of the 255th delay module B, which means that there are 255 delay modules B participating in the delay calculation, that is, Z255; When N=256, the step clock is the clock signal output of the 256th delay module B, which means that there are 256 delay modules B participating in the delay calculation, that is, Z256.

[0023] When the work enable is turned on, the step clock and work enable output by the 256-to-1 selector are input to the input of the first-stage delay module B after being operated by the NAND gate.

[0024] If the period value of the step clock is P, the number of delay stages N is C, and the delay time of delay module B is M, then the period value P of the step clock is calculated as follows: (1); The step clock diagram is as follows Figure 3 As shown; According to the description of the delay level N, the step clock frequency must be less than the system clock frequency. If the system clock frequency is 100Mhz, the period is 10ns, and the delay of the delay module B is 150ps, then the maximum step clock frequency is 100Mhz. According to formula (1), the minimum value of the level value C of the delay level N can be calculated to be 34, that is, the minimum value of the level value of the user-configured delay level N is 34, and the maximum value is Figure 2 The number of all delay modules B in the delay unit is 256. To be on the safe side, it is not recommended to configure the step clock frequency close to the system clock frequency, because changes in temperature and voltage may cause the delay time of delay module B to vary greatly, causing the step clock frequency to exceed the system clock frequency.

[0025] 4. System Counters The system counter is used to count according to the system clock and count enable, generate a count value and send it to the comparator.

[0026] 5. Comparator The comparator is used to compare the system counter count value with the period value of the user-configured period register to generate a trigger signal. When the two are equal, the trigger signal is valid and sent to the latch, AND gate 1, and AND gate 2. The control latch turns off the count enable, and at the same time cooperates with the step latch L1 enable and the step latch L2 enable. After the operation of AND gate 1 and AND gate 2, latch enable 1 and latch enable 2 are generated.

[0027] 6. Latch The latch is used to turn on the count enable according to the user-configured work enable and send it to the system counter, step counter, and user read module. When the count enable is turned on, it means that the system counter and step counter are counting. When the system counter count value is equal to the period register period value, the trigger signal is valid and the latch turns off the count enable, indicating that the system counter and step counter are counting completed.

[0028] 7. Step Counter The step counter is used to count according to the step clock and count enable generated by the delay unit to generate a count value; the period value of the period register remains unchanged when the system counter counts twice, so the generation time of the trigger signal is fixed. When the delay count N is configured with two different level values, the step counter counts twice and latches different count values ​​into the step latch L1 and step latch L2 respectively.

[0029] 8. Inverter The inverter is used to invert the user-configured work enable and clear the system counter and step counter. The system counter cannot count and clear at the same time, and the step counter cannot count and clear at the same time. Therefore, the work enable needs to be inverted to clear the system counter and step counter.

[0030] 9. AND gate 1 AND gate 1 is used to generate latch enable 1 for step latch L1 based on the trigger signal and the user-configured step latch L1 enable. The output logic of AND gate 1 is: when all inputs are 1, AND gate 1 outputs 1; when any input is 0, AND gate 1 outputs 0. Therefore, when step latch L1 is enabled and the trigger signal is valid, AND gate 1 outputs 1, latch enable 1 is valid, and the step counter count value is latched into step latch L1. When step latch L1 is enabled or the trigger signal is invalid, AND gate 1 outputs 0, latch enable 1 is invalid, and the step counter count value is prohibited from being latched into step latch L1.

[0031] 10. AND Gate 2 AND gate 2 is used to generate latch enable 2 for step latch L2 based on the trigger signal and the user-configured step latch L2 enable. The output logic of AND gate 2 is: when all inputs are 1, AND gate 2 outputs 1; when any input is 0, AND gate 2 outputs 0. Therefore, when step latch L2 is enabled and the trigger signal is valid, AND gate 2 outputs 1, latch enable 2 is valid, and the step counter count value is latched into step latch L2. When step latch L2 is enabled or the trigger signal is invalid, AND gate 2 outputs 0, latch enable 2 is invalid, and the step counter count value is prohibited from being latched into step latch L2.

[0032] 11. Step latch L1 and step latch L2 The step latch L1 and the step latch L2 are used to latch the count values ​​of the step counter under two different frequency step clocks according to latch enable 1 and latch enable 2 respectively.

[0033] 12. Step length calculation module The step length calculation module is used to calculate the step length according to the step length counter count values ​​latched by the step length latch L1 and the step length latch L2 under the step length calculation enable control configured by the user, and send it to the step length register of the user reading module.

[0034] 13. User reading module The user read module is used for users to read the count enable and step value.

[0035] Count enable is used to mark whether the system counter and step counter are working. When count enable is turned on, it means that the system counter and step counter are working, and the system counter count value is less than the period register period value. When count enable is turned off, it means that the system counter and step counter have completed their work at the current step clock frequency, the system counter count value is equal to the period register period value, and the step counter count value is latched into the step latch L1 or step latch L2.

[0036] The step length register is used to read the step length value. The user reads the step length value to generate an integer frequency pulse signal.

[0037] A method for calculating the step length of an integer frequency pulse signal, using the above-mentioned calculation circuit for the step length of an integer frequency pulse signal, comprises the following steps: Step 1: Configure the user configuration module: Turn off the work enable, automatically clear the system counter and step counter, and turn off the step clock; configure the period register period value; configure the level value of the delay level N for the first time; turn on the step latch L1 enable, turn off the step latch L2 enable and the step calculation enable; Step 2: Configure the user configuration module: Turn on the work enable, control the NAND gate and delay unit to generate the step clock, turn on the count enable in the latch, and the system counter and step counter start the first count; Step 3: Read the user reading module: Read count enable cyclically. When the system counter value is equal to the period register value, a trigger signal is generated and the latch turns off the count enable. At this time, the user reads that the count enable is off, which means that the system counter and step counter have completed the first count. The trigger signal and the step latch L1 enable are both valid. After passing through AND gate 1, latch enable 1 is generated to latch the step counter value into the step latch L1. Step 4: Configure the user configuration module: Turn off the work enable, the system counter and step counter are automatically cleared, the trigger signal is invalid, the second configuration delay count N level value is different from the first configuration delay level value N level value, turn off the step latch L1 enable, turn on the step latch L2 enable; Step 5: Configure the user configuration module: Turn on the work enable, control the NAND gate and delay unit to generate the step clock, turn on the count enable in the latch, and the system counter and step counter start the second count; Step 6: Read the user reading module: Read count enable cyclically. When the system counter value is equal to the period register value, a trigger signal is generated and the latch turns off the count enable. At this time, the user reads that the count enable is off, which means that the system counter and step counter have completed the second count. The trigger signal and the step latch L2 enable are both valid. After passing through AND gate 2, latch enable 2 is generated to latch the step counter value into the step latch L2. Step 7: Configure the user configuration module: Turn off the work enable, control the NAND gate and delay unit to turn off the step clock, the system counter and step counter are automatically cleared, and the step latch L2 is turned off; Step 8: Configure the user configuration module: Turn on the step length calculation enable, the step length calculation module starts working, calculates the step length according to the step length counter count value latched by the step length latch L1 and the step length latch L2, and inputs it to the step length register of the user reading module for the user to read and use.

[0038] The step length is calculated as follows: Assume that the period value of the period register is D, the system clock period is T, and the delay time of the delay module B is M. Since the period value D of the period register remains unchanged during the operation of the step calculation circuit, the time W of the step counter counting twice is the same, that is: ; The delay level N is configured with two different level values, C1 and C2, to generate two step clocks with different frequencies. After the step counter counts twice, the latch value of the step latch L1 is V1, and the latch value of the step latch L2 is V2. ; ; Calculate the intermediate variable H: ; The calculation formula of step length S is as follows: ; After the step length S is calculated, S is rounded off to an integer value, which is the final step length.

[0039] For example, if the system clock frequency is 100 MHz, the period T is 10 ns, the delay M of the delay unit module B is 150 ps, ​​and the delay unit has a total of 256 levels of delay, the working process is as follows: Step size S=T / M=10ns / 150ps=67.

[0040] 1. Configure the user configuration module, turn off the work enable, configure the period register to 65535, configure the first delay level N to 80, and enable the step latch L1; 2. Turn on the working enable, the step length calculation circuit starts working for the first time, and the counting enable is turned on; 3. Read the user read module and cyclically read the count enable. When the user read count enable is turned off, turn off the work enable. The latch value V1 of the step latch L1 is 26966 (obtained by simulation); 4. The second time, configure the delay level N to 200, turn off the step latch L1 and turn on the step latch L2. 5. Turn on the working enable, the step length calculation circuit starts working for the second time, and the counting enable is turned on; 6. Read the user read module and cyclically read the count enable. When the user read count enable is turned off, turn off the work enable. The latch value V2 of the step latch L2 is 10865 (obtained by simulation); 7. Configure the user configuration module, turn off the step length latch L2 enable, turn on the step length calculation enable, and the step length calculation module starts working. Substitute the step length latch L1 latch value 26966 and the step length latch L2 latch value 10865 into the calculation formula of the step length S to obtain the value of the step length S: ; By rounding the value of the step length S, the integer value of the step length S is 67.

[0041] The calculation results show that the step length calculated by the step length calculation circuit is the same as the step length calculated by the system clock period T value of 10ns and the delay value of the delay module B of 150ps.

[0042] In summary, the step length calculation circuit perfectly realizes the automatic calculation of the step length and solves the problem of step length error caused by temperature and voltage changes.

[0043] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A circuit for calculating the step size of an integer frequency pulse signal, characterized in that: It includes a user configuration module, a NAND gate, a delay unit, a system counter, a comparator, a latch, a step counter, an inverter, an AND gate 1, an AND gate 2, a step latch L1, a step latch L2, a step calculation module and a user reading module; The user configuration module is used for the user to configure the period value, work enable, delay level N, step latch L1 enable, step latch L2 enable and step calculation enable of the period register; The NAND gate is used to generate a clock signal to the delay unit according to the work enable configured by the user and the step clock returned by the delay unit; The delay unit is used to generate a step clock according to the delay level N configured by the user and the clock signal output by the NAND gate, and send it to the step counter and feed it back to the NAND gate input at the same time; The system counter is used to count according to the system clock and the counting enable, generate a count value and send it to the comparator; The comparator is used to compare the count value of the system counter with the period value of the period register configured by the user to generate a trigger signal. When the two are equal, the trigger signal is valid and sent to the latch, AND gate 1 and AND gate 2; The latch is used to turn on the counting enable according to the work enable configured by the user, turn off the counting enable when the trigger signal is valid, and send it to the system counter, step counter and user reading module; The step counter is used to count according to the step clock generated by the delay unit and the counting enable to generate a count value; The inverter is used to invert the work enable configured by the user and clear the control system counter and the step counter; The AND gate 1 is used to generate a latch enable 1 for the step latch L1 according to the trigger signal and the step latch L1 enabled by the user; The AND gate 2 is used to generate a latch enable 2 for the step latch L2 according to the trigger signal and the step latch L2 enabled by the user; The step latch L1 and the step latch L2 are used to respectively latch the step counter count values ​​under two different frequency step clocks according to latch enable 1 and latch enable 2; The step length calculation module is used to calculate the step length according to the step length counter count values ​​latched by the step length latch L1 and the step length latch L2 under the step length calculation enable control configured by the user, and send it to the step length register of the user reading module; The user reading module is used for allowing the user to read the counting enable and step value.

2. A calculation circuit for integer frequency pulse signal step length according to claim 1, characterized in that: The delay unit includes 256 delay modules B connected in series and a 256-to-1 selector; The delay module B is used to delay the clock signal. The input of the first delay module B is the clock signal output by the NAND gate. Except for the first delay module B, the input of the i-th delay module B is A i , the output is Z i The output of each delay module B simultaneously enters the next level delay module B and the 256 to 1 selector; The 256-to-1 selector is used to select the clock signal of a delay module B to be output according to the delay level N, that is, to obtain a step clock. When the delay level N is x, the output Z of the x-th delay module B is output. x Output, that is, the step clock is Z x .

3. A method for calculating the step length of an integer frequency pulse signal, using a circuit for calculating the step length of an integer frequency pulse signal according to claim 1 or 2, characterized in that: The steps include: Step 1: Configure the user configuration module: Turn off the work enable, automatically clear the system counter and step counter, and turn off the step clock; configure the period register period value; configure the level value of the delay level N for the first time; turn on the step latch L1 enable, turn off the step latch L2 enable and the step calculation enable; Step 2: Configure the user configuration module: Turn on the work enable, control the NAND gate and delay unit to generate the step clock, turn on the count enable in the latch, and the system counter and step counter start the first count; Step 3: Read the user reading module: Read count enable cyclically. When the system counter value is equal to the period register value, a trigger signal is generated and the latch turns off the count enable. At this time, the user reads that the count enable is off, which means that the system counter and step counter have completed the first count. The trigger signal and the step latch L1 enable are both valid. After passing through AND gate 1, latch enable 1 is generated to latch the step counter value into the step latch L1. Step 4: Configure the user configuration module: Turn off the work enable, the system counter and step counter are automatically cleared, the trigger signal is invalid, the second configuration delay count N level value is different from the first configuration delay level value N level value, turn off the step latch L1 enable, turn on the step latch L2 enable; Step 5: Configure the user configuration module: Turn on the work enable, control the NAND gate and delay unit to generate the step clock, turn on the count enable in the latch, and the system counter and step counter start the second count; Step 6: Read the user reading module: Read count enable cyclically. When the system counter value is equal to the period register value, a trigger signal is generated and the latch turns off the count enable. At this time, the user reads that the count enable is off, which means that the system counter and step counter have completed the second count. The trigger signal and the step latch L2 enable are both valid. After passing through AND gate 2, latch enable 2 is generated to latch the step counter value into the step latch L2. Step 7: Configure the user configuration module: Turn off the work enable, control the NAND gate and delay unit to turn off the step clock, the system counter and step counter are automatically cleared, and the step latch L2 is turned off; Step 8: Configure the user configuration module: Turn on the step length calculation enable, the step length calculation module starts working, calculates the step length according to the step length counter count value latched by the step length latch L1 and the step length latch L2, and inputs it to the step length register of the user reading module for the user to read and use.

4. The method for calculating the step length of an integer frequency pulse signal according to claim 3, wherein: The delay level N is configured so that the step clock frequency is less than the system clock frequency.

5. The method for calculating the step length of an integer frequency pulse signal according to claim 3, wherein: In step eight, the step length is calculated as follows: Assume that the period value of the period register is D, the delay level N is configured with two different level values, namely C1 and C2, the latch value of the step latch L1 is V1, and the latch value of the step latch L2 is V2; The calculation formula of step length S is as follows: ； After the step length S is calculated, S is rounded off to an integer value, which is the final step length.

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