An adaptive dead-time non-overlapping clock generation circuit and charge pump circuit

Abstract

This invention belongs to the field of analog integrated circuit technology, and specifically relates to an adaptive dead-time non-overlapping clock generation circuit and a charge pump circuit. It includes a first delay unit and a second delay unit, both with identical structures, each composed of a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, and a parasitic capacitance; a first trigger gate unit, whose first input terminal is used to receive the input clock signal CLK, and whose second input terminal is used to receive the inverted output clock signal CLKB output by the second delay unit; the output terminal of the first trigger gate unit is used to connect to the input terminal of the first delay unit; and a second trigger gate unit. This invention solves the problem that the dead time of existing non-overlapping clock generation circuits cannot accurately match the required dead time of the driven switching transistor, thereby improving the working efficiency of power switching circuits such as charge pumps.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to an adaptive dead-time non-overlapping clock generation circuit and a charge pump circuit. Background Technology

[0002] Dead time in a non-overlapping clock refers to the time interval between two clock signals during a switching process. During this period, both clock signals are either low or high to prevent simultaneous conduction of the upper and lower switching transistors and thus avoid current spikes. The setting of dead time is crucial for the normal operation of electronic circuits, especially in high-voltage and high-speed circuits.

[0003] In traditional non-overlapping clock generation circuits, the dead time of the clock signal is determined by an RC delay unit composed of resistors and capacitors. During integrated circuit manufacturing, unavoidable process variations exist. Changes in process angles cause errors in the values ​​of resistors and capacitors, resulting in a deviation between the dead time of the traditional non-overlapping clock generation circuit and the design value. This makes it impossible to accurately match the dead time requirements of the driven switching transistor. Traditional non-overlapping clock generation circuits, such as... Figure 1 As shown, the system includes a first delay unit 101, a second delay unit 102, a third delay unit 103, a fourth delay unit 104, inverters INV1~INV3, NAND gates NAND1~NAND2, an input clock signal CLK, a non-inverting output clock signal CLKA, and an inverting output clock signal CLKB. The first delay unit 101 includes a PMOS transistor P1, an NMOS transistor N1, a resistor R1, and a capacitor C1. The second delay unit 102 includes a PMOS transistor P2, an NMOS transistor N2, a resistor R2, and a capacitor C2. The third delay unit 103 includes a PMOS transistor P3, an NMOS transistor N3, a resistor R3, and a capacitor C3. The fourth delay unit 104 includes a PMOS transistor P4, an NMOS transistor N4, a resistor R4, and a capacitor C4. The positive power supply for all delay units 101~104 is VCC, and the negative power supply for all delay units is GND.

[0004] The above Figure 1 The circuit shown works as follows: the first delay unit 101 and the third delay unit 103 are used to generate a falling edge delay for the clock signal. Further, the second delay unit 102 and the fourth delay unit 104 are used to generate a rising edge delay for the clock signal. The delay time of the delay units 101-104 is determined by the values ​​of resistors R1-R4 and capacitors C1-C4. When the clock signal CLK is input, after the delay effect of the delay units 101-104, the clock edge of the output clock signal shifts, thereby generating a set of low-level non-overlapping clock signals CLKA and CLKB.

[0005] The timing diagram of a traditional non-overlapping clock generation circuit is as follows: Figure 2 As shown, the time during which the output set of low-level non-overlapping clock signals CLKA and CLKB are simultaneously high is the dead time of the non-overlapping clock signals CLKA and CLKB. Similarly, if... Figure 1 Replacing NAND1~NAND2 with NOR gates generates a set of high-level non-overlapping clock signals. The dead time is the time during which these clock signals are simultaneously low. The dead time is entirely determined by the values ​​of the resistors and capacitors in delay units 101~104, and cannot precisely match the dead time requirements of the driven switching transistor.

[0006] Given the aforementioned traditional non-overlapping clock generation circuit, the dead time of its clock signal is determined by an RC delay unit composed of resistors and capacitors. During integrated circuit manufacturing, unavoidable process deviations exist. Variations in process angles cause errors in the values ​​of resistors and capacitors, resulting in a deviation between the dead time of the traditional non-overlapping clock generation circuit and the design value, making it impossible to accurately match the dead time requirements of the driven switching transistor.

[0007] In summary, in charge pump circuits, if the dead time of the clock signal driving the switching MOSFET is too small, there is a risk of shoot-through in the upper and lower switching MOSFETs; if the dead time is too large, the charge pump efficiency will be greatly reduced. Therefore, to improve the matching between the dead time of the clock signal and the dead time required by the driven switching MOSFET, this invention proposes an adaptive dead time non-overlapping clock generation circuit. By precisely setting the dead time of the non-overlapping clock, the operating efficiency of power switching circuits such as charge pumps can be improved. Summary of the Invention

[0008] The purpose of this invention is to provide an adaptive dead-time non-overlapping clock generation circuit and a charge pump circuit. This invention can shorten the dead time as much as possible while ensuring that the upper and lower switching MOSFETs do not shoot through, in order to solve the problem that the dead time of the existing non-overlapping clock generation circuit cannot accurately match the dead time required by the driven switching transistor, thereby improving the working efficiency of power switching circuits such as charge pumps.

[0009] To address the aforementioned technical problems, this invention provides an adaptive dead-time non-overlapping clock generation circuit for generating two non-overlapping clock signals, comprising:

[0010] The fifth and sixth delay units have the same structure, both consisting of a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, and a parasitic capacitor. The gates of the first PMOS transistor and the first NMOS transistor are connected together and serve as the input terminal. The sources of the first PMOS transistor and the first NMOS transistor are respectively connected to the positive power supply VCC and the negative power supply GND. The drains of the first PMOS transistor and the first NMOS transistor are respectively connected to one end of the first resistor and the second resistor. The other ends of the first resistor and the second resistor are connected to the parasitic capacitor connected to the negative power supply GND and serve as the output terminal.

[0011] The first trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the inverted output clock signal CLKB output by the sixth delay unit, and an output terminal for receiving the input terminal of the fifth delay unit.

[0012] The second trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the in-phase output clock signal CLKA output by the fifth delay unit, and an output terminal for receiving the input terminal of the sixth delay unit.

[0013] Preferably, the first trigger gate unit includes: a first Schmitt trigger and a first logic gate; the input terminal of the first Schmitt trigger serves as the second input terminal of the first trigger gate unit, the output terminal of the first Schmitt trigger is connected to the first input terminal of the first logic gate, the second input terminal of the first logic gate serves as the first input terminal of the first trigger gate unit, and the output terminal of the first logic gate serves as the output terminal of the first trigger gate unit.

[0014] Preferably, the first logic gate includes: a first inverter, a second inverter, a third inverter, and a first NAND gate or a first NOR gate; the input terminal of the first inverter is connected to the output terminal of the first Schmitt trigger, the input terminal of the second inverter is connected to the input clock signal CLK, the output terminals of the first inverter and the second inverter are connected to the two input terminals of the first NAND gate or the first NOR gate, the output terminal of the first NAND gate or the first NOR gate is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the input terminal of the fifth delay unit.

[0015] Preferably, the second trigger gate unit includes: a second Schmitt trigger and a second logic gate; the input terminal of the second Schmitt trigger serves as the second input terminal of the second trigger gate unit, the output terminal of the second Schmitt trigger is connected to the first input terminal of the second logic gate, the second input terminal of the second logic gate serves as the first input terminal of the second trigger gate unit, and the output terminal of the second logic gate serves as the output terminal of the second trigger gate unit.

[0016] Preferably, the second logic gate includes: a fourth inverter, a fifth inverter, and a second NAND gate or a second NOR gate; the input terminal of the fourth inverter is connected to the output terminal of the second Schmitt trigger, the input clock signal CLK and the output terminal of the fourth inverter are connected to the two input terminals of the second NAND gate or the second NOR gate, the output terminal of the second NAND gate or the second NOR gate is connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the input terminal of the sixth delay unit.

[0017] Preferably, the first Schmitt trigger and the second Schmitt trigger have the same structure, each including: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gates of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected to the signal input terminal VIN; the source of the first PMOS transistor and the gate of the fourth NMOS transistor are connected to the positive power supply VCC; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the third PMOS transistor; the third... The drain of the PMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to the negative power supply GND. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor, and serves as the signal output terminal VOUT. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the source of the third NMOS transistor. The source of the second NMOS transistor and the gate of the fourth PMOS transistor are connected to the negative power supply GND. The drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the positive power supply VCC.

[0018] The present invention also provides an adaptive dead-time non-overlapping clock generation circuit for generating four non-overlapping clock signals, comprising:

[0019] The seventh to tenth delay units have the same structure, each consisting of a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, and a parasitic capacitor. The gates of the first PMOS transistor and the first NMOS transistor are connected together and serve as the input terminal. The sources of the first PMOS transistor and the first NMOS transistor are respectively connected to the positive power supply VCC and the negative power supply GND. The drains of the first PMOS transistor and the first NMOS transistor are respectively connected to one end of the first resistor and the second resistor. The other ends of the first resistor and the second resistor are connected to the parasitic capacitor connected to the negative power supply GND and serve as the output terminal.

[0020] The first trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the inverted output clock signal CLKB1 output by the tenth delay unit, a third input terminal for receiving the inverted output clock signal CLKB2 output by the ninth delay unit, and an output terminal for receiving the input terminals of the seventh and eighth delay units.

[0021] The second trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the in-phase output clock signal CLKA1 output by the seventh delay unit, a third input terminal for receiving the in-phase output clock signal CLKA2 output by the eighth delay unit, and an output terminal for receiving the input terminals of the ninth and tenth delay units.

[0022] Preferably, the first trigger gate unit includes: a first Schmitt trigger, a second Schmitt trigger, a first inverter to a third inverter, a first NAND gate, and a second NAND gate; the input terminal of the third inverter is connected to the input clock signal CLK, the input terminal of the first Schmitt trigger is connected to the inverted output clock signal CLKB1, the input terminal of the second Schmitt trigger is connected to the inverted output clock signal CLKB2, the output terminal of the second Schmitt trigger is connected to the input terminal of the first inverter, the output terminals of the first inverter and the first Schmitt trigger are connected to the two input terminals of the first NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the second inverter, the output terminals of the second inverter and the third inverter are connected to the two input terminals of the second NAND gate, and the output terminal of the second NAND gate serves as the output terminal of the first trigger gate unit.

[0023] Preferably, the second trigger gate unit includes: a third Schmitt trigger, a fourth Schmitt trigger, a fourth inverter, a fifth inverter, a third NAND gate, and a fourth NAND gate; the input terminal of the third Schmitt trigger is connected to the in-phase output clock signal CLKA1, the input terminal of the fourth Schmitt trigger is connected to the in-phase output clock signal CLKA2, the output terminals of the third and fourth Schmitt triggers are connected to the two input terminals of the third NAND gate, the output terminal of the third NAND gate is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter and the input clock signal CLK are connected to the two input terminals of the fourth NAND gate, the output terminal of the fourth NAND gate is connected to the input terminal of the fifth inverter and the input terminal of the tenth delay unit, and the output terminal of the fifth inverter is connected to the input terminal of the ninth delay unit.

[0024] The present invention also provides a charge pump circuit, comprising:

[0025] The non-overlapping clock generation circuit described above;

[0026] The charge pump circuit unit includes: a second PMOS transistor to a fourth PMOS transistor, a second NMOS transistor, a flying lead capacitor, and an output capacitor; the sources of the second PMOS transistor and the third PMOS transistor are connected to the positive power supply VCC, the gate of the second PMOS transistor is connected to the non-inverting output clock signal CLKA1, the drain of the second PMOS transistor is connected to one end of the flying lead capacitor and the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the inverting output clock signal CLKB2, the source of the second NMOS transistor is connected to the negative power supply GND, the other end of the flying lead capacitor is connected to the drain of the third PMOS transistor and the source of the fourth PMOS transistor, the gate of the third PMOS transistor is connected to the inverting output clock signal CLKB1, the gate of the fourth PMOS transistor is connected to the non-inverting output clock signal CLKA2, and the drain of the fourth PMOS transistor is connected to the output capacitor connected to the negative power supply GND and the voltage output terminal CPOUT.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] This invention utilizes the resistors, Schmitt triggers, and parasitic capacitance of the driven switch gate in the delay unit to determine the dead time of the non-overlapping clock. Furthermore, the dead time of the non-overlapping clock can be adaptively adjusted based on the size of the parasitic capacitance of the driven switch gate. While ensuring that the driven upper and lower MOSFETs do not shoot-through, the dead time of the generated non-overlapping clock signal is shortened as much as possible, allowing the dead time of the non-overlapping clock signal to precisely match the driven MOSFET, thereby improving the operating efficiency of power switching circuits such as charge pumps. Attached Figure Description

[0029] Figure 1 This is a traditional non-overlapping clock generation circuit diagram.

[0030] Figure 2 It is a timing diagram of a traditional non-overlapping clock generation circuit.

[0031] Figure 3 This is a circuit diagram of an adaptive dead-time non-overlapping clock generation circuit provided in Embodiment 1 of the present invention.

[0032] Figure 4 This is a circuit diagram of the Schmitt trigger provided in Embodiment 1 of the present invention.

[0033] Figure 5 This is a timing diagram of the non-overlapping clock driving PMOS switch signal provided in Embodiment 1 of the present invention.

[0034] Figure 6 This is a circuit diagram of an adaptive dead-time non-overlapping clock generation circuit provided in Embodiment 2 of the present invention.

[0035] Figure 7 This is a timing diagram of the non-overlapping clock driving NMOS switch signal provided in Embodiment 2 of the present invention.

[0036] Figure 8 This is a schematic diagram of the four-channel non-overlapping clock generation circuit provided in Embodiment 3 of the present invention applied to a charge pump circuit.

[0037] Figure 9 This is a circuit diagram of the charge pump circuit unit provided in Embodiment 3 of the present invention.

[0038] Figure 10 This is a timing diagram of the four-channel non-overlapping clock generation circuit provided in Embodiment 3 of the present invention applied to a charge pump circuit. Detailed Implementation

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Example 1

[0040] like Figure 3As shown, this embodiment of the invention provides an adaptive dead-time non-overlapping clock generation circuit for outputting two non-overlapping clock signals. The adaptive dead-time non-overlapping clock generation circuit includes inverters INV4~INV8, NAND gates NAND3~NAND4, Schmitt triggers SMIT1~SMIT2, a fifth delay unit 201, a sixth delay unit 202, an input clock signal CLK, a non-inverting output clock signal CLKA, and an inverting output clock signal CLKB.

[0041] The fifth delay unit 201 includes an NMOS transistor NM1, a PMOS transistor PM1, resistors R5~R6, a parasitic gate capacitance CC1 of the driven switch, a positive power supply VCC, and a negative power supply GND.

[0042] The sixth delay unit 202 includes an NMOS transistor NM2, a PMOS transistor PM2, resistors R7~R8, a parasitic gate capacitance CC2 of the driven switch, a positive power supply VCC, and a negative power supply GND.

[0043] In the fifth delay unit 201, the gates of NMOS transistor NM1 and PMOS transistor PM1 are connected to the output terminal of inverter INV5. The source of PMOS transistor PM1 is connected to the positive power supply VCC, and the source of NMOS transistor NM1 is connected to the negative power supply GND. The drain of PMOS transistor PM1 is connected to one end of resistor R5. The other end of resistor R5 is connected to one end of resistor R6, one end of the gate parasitic capacitance CC1 of the driven switch transistor, the input terminal of Schmitt trigger SMIT2, and the non-inverting output clock signal CLKA. The other end of resistor R6 is connected to the drain of NMOS transistor NM1.

[0044] In the sixth delay unit 202, the gates of NMOS transistor NM2 and PMOS transistor PM2 are connected to the output terminal of inverter INV6. The source of PMOS transistor PM2 is connected to the positive power supply VCC, and the source of NMOS transistor NM2 is connected to the negative power supply GND. The drain of PMOS transistor PM2 is connected to one end of resistor R7. The other end of resistor R7 is connected to one end of resistor R8, one end of the parasitic gate capacitance CC2 of the driven switch transistor, the input terminal of Schmitt trigger SMIT1, and the inverted output clock signal CLKB. The other end of resistor R8 is connected to the drain of NMOS transistor NM2.

[0045] In the adaptive dead-time non-overlapping clock generation circuit, the input clock signal CLK is connected to the input of inverter INV4 and one input of NAND gate NAND4. The output of inverter INV4 is connected to one input of NAND gate NAND3, and the output of NAND gate NAND3 is connected to the input of inverter INV5. The output of Schmitt trigger SMIT1 is connected to the input of inverter INV7, and the output of inverter INV7 is connected to the other input of NAND gate NAND3. The output of Schmitt trigger SMIT2 is connected to the input of inverter INV8, and the output of inverter INV8 is connected to the other input of NAND gate NAND4.

[0046] The circuit schematics of Schmitt triggers SMIT1~SMIT2 are as follows: Figure 4 As shown. The Schmitt triggers SMIT1~SMIT2 include NMOS transistors NM3~NM6, PMOS transistors PM3~PM6, positive power supply VCC, negative power supply GND, signal input terminal VIN, and signal output terminal VOUT.

[0047] In the Schmitt triggers SMIT1~SMIT2, the signal input terminal VIN is connected to the gates of NMOS transistors NM3~NM4 and PMOS transistors PM3~PM4. The source of PMOS transistor PM3 is connected to the gate of NMOS transistor NM6 and the positive power supply VCC. The drain of PMOS transistor PM3 is connected to the source of PMOS transistors PM4~PM5. The drain of PMOS transistor PM5 is connected to the drain of NMOS transistor NM6. The source of NMOS transistor NM6 is connected to the negative power supply GND. The drain of S-MOSFET PM4 is connected to the drain of MMOS transistor MM3, the gate of PMOS transistor PM5, the gate of NMOS transistor NM5, and the signal output terminal VOUT. The source of NMOS transistor NM3 is connected to the drain of NMOS transistor NM4 and the source of NMOS transistor NM5. The drain of NMOS transistor NM5 is connected to the drain of PMOS transistor PM6. The source of PMOS transistor PM6 is connected to the positive power supply VCC. The source of NMOS transistor NM4 is connected to the gate of PMOS transistor PM6 and the negative power supply GND.

[0048] like Figure 3 As shown, in the adaptive dead-time non-overlapping clock generation circuit, the fifth delay unit 201 and the sixth delay unit 202 are used to generate the phase delay of the clock signal. Figure 1 Unlike traditional non-overlapping clock generation circuits, Figure 3The rising edge delay of the clock signal in the fifth delay unit 201 is determined by the values ​​of resistor R6, the gate parasitic capacitance CC1 of the driven switch, and the positive toggle threshold of Schmitt trigger SMIT2. The falling edge delay of the clock signal in the fifth delay unit 201 is determined by the values ​​of resistor R5, the gate parasitic capacitance CC1 of the driven switch, and the negative toggle threshold of Schmitt trigger SMIT2. The rising edge delay of the clock signal in the sixth delay unit 202 is determined by the values ​​of resistor R8, the gate parasitic capacitance CC2 of the driven switch, and the positive toggle threshold of Schmitt trigger SMIT1. The falling edge delay of the clock signal in the sixth delay unit 202 is determined by the values ​​of resistor R7, the gate parasitic capacitance CC2 of the driven switch, and the negative toggle threshold of Schmitt trigger SMIT2.

[0049] As a further illustration of the embodiments of the present invention, Figure 4 The forward switching thresholds of Schmitt triggers SMIT1~SMIT2 are determined by the width-to-length ratios of NMOS transistors NM4~NM5 and PMOS transistor PM6. The smaller the width-to-length ratio of NMOS transistor NM4, or the larger the width-to-length ratios of NMOS transistors NM5 and PMOS transistor PM6, the higher the forward switching thresholds of Schmitt triggers SMIT1~SMIT2; conversely, the larger the width-to-length ratio of NMOS transistor NM4, or the smaller the width-to-length ratios of NMOS transistors NM5 and PMOS transistor PM6, the lower the forward switching thresholds of Schmitt triggers SMIT1~SMIT2.

[0050] As a further illustration of the embodiments of the present invention, Figure 4 The negative switching thresholds of Schmitt triggers SMIT1~SMIT2 are determined by the width-to-length ratios of PMOS transistors PM3 and PM5, and NMOS transistor NM6. The smaller the width-to-length ratio of PMOS transistor PM3, or the larger the width-to-length ratios of PMOS transistors PM5 and NMOS transistor NM6, the lower the negative switching thresholds of Schmitt triggers SMIT1~SMIT2. Conversely, the larger the width-to-length ratio of PMOS transistor PM3, or the smaller the width-to-length ratios of PMOS transistors PM5 and NMOS transistor NM6, the lower the negative switching thresholds of Schmitt triggers SMIT1~SMIT2.

[0051] As a further illustration of the embodiments of the present invention, the positive flip-flop thresholds of Schmitt triggers SMIT1 and SMIT2 are set to be slightly greater than the threshold voltage of the driven switch, and the negative flip-flop thresholds of Schmitt triggers SMIT1 and SMIT2 are set to be slightly less than the threshold voltage of the driven switch. Figure 3The non-overlapping clock generation circuit with adaptive dead time can generate a set of low-level non-overlapping clock signals CLKA and CLKB to drive the PMOS switch. The signal timing of the non-overlapping clock generation circuit driving the PMOS switch is as follows: Figure 5 As shown. During the rising edge of the clock signal CLKA, when CLKA rises to the positive toggle threshold of the Schmitt trigger SMIT2, the PMOS switch driven by the clock signal CLKA is completely turned off. Subsequently, the clock signal CLKB begins to fall, and the PMOS switch driven by the clock signal CLKB turns on again. Therefore, there is no shoot-through phenomenon between the upper and lower switches. Example 2

[0052] like Figure 6 As shown, this embodiment of the invention provides another adaptive dead-time non-overlapping clock generation circuit, which... Figure 3 The NAND gates NAND3~NAND4 are replaced with NOR gates NOR1~NOR2, thereby generating a set of high-level non-overlapping clock signals CLKA and CLKB, which can be used to drive the NMOS switching transistors. Another adaptive dead-time non-overlapping clock generation circuit of the present invention drives the NMOS switching transistors with the following signal timing: Figure 7 As shown. During the falling edge of the clock signal CLKA, when CLKA falls to the negative toggle threshold of the Schmitt trigger SMIT2, the NMOS switch driven by the clock signal CLKA is completely turned off. Subsequently, the clock signal CLKB begins to rise, and the NMOS switch driven by the clock signal CLKB turns on again. Therefore, there is no shoot-through phenomenon between the upper and lower switches.

[0053] As a further illustration of the embodiments of the present invention, Figure 3 , Figure 6 The dead time of the non-overlapping clock signal generated by the non-overlapping clock generation circuit is affected by the values ​​of the parasitic gate capacitances CC1 and CC2 of the driven switch. A larger value of the parasitic gate capacitance results in a longer dead time for the generated non-overlapping clock signal; conversely, a smaller value results in a shorter dead time. Therefore, the non-overlapping clock generation circuit of this invention can adaptively adjust the dead time of the output non-overlapping clock signal based on the magnitude of the parasitic gate capacitance of the driven switch. By setting an appropriate dead time for the non-overlapping clock signal while ensuring that the upper and lower switches do not shoot through, the operating efficiency of the driven switch is improved. Example 3

[0054] like Figure 8As shown, this embodiment of the invention provides a specific embodiment of a non-overlapping clock generation circuit applied in a charge pump circuit. This specific embodiment of the non-overlapping clock generation circuit includes a seventh delay unit 301, an eighth delay unit 302, a ninth delay unit 303, a tenth delay unit 304, a charge pump circuit unit 300, inverters INV9~INV13, NAND gates NAND5~NAND8, Schmitt triggers SMIT3~SMIT6, an input clock signal CLK, and output clock signals CLKA1, CLKA2, CLKB1, and CLKB2.

[0055] The seventh delay unit 301 includes a PMOS transistor PM7, an NMOS transistor NM7, resistors R9-R10, the gate parasitic capacitance CC3 of the driven switch, a positive power supply VCC, and a negative power supply GND. The eighth delay unit 302 includes a PMOS transistor PM8, an NMOS transistor NM8, resistors R11-R12, the gate parasitic capacitance CC4 of the driven switch, a positive power supply VCC, and a negative power supply GND. The ninth delay unit 303 includes a PMOS transistor PM9, an NMOS transistor NM9, resistors R13-R14, the gate parasitic capacitance CC5 of the driven switch, a positive power supply VCC, and a negative power supply GND. The tenth delay unit 304 includes a PMOS transistor PM10, an NMOS transistor NM10, resistors R15-R16, the gate parasitic capacitance CC6 of the driven switch, a positive power supply VCC, and a negative power supply GND.

[0056] Figure 9 The circuit schematic of the charge pump circuit unit 300 includes PMOS transistors PM11~PM13, NMOS transistor NM11, flying lead capacitor Cf, output capacitor Cout, clock signals CLKA1, CLKA2, CLKB1, CLKB2, charge pump voltage output terminal CPOUT, positive power supply VCC, and negative power supply GND.

[0057] As a further illustration of the embodiments of the present invention, Figure 8The non-overlapping clock generation circuit generates clock signals CLKA1, CLKA2, CLKB1, and CLKB2 to drive the switching transistors in the charge pump circuit unit 300, including PMOS transistors PM11~PM13 and NMOS transistor NM11. The seventh delay unit 301, the eighth delay unit 302, the ninth delay unit 303, and the tenth delay unit 304 are used to set the dead time of the non-overlapping clock signals required by the switching transistors in the charge pump circuit unit 300. The magnitude of the dead time is jointly determined by the values ​​of the resistors in the seventh delay unit 301, the eighth delay unit 302, the ninth delay unit 303, and the tenth delay unit 304, the values ​​of the gate parasitic capacitances CC3~CC6 of the driven switching transistors, and the toggling thresholds of the Schmitt triggers SMIT3~SMIT36. That is, the dead time of the non-overlapping clock signals CLKA2 and CLKB1, and CLKA1 and CLKB2 can be adaptively adjusted according to the values ​​of the gate parasitic capacitances CC3~CC6 of the switching transistors in the charge pump circuit unit 300.

[0058] like Figure 10 As shown, clock signals CLKA2 and CLKB1 are a set of low-level, non-overlapping clock signals. During the rising edge of clock signal CLKB1, when CLKB1 rises to the positive toggle threshold of Schmitt trigger SMIT3, the PMOS switch PM13 driven by clock signal CLKB1 is completely turned off. Subsequently, clock signal CLKA2 begins to fall, and the PMOS switch PM12 driven by clock signal CLKA2 turns on again. Therefore, there is no shoot-through phenomenon between the upper and lower switches.

[0059] Similarly, the clock signal ( The inverted clock signal CLKA1 and clock signal CLKB2 form a set of high-level, non-overlapping clock signals. During the falling edge of clock signal CLKB2, when CLKB2 falls to the negative toggle threshold of Schmitt trigger SMIT4, the NMOS switch NM11 driven by clock signal CLKB2 is completely turned off. Subsequently, clock signal CLKA1 begins to fall, and the PMOS switch PM11 driven by clock signal CLKA1 turns on again. Therefore, there is no shoot-through phenomenon between the upper and lower switches.

[0060] When process deviations or changes in process angles cause changes in the value of the parasitic gate capacitance of the switching transistor in the charge pump circuit unit 300, the dead time of the clock signals CLKA1, CLKA2, CLKB1, and CLKB2 generated by the non-overlapping clock generation circuit can be adaptively adjusted to improve the working efficiency of the charge pump circuit.

[0061] This invention solves the problem that the dead time of existing non-overlapping clock generation circuits cannot accurately match the required dead time of the driven switching transistor, thereby improving the operating efficiency of power switching circuits such as charge pumps. Furthermore, this invention is not only applicable to the charge pump circuit exemplified above, but can be applied to any electronic circuit that meets the requirements of this invention.

[0062] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A non-overlapping clock generation circuit with adaptive dead time, used to generate two non-overlapping clock signals, characterized in that, include: The fifth and sixth delay units have the same structure, both consisting of a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, and a parasitic capacitor. The gates of the first PMOS transistor and the first NMOS transistor are connected together and serve as the input terminal. The sources of the first PMOS transistor and the first NMOS transistor are respectively connected to the positive power supply VCC and the negative power supply GND. The drains of the first PMOS transistor and the first NMOS transistor are respectively connected to one end of the first resistor and the second resistor. The other ends of the first resistor and the second resistor are connected to the parasitic capacitor connected to the negative power supply GND and serve as the output terminal. The first trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the inverted output clock signal CLKB output by the sixth delay unit, and an output terminal for receiving the input terminal of the fifth delay unit. The second trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the in-phase output clock signal CLKA output by the fifth delay unit, and an output terminal for receiving the input terminal of the sixth delay unit. The first trigger gate unit includes: a first Schmitt trigger and a first logic gate; the input terminal of the first Schmitt trigger serves as the second input terminal of the first trigger gate unit, the output terminal of the first Schmitt trigger is connected to the first input terminal of the first logic gate, the second input terminal of the first logic gate serves as the first input terminal of the first trigger gate unit, and the output terminal of the first logic gate serves as the output terminal of the first trigger gate unit. The second trigger gate unit includes: a second Schmitt trigger and a second logic gate; the input terminal of the second Schmitt trigger serves as the second input terminal of the second trigger gate unit, the output terminal of the second Schmitt trigger is connected to the first input terminal of the second logic gate, the second input terminal of the second logic gate serves as the first input terminal of the second trigger gate unit, and the output terminal of the second logic gate serves as the output terminal of the second trigger gate unit.

2. The adaptive dead-time non-overlapping clock generation circuit as described in claim 1, characterized in that, The first logic gate includes: a first inverter, a second inverter, a third inverter, and a first NAND gate or a first NOR gate; the input terminal of the first inverter is connected to the output terminal of the first Schmitt trigger, the input terminal of the second inverter is connected to the input clock signal CLK, the output terminals of the first inverter and the second inverter are connected to the two input terminals of the first NAND gate or the first NOR gate, the output terminal of the first NAND gate or the first NOR gate is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the input terminal of the fifth delay unit.

3. The adaptive dead-time non-overlapping clock generation circuit as described in claim 1, characterized in that, The second logic gate includes: a fourth inverter, a fifth inverter, and a second NAND gate or a second NOR gate; the input terminal of the fourth inverter is connected to the output terminal of the second Schmitt trigger, the input clock signal CLK and the output terminal of the fourth inverter are connected to the two input terminals of the second NAND gate or the second NOR gate, the output terminal of the second NAND gate or the second NOR gate is connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the input terminal of the sixth delay unit.

4. The adaptive dead-time non-overlapping clock generation circuit as described in claim 1, characterized in that, The first Schmitt trigger and the second Schmitt trigger have the same structure, each including: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gates of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected to the signal input terminal VIN; the source of the first PMOS transistor and the gate of the fourth NMOS transistor are connected to the positive power supply VCC; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the third PMOS transistor; the third PMOS transistor... The drain of the OS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to the negative power supply GND. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor, and serves as the signal output terminal VOUT. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor and the source of the third NMOS transistor. The source of the second NMOS transistor and the gate of the fourth PMOS transistor are connected to the negative power supply GND. The drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the positive power supply VCC.

5. A non-overlapping clock generation circuit with adaptive dead time, used to generate four non-overlapping clock signals, characterized in that, include: Delay units 7 to 10; All four components have the same structure, consisting of a first PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, and a parasitic capacitor. The gates of the first PMOS transistor and the first NMOS transistor are connected together and serve as the input terminal. The sources of the first PMOS transistor and the first NMOS transistor are connected to the positive power supply VCC and the negative power supply GND, respectively. The drains of the first PMOS transistor and the first NMOS transistor are connected to one end of the first resistor and the second resistor, respectively. The other ends of the first resistor and the second resistor are connected to the parasitic capacitor connected to the negative power supply GND and serve as the output terminal. The first trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the inverted output clock signal CLKB1 output by the tenth delay unit, a third input terminal for receiving the inverted output clock signal CLKB2 output by the ninth delay unit, and an output terminal for receiving the input terminals of the seventh and eighth delay units. The second trigger gate unit has a first input terminal for receiving the input clock signal CLK, a second input terminal for receiving the in-phase output clock signal CLKA1 output by the seventh delay unit, a third input terminal for receiving the in-phase output clock signal CLKA2 output by the eighth delay unit, and an output terminal for receiving the input terminals of the ninth and tenth delay units.

6. The adaptive dead-time non-overlapping clock generation circuit as described in claim 5, characterized in that, The first trigger gate unit includes: a first Schmitt trigger, a second Schmitt trigger, a first inverter to a third inverter, a first NAND gate, and a second NAND gate; the input terminal of the third inverter is connected to the input clock signal CLK, the input terminal of the first Schmitt trigger is connected to the inverted output clock signal CLKB1, the input terminal of the second Schmitt trigger is connected to the inverted output clock signal CLKB2, the output terminal of the second Schmitt trigger is connected to the input terminal of the first inverter, the output terminals of the first inverter and the first Schmitt trigger are connected to the two input terminals of the first NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the second inverter, the output terminals of the second inverter and the third inverter are connected to the two input terminals of the second NAND gate, and the output terminal of the second NAND gate serves as the output terminal of the first trigger gate unit.

7. The adaptive dead-time non-overlapping clock generation circuit as described in claim 5, characterized in that, The second trigger gate unit includes: a third Schmitt trigger, a fourth Schmitt trigger, a fourth inverter, a fifth inverter, a third NAND gate, and a fourth NAND gate; the input of the third Schmitt trigger is connected to the in-phase output clock signal CLKA1, the input of the fourth Schmitt trigger is connected to the in-phase output clock signal CLKA2, the outputs of the third and fourth Schmitt triggers are connected to the two inputs of the third NAND gate, the output of the third NAND gate is connected to the input of the fourth inverter, the output of the fourth inverter and the input clock signal CLK are connected to the two inputs of the fourth NAND gate, the output of the fourth NAND gate is connected to the input of the fifth inverter and the input of the tenth delay unit, and the output of the fifth inverter is connected to the input of the ninth delay unit.

8. A charge pump circuit, characterized in that, include: An adaptive dead-time non-overlapping clock generation circuit as described in any one of claims 5 to 7; The charge pump circuit unit includes: a second PMOS transistor to a fourth PMOS transistor, a second NMOS transistor, a flying lead capacitor, and an output capacitor; the sources of the second PMOS transistor and the third PMOS transistor are connected to the positive power supply VCC, the gate of the second PMOS transistor is connected to the non-inverting output clock signal CLKA1, the drain of the second PMOS transistor is connected to one end of the flying lead capacitor and the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the inverting output clock signal CLKB2, the source of the second NMOS transistor is connected to the negative power supply GND, the other end of the flying lead capacitor is connected to the drain of the third PMOS transistor and the source of the fourth PMOS transistor, the gate of the third PMOS transistor is connected to the inverting output clock signal CLKB1, the gate of the fourth PMOS transistor is connected to the non-inverting output clock signal CLKA2, and the drain of the fourth PMOS transistor is connected to the output capacitor connected to the negative power supply GND and the voltage output terminal CPOUT.

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