A memory chip electrical connection performance test method, system and storage medium

Abstract

The application relates to the field of memory testing, and discloses a memory chip electrical connection performance testing method and system and a storage medium. The method comprises the following steps: a test device sends a first valid input data group to a preset key signal line set of a memory chip; the memory chip calculates first valid output data by using a preset logic algorithm; the test device selects a to-be-tested key signal line from the preset key signal line set, obtains a second valid input data group according to the to-be-tested key signal line and the first valid input data group, and matches the second valid input data group to be sent to the preset key signal line set of the memory chip; the memory chip calculates second valid output data by using the preset logic algorithm; and the test device determines whether the to-be-tested key signal line has an electrical connection fault according to the first valid output data and the second valid output data. The application effectively solves the technical bottleneck of low testing efficiency and difficult fault positioning in the prior art, and ensures the reliability verification of the electrical connection performance between a memory bank and a mainboard.

Description

Technical Field

[0001] This invention relates to the field of memory testing, and more particularly to a method, system, and storage medium for testing the electrical connection performance of memory chips. Background Technology

[0002] A memory module consists of multiple memory chips and a PCB (Printed Circuit Board). Users typically plug the memory module into the motherboard for use.

[0003] In existing technologies, when a memory module is plugged into the motherboard and multiple signal lines on the memory chip malfunction, it's impossible to accurately locate the faulty signal line, let alone determine whether it's an open circuit or a short circuit. Furthermore, the algorithm specified in the JEDEC standard requires extensive calculations, resulting in low computational efficiency. Therefore, existing technologies cannot guarantee the continuity of the electrical connection between the memory chip and the motherboard. There is an urgent need to provide a solution for testing the continuity of the electrical connection between the memory chip and the motherboard. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to overcome the shortcomings of the prior art and provide a method, system and storage medium for testing the electrical connection performance of memory chips.

[0005] This invention provides the following technical solution: In a first aspect, this disclosure provides a method for testing the electrical connection performance of a memory chip, applied to a memory chip electrical connection performance testing system. The memory chip electrical connection performance testing system includes a testing device and a memory module. The memory module includes gold fingers and a memory chip. The testing device is electrically connected to one end of the gold fingers, and the other end of the gold fingers is electrically connected to the TEN pin of the memory chip. The method includes: The testing equipment sets the TEN pin of the memory chip high via the gold finger and sends the first valid input data group to the preset key signal line set of the memory chip; The memory chip uses a preset logic algorithm to calculate the first valid output data based on the first valid input data group; The testing device selects a key signal line to be tested from the preset key signal line set, and obtains a second valid input data group based on the key signal line to be tested and the first valid input data group, and sends the second valid input data group to the preset key signal line set of the memory chip in a matching manner; The memory chip uses the preset logic algorithm to calculate the second valid output data based on the second valid input data group; The testing equipment determines whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data, wherein the electrical connection fault includes open circuit or short circuit.

[0006] In an optional implementation, when the TEN pin of the memory chip is set to high, the memory chip enters the electrical connection performance test mode. The preset key signal line set includes multiple command address signal lines, multiple clock signal lines, and one alarm signal line; The first valid input data group includes multiple valid input levels. One valid input level in the first valid input data group corresponds to one of the command address signal line, clock signal line, and alarm signal line of the preset key signal line set.

[0007] In an optional implementation, each of the valid input levels in the first valid input data group is a low level, and the test device sends the first valid input data group to a preset key signal line set of the memory chip, including: The test equipment inputs a low level to each key signal line of the preset key signal line set; The step of obtaining the second valid input data group based on the key signal line under test and the first valid input data group includes: The low level corresponding to the key signal line under test in the first valid input data group is flipped to a high level to obtain the second valid input data group.

[0008] In an optional implementation, sending the second valid input data group to the preset key signal line set of the memory chip includes: Determine the correspondence between each valid input level in the first valid input data group and each key signal line in the preset key signal line set; According to the correspondence, each valid input level in the second valid input data group is input to the corresponding key signal line in the preset key signal line set.

[0009] In an optional implementation, the testing equipment determines whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data, including: The testing equipment determines whether the first valid output data and the second valid output data are the same; If they are the same, then it is determined that there is an electrical connection fault in the key signal line under test; If they are different, then the electrical connection of the key signal line under test is normal.

[0010] In an optional implementation, the method further includes: When a target signal line with an electrical connection fault exists in the preset critical signal line set, the test equipment sends a third valid input data group to the preset critical signal line set, wherein the valid input voltages in the third valid input data group are all set to a preset level, and the preset level is 0 or 1; The memory chip selects a target logic sub-algorithm corresponding to the target signal line from the preset logic algorithm, and uses the target logic sub-algorithm to calculate the third valid output data based on the third valid input data group; The testing equipment determines whether the target signal line is in an open circuit or short circuit state based on the third valid output data.

[0011] In an optional implementation, the testing device determines whether the target signal line is in an open-circuit or short-circuit state based on the third valid output data, including: When the preset level is 0 and the third valid output data is 0, it is determined that the target signal line is in a short-circuit state. When the preset level is 0 and the third valid output data is 1, it is determined that the target signal line is in an open circuit state.

[0012] In an optional implementation, the testing device determines whether the target signal line is in an open-circuit or short-circuit state based on the third valid output data, including: When the preset level is 1 and the third valid output data is 1, it is determined that the target signal line is in a short-circuit state. When the preset level is 1 and the third valid output data is 0, it is determined that the target signal line is in an open circuit state.

[0013] Secondly, this disclosure provides a test system for the electrical connection performance of a memory chip. The system includes a test device and a memory module. The memory module includes a gold finger and a memory chip. The test device is electrically connected to one end of the gold finger, and the other end of the gold finger is electrically connected to the TEN pin of the memory chip. The testing equipment is used to set the TEN pin of the memory chip to a high position through the gold fingers and send a first valid input data group to the preset key signal line set of the memory chip; The memory chip is used to calculate the first valid output data based on the first valid input data group using a preset logic algorithm. The testing equipment is further configured to select a key signal line to be tested from the preset key signal line set, obtain a second valid input data set based on the key signal line to be tested and the first valid input data set, and send the second valid input data set to the preset key signal line set of the memory chip in a matching manner; The memory chip is also used to calculate the second valid output data based on the second valid input data group using the preset logic algorithm; The testing equipment is also used to determine whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data, wherein the electrical connection fault includes an open circuit or a short circuit.

[0014] Thirdly, this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method for testing the electrical connection performance of a memory chip as described in the first aspect.

[0015] The beneficial effects of this application are: The electrical connection performance testing method for memory chips provided in this application involves the testing device setting the TEN pin of the memory chip high via the gold fingers and sending a first valid input data group to a preset set of key signal lines of the memory chip. The memory chip calculates a first valid output data based on the first valid input data group using a preset logic algorithm. The testing device selects a key signal line to be tested from the preset set of key signal lines and obtains a second valid input data group based on the key signal line to be tested and the first valid input data group, and sends the second valid input data group to the preset set of key signal lines of the memory chip. The memory chip calculates a second valid output data based on the second valid input data group using the preset logic algorithm. The testing device determines whether there is an electrical connection fault in the key signal line to be tested based on the first valid output data and the second valid output data, wherein the electrical connection fault includes open circuit or short circuit. This application enables precise location of specific faulty signal lines in a single test and effectively solves the technical bottlenecks of low testing efficiency, difficulty in fault location, and misjudgment of multiple faults in the prior art through an output data comparison mechanism, ensuring the reliability verification of the electrical connection performance between the memory module and the motherboard.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the various drawings, similar components are numbered similarly.

[0018] Figure 1 A flowchart of a method for testing the electrical connection performance of a memory chip according to an embodiment of this application is shown; Figure 2 This illustration shows a schematic diagram of the structure of a memory chip electrical connection performance testing system provided in an embodiment of this application; Figure 3 This paper shows a schematic diagram of another memory chip electrical connection performance testing system provided in an embodiment of this application; Figure 4 This illustrates the computational complexity required in the prior art to calculate the electrical connectivity of each critical signal line; Figure 5 A flowchart of another method for testing the electrical connection performance of a memory chip provided in an embodiment of this application is shown. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the template description is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1 like Figure 1The diagram shown is a flowchart of a method for testing the electrical connection performance of a memory chip according to an embodiment of this application. The method for testing the electrical connection performance of a memory chip provided in this embodiment is applied to a memory chip electrical connection performance testing system, and the method specifically includes the following steps: In step S110, the test device sets the TEN pin of the memory chip to a high position using the gold fingers and sends the first valid input data group to the preset key signal line set of the memory chip.

[0023] like Figure 2 As shown, the electrical connection performance testing system for memory chips in this application includes a testing device and a memory module. The memory module includes gold fingers and multiple memory chips. The testing device is electrically connected to one end of the gold fingers, and the other end of the gold fingers is electrically connected to the TEN pin of each memory chip. The memory chip contains a preset critical signal line set, which includes multiple command address signal lines CA0~CA13 (14 bits in total), multiple clock signal lines (CK_t, CK_c), and an alarm signal line ALERT_n.

[0024] Preferably, in practical applications, such as Figure 3 As shown, a test device can be connected in parallel to multiple memory modules to test the memory chips in multiple memory modules simultaneously. The connection method between the test device and each memory module is the same as the connection method between the test device and a memory module in this application, and will not be described in detail here.

[0025] Understandably, the test equipment first generates a test command, then sends the test command to the gold finger, and the gold finger then sets the TEN pin of the memory chip high according to the test command, so that the memory chip enters the Connectivity Test (CT) mode.

[0026] Upon entering CT mode, the testing equipment sends a first valid input data group to the preset critical signal line set of the memory chip. This first valid input data group includes multiple valid input levels. Each valid input level in the first valid input data group corresponds to one of the command address signal line, clock signal line, and alarm signal line input to the preset critical signal line set. In this application, all valid input levels in the first valid input data group are low, meaning a low level is input to each critical signal line of the preset critical signal line set. At this time, CA0~CA13=0, CK_t, CK_c=0, and ALERT_n=0.

[0027] The above method initializes the memory chip by setting the TEN pin high using the gold fingers, enabling it to enter a specific test mode. This provides the prerequisites for subsequent testing operations, ensuring that the testing process proceeds according to predetermined rules and logic, thereby guaranteeing the validity and accuracy of the test results. A baseline state is established for subsequent logic operations by sending a first valid input data group with all-low levels to the preset key signal line set.

[0028] In step S120, the memory chip uses a preset logic algorithm to calculate the first valid output data based on the first valid input data group.

[0029] It should be noted that the preset logic algorithm in this application adopts the logic algorithm defined by the JEDEC standard. The JEDEC standard is a memory standard developed by JEDEC (Solid State Technology Association, the leading standards body for the microelectronics industry). This preset logic algorithm includes multiple logic sub-algorithms, as shown in Table 1 below: Table 1 JEDEC Standard Logic Algorithm

[0030] Understandably, in the preset logic algorithms in Table 1 above, XOR(CA[0,1,2,3,8,9,10,11]) represents performing an XOR operation on the command address signal line CA[0,1,2,3,8,9,10,11], and the result of this XOR operation is fed back as MT0; XOR(CA[0,4,5,6,8,12,13],ALERT_n) represents performing an XOR operation on the command address signal line CA[0,4,5,6,8,12,13] and the alarm signal line ALERT_n, and the result of this XOR operation is fed back as MT1; XOR(CA[1,4,9,12],CK_t,CK_c) represents performing an XOR operation on the command address signal line CA[1,4,9,12], the clock signal lines CK_t and CK_c, and the result of this XOR operation is fed back as MT1; XOR(CA[1,4,9,12],CK_t,CK_c) represents performing an XOR operation on the command address signal line CA[1,4,9,12], the clock signal lines CK_t and CK_c, and the result of this XOR operation is fed back as MT0 ...0,1,2,3,8,9,10,11]) represents performing an XOR operation The result is fed back as MT2; XOR(CA[2,5,7,10,13],CK_t) means performing an XOR operation on the command address signal line CA[2,5,7,10,13] and the clock signal line CK_t, and the result of this XOR operation is fed back as MT3; XOR(CA[3,6,7,11],CK_c,ALERT_n) means performing an XOR operation on the command address signal line CA[3,6,7,11], the clock signal line CK_c, and the alarm signal line ALERT_n, and the result of this XOR operation is fed back as MT4; !(MT0) means inverting (MT0); !(MT1) means inverting (MT1); !(MT2) means inverting (MT2); !(MT3) means inverting (MT3); !(MT4) means inverting (MT4).

[0031] Preferably, the above calculation results are fed back by multiple valid output data lines DQ in the memory chip, and the correspondence between each valid output data line and each calculation result is shown in Table 2 below: Table 2. Correspondence between each valid output data line and each calculation result.

[0032] Understandably, DQL0~DQL7, DML, TDQS_c, DQSL_t, DQSL_c, DQU0~DQU7, DMU, ​​DQSU_t, and DQSU_c in Table 2 above are all valid output data lines used to provide feedback on valid outputs. X16, X8, and X4 in the table represent the number of data bits in the memory chip, which are 16 valid output data lines, 8 valid output data lines, and 4 valid output data lines, respectively.

[0033] The memory chip uses the aforementioned preset logic algorithm to calculate the first valid output data value0 based on the first valid input data group (CA0~CA13=0, CK_t, CK_c=0, ALERT_n=0).

[0034] The above method uses a logic algorithm defined by the JEDEC standard to calculate and process the input data of the memory chip, so that the output data can reflect the electrical connection status of the key signal lines inside the memory chip, providing specific quantitative basis for subsequent fault detection.

[0035] In step S130, the testing device selects a key signal line to be tested from the preset key signal line set, obtains a second valid input data group based on the key signal line to be tested and the first valid input data group, and sends the second valid input data group to the preset key signal line set of the memory chip.

[0036] Preferably, the testing device selects a key signal line to be tested (ALERT_n or CA0~CA13) from a preset set of key signal lines, flips the low level corresponding to the key signal line to be tested in the first valid input data group to a high level, obtains a second valid input data group, and determines the correspondence between each valid input level in the first valid input data group and each key signal line in the preset set of key signal lines.

[0037] For example, if the selected key signal line to be tested is ALERT_n, then the low level of ALERT_n in the first valid input data group is toggled to a high level. At this time, the second valid input data group is CA0~CA13=0, CK_t, CK_c=0, and ALERT_n=1. If the selected key signal line to be tested is CA0, then the low level of CA0 in the first valid input data group is toggled to a high level. At this time, the second valid input data group is CA0=1, CA1~CA13=0, CK_t, CK_c=0, and ALERT_n=0.

[0038] Furthermore, after obtaining the second valid input data group, the second valid input data group is sent to the preset key signal line set of the memory chip. Specifically, each valid input level in the second valid input data group can be input to the corresponding key signal line in the preset key signal line set according to the correspondence between the valid input level and the key signal line, thereby ensuring the matching between the two valid input level inputs and the key signal line.

[0039] The above method constructs a second valid input data group by flipping the level state of a single signal line under test. This design keeps the states of other signal lines unchanged, ensuring the singleness of the test variable and avoiding the cumbersome process of locating the problem by performing a large number of combined tests in the prior art, which greatly improves the test efficiency and accuracy.

[0040] In step S140, the memory chip uses a preset logic algorithm to calculate the second valid output data based on the second valid input data group.

[0041] Similarly, the memory chip uses the preset logic algorithm in Table 1 above to calculate the second valid output data based on the second valid input data group.

[0042] The above method calculates the second valid output data by re-executing the JEDEC standard algorithm. By maintaining algorithm consistency and changing only a single input variable, the output difference directly reflects the electrical connection status of the signal line under test, providing a quantitative basis for fault diagnosis.

[0043] Step S150: The test equipment determines whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data. The electrical connection fault includes open circuit or short circuit.

[0044] Preferably, after calculating the first valid output data and the second valid output data, the testing equipment determines whether the first valid output data and the second valid output data are the same. If they are the same, it is determined that there is an electrical connection fault (open circuit or short circuit) in the key signal line under test; if they are different, it is determined that the electrical connection of the key signal line under test is normal.

[0045] For example, (1) if the selected key signal line to be tested is ALERT_n, and the second valid output data calculated according to the preset logic algorithm is value-ALERT_n_1, then the first valid output data value0 is determined. (2) If the selected key signal line to be tested is CA0, and the second effective output data value-ALERT_n_1 is calculated according to the preset logic algorithm, determine whether value0==value-ALERT_n_1. If the calculation results of each logic sub-algorithm in the two effective output data are equal, then it is determined that ALERT_n has an electrical connection fault (open circuit or short circuit). If the calculation results of the logic sub-algorithm related to ALERT_n in the two effective output data are not equal, then it is determined that ALERT_n is electrically connected normally.

[0046] In an optional implementation, if some signal lines in the memory chip are fixed (fixed to 1 or fixed to 0), the following method is used to determine whether a fault exists in the signal line: The test device inputs the fourth valid input data group CA0~CA13=1, CK_t, CK_c=1, ALERT_n=1 to each key signal line of the preset key signal line set, and calculates the fourth valid output data value1 using a preset logic algorithm; The test device selects a key signal line to be tested from the preset key signal line set, flips the high level corresponding to the key signal line to be tested to a low level to obtain the fifth valid input data group, and inputs the fifth valid input data group to each key signal line of the preset key signal line set, and calculates the fifth valid output data using a preset logic algorithm; The test device determines whether there is an electrical connection fault in the key signal line to be tested based on the fourth and fifth valid output data. The logic of the above method is the same as that of steps S110~S150, only the valid input level within the valid input data group is changed, so it will not be described in detail here.

[0047] It should be noted that "fixed" means that the signal line's voltage level does not change with the input and remains in a fixed high (1) or low (0) state. Under normal circumstances, the signal line's voltage level should change accordingly with the input signal to reflect the circuit's logic state and data transmission. However, when a signal line malfunctions, such as being open-circuited or short-circuited, its voltage level becomes fixed and can no longer respond normally to changes in the input signal.

[0048] In existing technologies, such as Figure 4 As shown, if it is necessary to calculate the electrical connectivity of CA0~CA13, CK_t, CK_c, and ALERT_n, then C needs to be performed. 1 17 +C 2 17 +...+C 17 17 The previous combination test involved a huge number of tests, requiring all calculations to pinpoint the faulty signal line. Furthermore, it inherently suffers from the problem that when multiple lines fail in a single test, the correct test result cannot be obtained. The method proposed in this application, through comparative analysis of two valid output data sets, can accurately determine whether each critical signal line under test has an electrical connection fault. This simplifies the calculation process of existing technologies, and can specifically locate the faulty line, significantly reducing the computational load and enabling effective testing of the continuity of the electrical connection between the memory chip and the motherboard.

[0049] In a preferred embodiment, such as Figure 5 As shown, the method for testing the electrical connection performance of a memory chip provided in this application embodiment further includes the following steps: Step S160: When there is a target signal line with an electrical connection fault in the preset key signal line set, the test equipment sends a third valid input data group to the preset key signal line set, wherein the valid input voltages in the third valid input data group are all set to a preset level, and the preset level is 0 or 1. In step S170, the memory chip selects the target logic sub-algorithm corresponding to the target signal line from the preset logic algorithm, and uses the target logic sub-algorithm to calculate the third valid output data based on the third valid input data group; In step S180, the test equipment determines whether the target signal line is in an open circuit or short circuit state based on the third valid output data.

[0050] Understandably, after determining which signal line is open or short-circuited through steps S110 to S150, this application can further determine whether the signal line is open or short-circuited through steps S160 to S180.

[0051] Specifically, when a target signal line with an electrical connection fault exists in the preset critical signal line set, the test equipment first sends a third valid input data group to the preset critical signal line set. The valid input voltages in the third valid input data group are all set to a preset level, which is either 0 or 1. Next, the memory chip selects a target logic sub-algorithm corresponding to the target signal line from a preset logic algorithm. Using the target logic sub-algorithm, it calculates the third valid output data based on the third valid input data group. Finally, the test equipment determines whether the target signal line is in an open-circuit or short-circuit state based on the third valid output data.

[0052] For example, when the target signal line with an electrical connection fault is ALERT_n, the test equipment sends the third valid input data group to the preset key signal line set. (1) Assume that the valid input electrical values ​​in the third valid input data group are all set to 0. At this time, CA0~CA13=0, CK_t, CK_c=0, and ALERT_n=0. The memory chip selects the target logic sub-algorithm corresponding to ALERT_n from the preset logic algorithm (e.g., the logic sub-algorithms corresponding to MT1 and MT4), and uses the target logic sub-algorithm to calculate the third valid output data according to the third valid input data group. If the third valid output data is 0, it means that ALERT_n is fixed to 1. At this time, ALERT_n is in a short circuit state. If the third valid output data is 1, it means that ALERT_n is fixed to 0. At this time, ALERT_n is in an open circuit state. (2) Assume that the effective input currents in the third effective input data group are all set to 1. At this time, CA0~CA13=1, CK_t, CK_c=1, and ALERT_n=1. The memory chip selects the target logic sub-algorithm corresponding to ALERT_n from the preset logic algorithm (for example, the logic sub-algorithms corresponding to MT1 and MT4), and uses the target logic sub-algorithm to calculate the third effective output data according to the third effective input data group. If the third effective output data is 1, it means that ALERT_n is fixed to 1. At this time, ALERT_n is in a short circuit state. If the third effective output data is 0, it means that ALERT_n is fixed to 0. At this time, ALERT_n is in an open circuit state.

[0053] Understandably, if the faults of the two lines ALERT_n and CA0 have been identified, the above steps are first used to determine whether ALERT_n is in an open circuit or a short circuit state. Similarly, the memory chip needs to select a target logic sub-algorithm (e.g., the logic sub-algorithm corresponding to MT1) from the preset logic algorithm that only contains CA0 and does not contain ALERT_n to determine whether CA0 is in an open circuit or a short circuit state.

[0054] It should be noted that the above method can only be used to determine whether each critical signal line is short-circuited or open-circuited when four or fewer critical signal lines have electrical connection faults. When five or more critical signal lines have electrical connection faults, due to the XOR logic characteristic of the JEDEC algorithm, the fault effects of multiple signal lines will overlap and cancel each other out. For example, when CA0 is open-circuited (fixed 0) and CA1 is short-circuited (fixed 1) simultaneously, in the calculation of MT0=XOR(CA[0,1,2,3...]), the fault effects of both may be masked by other normal signal lines, causing the final output to fail to accurately reflect the true state of individual signal lines. This logical coupling effect means that when the number of faulty signal lines exceeds four, the system cannot infer the specific fault type from the output difference, but it can still accurately identify the existence of faulty signal lines.

[0055] After detecting a fault signal line, the above method further distinguishes between open-circuit and short-circuit fault types by combining all-high / all-low level inputs with the target logic sub-algorithm, thus solving the defect of unknown fault type in the prior art.

[0056] The electrical connection performance testing method for memory chips provided in this application involves a testing device setting the TEN pin of the memory chip high via gold fingers and sending a first valid input data group to a preset set of critical signal lines of the memory chip. The memory chip then uses a preset logic algorithm to calculate a first valid output data based on the first valid input data group. The testing device selects a key signal line to be tested from the preset set of critical signal lines and obtains a second valid input data group based on the key signal line to be tested and the first valid input data group. This second valid input data group is then sent to the preset set of critical signal lines of the memory chip. The memory chip uses a preset logic algorithm to calculate a second valid output data based on the second valid input data group. Based on the first and second valid output data, the testing device determines whether there is an electrical connection fault in the key signal line to be tested, where the electrical connection fault includes an open circuit or a short circuit. This application enables precise location of a specific faulty signal line in a single test and effectively solves the technical bottlenecks of low testing efficiency, difficulty in fault location, and misjudgment of multiple faults in the prior art through an output data comparison mechanism, ensuring the reliability verification of the electrical connection performance between the memory module and the motherboard.

[0057] Example 2 like Figure 2 The diagram shown is a structural schematic of a memory chip electrical connection performance testing system 200 according to an embodiment of this application. The system includes: a testing device 210 and a memory module 220. The memory module 220 includes a gold finger 221 and a memory chip 222. The testing device 210 and one end of the gold finger 221 are electrically connected, and the other end of the gold finger 221 is electrically connected to the TEN pin of the memory chip 222. Test device 210 is used to set the TEN pin of memory chip 222 high through gold finger 221 and send the first valid input data group to the preset key signal line set of memory chip 222; Memory chip 222 is used to calculate first valid output data based on the first valid input data group using a preset logic algorithm; The test device 210 is also used to select a key signal line to be tested from a preset set of key signal lines, and obtain a second valid input data group according to the key signal line to be tested and the first valid input data group, and send the second valid input data group to the preset set of key signal lines of the memory chip 222. The memory chip 222 is also used to calculate the second valid output data based on the second valid input data group using a preset logic algorithm; The test equipment 210 is also used to determine whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data, wherein the electrical connection fault includes an open circuit or a short circuit.

[0058] The electrical connection performance testing system 200 for memory chips provided in this application embodiment can implement all processes of the electrical connection performance testing method for memory chips corresponding to Embodiment 1, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0059] The electrical connection performance testing system for memory chips provided in this application embodiment enables precise location of specific faulty signal lines in a single test. It also effectively solves the technical bottlenecks of low testing efficiency, difficulty in fault location, and misjudgment of multiple faults in the prior art through an output data comparison mechanism, ensuring the reliability verification of the electrical connection performance between the memory module and the motherboard.

[0060] Example 3 This embodiment also provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the steps of the electrical connection performance testing method for the memory chip in this embodiment.

[0061] In this embodiment, the computer-readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (e.g., SD or XD memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the computer-readable storage medium can be an internal storage unit of a computer device, such as the hard disk or memory of the computer device. In other embodiments, the computer-readable storage medium can also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computer device. Of course, the computer-readable storage medium can also include both the internal storage unit and the external storage device of the computer device. In this embodiment, the computer-readable storage medium is typically used to store the operating system and various application software installed on the computer device. In addition, the computer-readable storage medium can also be used to temporarily store various types of data that have been output or will be output.

[0062] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0063] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0064] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium can be a non-volatile storage medium or a volatile storage medium. For example, the storage medium can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code.

[0065] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for testing the electrical connection performance of a memory chip, characterized in that, An electrical connection performance testing system for memory chips, comprising a testing device and a memory module, the memory module including gold fingers and a memory chip, wherein the testing device is electrically connected to one end of the gold fingers, and the other end of the gold fingers is electrically connected to the TEN pin of the memory chip, the method comprising: The testing equipment sets the TEN pin of the memory chip high via the gold finger and sends the first valid input data group to the preset key signal line set of the memory chip; The memory chip uses a preset logic algorithm to calculate the first valid output data based on the first valid input data group; The testing device selects a key signal line to be tested from the preset key signal line set, and obtains a second valid input data group based on the key signal line to be tested and the first valid input data group, and sends the second valid input data group to the preset key signal line set of the memory chip in a matching manner; The memory chip uses the preset logic algorithm to calculate the second valid output data based on the second valid input data group; The testing equipment determines whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data, wherein the electrical connection fault includes open circuit or short circuit; When the TEN pin of the memory chip is set to high, the memory chip enters the electrical connection performance test mode. The preset key signal line set includes multiple command address signal lines, multiple clock signal lines, and one alarm signal line; The first valid input data group includes multiple valid input levels. One valid input level in the first valid input data group corresponds to one of the command address signal line, clock signal line, and alarm signal line of the preset key signal line set.

2. The method for testing the electrical connection performance of a memory chip according to claim 1, characterized in that, Each valid input level in the first valid input data group is low, and the test device sends the first valid input data group to a preset key signal line set of the memory chip, including: The test equipment inputs a low level to each key signal line of the preset key signal line set; The step of obtaining the second valid input data group based on the key signal line under test and the first valid input data group includes: The low level corresponding to the key signal line under test in the first valid input data group is flipped to a high level to obtain the second valid input data group.

3. The method for testing the electrical connection performance of a memory chip according to claim 1, characterized in that, The step of sending the second valid input data group to the preset key signal line set of the memory chip includes: Determine the correspondence between each valid input level in the first valid input data group and each key signal line in the preset key signal line set; According to the correspondence, each valid input level in the second valid input data group is input to the corresponding key signal line in the preset key signal line set.

4. The method for testing the electrical connection performance of a memory chip according to claim 1, characterized in that, The testing equipment determines whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data, including: The testing equipment determines whether the first valid output data and the second valid output data are the same; If they are the same, then it is determined that there is an electrical connection fault in the key signal line under test; If they are different, then the electrical connection of the key signal line under test is normal.

5. The method for testing the electrical connection performance of a memory chip according to claim 1, characterized in that, The method further includes: When a target signal line with an electrical connection fault exists in the preset critical signal line set, the test equipment sends a third valid input data group to the preset critical signal line set, wherein the valid input voltages in the third valid input data group are all set to a preset level, and the preset level is 0 or 1; The memory chip selects a target logic sub-algorithm corresponding to the target signal line from the preset logic algorithm, and uses the target logic sub-algorithm to calculate the third valid output data based on the third valid input data group; The testing equipment determines whether the target signal line is in an open circuit or short circuit state based on the third valid output data.

6. The method for testing the electrical connection performance of a memory chip according to claim 5, characterized in that, The testing equipment determines whether the target signal line is in an open-circuit or short-circuit state based on the third valid output data, including: When the preset level is 0 and the third valid output data is 0, it is determined that the target signal line is in a short-circuit state. When the preset level is 0 and the third valid output data is 1, it is determined that the target signal line is in an open circuit state.

7. The method for testing the electrical connection performance of a memory chip according to claim 5, characterized in that, The testing equipment determines whether the target signal line is in an open-circuit or short-circuit state based on the third valid output data, including: When the preset level is 1 and the third valid output data is 1, it is determined that the target signal line is in a short-circuit state. When the preset level is 1 and the third valid output data is 0, it is determined that the target signal line is in an open circuit state.

8. A system for testing the electrical connection performance of a memory chip, characterized in that, The system includes a testing device and a memory module. The memory module includes a gold finger and a memory chip. The testing device is electrically connected to one end of the gold finger, and the other end of the gold finger is electrically connected to the TEN pin of the memory chip. The testing equipment is used to set the TEN pin of the memory chip to a high position through the gold fingers and send a first valid input data group to the preset key signal line set of the memory chip; The memory chip is used to calculate the first valid output data based on the first valid input data group using a preset logic algorithm. The testing equipment is further configured to select a key signal line to be tested from the preset key signal line set, obtain a second valid input data set based on the key signal line to be tested and the first valid input data set, and send the second valid input data set to the preset key signal line set of the memory chip in a matching manner; The memory chip is also used to calculate the second valid output data based on the second valid input data group using the preset logic algorithm; The testing equipment is also used to determine whether there is an electrical connection fault in the key signal line under test based on the first valid output data and the second valid output data, wherein the electrical connection fault includes an open circuit or a short circuit. When the TEN pin of the memory chip is set to high, the memory chip enters the electrical connection performance test mode. The preset key signal line set includes multiple command address signal lines, multiple clock signal lines, and one alarm signal line; The first valid input data group includes multiple valid input levels. One valid input level in the first valid input data group corresponds to one of the command address signal line, clock signal line, and alarm signal line of the preset key signal line set.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for testing the electrical connection performance of the memory chip according to any one of claims 1-7.

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