Deep silicon etching method and semiconductor process apparatus

Abstract

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a circulation step, and the circulation step comprises an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and an oxidation step for forming a protective layer on the sidewall of the groove. The process gas used in the removal step comprises fluorocarbon gas and oxygen-containing gas, and the fluorocarbon ratio of the fluorocarbon gas is less than 1 / 2. The lower electrode power of the removal step is greater than 0 and less than 50 W. Through the cooperation of the process gas and the lower electrode power in the removal step, the process gas can effectively remove the by-products on the top, sidewall and inner wall of the groove of the mask layer during the etching process of the removal step, and the over-etching of the silicon sidewall in the head region of the isolation groove is effectively reduced, so that the morphology precision of the isolation groove and the active region is improved, and the product yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a deep silicon etching method and semiconductor process equipment. Background Technology

[0002] Dynamic Random Access Memory (DRAM), as a semiconductor storage device that directly exchanges data with the Central Processing Unit (CPU) inside a computer, has seen its capacity and read / write speed become bottlenecks restricting computer performance as CPU performance improves. In DRAM, the distance between active arrays (AAs) determines its storage density. To ensure sufficient conductive channel width and reduce leakage between AAs, the deep silicon etching linewidth of the isolation trenches between AAs is only on the order of tens of nanometers, while the depth of the isolation trenches needs to reach over 200 nm.

[0003] For isolation trenches with small critical dimensions (CD), byproducts formed during etching are mainly deposited on the top and sidewalls of the mask layer, with only a small amount forming on the trench sidewalls and bottom wall. However, in related technologies for etching to form high aspect ratio isolation trenches, it is generally impossible to effectively remove byproducts from the outer wall of the mask layer, leading to deformation or even blockage at the top of the opening. Alternatively, if the etching intensity is high, although it can remove byproducts from the outer wall of the mask layer, it will cause severe sidewall erosion problems on the silicon sidewalls of the isolation trench near the head region of the mask layer. Both situations will affect the morphological accuracy of the isolation trench and AA, thereby affecting the product yield.

[0004] Therefore, how to effectively remove byproducts while reducing excessive erosion of the silicon sidewalls in the head region of the isolation trench is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a deep silicon etching method and semiconductor process equipment to solve the technical problem in related technologies that it is impossible to simultaneously and effectively remove by-products and reduce excessive erosion of the silicon sidewalls in the head region of the isolation trench.

[0006] To address the aforementioned problems, this invention provides a deep silicon etching method, comprising a cyclic step. The cyclic step includes an etching step for etching trenches on a silicon substrate, a removal step for removing byproducts, and an oxidation step for forming a protective layer on the sidewalls of the trenches. The process gas used in the removal step includes a fluorocarbon gas and an oxygen-containing gas, and the carbon-to-fluorine ratio of the fluorocarbon gas is less than 1 / 2. The lower electrode power in the removal step is greater than 0 and less than 50W.

[0007] Optionally, in the process gas used in the removal step, the carbon-fluorine ratio of the fluorocarbon gas is less than or equal to 1 / 3.

[0008] Optionally, in the process gas used in the removal step, the flow rate ratio of the fluorocarbon gas to the oxygen-containing gas is 1:0.5 to 1:0.25.

[0009] Optionally, the cyclic steps are two, namely a first cyclic step and a second cyclic step, wherein in the first cyclic step, the etching step, the oxidation step and the removal step are executed sequentially; and in the second cyclic step, the etching step, the removal step and the oxidation step are executed sequentially.

[0010] Optionally, after the first cycle step is completed, an intermediate oxidation step is performed, and after the intermediate oxidation step is completed, the second cycle step is performed.

[0011] Optionally, before performing the cyclic steps, a pre-removal step is first performed to remove the oxide layer on the surface of the silicon substrate.

[0012] Optionally, the process gas used in the pre-removal step includes fluorocarbon gases and oxygen-containing gases, and the carbon-fluorine ratio of the fluorocarbon gases is greater than or equal to 1 / 2.

[0013] Optionally, the lower electrode power of the pre-removal step is 500-800W.

[0014] Optionally, in the process gas used in the pre-removal step, the flow ratio of the fluorocarbon gas to the oxygen-containing gas is 1:0.35 to 1:0.2.

[0015] The present invention also provides a semiconductor process apparatus, comprising: a process chamber, a carrier substrate, an upper radio frequency power supply, a lower radio frequency power supply, and a controller, wherein,

[0016] The support base is used to support the silicon substrate;

[0017] The upper radio frequency power supply is used to apply upper electrode power to the process chamber;

[0018] The lower radio frequency power supply is used to apply lower electrode power to the support base;

[0019] The controller includes a memory and a processor, the memory storing computer instructions, and the processor executing the computer instructions to perform the deep silicon etching method according to any one of claims 1-9.

[0020] In the deep silicon etching method provided by this invention, the removal step (BT) uses fluorocarbon gas and oxygen-containing gas as process gases and applies a lower electrode power of 0-50W. The lower lower electrode power makes the etching process of the BT step more inclined towards chemical etching. The carbon-to-fluorine ratio of the fluorocarbon gas is less than 1 / 2, which has strong activity and chemical etching ability. During the reaction, the fluorocarbon gas can dissociate into sufficient active gas F, and the oxygen-containing gas can react with the carbon polymer formed by the fluorocarbon gas. The carbon-to-fluorine ratio is further adjusted to reduce the consumption caused by the reaction of active gas F with carbon polymer. Under the action of a small downward traction force applied by the lower lower electrode power, a large amount of active gas F accumulates in the opening area of ​​the mask layer, which can fully contact and react with the by-products on the top and sidewalls of the mask layer, thereby effectively removing the by-products on the top and sidewalls of the mask layer. A small amount of active gas F enters the trench under the traction of the lower electrode power to remove a small amount of by-products on its inner wall, thereby achieving comprehensive and effective removal of by-products.

[0021] Simultaneously, by effectively removing byproducts from the top, sidewalls, and inner walls of the mask layer, a lower lower electrode power is applied in the BT step. This makes the etching process more chemically oriented, resulting in less process gas entering the trench and less reflection of process gas towards the trench sidewalls under less traction force. This reduces lateral erosion of the trench sidewalls, especially minimizing excessive erosion of the silicon sidewalls in the isolation trench head region. Through this cyclic etching process, the trench depth continuously increases until the target depth of the isolation trench is achieved. The lateral erosion of the silicon sidewalls in the isolation trench head region is weak, and the morphological accuracy is high. Consequently, the morphological accuracy of the active region (AA) formed between the isolation trenches is also high, thereby improving the morphological accuracy of the isolation trench and AA, and ultimately improving product yield. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the deep silicon etching method in related technologies;

[0024] Figure 2 The image shows the etch morphology of the isolation trench obtained using a deep silicon etching method provided by relevant technologies.

[0025] Figure 3 The image shows the etched topography of the isolation trench and active region obtained using the deep silicon etching method provided by the relevant technology.

[0026] Figure 4 An electron microscope image of the etching morphology of the isolation trench obtained by the first deep silicon etching method provided in an embodiment of the present invention;

[0027] Figure 5 This is an etching morphology diagram of an isolation trench obtained by the first deep silicon etching method provided in an embodiment of the present invention;

[0028] Figure 6 A flowchart illustrating the deep silicon etching method provided in this embodiment of the invention, including a first cycle step and a second cycle step;

[0029] Figure 7 The deep silicon etching method provided in this embodiment of the invention includes a first cycle step and a second cycle step, and an electron microscope image of the trench morphology formed by etching in the first cycle step;

[0030] Figure 8 for Figure 7 Etching morphology of the central groove;

[0031] Figure 9 An electron microscope image of the etching morphology of the isolation trench obtained by the second deep silicon etching method provided in an embodiment of the present invention;

[0032] Figure 10 This is an etching morphology diagram of an isolation trench obtained by the second deep silicon etching method provided in an embodiment of the present invention;

[0033] Figure 11 A schematic diagram of the deep silicon etching method provided in this embodiment of the invention when an intermediate oxidation step is added between the first cycle step and the second cycle step.

[0034] Figure 12 This is an electron microscope image of the etching morphology of the isolation trench obtained by the third deep silicon etching method provided in the embodiments of the present invention;

[0035] Figure 13 The etching morphology of the isolation trench obtained by the third deep silicon etching method provided in the embodiment of the present invention is shown in the figure.

[0036] Figure 14 Electron micrographs of the etching morphology of the isolation trench and the active region obtained by the fourth deep silicon etching method provided in the embodiments of the present invention;

[0037] Figure 15 The etching topography of the isolation trench and active region obtained by the fourth deep silicon etching method provided in the embodiments of the present invention is shown in the figure.

[0038] Figure 16 This is a schematic diagram of a semiconductor process equipment provided in an embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10-Mask layer; 11-Opening; 20-Silicon substrate; 21-Isolation trench; 211-Head region; A-Lateral etching; B-Carbon polymer; 212-Lower region; 22-Active region; 221-End; 222-Middle;

[0041] 110 - Process chamber; 120 - Support base; 130 - Upper RF power supply; 140 - Upper matching unit; 150 - RF coil; 160 - Dielectric window; 170 - Lower matching unit; 180 - Lower RF power supply. Detailed Implementation

[0042] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0045] Figure 1 This is a schematic diagram of the deep silicon etching method in related technologies. Figure 2 This is an etching morphology diagram of the isolation trench 21 obtained according to the deep silicon etching method provided by the relevant technology.

[0046] like Figure 1As shown, in the related techniques for etching the silicon substrate 20 to form the isolation trench 21 between A and B, a cyclical process is typically used: a main etch (ME) step, a breakthrough (BT) step, and an oxidation (OX) step to cyclically etch the silicon substrate 20 to obtain the isolation trench 21 with the desired morphology and depth. In the ME step, a mixed gas of Cl2 and O2 is used as the process gas to etch the silicon substrate 20 to improve the selectivity of the mask layer 10 and reduce the lateral erosion A of the trench sidewalls. This precisely transfers the pattern of the openings 11 of the mask layer 10 to the silicon substrate 20 to form a trench of a certain depth. Due to the C of the trench... With a smaller D, a large amount of Si-O-Cl byproducts generated by the reaction of Cl2, O2, and Si are deposited on the top and sidewalls of mask layer 10, while only a small amount of byproducts are deposited on the sidewalls and bottom walls of the trenches. The BT step uses CH2F2 and CH3F as etching gases and applies a high lower electrode power to ensure the removal of byproducts generated in the ME step, allowing for smooth etching. However, the high lower electrode power makes the BT step etching process more like plasma etching, causing the plasma generated in the BT step to erode the trenches near mask layer 10. Figure 2 As shown, this process causes severe sidewall erosion on the silicon sidewalls of the trench in the head region 211, affecting the morphological accuracy of the isolation trench 21 and AA, and impacting product yield. The OX step forms a SiO2 protective layer with better resistance to ion bombardment through the silicon oxide sidewalls. The chemical bond energy of Si-O is greater than that of Si-Cl, Si-F, and Si-Si, effectively protecting the silicon sidewalls and reducing the erosion caused by the ME step. This cyclic etching process continuously increases the trench depth until the target depth is achieved. Finally, the protective layer formed in the OX step is removed by the ME step to obtain the isolation trench 21. However, the silicon sidewall erosion problem in the head region 211 of the isolation trench 21 is quite severe.

[0047] The reaction formula for the formation of the byproduct Si-O-Cl in the ME step is as follows:

[0048] Si(s)+SiO2(s)+CL2(g)→Si-O-CL(s).

[0049] This embodiment provides a deep silicon etching method. In the removal step of the cycle, a fluorocarbon gas and an oxygen-containing gas are used as process gases, and a lower electrode power of 0-50W is applied. The lower lower electrode power makes the etching process of the removal step more like chemical etching. At the same time, the carbon-fluorine ratio of the fluorocarbon gas is less than 1 / 2, and its activity and chemical etching ability are strong. By coordinating the process gas and the lower electrode power, the process gas can effectively remove by-products from the top, sidewalls and inner walls of the mask layer 10 and the trench during the removal step etching process, while effectively reducing excessive erosion of the silicon sidewalls of the head region 211 of the isolation trench 21. The deep silicon etching method provided by this embodiment of the invention will be further described in detail below with reference to the accompanying drawings.

[0050] Figure 4 The image shows an electron microscope (EM) image of the etching morphology of the isolation trench 21 obtained by the first deep silicon etching method according to an embodiment of the present invention; wherein the dark gray area is the active region 22 and the light gray area is the isolation trench 21. Figure 5 This is an etching topography diagram of the isolation trench 21 obtained by the first deep silicon etching method provided in an embodiment of the present invention.

[0051] This invention provides a deep silicon etching method, including a cyclic step. The cyclic step includes an etching step for etching trenches on a silicon substrate 20, a removal step for removing byproducts, and an oxidation step for forming a protective layer on the sidewalls of the trenches. The process gas used in the removal step includes a fluorocarbon gas and an oxygen-containing gas, and the carbon-fluorine ratio of the fluorocarbon gas is less than 1 / 2. The lower electrode power of the removal step is greater than 0 and less than 50W.

[0052] Initially, a mask layer 10, such as a SiO2 mask layer 10, is provided on the top of the silicon substrate 20, and the mask layer 10 has an opening 11 that can define the region of the isolation trench 21. During the process, the oxidation step (OX) forms a protective layer with better resistance to ion bombardment through the silicon oxide sidewalls to protect the silicon sidewalls and reduce the erosion of the silicon sidewalls by the etching step (ME). The etching step (ME) etches the silicon substrate 20 in the region of the opening 11, transferring the pattern of the opening 11 of the mask layer 10 to the silicon substrate 20 to form a trench of a certain depth. Most of the byproducts generated by the ME step are deposited on the top and sidewalls of the mask layer 10, and a small portion enters the trench and is deposited on the inner wall of the trench.

[0053] The etching process (BT) uses fluorocarbon gases and oxygen-containing gases as process gases, and applies a lower electrode power of 0-50W. The lower lower electrode power makes the etching process of the BT step more inclined towards chemical etching. The carbon-to-fluorine ratio of the fluorocarbon gases is less than 1 / 2, which has strong activity and chemical etching ability. During the reaction, the fluorocarbon gases can dissociate into sufficient active gas F, and the oxygen-containing gas can react with the carbon polymer B formed by the fluorocarbon gases. The carbon-to-fluorine ratio is further adjusted to reduce the consumption caused by the reaction of active gas F with carbon polymer B. Under the action of a small downward traction force applied by the lower lower electrode power, a large amount of active gas F accumulates in the opening 11 area of ​​the mask layer 10, which can fully contact and react with the by-products on the top and sidewalls of the mask layer 10, thereby effectively removing the by-products on the top and sidewalls of the mask layer 10. A small amount of active gas F enters the trench under the traction of the lower electrode power to remove a small amount of by-products on its inner wall, thereby achieving comprehensive and effective removal of by-products.

[0054] Simultaneously, after effectively removing byproducts from the top, sidewalls, and inner walls of the mask layer 10, a lower lower electrode power is applied in the BT step, making the etching process more chemically oriented. Less process gas enters the trench during the process, and less process gas is reflected back to the trench sidewalls under a smaller traction force, thus reducing lateral erosion A on the trench sidewalls, especially reducing excessive erosion of the silicon sidewalls in the head region 211 of the isolation trench 21. This cyclic etching process continuously increases the trench depth until the target depth of the isolation trench 21 is achieved. The lateral erosion A on the silicon sidewalls in the head region 211 of the isolation trench 21 is weak, and the morphological accuracy is high. Correspondingly, the morphological accuracy of the active region 22 (AA) formed between the isolation trenches 21 is also high, thereby improving the morphological accuracy of the isolation trench 21 and AA, and ultimately improving product yield.

[0055] In the deep silicon etching method provided in this embodiment of the invention, by coordinating the process gas and the lower electrode power in the removal step, the process gas can effectively remove the byproducts on the top, sidewalls and inner walls of the mask layer 10 during the etching process, while effectively reducing the excessive erosion of the silicon sidewalls of the head region 211 of the isolation trench 21, thereby improving the morphological accuracy of the isolation trench 21 and the active region 22, and thus improving the product yield.

[0056] like Figure 4 and Figure 5 As shown, in this embodiment of the invention, by coordinating the process gas and the power of the lower electrode in the removal step, the degree of lateral erosion A in the head region 211 of the isolation tank 21 is relatively... Figure 2 The transverse erosion A of the head region 211 of the middle isolation tank 21 was significantly improved; specifically, the power of the lower electrode in the removal step was 0 to 30 W, preferably 10 to 20 W.

[0057] In this embodiment of the invention, the process gas used in the removal step is, for example, a carbon-fluorine ratio of less than or equal to 1 / 3 for a carbon-fluorine gas. During the process, in the removal step, fluorocarbon gases are used as the main etching gases. A carbon-to-fluorine ratio of less than or equal to 1 / 3 results in stronger activity and chemical etching capabilities. During the reaction, more active gas F is released, which fully contacts and reacts with the byproducts in the opening 11 area of ​​the mask layer 10 to remove them. This ensures effective removal of byproducts in the opening 11 area of ​​the mask layer 10, guaranteeing the accuracy of the pattern in the opening 11 area of ​​the mask layer 10, and correspondingly improving the morphological accuracy of the etched isolation trench 21 and the active region 22 between it. Simultaneously, in the removal step, the carbon-to-fluorine ratio of the fluorocarbon gases is positively correlated with the lower electrode power. A lower carbon-to-fluorine ratio, combined with a lower lower electrode power, ensures comprehensive and effective removal of byproducts in the opening 11 area of ​​the mask layer 10 and the byproducts on the inner wall of the trench. Furthermore, it reduces the lateral erosion A of the trench sidewalls by the process gases, further improving the morphological accuracy of the etched isolation trench 21 and the active region 22 between it, and consequently, further improving the product yield.

[0058] Specifically, the removal of carbon and fluorine gases in the step can be achieved using CHF3, CF4, etc. The reaction formula for CHF3 in removing the byproduct Si-O-Cl is as follows:

[0059] Si-O-CL(s) + CHF3(g) → SiF x (g)+CO(g)+CO2(g)+HF(g)+HCL(g).

[0060] In this embodiment of the invention, the flow ratio of fluorocarbon gas to oxygen-containing gas in the process gas used in the removal step is 1:0.5 to 1:0.25. The oxygen-containing gas can react with the carbon polymer B formed by the fluorocarbon gas. Further adjusting the carbon-to-fluorine ratio reduces the consumption of reactive gas F released from the fluorocarbon gas in reaction with carbon polymer B, thereby improving the effectiveness of reactive gas F in removing byproducts.

[0061] In this embodiment of the invention, an inert gas can be added to the process gas in the removal step as a diluent gas to improve etching uniformity; specifically, the inert gas can be Ar, He, etc.

[0062] Specifically, in the removal step, the process gases include CHF3, Ar, and O2, wherein the flow rate of CHF3 is 100–200 sccm, the flow rate of Ar is 100–300 sccm, and the flow rate of O2 is 0–40 sccm. The process gas flow rate ratio is approximately 3:3:1 (CHF3:Ar:O2). The chamber pressure is 3–5 mT, the chamber temperature is 35–60 °C, the upper electrode power is 100–300 W, and the lower electrode power is 0–50 W. The flow rate ratio of the process gases ejected from the nozzles in the chamber and distributed in the central, middle, and edge regions of the silicon substrate 20 is approximately 33:33:34. When using ICP (Inductively Coupled Plasma) dry etching, the current ratio of the inner and outer coils is approximately 0.25–0.75, and the process time is 5–12 s.

[0063] Figure 6 The deep silicon etching method provided in the embodiments of the present invention includes a flowchart of the first cycle step and the second cycle step. Figure 7 The deep silicon etching method provided in the embodiments of the present invention includes a first cycle step and a second cycle step, and an electron microscope image of the trench morphology formed by etching in the first cycle step. Figure 8 for Figure 7 Etching morphology diagram of the central groove.

[0064] like Figure 6 As shown in the embodiment of the present invention, there are two cyclic steps, namely the first cyclic step Cycle1 and the second cyclic step Cycle2. In the first cyclic step, the etching step, oxidation step, and removal step are executed sequentially; in the second cyclic step, the etching step, removal step, and oxidation step are executed sequentially. The first cyclic step is used to etch the head region 211 of the isolation trench 21 near the mask layer 10, and the second cyclic step is used to etch the lower region 212 of the isolation trench 21. The fluorocarbon gas in the BT step contains a certain amount of carbon. In the head region 211 near the mask layer 10 where the trench depth is small, a certain amount of carbon will remain on the bottom and side walls of the trench during the BT step reaction. The first cyclic step is set to execute the ME step, OX step, and BT step sequentially. After the BT step in the previous cycle ends, the ME step in the next cycle immediately follows. The carbon remaining in the BT step in the previous cycle can form carbon polymer B in the ME step and be deposited on the side and bottom walls of the trench, thus protecting the side walls of the trench.

[0065] like Figure 7 and Figure 8As shown, as the first cycle proceeds, the trench depth continuously increases, and the thickness of the carbon polymer B formed on the trench sidewalls also gradually increases, forming a conical trench with sidewalls sloping downwards towards the central region. The carbon polymer B provides etching allowance for the lateral erosion A of the head region 211 of the isolation trench 21 during the ME and BT steps of the second cycle, resisting the lateral erosion A of the silicon sidewalls of the head region 211 of the isolation trench 21 during the second cycle. After the first cycle is completed, the second cycle continues: the ME, BT, and OX steps are executed sequentially, ensuring smooth etching and maintaining the verticality of the silicon sidewalls of the lower region 212. Simultaneously, the carbon polymer B formed on the head region 211 of the isolation trench 21 protects the silicon sidewalls of this region, resisting the lateral erosion A of the silicon sidewalls in this region during the second cycle, further reducing the lateral erosion A experienced by the head region 211 of the isolation trench 21, thereby further improving the morphological accuracy of the isolation trench 21 and further improving product yield.

[0066] Figure 9 An electron microscope image of the etching morphology of the isolation trench 21 obtained by the second deep silicon etching method provided in an embodiment of the present invention. Figure 10 This is an etching topography diagram of the isolation trench 21 obtained by the second deep silicon etching method provided in an embodiment of the present invention. Figure 9 and Figure 10 As shown, in this embodiment of the invention, the cyclic steps are divided into a first cyclic step and a second cyclic step. The first cyclic step is set to the cyclic sequence of ME step, OX step and BT step. When the second cyclic step is set to the cyclic sequence of ME step, BT step and OX step, the lateral erosion A of the head region 211 in the isolation trench 21 obtained by sequentially executing the first cyclic step and the second cyclic step is smaller, and the morphological accuracy of the isolation trench 21 is higher.

[0067] Figure 11 This is a schematic diagram of the process of adding an intermediate oxidation step between the first and second cycle steps in the deep silicon etching method provided in the embodiments of the present invention.

[0068] In embodiments of the present invention, such as Figure 11As shown, after the first cycle step is completed, an intermediate oxidation step is performed, and after the intermediate oxidation step is completed, the second cycle step continues. An intermediate oxidation step is added between the first and second cycle steps. After the BT step of the last cycle of the first cycle removes the byproducts and protective layer from the trench sidewall, the first cycle step is completed. Subsequently, the intermediate oxidation step is performed. The process parameters of this intermediate oxidation step can be the same as those of the oxidation steps in the first and second cycle steps to oxidize the silicon sidewall and form a protective layer. Then, the ME and BT steps of the first cycle in the second cycle step are performed. The protective layer formed by the intermediate oxidation step can protect the silicon sidewall in the MR and BT steps. This reduces the occurrence of the ME and BT steps of the first cycle of the second cycle step immediately following the last BT step of the first cycle step, which would result in the silicon sidewall lacking a protective layer during the latter ME and BT steps, leading to more severe lateral erosion A on the silicon sidewall. This protects the silicon sidewall and further improves the morphological accuracy of the isolation trench 21.

[0069] Figure 12 An electron microscope image of the etching morphology of the isolation trench 21 obtained by the third deep silicon etching method provided in the embodiment of the present invention. Figure 13 This is an etching morphology diagram of the isolation trench 21 obtained by the third deep silicon etching method provided in an embodiment of the present invention. Figure 12 and Figure 13 As shown in the embodiment of the present invention, after adding an intermediate oxidation step between the first cycle step and the second cycle step, the lateral erosion A of the head region 211 of the obtained isolation trench 21 is further reduced, and the verticality and morphological accuracy of the isolation trench 21 are higher.

[0070] In this embodiment of the invention, a pre-removal step is performed before the cycling step. The pre-removal step is used to remove the oxide layer on the surface of the silicon substrate 20. The surface of the silicon substrate 20 is exposed in the opening 11 region of the mask layer 10. The exposed area of ​​the silicon substrate 20 can be oxidized by contact with the ambient gas to form a natural oxide layer. Before the cycling step, the pre-removal step (BT0) is performed to remove the natural oxide layer to ensure that the etching of the subsequent cycling step proceeds smoothly.

[0071] The pattern of the openings 11 in the mask layer 10 corresponds to the area of ​​the isolation trench 21, and the reserved area of ​​the mask layer 10 corresponds to the area of ​​AA, forming multiple strip-shaped mask islands. In the pre-removal step, the process gas contacts the surface of the silicon substrate 20 through the openings 11 of the mask layer 10, removing oxides from its surface. During this process, the process gas simultaneously etches the strip-shaped mask islands, and the two ends of the strip-shaped mask islands have more contact with the process gas than the middle part in the length direction, resulting in a higher etching rate at the two ends of the strip-shaped mask islands than in the middle part, and they tend to become thinner under the etching action of the BTO step; correspondingly, as Figure 3 As shown, the two ends 221 of the AA etched based on the mask layer 10 are also relatively thin, which increases its contact resistance and affects its electrical properties, thereby affecting the product's input and output of stored signals.

[0072] To address the issue of the AA end being too thin due to the micro-load effect in the BT0 step, in this embodiment of the invention, the process gas used in the pre-removal step includes fluorocarbon gases and oxygen-containing gases, and the carbon-fluorine ratio of the fluorocarbon gases is greater than or equal to 1 / 2. Fluorocarbon gases are used as the main etching gas in the BTO step, with a carbon-to-fluorine ratio greater than or equal to 1 / 2. Correspondingly, their activity and chemical etching ability are relatively weak. During the reaction, the fluorocarbon gases can generate carbon polymer B. Oxygen-containing gases can react with the carbon polymer B formed on the oxide layer surface, ensuring the etching and removal of oxides by the process gases. Simultaneously, under the micro-loading effect, the process gases generate more carbon polymer B at the end regions of the strip mask island. Correspondingly, more carbon polymer B is deposited at the ends of the strip mask island, which can significantly slow down the etching rate of the process gases at the ends. This balances the etching rate of the process gases at the ends and middle of the strip mask island, improving the over-etching effect at the ends due to the micro-loading effect, improving the morphological accuracy of the strip mask island, and further improving the morphological accuracy of the ends 221 and middle 222 of the AA formed by subsequent cyclic etching steps, ensuring the input and output of stored signals by the AA in the product. Figure 14 and Figure 15 As shown, after adjusting BT0 in this embodiment of the invention, the end 221 of AA becomes less thinner, and its shape can be maintained to a greater extent.

[0073] Specifically, in the BT0 step, the fluorocarbon gas can be C4F6, and the oxygen-containing gas can be O2.

[0074] In this embodiment of the invention, the lower electrode power in the pre-removal step is 500-800W. The higher lower electrode power used in the BTO step makes the etching process more similar to plasma etching. During etching, the fluorocarbon gas can dissociate to generate more carbon polymer B and active gas F, thereby improving the overall removal rate of the oxide layer in the BTO step, shortening the removal time, and reducing etching damage to the strip mask islands. Furthermore, plasma etching has higher directionality, which can further reduce the micro-load effect compared to chemical etching, thereby further improving the morphological accuracy of the strip mask islands. This, in turn, improves the morphological accuracy of the AA formed in subsequent cyclic etching steps, ensuring the input and output of stored signals by the AA in the product.

[0075] In this embodiment of the invention, the flow ratio of fluorocarbon gas to oxygen-containing gas in the process gas used in the pre-removal step is 1:0.35 to 1:0.2. The oxygen-containing gas can react with the carbon polymer B formed on the oxide layer surface by the fluorocarbon gas. The carbon-fluorine ratio is further adjusted to ensure that the process gas can effectively etch and remove the oxide.

[0076] In this embodiment of the invention, an inert gas can be added to the process gas in the pre-removal step as a diluent gas to improve etching uniformity; specifically, the inert gas can be Ar, He, etc.

[0077] Specifically, in the pre-removal step, the process gases include C4F6, Ar, and O2, wherein the flow rate of C4F6 is 20–60 sccm, the flow rate of Ar is 100–300 sccm, and the flow rate of O2 is 0–20 sccm. The flow rate ratio of C4F6:Ar:O2 is approximately 4:24:1. The chamber pressure is 5–10 mT, the chamber temperature is 35–60 °C, the upper electrode power is 500–800 W, and the lower electrode power is 500–800 W. The flow rate ratio of the process gases ejected from the nozzles in the chamber to the central, middle, and edge regions of the silicon substrate 20 is approximately 33:33:34. When using the ICP dry etching process, the current ratio of the inner and outer coils is approximately 0.25–0.75, and the process time is 5–10 s.

[0078] like Figure 16 As shown, this embodiment also provides a semiconductor process apparatus, including: a process chamber 110, a support base 120, an upper radio frequency power supply 130, a lower radio frequency power supply 180, and a controller. The support base 120 is used to support a silicon substrate 20; the upper radio frequency power supply 130 is used to apply upper electrode power to the process chamber 110; the lower radio frequency power supply 180 is used to apply lower electrode power to the support base 120; the controller includes a memory and a processor. The memory stores computer instructions, and the processor executes the computer instructions to perform the aforementioned deep silicon etching method. This semiconductor process apparatus is capable of performing the aforementioned deep silicon etching method and possesses all the beneficial effects of the etching method, which will not be elaborated further here.

[0079] Specifically, in this semiconductor process equipment, a dielectric window 160 is provided above the carrier base 120 within the process chamber 110. An RF coil 150 is positioned above the dielectric window 160. An upper matching unit 140 is provided between the RF coil 150 and the upper RF power supply 130. The upper RF power supply 130 provides RF power to the RF coil 150 through the upper matching unit 140, thereby exciting the process gas inside the process chamber 110 to generate plasma. A lower matching unit 170 is provided between the carrier base 120 and the lower RF power supply 180. The lower RF power supply 180 provides RF power to the carrier base 120 through the lower matching unit 170 to provide RF bias. The carrier base 120 can be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum adsorption chuck.

[0080] The semiconductor process equipment in this application embodiment can be an inductively coupled plasma (ICP) device or a capacitively coupled plasma (CCP) device. This application embodiment does not limit the type of semiconductor process equipment.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A deep silicon etching method, characterized in that, The process includes a cycle step, which includes an etching step for etching trenches on a silicon substrate (20), a removal step for removing byproducts, and an oxidation step for forming a protective layer on the sidewalls of the trenches. The process gas used in the removal step includes a fluorocarbon gas and an oxygen-containing gas, and the carbon-to-fluorine ratio of the fluorocarbon gas is less than 1 / 2. The lower electrode power in the removal step is greater than 0 and less than 50W, and the carbon-to-fluorine ratio of the fluorocarbon gas in the removal step is positively correlated with the lower electrode power.

2. The deep silicon etching method according to claim 1, characterized in that, In the process gas used in the removal step, the carbon-to-fluorine ratio of the fluorocarbon gas is less than or equal to 1 / 3.

3. The deep silicon etching method according to claim 1, characterized in that, In the process gas used in the removal step, the flow rate ratio of the fluorocarbon gas to the oxygen-containing gas is 1:0.5 to 1:0.

25.

4. The deep silicon etching method according to any one of claims 1-3, characterized in that, The cycle consists of two steps, namely a first cycle step and a second cycle step. In the first cycle step, the etching step, the oxidation step, and the removal step are executed sequentially. In the second cycle step, the etching step, the removal step, and the oxidation step are executed sequentially.

5. The deep silicon etching method according to claim 4, characterized in that, After the first cycle step is completed, an intermediate oxidation step is executed, and after the intermediate oxidation step is completed, the second cycle step is executed.

6. The deep silicon etching method according to any one of claims 1-3, characterized in that, Before performing the cycle steps, a pre-removal step is first performed to remove the oxide layer on the surface of the silicon substrate (20).

7. The deep silicon etching method according to claim 6, characterized in that, The process gases used in the pre-removal step include fluorocarbon gases and oxygen-containing gases, and the carbon-fluorine ratio of the fluorocarbon gases is greater than or equal to 1 / 2.

8. The deep silicon etching method according to claim 7, characterized in that, The lower electrode power of the pre-removal step is 500~800W.

9. The deep silicon etching method according to claim 8, characterized in that, In the process gas used in the pre-removal step, the flow ratio of the fluorocarbon gas to the oxygen-containing gas is 1:0.35 to 1:0.

2.

10. A semiconductor process apparatus, characterized in that, include: The process chamber (110), the support base (120), the upper RF power supply (130), the lower RF power supply (180), and the controller, wherein, The support base (120) is used to support the silicon substrate (20); The upper radio frequency power supply (130) is used to apply upper electrode power to the process chamber (110); The lower radio frequency power supply (180) is used to apply lower electrode power to the support base (120); The controller includes a memory and a processor, the memory storing computer instructions, and the processor executing the computer instructions to perform the deep silicon etching method according to any one of claims 1-9.

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