Annular amplifying circuit

Abstract

The invention discloses an annular amplifying circuit which comprises an amplifying circuit and a switching circuit. The drain end of the first MOS tube and the drain end of the second MOS tube are connected with the gate end of the third MOS tube and the gate end of the fourth MOS tube; a resistor RB is connected in series between the drain end of the third MOS tube and the drain end of the fourth MOS tube, and the resistor RB is connected in parallel with the first amplification switch AMPLIFY1; the drain end of the third MOS tube and the drain end of the fourth MOS tube are connected with the gate end of a fifth MOS tube and the gate end of a sixth MOS tube; the gate end of the first MOS tube and the gate end of the second MOS tube are both used for inputting signals; and the drain end of the fifth MOS tube and the drain end of the sixth MOS tube are connected with an output voltage. And obvious advantages are shown in the aspects of reducing the power consumption, optimizing the phase margin and the like.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a ring amplifier circuit. Background Art

[0002] With the continuous deepening of communication technology research, the signal bandwidth has been significantly improved to several hundred megahertz, which has brought huge challenges to the performance of analog-to-digital converters (ADCs). In order to meet the needs of applications, the sampling rate of the ADC should be at least twice the signal bandwidth to meet the requirements of the Nyquist theory. In order to achieve the goals of high sampling rate, high resolution and low power consumption, researchers have proposed a hybrid ADC architecture using pipeline and register SAR (Successive Approximation Register), such as Figure 1 shown.

[0003] Accurately amplifying the residual voltage is a key requirement when building a high-performance pipeline ADC. Traditional pipeline ADCs require an amplifier with high DC gain, such as an operational transconductance amplifier (OTA), to ensure accurate voltage amplification. OTAs are used for inter-stage amplification, but they not only suffer from high power consumption and limited output swing, but also require two time-consuming stages: large-signal and small-signal settling. Furthermore, with the continuous reduction of process nodes, the DC open-loop gain of OTAs decreases, requiring more power to achieve stable closed-loop gain and phase margin. If an open-loop dynamic residual amplifier is used instead of an OTA, while the settling speed is greatly increased and there are significant advantages in achieving low power consumption and output swing, the required gain and linearity are often not met.

[0004] To address these issues related to residual amplification, researchers have proposed methods such as gain bootstrapping and open-loop dynamic amplifiers. While these gain bootstrapping structures and open-loop dynamic amplifiers improve op amp gain when used in OTAs, they require additional circuitry and consume chip area. Furthermore, these methods are subject to process limitations and are difficult to meet the demands of high-performance pipeline ADCs. Therefore, further research and innovation are needed to overcome these limitations and improve the performance of analog-to-digital converters. Summary of the Invention

[0005] In order to solve the problems of op amp power consumption and process node scaling, a ring amplifier circuit is proposed. A ring amplifier derived from a ring oscillator replaces the op amp for residual amplification, showing significant advantages in reducing power consumption and optimizing phase margin.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] According to a first aspect of an embodiment of the present application, a ring amplifier circuit is provided, comprising an amplifier circuit and a switch circuit; the amplifier circuit comprises first to sixth MOS transistors; the switch circuit comprises first to fifth switches RST1 to RST5, and first to fourth amplifier switches AMPLIFY1 to AMPLIFY4; wherein,

[0008] The drain end of the first MOS transistor and the drain end of the second MOS transistor are both connected to the gate end of the third MOS transistor and the gate end of the fourth MOS transistor;

[0009] A resistor RB is connected in series between the drain end of the third MOS transistor and the drain end of the fourth MOS transistor, and the resistor RB is connected in parallel with the first amplifying switch AMPLIFY1;

[0010] The drain end of the third MOS tube and the drain end of the fourth MOS tube are both connected to the gate end of the fifth MOS tube and the gate end of the sixth MOS tube;

[0011] The gate end of the first MOS tube and the gate end of the second MOS tube are both used for inputting signals; the drain end of the fifth MOS tube and the drain end of the sixth MOS tube are connected to the output voltage.

[0012] Optionally, the ring amplifying circuit further includes: a feedback circuit; the feedback circuit includes a compensation capacitor CC, a sampling capacitor CS, a feedback capacitor CF and a load capacitor CL;

[0013] The gate terminal of the first MOS transistor is connected to the first port of the fourth switch RST4, and is connected to the second port of the fourth switch RST4 through the drain terminal of the fifth MOS transistor; the first port of the fourth switch RST4 is connected to the third amplifying switch AMPLIFY3 through the compensation capacitor CC, and the second port of the fourth switch RST4 is connected to the output voltage through the fourth amplifying switch AMPLIFY4.

[0014] Optionally, the input signal is connected to the first port of the sampling capacitor CS through the first switch RST1 and is also connected to the second amplifying switch AMPLIFY2 at the VDAC signal terminal; the second port of the sampling capacitor CS is connected to the first port of the compensation capacitor CC through the third amplifying switch AMPLIFY3;

[0015] The VCM1 signal terminal is connected to both ends of the third amplifying switch AMPLIFY3 through the second switch RST2 and the third switch RST3 respectively.

[0016] Optionally, one end of the feedback capacitor CF is connected to the first port of the compensation capacitor CC; the other end of the feedback capacitor CF is connected to the output voltage and is connected to a fifth switch RST5 at the VCM2 signal terminal.

[0017] Optionally, when the ring amplifier circuit operates in a reset phase, all amplifier switches AMPLIFY are disconnected, all switches RST are closed, and the resistor RB is connected in series to the ring amplifier circuit.

[0018] Optionally, when the ring amplifier circuit operates in the amplification phase, all amplification switches AMPLIFY are closed, all switches RST are opened, and the resistor RB is short-circuited.

[0019] Optionally, the feedback network further includes: a load capacitor CL;

[0020] One end of the load capacitor CL is connected to the output voltage, and the other end is grounded.

[0021] Optionally, the first MOS transistor is a PMOS transistor; the second MOS transistor is an NMOS transistor; a source terminal of the first MOS transistor is connected to a power supply, and a source terminal of the second MOS transistor is grounded.

[0022] Optionally, the third MOS transistor is a PMOS transistor; the fourth MOS transistor is an NMOS transistor; the source end of the third MOS transistor is connected to a power supply, and the source end of the fourth MOS transistor is grounded.

[0023] Optionally, the fifth MOS transistor is a PMOS transistor; the sixth MOS transistor is an NMOS transistor; the source end of the fifth MOS transistor is connected to a power supply, and the source end of the sixth MOS transistor is grounded.

[0024] In summary, the embodiment of the present application provides a ring amplifier circuit, including an amplifier circuit and a switch circuit; the amplifier circuit includes first to sixth MOS transistors; the switch circuit includes first switches RST1 to fifth switches RST5, and first to fourth amplifier switches AMPLIFY1 to AMPLIFY4; wherein the drain end of the first MOS transistor and the drain end of the second MOS transistor are both connected to the gate end of the third MOS transistor and the gate end of the fourth MOS transistor; a resistor RB is connected in series between the drain end of the third MOS transistor and the drain end of the fourth MOS transistor, and the resistor RB is connected in parallel with the first amplifier switch AMPLIFY1; the drain end of the third MOS transistor and the drain end of the fourth MOS transistor are both connected to the gate end of the fifth MOS transistor and the gate end of the sixth MOS transistor; the gate end of the first MOS transistor and the gate end of the second MOS transistor are both used for input signals; the drain end of the fifth MOS transistor and the drain end of the sixth MOS transistor are connected to the output voltage. The ring amplifier derived from the ring oscillator replaces the op amp for residual amplification, showing significant advantages in reducing power consumption and optimizing phase margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0026] The structures, proportions, sizes, etc. illustrated in this specification are intended solely to complement the contents disclosed herein and to facilitate understanding and reading by persons skilled in the art. They are not intended to limit the conditions under which the present invention may be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in sizes, without affecting the efficacy and objectives of the present invention, shall remain within the scope of the technical contents disclosed herein.

[0027] Figure 1 A schematic diagram of a hybrid analog-to-digital converter ADC in the prior art;

[0028] Figure 2 A schematic diagram of a ring amplifier in the prior art;

[0029] Figure 3 It is a schematic diagram of a unipolar push-pull amplifier in the prior art;

[0030] Figure 4 A schematic diagram of the main body of the ring amplifier provided in an embodiment of the present application;

[0031] Figure 5A schematic diagram of a ring amplifier circuit provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the reset phase provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of an amplified phase provided in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of the simulation structure provided in the embodiment of the present application;

[0035] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0037] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0038] In addition, the terms "first," "second," and so on, used in this disclosure are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referenced. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this disclosure, "plurality" means at least two, such as two or three, unless otherwise specifically defined.

[0039] In the present invention, unless otherwise specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0040] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0041] Figure 2 The figure shows a classic ring amplifier, consisting of three inverters, similar to a ring oscillator. Ring amplifiers evolved from inverters. Using inverters as amplifiers is a push-pull amplifier, which can suffer from a problem: when the input voltage is low or high, either the nmos or pmos circuits may not conduct, resulting in distorted output voltage.

[0042] Figure 3 The unipolar push-pull amplifier shown is a solution. Based on a push-pull amplifier, a DC voltage is added in series with the input voltage to reduce the input voltage. This reduces the quiescent current and power consumption of the NMOS and PMOS, while also reducing the distortion range. Using multiple amplifier stages to increase gain can lead to stability issues and excessive power consumption.

[0043] To address these issues, an improved version of the ring amplifier was introduced that can utilize the scalability of technologies such as digital circuits.

[0044] The embodiment of the present application proposes a ring amplifier derived from a ring oscillator to replace the traditional operational amplifier for residual amplification. The improved ring amplifier is as follows: Figure 4 As shown in Figure 1, this design uses resistors in the second stage to accelerate amplification, resulting in a self-biased ring amplifier. This design offers high power efficiency and rail-to-rail output swing, improving the performance of analog-to-digital converters. This type of ring amplifier not only offers high stability but also low power consumption, meeting the demands of practical applications.

[0045] The ring amplifier includes first to sixth MOS transistors; the switching circuit includes first to fifth switches RST1 to RST5, and first to fourth amplifying switches AMPLIFY1 to AMPLIFY4; wherein the drain terminals of the first and second MOS transistors are both connected to the gate terminals of the third and fourth MOS transistors; a resistor RB is connected in series between the drain terminals of the third and fourth MOS transistors, and the resistor RB is connected in parallel with the first amplifying switch AMPLIFY1; the drain terminals of the third and fourth MOS transistors are both connected to the gate terminals of the fifth and sixth MOS transistors; the gate terminals of the first and second MOS transistors are both used for inputting signals; and the drain terminals of the fifth and sixth MOS transistors are connected to an output voltage.

[0046] In a possible implementation, the ring amplifier circuit further includes: a feedback circuit; the feedback circuit includes a compensation capacitor CC, a sampling capacitor CS, a feedback capacitor CF, and a load capacitor CL;

[0047] The gate terminal of the first MOS transistor is connected to the first port of the fourth switch RST4, and is connected to the second port of the fourth switch RST4 through the drain terminal of the fifth MOS transistor; the first port of the fourth switch RST4 is connected to the third amplifying switch AMPLIFY3 through the compensation capacitor CC, and the second port of the fourth switch RST4 is connected to the output voltage through the fourth amplifying switch AMPLIFY4.

[0048] In one possible implementation, the input signal is connected to the first port of the sampling capacitor CS through the first switch RST1 and is also connected to the second amplifying switch AMPLIFY2 at the VDAC signal terminal; the second port of the sampling capacitor CS is connected to the first port of the compensation capacitor CC through the third amplifying switch AMPLIFY3;

[0049] The VCM1 signal terminal is connected to both ends of the third amplifying switch AMPLIFY3 through the second switch RST2 and the third switch RST3 respectively.

[0050] In a possible implementation, one end of the feedback capacitor CF is connected to the first port of the compensation capacitor CC; the other end of the feedback capacitor CF is connected to the output voltage and to the fifth switch RST5 at the VCM2 signal terminal.

[0051] In a possible implementation, when the ring amplifier circuit operates in a reset phase, all amplifier switches AMPLIFY are disconnected, all switches RST are closed, and the resistor RB is connected in series to the ring amplifier circuit.

[0052] In a possible implementation, when the ring amplifier circuit operates in the amplification phase, all amplifier switches AMPLIFY are closed, all switches RST are opened, and the resistor RB is short-circuited.

[0053] In a possible implementation manner, the feedback network further includes: a load capacitor CL;

[0054] One end of the load capacitor CL is connected to the output voltage, and the other end is grounded.

[0055] In a possible implementation, the first MOS transistor is a PMOS transistor; the second MOS transistor is an NMOS transistor; a source terminal of the first MOS transistor is connected to a power supply, and a source terminal of the second MOS transistor is grounded.

[0056] In a possible implementation, the third MOS transistor is a PMOS transistor; the fourth MOS transistor is an NMOS transistor; a source terminal of the third MOS transistor is connected to a power supply, and a source terminal of the fourth MOS transistor is grounded.

[0057] In a possible implementation, the fifth MOS transistor is a PMOS transistor; the sixth MOS transistor is an NMOS transistor; a source terminal of the fifth MOS transistor is connected to a power supply, and a source terminal of the sixth MOS transistor is grounded.

[0058] The improved ring amplifier is divided into first-stage, second-stage and third-stage structures, and the coupling mode between them is direct coupling;

[0059] The first stage includes a push-pull amplifier PMOS tube M1 and an NMOS tube M2. The input signal VIN is connected to the G end of M1 and the G end of M2, the D end of M1 and the D end of M2 are connected, and the S end of M1 is connected to the power supply. M1 and M2 work in push-pull amplification mode.

[0060] The second stage includes a PMOS transistor M3, a resistor RB, and an NMOS transistor M4. The D terminals of M1 and M2 are connected to the G terminals of M3 and M4, and the S terminal of M3 is connected to the power supply. The D terminals of M3 and M4 are connected in series with an RB, and the resistor RB is connected in parallel with a switch. M3 and M4 operate in push-pull amplification mode.

[0061] The third stage includes a PMOS transistor M5 and an NMOS transistor M6, which work in a push-pull amplification mode. The D terminals of M3 and M4 are connected to the G terminals of M5 and M6, and the D terminals of M5 and M6 are connected to the output voltage.

[0062] In the specific application of the ring amplifier, during the amplification phase, the switch is closed, R B Short circuit, the ring amplifier settling speed is accelerated. In the reset phase, the switch is open, R B Added in series to the circuit, increases the resistor value to meet phase margin requirements.

[0063] When the input voltage is smaller or larger, the input voltage transmitted by the first-stage SAR ADC will be in an appropriate range and will not be smaller or larger.

[0064] Switched capacitor circuit based on ring amplifier such as Figure 5 As shown. The overall circuit consists of Figure 4 Ring amplifier, sampling capacitor Cs, compensation capacitor C C , feedback capacitor C f , the input signal control switch is connected to the RST switch of the VIN signal, and the RST switch is connected to the V DAC Signal AMP switch, connected to V CM Reset signal of the RST switch.

[0065] Figure 5 It shows that in the reset phase, when the negative feedback is unity, the ring amplifier used in the closed loop will be the most unstable. B It can bring better phase margin, making the ring amplifier more stable in closed-loop applications. However, if the phase margin of the ring amplifier is too large during the amplification stage, the stabilization time will be longer. B The opposite situation will occur, that is, the system establishment time is faster, but the stability is poor. Therefore, it is necessary to select the appropriate R B value to balance stability and responsiveness.

[0066] The working phase can be divided into two stages: reset and amplification. The two working stages and the proposed architecture are discussed below.

[0067] a. Reset phase as Figure 6 As shown: In the reset phase, the switch RST is in the on state and the ring amplifier is in the off state; the input and output of the amplifier are short-circuited, and the feedback factor is 1; the feedback capacitor C f The upper and lower plates are precharged to V CM ; The two plates of the compensation capacitor Cc are also precharged to V CM This is the most unstable moment of the switched capacitor circuit because the phase margin is the lowest. A relatively large set resistor value R is required. B To generate enough phase margin to meet the stability requirements.

[0068] b. Amplify the phase as Figure 7 Shown: In Figure 5 Based on the situation that the AMPLIFY switch is closed and the RST switch is open. In the amplification phase, the switch AMPLIFY is in the on state and the RST is in the off state; the capacitor C f and C C The series connection serves as a feedback loop; the feedback coefficient of the switched capacitor circuit is C S / (C S +C f ), the phase margin is much higher. If the same R B , then the speed at which the amplifier oscillates to stability will be limited.

[0069] From the above analysis, it can be concluded that in the amplification stage, a smaller bias resistor R B To obtain a shorter stabilization time. Use the switch controlled by RST to adjust R B Different resistors are required for access and short circuit, amplification state and reset state.

[0070] During the amplification phase, the AMPLIFY switch is closed and the RST switch is open. During the amplification phase, the switch is open and R BIt will be a short circuit with zero resistance, so the ring amplifier can settle faster.

[0071] During the reset phase, the AMPLIFY switch is open and the RST switch is closed. B Connect in series to the circuit to increase the resistance value to meet the phase margin requirement, reset the state R B Connected to the circuit, using R B and RST switches, the speed of the ring amplifier can be increased without instability issues.

[0072] The conclusion can be drawn well by simulating a high-speed pipeline SAR ADC based on a resistor-based self-biased ring amplifier.

[0073] Figure 8 A schematic diagram of the simulation structure is shown, where the first-stage SAR ADC is connected to a ring amplifier, and then to a second-stage SAR ADC.

[0074] The first stage of the simulation architecture consists of a 5-bit asynchronous bottom-plate sampling SAR logic, which provides the common-mode voltage for the interstage amplifier. This 5-bit asynchronous bottom-plate sampling SAR logic is a successive approximation analog-to-digital converter (ADC) that uses asynchronous timing, an effective number of 5 bits, and bottom-plate sampling. The simulated sampling rate of the proposed pipelined SAR ADC can reach 200MHz, while a conventional architecture can only achieve 160MHz under the same conditions.

[0075] The second stage is an 8-bit asynchronous top-plate sampling SAR logic, which is faster and more energy-efficient. 8-bit asynchronous bottom-plate sampling SAR logic refers to a successive approximation analog-to-digital converter with asynchronous timing, an effective number of 8 bits, and top-plate sampling technology.

[0076] Compared with the prior art, the advantages of the present invention mainly include:

[0077] 1. Reduced Power Consumption: By replacing the traditional operational transconductance amplifier (OTA) with a ring amplifier derived from a ring oscillator, the present invention significantly reduces the power consumption of the analog-to-digital converter. Ring amplifiers are known for their high power efficiency, which is particularly important in battery-powered applications.

[0078] 2. Optimizing Phase Margin: This invention utilizes a variable resistor-based self-biased ring amplifier structure, which allows for optimization of the amplifier's phase margin. This optimization ensures system stability and reduces signal distortion, thereby improving the overall performance of the analog-to-digital converter.

[0079] 3. Improved settling speed: The optimized ring amplifier has a faster settling speed, which means that the analog-to-digital converter can respond more quickly to changes in the input signal. This is crucial for applications that require high-speed data processing, such as 5G communications.

[0080] 4. Rail-to-rail output swing: The design of the ring amplifier also achieves rail-to-rail output swing, which expands the output dynamic range and improves the linearity of the signal.

[0081] 5. Reduced dependence on process: Compared with some existing technologies that are subject to greater process restrictions, the ring amplifier structure of the present invention is less sensitive to process, and therefore can maintain relatively stable performance under different process conditions.

[0082] 6. Promote technological progress: The implementation of this invention not only solves the technical challenges faced by analog-to-digital converters in the 5G era, but also provides new ideas and directions for the design of analog-to-digital converters, and promotes technological progress in related fields.

[0083] In summary, the present invention provides a ring amplifier circuit by introducing an innovative ring amplifier structure, comprising an amplifier circuit and a switch circuit; the amplifier circuit comprises first to sixth MOS transistors; the switch circuit comprises first switches RST1 to fifth switches RST5, and first to fourth amplifier switches AMPLIFY1 to AMPLIFY4; wherein the drain end of the first MOS transistor and the drain end of the second MOS transistor are both connected to the gate end of the third MOS transistor and the gate end of the fourth MOS transistor; a resistor RB is connected in series between the drain end of the third MOS transistor and the drain end of the fourth MOS transistor, and the resistor RB is connected in parallel with the first amplifier switch AMPLIFY1; the drain end of the third MOS transistor and the drain end of the fourth MOS transistor are both connected to the gate end of the fifth MOS transistor and the gate end of the sixth MOS transistor; the gate end of the first MOS transistor and the gate end of the second MOS transistor are both used for input signals; the drain end of the fifth MOS transistor and the drain end of the sixth MOS transistor are connected to the output voltage. The invention has shown significant advantages in reducing power consumption, optimizing phase margin, improving settling speed, expanding output dynamic range, reducing dependence on process, and promoting technological progress.

[0084] It should be noted that:

[0085] The algorithms and displays provided herein are not inherently related to any particular computer, virtual device, or other device. Various general-purpose devices may also be used in conjunction with the teachings herein. Based on the above description, it is apparent that the structure required for constructing such devices is suitable. In addition, the present application is not directed to any specific programming language. It should be understood that various programming languages ​​may be utilized to implement the present application described herein, and the above description of specific languages ​​is provided for the purpose of disclosing the best mode of implementation of the present application.

[0086] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description.

[0087] Similarly, it is to be understood that the mechanical details of the various features of the application that are described in the exemplary embodiments above are sometimes interchangeable with other mechanical details of the various features of the application, and that the various embodiments of the application have not been described with this level of particularity to limit the protection afforded to this application. Accordingly, the protection afforded applicant is to be governed by the following claims and their equivalents.

[0088] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adapted and placed in one or more apparatuses other than the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and further can be divided into more sub-modules or sub-units or sub-components. Any combination of all the features disclosed in the specification (including the accompanying claims, abstract and drawings), and any method or apparatus so disclosed, can be used in any combination, except that at least some of such features and / or processes or units are mutually exclusive, unless otherwise explicitly stated. Each feature disclosed in the specification (including the accompanying claims, abstract and drawings) can be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

[0089] Further, those skilled in the art will appreciate that a combination of features of different embodiments can be meant to be within the scope of the application and form a different embodiment. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0090] The various component embodiments of the present application can be implemented in hardware, or implemented in a software module running on one or more processors, or implemented in a combination thereof. Those skilled in the art will appreciate that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the creation device of the virtual machine according to an embodiment of the present application. The application can also be implemented as a part or all of the equipment or device program (for example, computer program and computer program product) for performing the method described herein. Such a program realizing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0091] It should be noted that the above embodiments illustrate rather than limit the present application, and that a person skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbols placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of appropriately programmed computers. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0092] The above description is merely a preferred embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0093] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A ring amplifier circuit, characterized in that: It includes an amplifier circuit and a switch circuit; the amplifier circuit includes first to sixth MOS transistors; the switch circuit includes first to fifth switches RST1 to RST5, and first to fourth amplifier switches AMPLIFY1 to AMPLIFY4; wherein, The drain end of the first MOS transistor and the drain end of the second MOS transistor are both connected to the gate end of the third MOS transistor and the gate end of the fourth MOS transistor; A resistor R is connected in series between the drain end of the third MOS tube and the drain end of the fourth MOS tube. B , the resistor R B connected in parallel with the first amplifying switch AMPLIFY1; The drain end of the third MOS tube and the drain end of the fourth MOS tube are both connected to the gate end of the fifth MOS tube and the gate end of the sixth MOS tube; The gate end of the first MOS tube and the gate end of the second MOS tube are both used for inputting signals; the drain end of the fifth MOS tube and the drain end of the sixth MOS tube are connected to the output voltage.

2. The ring amplifier circuit according to claim 1, wherein: The ring amplifier circuit further includes: a feedback circuit; the feedback circuit includes a compensation capacitor C C , sampling capacitor C S , feedback capacitor C F and load capacitance C L ; The gate end of the first MOS transistor is connected to the first port of the fourth switch RST4, and is connected to the second port of the fourth switch RST4 through the drain end of the fifth MOS transistor; the first port of the fourth switch RST4 is connected to the compensation capacitor C C The second port of the fourth switch RST4 is connected to the third amplifying switch AMPLIFY3 , and the second port of the fourth switch RST4 is connected to the output voltage through the fourth amplifying switch AMPLIFY4 .

3. The ring amplifier circuit according to claim 2, wherein: The input signal is connected to the sampling capacitor C through the first switch RST1 S The first port is also connected to V DAC The second amplifying switch AMPLIFY2 at the signal end; the sampling capacitor C S The second port is connected to the compensation capacitor C through the third amplifying switch AMPLIFY3 C The first port; The VCM1 signal terminal is connected to both ends of the third amplifying switch AMPLIFY3 through the second switch RST2 and the third switch RST3 respectively.

4. The ring amplifier circuit according to claim 3, wherein: The feedback capacitor C F One end is connected to the compensation capacitor C C The first port of the feedback capacitor C F The other end is connected to the output voltage and is connected to the fifth switch RST5 of the VCM2 signal terminal.

5. The ring amplifier circuit according to any one of claims 1 to 4, wherein: When the ring amplifier circuit operates in the reset phase, all amplifier switches AMPLIFY are disconnected, all switches RST are closed, and the resistor R B Connected in series to the ring amplifier circuit.

6. The ring amplifier circuit according to any one of claims 1 to 4, characterized in that: When the ring amplifier circuit operates in the amplification phase, all amplifier switches AMPLIFY are closed, all switches RST are open, and the resistor R B Short circuit.

7. The ring amplifier circuit according to claim 4, wherein: The feedback network also includes: load capacitor C L ; The load capacitance C L One end is connected to the output voltage, and the other end is grounded.

8. The ring amplifier circuit according to claim 1, wherein: The first MOS transistor is a PMOS transistor; the second MOS transistor is an NMOS transistor; a source terminal of the first MOS transistor is connected to a power supply, and a source terminal of the second MOS transistor is grounded.

9. The ring amplifier circuit according to claim 1, wherein: The third MOS tube is a PMOS tube; the fourth MOS tube is an NMOS tube; the source end of the third MOS tube is connected to a power supply, and the source end of the fourth MOS tube is grounded.

10. The ring amplifier circuit according to claim 1, wherein: The fifth MOS transistor is a PMOS transistor; the sixth MOS transistor is an NMOS transistor; a source terminal of the fifth MOS transistor is connected to a power supply, and a source terminal of the sixth MOS transistor is grounded.

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