Vacuum ultraviolet light source chip, preparation method thereof and miniature photoionization detector

Abstract

The embodiment of the invention provides a vacuum ultraviolet light source chip, a preparation method of the vacuum ultraviolet light source chip and a miniature photoionization detector, and belongs to the field of photoionization detectors. The vacuum ultraviolet light source chip is applied to a photoionization detector and comprises a first substrate, a first silicon electrode layer, a dielectric barrier layer and an ultraviolet light transmitting cover plate, the first silicon electrode layer is arranged on the first substrate and comprises a first excitation electrode and a second excitation electrode which are arranged at an interval; the dielectric barrier layer at least partially covers the first excitation electrode and the second excitation electrode; the ultraviolet-light-transmitting cover plate is arranged on the side, away from the first silicon electrode layer, of the dielectric barrier layer, a gas cavity is formed between the ultraviolet-light-transmitting cover plate and the first silicon electrode layer, and the gas cavity is filled with first gas. According to the invention, high integration, miniaturization and low cost of the vacuum ultraviolet light source chip and the PID can be realized, the service life of the vacuum ultraviolet light source chip and the PID can be prolonged, and the reliability of the vacuum ultraviolet light source chip and the PID can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of photo ionization detectors, and particularly relates to a vacuum ultraviolet light source chip, a preparation method thereof and a micro photo ionization detector. BACKGROUND

[0002] A photo ionization detector (PID) uses ultraviolet light generated by an ultraviolet light source with a specific ionization energy to ionize volatile organic compounds (VOCs), and the concentration of VOCs can be detected by measuring the ionization current. The PID is widely used in the field of gas detection due to its high precision, fast response and wide detection range. The ultraviolet light source is the core component of the PID.

[0003] In related technologies, the ultraviolet light source includes a glass shell, an ultraviolet light-transmitting cover plate and two excitation electrodes. The glass shell has a gas cavity, the gas cavity is filled with a gas used for being excited to radiate ultraviolet light, the glass shell is bonded with the ultraviolet light-transmitting cover plate, and the two excitation electrodes are respectively arranged on the two sides of the outer wall of the glass shell.

[0004] However, arranging the gas cavity in the glass shell and arranging the two excitation electrodes on the two sides of the outer wall of the glass shell will affect the integration of the ultraviolet light source, resulting in a large size and high cost of the ultraviolet light source and the PID. SUMMARY

[0005] The present disclosure provides a vacuum ultraviolet light source chip, a preparation method thereof and a micro photo ionization detector, which can realize high integration, miniaturization and low cost of the vacuum ultraviolet light source chip and the PID, and can improve the service life and reliability of the vacuum ultraviolet light source chip and the PID. The technical solution at least includes the following solutions: In one aspect, a vacuum ultraviolet light source chip is provided, which is applied to a photo ionization detector, and includes a first substrate, a first silicon electrode layer, a dielectric barrier layer and an ultraviolet light-transmitting cover plate. The first silicon electrode layer is arranged on the first substrate, and the first silicon electrode layer includes a first excitation electrode and a second excitation electrode arranged at intervals. At least part of the dielectric barrier layer covers the first excitation electrode and the second excitation electrode. The ultraviolet light-transmitting cover plate is arranged on a side of the dielectric barrier layer away from the first silicon electrode layer, and a gas cavity is formed between the ultraviolet light-transmitting cover plate and the first silicon electrode layer, and the gas cavity is filled with a first gas. The first gas is used for being excited to radiate ultraviolet light, and the dielectric barrier layer is used for isolating the first gas from the first excitation electrode and the second excitation electrode.

[0006] Optionally, the first excitation electrode and the second excitation electrode are interdigital electrodes.

[0007] Optionally, the first silicon electrode layer further comprises a first connecting portion, a second connecting portion, an isolation portion and a peripheral portion, the first connecting portion is connected with the first excitation electrode, the second connecting portion is connected with the second excitation electrode, the first connecting portion and the second connecting portion are used for introducing external electrical signals, the isolation portion is located at the periphery of the first excitation electrode and the second excitation electrode, the peripheral portion is located at the periphery of the first connecting portion, the second connecting portion and the isolation portion, an isolation groove is formed between the first connecting portion and the isolation portion, between the second connecting portion and the isolation portion, the isolation groove is filled with a first insulating layer and is filled flat by the first insulating layer; the outer contour of the orthographic projection of the ultraviolet light-transmitting cover plate on the first substrate is located inside the sum of the orthographic projection of the isolation portion, the isolation groove, the first connecting portion and the second connecting portion on the first substrate, and intersects with the orthographic projection of the first connecting portion and the second connecting portion on the first substrate.

[0008] Optionally, the first substrate comprises a first silicon substrate and a second insulating layer, the second insulating layer is located between the first silicon substrate and the first silicon electrode layer.

[0009] Optionally, the vacuum ultraviolet light source chip further comprises a stress matching ring, the stress matching ring is arranged between the ultraviolet light-transmitting cover plate and the dielectric barrier layer, and is used for matching the thermal expansion coefficient of the ultraviolet light-transmitting cover plate; the dielectric barrier layer, the stress matching ring and the ultraviolet light-transmitting cover plate are fixedly connected through alloy solder.

[0010] Optionally, the gas pressure of the first gas is 10 -2 Pa to 10 4 Pa; the first gas comprises at least one of He, Ne, Ar, Kr, Xe, Rn, H2, N2, O2, H2O, CO2, Cl2, CH4, CF4, NH3, F2 and air; or, the first gas comprises one of the following quasi-molecules: Ar2, Kr2, Xe2, ArF, XeF, XeCl, F2, Ar2Cl, Kr2F and Xe2Cl.

[0011] Optionally, the gas pressure of the first gas is 10 -8 Pa to 10 4 Pa; the first gas comprises at least one of Rb, Cs, Sr, Yb, Hg, Sn and Th.

[0012] In another aspect, a method for manufacturing a vacuum ultraviolet light source chip is provided, the vacuum ultraviolet light source chip being applied to a photo-ionization detector, and the method comprises: forming a first silicon electrode layer on a first substrate, the first silicon electrode layer comprising a first excitation electrode and a second excitation electrode arranged at intervals; forming a dielectric barrier layer on the first silicon electrode layer, at least part of the dielectric barrier layer covering the first excitation electrode and the second excitation electrode; and fixedly connecting the dielectric barrier layer with a transparent ultraviolet light cover plate, the transparent ultraviolet light cover plate being arranged on a side of the dielectric barrier layer away from the first silicon electrode layer, a gas cavity being formed between the transparent ultraviolet light cover plate and the dielectric barrier layer, and the gas cavity being filled with a first gas, wherein the first gas is used to be excited to radiate ultraviolet light, and the dielectric barrier layer is used to isolate the first gas from the first excitation electrode and the second excitation electrode.

[0013] In yet another aspect, a micro photo-ionization detector is provided, comprising any one of the aforementioned vacuum ultraviolet light source chips and a micro ionization chamber structure, the micro ionization chamber structure being arranged on a light emitting side of the vacuum ultraviolet light source chip.

[0014] Optionally, the micro ionization chamber structure comprises a second substrate and a second silicon electrode layer, the second silicon electrode layer being arranged on the second substrate and located between the transparent ultraviolet light cover plate and the second substrate, the second silicon electrode layer comprising a first electrode and a second electrode arranged at intervals, the first electrode and the second electrode being serpentine interdigital electrodes, a serpentine groove being formed between the first electrode and the second electrode, and a first opening and a second opening being arranged at two ends of the serpentine groove, respectively.

[0015] The technical solutions provided by the embodiments of the present disclosure have at least the following beneficial effects: In the embodiments of the present disclosure, by arranging the first silicon electrode layer comprising the first excitation electrode and the second excitation electrode on the first substrate, and forming the gas cavity between the transparent ultraviolet light cover plate and the first silicon electrode layer, that is, by integrally arranging the first excitation electrode and the second excitation electrode in the gas cavity, the integration degree of the vacuum ultraviolet light source chip can be improved, which is conducive to realizing high integration, miniaturization and low cost of the vacuum ultraviolet light source chip and the PID. Moreover, the dielectric barrier layer covers the first excitation electrode and the second excitation electrode, the dielectric barrier layer can isolate the first gas from the first excitation electrode and the second excitation electrode, so as to reduce the loss of the first excitation electrode and the second excitation electrode caused by the plasma in the process of exciting the first gas to radiate ultraviolet light, thereby improving the service life and reliability of the vacuum ultraviolet light source chip and the PID. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0017] Figure 1 is a structural schematic diagram of a vacuum ultraviolet light source chip provided by an embodiment of the present disclosure; Figure 2 is a top view of a vacuum ultraviolet light source chip provided by an embodiment of the present disclosure; Figure 3 is a structural schematic diagram of another vacuum ultraviolet light source chip provided by an embodiment of the present disclosure; Figure 4 is a flowchart of a preparation method of a vacuum ultraviolet light source chip provided by an embodiment of the present disclosure; Figures 5 to 14 is a structural schematic diagram of a vacuum ultraviolet light source chip in a preparation process in Embodiment One; Figure 15 is a structural schematic diagram of a micro ionization detector provided by an embodiment of the present disclosure; Figure 16 is a structural schematic diagram of a micro ionization chamber structure provided by an embodiment of the present disclosure; Figure 17 is a top view of a micro ionization chamber structure provided by an embodiment of the present disclosure; Figures 18 to 19 is a structural schematic diagram of a micro ionization chamber structure in a preparation process provided by an embodiment of the present disclosure.

[0018] Reference signs: 1: vacuum ultraviolet light source chip; 2: micro ionization chamber structure; 10: first substrate; 11: first silicon substrate; 11': first silicon substrate material layer; 12: second insulating layer; 12': second insulating material layer; 20: first silicon electrode layer; 20': first silicon electrode material layer; 201: isolation groove; 21: first excitation electrode; 22: second excitation electrode; 23: first connecting part; 24: second connecting part; 25: isolation part; 26: peripheral part; 30: dielectric barrier layer; 30': dielectric barrier material layer; 40: ultraviolet light transparent cover plate; 41: recess cavity; 42: gas cavity; 50: first insulating layer; 50': first insulating material layer; 60: first pad; 61: second pad; 70: stress matching ring; 80: first metal connecting ring; 81: second metal connecting ring; 82: third metal connecting ring; 83: fourth metal connecting ring; 85: alloy solder; 90: second substrate; 901: second silicon substrate; 902: third insulating layer; 91: second silicon electrode layer; 91': second silicon electrode material layer; 911: first electrode; 912: second electrode; 913: serpentine groove; 914: first opening; 915: second opening; 92: third pad; 93: fourth pad. DETAILED DESCRIPTION

[0019] Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meanings as understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first", "second", "third", and the like used in the specification and claims of this disclosure do not necessarily denote any ordinal, quantity, or importance, but merely are used to distinguish different components. Similarly, the terms "one", "a", or "an" do not denote a quantity of at least one, but rather are understood to mean that at least one of something is present. The terms "comprises", "comprising", "includes", "including" and the like can mean encompassing, containing, or accommodating, but do not necessarily exclude other elements or articles. The terms "connected", "coupled", or the like, can not necessarily denote a physical or mechanical connection or attachment, but can include an electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like, are used only to denote relative positions for the purpose of illustration and description and can be reversed when the described object is turned over. A and / or B means that there are three cases: A, B, and A and B.

[0020] In order to make the purpose, technical solutions and advantages of the disclosure clearer, the following will further describe the embodiments of the disclosure in conjunction with the drawings.

[0021] Embodiment one: Figure 1 is a structural schematic diagram of a vacuum ultraviolet light source chip provided by an embodiment of the disclosure.Figure 2 is a top view of a vacuum ultraviolet light source chip provided by an embodiment of the present disclosure. Figure 1 may represent Figure 2 a cross-sectional structure schematic view at a cross-sectional line AA. The vacuum ultraviolet light source chip is applied to a PID, see Figure 1 and Figure 2 The vacuum ultraviolet light source chip includes a first substrate 10, a first silicon electrode layer 20, a dielectric barrier layer 30, and an ultraviolet light-transmissive cover plate 40. The first silicon electrode layer 20 is disposed on the first substrate 10, and the first silicon electrode layer 20 includes a first excitation electrode 21 and a second excitation electrode 22 arranged at intervals. At least part of the dielectric barrier layer 30 covers the first excitation electrode 21 and the second excitation electrode 22. The ultraviolet light-transmissive cover plate 40 is disposed on a side of the dielectric barrier layer 30 away from the first silicon electrode layer 20, and a gas cavity 42 is formed between the ultraviolet light-transmissive cover plate 40 and the first silicon electrode layer 20, and the gas cavity 42 is filled with a first gas. The first gas is used to be excited to radiate ultraviolet light, and the dielectric barrier layer 30 is used to isolate the first gas from the first excitation electrode 21 and the second excitation electrode 22.

[0022] In an embodiment of the present disclosure, by disposing the first silicon electrode layer 20 including the first excitation electrode 21 and the second excitation electrode 22 on the first substrate 10, the gas cavity 42 is formed between the ultraviolet light-transmissive cover plate 40 and the first silicon electrode layer 20, that is, the first excitation electrode 21 and the second excitation electrode 22 are integrally disposed in the gas cavity 42, so that the integration of the vacuum ultraviolet light source chip can be improved, which is conducive to realizing high integration, miniaturization, and low cost of the vacuum ultraviolet light source chip and the PID. Moreover, the dielectric barrier layer 30 covers the first excitation electrode 21 and the second excitation electrode 22, and the dielectric barrier layer 30 can isolate the first gas from the first excitation electrode 21 and the second excitation electrode 22, so as to reduce the loss of the first excitation electrode 21 and the second excitation electrode 22 caused by plasma in the process of exciting the first gas to radiate ultraviolet light, thereby improving the service life and reliability of the vacuum ultraviolet light source chip and the PID.

[0023] Optionally, the first substrate 10 includes a first silicon substrate 11 and a second insulating layer 12, and the second insulating layer 12 is located between the first silicon substrate 11 and the first silicon electrode layer 20. In this way, the first substrate 10 and the first silicon electrode layer 20 are facilitated to be batch-produced by a Silicon-On-Insulator (SOI) wafer, which is conducive to further realizing miniaturization of the vacuum ultraviolet light source chip, and can improve production efficiency and reduce production cost.

[0024] Optionally, the material of the first silicon substrate 11 can be high-resistance silicon in the SOI wafer, and the material of the first silicon electrode layer 20 can be low-resistance silicon in the SOI wafer.

[0025] Exemplarily, the thickness of the first silicon substrate 11 is greater than the thickness of the first silicon electrode layer 20. For example, the thickness of the first silicon substrate 11 can be 500 μm, and the thickness of the first silicon electrode layer 20 can be 100 μm.

[0026] Exemplarily, the material of the second insulating layer 12 can be silicon oxide.

[0027] Exemplarily, the thickness of the second insulating layer 12 can be 2 μm.

[0028] Optionally, the first excitation electrode 21 and the second excitation electrode 22 are interdigital electrodes. That is, the first excitation electrode 21 and the second excitation electrode 22 are arranged in a plurality of pairs of comb-tooth structures. In this way, when a voltage is applied to the first excitation electrode 21 and the second excitation electrode 22, the electric field strength and the electron energy can be improved, so that the first gas in the gas cavity 42 can be better excited, and the density of the generated plasma is higher, which is beneficial to improve the ultraviolet light intensity of the vacuum ultraviolet light source chip.

[0029] It should be noted that, Figure 1 or Figure 2 The number of pairs of the interdigital electrodes in the above description is only an example and does not represent a limitation on the number of pairs.

[0030] Optionally, the minimum spacing between the first excitation electrode 21 and the second excitation electrode 22 is greater than 5 μm. Here, the minimum spacing refers to the minimum value of the distance between the first excitation electrode 21 and the second excitation electrode 22. In this way, the gap between the first excitation electrode 21 and the second excitation electrode 22 can be ensured to be large, so that the first gas in the gas cavity 42 can be filled between the first excitation electrode 21 and the second excitation electrode 22 and be better excited.

[0031] Exemplarily, the minimum spacing between the first excitation electrode 21 and the second excitation electrode 22 can be 6 μm, 7 μm, or 8 μm, etc.

[0032] Exemplarily, the first silicon electrode layer 20 further comprises a first connecting portion 23, a second connecting portion 24, an isolation portion 25 and a peripheral portion 26. The first connecting portion 23 is connected with the first excitation electrode 21, the second connecting portion 24 is connected with the second excitation electrode 22, the first connecting portion 23 and the second connecting portion 24 are used for introducing external electrical signals, the isolation portion 25 is located at the periphery of the first excitation electrode 21 and the second excitation electrode 22, the peripheral portion 26 is located at the periphery of the first connecting portion 23, the second connecting portion 24 and the isolation portion 25, and an isolation groove 201 is formed between the first connecting portion 23 and the isolation portion 25 and between the second connecting portion 24 and the isolation portion 25, the isolation groove 201 is filled with the first insulating layer 50 and is filled flat by the first insulating layer 50. The outer contour of the orthographic projection of the ultraviolet light transparent cover plate 40 on the first substrate 10 is located inside the sum of the orthographic projections of the isolation portion 25, the isolation groove 201, the first connecting portion 23 and the second connecting portion 24 on the first substrate 10, and intersects with the orthographic projections of the first connecting portion 23 and the second connecting portion 24 on the first substrate 10. The electrical isolation between the first excitation electrode 21 and the second excitation electrode 22 can be ensured through the isolation groove 201, the isolation groove 201 being filled flat by the first insulating layer 50 not only can further play a role in electrical isolation, but also can reduce the probability of gas leakage at the isolation groove 201, ensure that the air tightness of the gas cavity 42 is good, and at the same time, the isolation groove 201 and the first insulating layer 50 are conducive to reducing the residual stress in the ultraviolet light transparent cover plate 40, enhancing the service life and practicality of the vacuum ultraviolet light source chip.

[0033] It should be noted that, Figure 1 and Figure 2 In the above embodiment, the isolation portion 25 is connected with the peripheral portion 26, and the isolation portion 25 and the isolation groove 201 are arranged in an approximately annular structure around the first excitation electrode 21 and the second excitation electrode 22. In other embodiments, the isolation portion 25 and the peripheral portion 26 can also be arranged separately, and the present disclosure does not limit this.

[0034] In other embodiments, the first insulating layer 50 can also fill at least one of the gap between the first excitation electrode 21 and the isolation portion 25, the gap between the second excitation electrode 22 and the isolation portion 25, the gap between the first connecting portion 23 and the peripheral portion 26, and the gap between the second connecting portion 24 and the peripheral portion 26, and the present disclosure does not limit this.

[0035] Exemplarily, the material of the first insulating layer 50 can be silicon oxide.

[0036] Exemplarily, the material of the dielectric barrier layer 30 can be silicon oxide. The silicon oxide can effectively isolate the first gas from the first excitation electrode 21 and the second excitation electrode 22, thereby effectively reducing the loss of the first excitation electrode 21 and the second excitation electrode 22 caused by the plasma in the process of exciting the first gas to radiate ultraviolet light.

[0037] Optionally, the thickness of the dielectric barrier layer 30 is greater than 100 nm. In this way, the thickness of the dielectric barrier layer 30 can be ensured to be large, and the isolation effect is good.

[0038] Illustratively, the thickness of the dielectric barrier layer 30 can be 150 nm, 200 nm, or 250 nm, etc.

[0039] Illustratively, the vacuum ultraviolet light source chip further includes a first pad 60 and a second pad 61, the first pad 60 and the second pad 61 are located outside the gas cavity 42 and are arranged on the side of the dielectric barrier layer 30 away from the first silicon electrode layer 20, the first pad 60 and the second pad 61 are insulated from each other, the first pad 60 penetrates the dielectric barrier layer 30 and is connected with the first connecting part 23, and the second pad 61 penetrates the dielectric barrier layer 30 and is connected with the second connecting part 24. Through the first pad 60 and the second pad 61, external electrical signals can be introduced into the first excitation electrode 21 and the second excitation electrode 22, respectively, from the side where the ultraviolet light transparent cover plate 40 is located, and the air tightness of the gas cavity 42 is not affected.

[0040] Illustratively, the material of the first pad 60 and the second pad 61 can be a metal material. For example, the material of the first pad 60 and the second pad 61 can include at least one of gold and aluminum.

[0041] In the embodiments of the present disclosure, the first insulating layer 50 is also located on the surface of the first silicon electrode layer 20 away from the first substrate 10, the dielectric barrier layer 30 is located on the side of the first insulating layer 50 away from the first substrate 10 and covers the side walls of the first excitation electrode 21 and the second excitation electrode 22, the first pad 60 penetrates the dielectric barrier layer 30 and the first insulating layer 50 and is connected with the first connecting part 23, and the second pad 61 penetrates the dielectric barrier layer 30 and the first insulating layer 50 and is connected with the second connecting part 24.

[0042] Optionally, the vacuum ultraviolet light source chip further comprises a stress matching ring 70, which is arranged between the ultraviolet light transparent cover plate 40 and the dielectric barrier layer 30, and is used to match the thermal expansion coefficient of the ultraviolet light transparent cover plate 40. The dielectric barrier layer 30, the stress matching ring 70 and the ultraviolet light transparent cover plate 40 are fixedly connected by the alloy solder 85. By arranging the stress matching ring 70, the residual stress of the fixed connection between the ultraviolet light transparent cover plate 40 and the dielectric barrier layer 30 can be effectively reduced, so as to reduce the probability of rupture of the ultraviolet light transparent cover plate 40 due to the difference in thermal expansion coefficient, and improve the reliability of the vacuum ultraviolet light source chip. Compared with conventional organic glue and glass solder and other materials, the alloy solder 85 has higher welding strength and air tightness, and will not age or degrade under ultraviolet light irradiation. The fixed connection of the dielectric barrier layer 30, the stress matching ring 70 and the ultraviolet light transparent cover plate 40 by the alloy solder 85 can reduce the probability of changes in the gas pressure, properties and composition of the first gas and the attenuation of the ultraviolet light intensity due to the leakage of the gas cavity 42, so as to effectively ensure the service life and reliability of the vacuum ultraviolet light source chip.

[0043] Optionally, the material of the stress matching ring 70 can be 4J49 Kovar alloy or 4J50 Kovar alloy.

[0044] Optionally, the vacuum ultraviolet light source chip further comprises a first metal connecting ring 80, a second metal connecting ring 81, a third metal connecting ring 82 and a fourth metal connecting ring 83. The first metal connecting ring 80 is arranged on the surface of the dielectric barrier layer 30 away from the first silicon electrode layer 20. The second metal connecting ring 81 is arranged on the periphery of the gas cavity 42 and on the surface of the ultraviolet light transparent cover plate 40 close to the first silicon electrode layer 20. The third metal connecting ring 82 is arranged on the surface of the stress matching ring 70 close to the ultraviolet light transparent cover plate 40. The fourth metal connecting ring 83 is arranged on the surface of the stress matching ring 70 close to the dielectric barrier layer 30. The first metal connecting ring 80 and the third metal connecting ring 82 are fixedly connected by the alloy solder 85, and the second metal connecting ring 81 and the fourth metal connecting ring 83 are fixedly connected by the alloy solder 85.

[0045] Optionally, the material of the first metal connecting ring 80, the second metal connecting ring 81, the third metal connecting ring 82 and the fourth metal connecting ring 83 can include at least one of gold and tin.

[0046] Optionally, the material of the alloy solder 85 can be indium-tin alloy. In this way, the strength of the fixed connection of the ultraviolet light transparent cover plate 40 is high, and the air tightness of the gas cavity 42 is good, while the indium-tin alloy is not easy to age under ultraviolet light irradiation, so as to improve the service life and reliability of the vacuum ultraviolet light source chip.

[0047] In other embodiments, the difference between the average coefficient of thermal expansion of the dielectric barrier layer 30, the first silicon electrode layer 20 and the first substrate 10 and the coefficient of thermal expansion of the UV transparent cover plate 40 is less than 10 -6 / K. In this case, the stress matching ring 70 can not be provided, and the UV transparent cover plate 40 can be directly connected to the dielectric barrier layer 30 by a bonding process or fixedly connected by an alloy solder 85. For example, the UV transparent cover plate 40 and the dielectric barrier layer 30 can be bonded by an indium-tin alloy.

[0048] For example, the gas cavity 42 has a leakage rate of less than or equal to 10 -9 atm·cc / s.

[0049] In one possible implementation, the gas pressure of the first gas is 10 -2 Pa to 10 4 Pa. The first gas includes at least one of He, Ne, Ar, Kr, Xe, Rn, H2, N2, O2, H2O, CO2, Cl2, CH4, CF4, NH3, F2 and air; or, the first gas includes one of the following excimers: Ar2, Kr2, Xe2, ArF, XeF, XeCl, F2, Ar2Cl, Kr2F and Xe2Cl. Under this gas pressure, He, Ne, Ar, Kr, Xe, Rn, H2, N2, O2, H2O, CO2, Cl2, CH4, CF4, NH3, F2 and air can be excited to a plasma state to radiate ultraviolet light. The excimers Ar2, Kr2, Xe2, ArF, XeF, XeCl, F2, Ar2Cl, Kr2F and Xe2Cl are unstable associates that are combined into molecules in an excited state and dissociated into atoms in a ground state, and can also be excited to radiate ultraviolet light.

[0050] In another possible implementation, the gas pressure of the first gas is 10 -8 Pa to 10 4 Pa. The first gas includes at least one of Rb, Cs, Sr, Yb, Hg, Sn and Th. Rb, Cs, Sr, Yb, Hg, Sn and Th are solid at room temperature and become gas after being heated, and under this gas pressure, these gases can also be excited to radiate ultraviolet light.

[0051] For example, the vacuum ultraviolet light source chip can radiate vacuum ultraviolet light with a wavelength of 100 nm or more outward.

[0052] Optionally, the side of the ultraviolet light transparent cover plate 40 close to the first silicon electrode layer 20 has a concave cavity 41. The concave cavity 41 is configured to increase the volume of the gas cavity 42. In other embodiments, the ultraviolet light transparent cover plate 40 can also be a flat plate with uniform thickness, and the volume of the gas cavity 42 can be ensured by stress matching ring 70 and alloy solder 85, etc., which are not limited in the present disclosure.

[0053] Optionally, the material of the ultraviolet light transparent cover plate 40 includes at least one of lithium fluoride, magnesium fluoride, calcium fluoride, barium fluoride, strontium fluoride, and aluminum oxide. These materials are conducive to transmitting at least part of the ultraviolet light with a wavelength of 100-200 nm. For example, the material of the ultraviolet light transparent cover plate 40 can be magnesium fluoride; or, the material of the ultraviolet light transparent cover plate 40 can be a multi-layer composite material composed of two or more of lithium fluoride, magnesium fluoride, calcium fluoride, barium fluoride, strontium fluoride, and aluminum oxide; or, the material of the ultraviolet light transparent cover plate 40 can be a doped material based on at least one of lithium fluoride, magnesium fluoride, calcium fluoride, barium fluoride, strontium fluoride, and aluminum oxide; or, the material of the ultraviolet light transparent cover plate 40 can be a surface waterproof modification material based on at least one of lithium fluoride, magnesium fluoride, calcium fluoride, barium fluoride, strontium fluoride, and aluminum oxide.

[0054] Embodiment Two Figure 3 is another schematic structural diagram of a vacuum ultraviolet light source chip provided by an embodiment of the present disclosure. As shown in Figure 3 Embodiment Two and the arrangement of each structure in Embodiment One are the same, and the difference between Embodiment Two and Embodiment One is that the material of the dielectric barrier layer 30 is different. In Embodiment Two, the material of the dielectric barrier layer 30 is silicon nitride.

[0055] Figure 4 is a flowchart of a preparation method of a vacuum ultraviolet light source chip provided by an embodiment of the present disclosure. The vacuum ultraviolet light source chip is applied to a PID, as shown in Figure 4 The preparation method includes: In step S101, a first silicon electrode layer is formed on a first substrate.

[0056] The first silicon electrode layer includes a first excitation electrode and a second excitation electrode arranged at intervals.

[0057] In step S102, a dielectric barrier layer is formed on the first silicon electrode layer.

[0058] At least part of the dielectric barrier layer covers the first excitation electrode and the second excitation electrode.

[0059] In step S103, the dielectric barrier layer is fixedly connected with an ultraviolet light transparent cover plate.

[0060] An ultraviolet light-transmitting cover plate is arranged on a side of the dielectric barrier layer away from the first silicon electrode layer, and a gas cavity is formed between the ultraviolet light-transmitting cover plate and the dielectric barrier layer, and the gas cavity is filled with a first gas, wherein the first gas is used to be excited to radiate ultraviolet light, and the dielectric barrier layer is used to isolate the first gas from the first excitation electrode and the second excitation electrode.

[0061] It should be noted that the preparation method embodiments are based on the same inventive concept as the above-mentioned embodiments one to two, and the beneficial effects of the embodiments of the present disclosure can be seen from the above-mentioned embodiments one to two, which will not be repeated here.

[0062] Figures 5 to 14 is a structural schematic diagram of the vacuum ultraviolet light source chip in the preparation process of embodiment one. Referring to Figures 1 to 2 and Figures 5 to 14 , the preparation method of the vacuum ultraviolet light source chip in embodiment one can include the following steps: Firstly, as shown in Figure 5 , an SOI wafer is provided.

[0063] The SOI wafer includes a first silicon substrate 11, a second insulating layer 12 and a first silicon electrode material layer 20' stacked in sequence. The first silicon substrate 11 and the second insulating layer 12 can be used as the first substrate 10.

[0064] Secondly, as shown in Figure 6 , the first silicon electrode material layer 20' is etched to form an isolation groove 201.

[0065] Exemplarily, the first silicon electrode material layer 20' can be etched by a deep reactive ion etching (DRIE) process.

[0066] Thirdly, as shown in Figure 7 , a first insulating material layer 50' is formed on the first silicon electrode material layer 20', and the first insulating material layer 50' is thinned and polished.

[0067] Exemplarily, a layer of silicon oxide layer can be deposited by a low pressure chemical vapor deposition (LPCVD) process, and the silicon oxide layer is thinned and polished.

[0068] Fourthly, as shown in Figure 7 and Figure 8 , the first insulating material layer 50' and the first silicon electrode material layer 20' are etched to form the first excitation electrode 21 and the second excitation electrode 22.

[0069] In this way, the first silicon electrode layer 20 can be formed on the first substrate 10.

[0070] Exemplarily, the first insulating material layer 50' and the first silicon electrode material layer 20' can be etched by using a DRIE process.

[0071] In the fifth step, as shown in the figure, a dielectric barrier material layer 30' is formed on the first insulating material layer 50'. Figure 9

[0072] Exemplarily, a silicon oxide layer with a thickness of 200 nm can be deposited by using an LPCVD process to form the dielectric barrier material layer 30'.

[0073] It should be noted that in the above-mentioned second step to the fifth step, the isolation trench 201, the first excitation electrode 21 and the second excitation electrode 22 can also be formed at the same time by using one etching process, and then the first insulating material layer 50' and the dielectric barrier material layer 30' are formed in sequence, which is not limited by the present disclosure.

[0074] In the sixth step, as shown in the figure, the dielectric barrier material layer 30' and the first insulating material layer 50' are etched to form an electrical connection through hole. Figure 9 Figure 10

[0075] Here, the electrical connection through hole is used for the subsequent first pad 60 and second pad 61 to realize electrical connection respectively.

[0076] Exemplarily, the dielectric barrier material layer 30' and the first insulating material layer 50' can be etched by using a reactive ion etching (RIE) process to form the dielectric barrier layer 30 and the first insulating layer 50 with the electrical connection through hole.

[0077] In the seventh step, as shown in the figure, the first pad 60, the second pad 61 and the first metal connecting ring 80 are formed on the dielectric barrier layer 30. Figure 11

[0078] Exemplarily, a layer of metal material can be deposited on the dielectric barrier layer 30, and then the metal material is etched to form the first pad 60, the second pad 61 and the first metal connecting ring 80.

[0079] In the eighth step, as shown in the figure, the ultraviolet light transparent cover material is etched, and the ultraviolet light transparent cover material is thinned and polished to form the ultraviolet light transparent cover 40. Figure 12

[0080] Exemplarily, the ultraviolet light transparent cover material can be etched by using an ion beam etching (IBE) process, and the ultraviolet light transparent cover material is thinned and polished to form the ultraviolet light transparent cover 40 with the concave cavity 41.

[0081] In the ninth step, as​​​​​Figure 13 As shown, the second metal connecting ring 81 is formed on the ultraviolet light-transmitting cover plate 40.

[0082] Exemplarily, the second metal connecting ring 81 can be formed by using a deposition and etching process.

[0083] Step 10, as shown, the third metal connecting ring 82 and the fourth metal connecting ring 83 are formed on opposite sides of the stress matching ring 70. Figure 14

[0084] Exemplarily, the third metal connecting ring 82 and the fourth metal connecting ring 83 can be respectively formed on opposite sides of the stress matching ring 70 by using a deposition and etching process.

[0085] Step 11, as shown, the dielectric barrier layer 30 and the ultraviolet light-transmitting cover plate 40 are fixedly connected through the stress matching ring 70 in a first gas environment. Figure 1

[0086] Exemplarily, the first metal connecting ring 80 and the third metal connecting ring 82 can be fixedly connected by the alloy solder 85, and the second metal connecting ring 81 and the fourth metal connecting ring 83 can be fixedly connected by the alloy solder 85, so as to fixedly connect the dielectric barrier layer 30 and the ultraviolet light-transmitting cover plate 40 in the first gas environment.

[0087] Through the above steps, the vacuum ultraviolet light source chip in the embodiment one can be obtained.

[0088] It should be noted that, in the above-mentioned fifth step, the material of the dielectric barrier material layer 30' is replaced by silicon nitride, so as to obtain the vacuum ultraviolet light source chip in the embodiment two.

[0089] Figure 15 is a structural schematic diagram of a micro photo-ionization detector provided by an embodiment of the present disclosure. As shown, Figure 15 the micro photo-ionization detector includes the vacuum ultraviolet light source chip 1 and the micro ionization chamber structure 2, the vacuum ultraviolet light source chip 1 is any one of the above-mentioned vacuum ultraviolet light source chips, and the micro ionization chamber structure 2 is arranged on the light-emitting side of the vacuum ultraviolet light source chip.

[0090] It should be noted that the micro photo-ionization detector embodiment and the above-mentioned vacuum ultraviolet light source chip are based on the same inventive concept, and the beneficial effects of the embodiment of the present disclosure can be referred to the above-mentioned embodiments one to two, which will not be repeated here.

[0091] Figure 16 is a structural schematic diagram of a micro ionization chamber structure provided by an embodiment of the present disclosure. Figure 17 is a top view of a micro ionization chamber structure provided by an embodiment of the present disclosure. Figure 16 may represent Figure 17 ​​A cross-sectional structure schematic view at the middle cross-section line BB. Referring to Figures 15 to 17 The micro ionization chamber structure 2 includes a second substrate 90 and a second silicon electrode layer 91, the second silicon electrode layer 91 is arranged on the second substrate 90 and between the ultraviolet light transparent cover plate 40 and the second substrate 90, the second silicon electrode layer 91 includes a first electrode 911 and a second electrode 912 arranged at intervals, the first electrode 911 and the second electrode 912 are serpentine interdigital electrodes, a serpentine groove 913 is formed between the first electrode 911 and the second electrode 912, and the serpentine groove 913 is provided with a first opening 914 and a second opening 915 at two ends respectively. That is, the first electrode 911 and the second electrode 912 are arranged at intervals in the form of multiple pairs of serpentine comb-shaped structures, and the sidewalls at the bending positions of the serpentine comb-shaped structures are in the form of circular arcs.

[0092] In the embodiment of the present disclosure, the to-be-detected gas can enter and exit the serpentine groove 913 through the first opening 914 and the second opening 915, the ultraviolet light radiated by the vacuum ultraviolet light source chip 1 can be emitted from the ultraviolet light transparent cover plate 40 to the serpentine groove 913, and the to-be-detected gas in the serpentine groove 913 can generate a photoionization reaction under the irradiation of the ultraviolet light, thereby generating positive and negative particles. An electric field can be generated in the serpentine groove 913 by applying a voltage to the first electrode 911 and the second electrode 912, and the positive and negative particles generated by the ionization of the to-be-detected gas can be adsorbed to the surfaces of the first electrode 911 or the second electrode 912 under the action of the electric field. The concentration of the to-be-detected gas can be measured by detecting the ionization current. Through the serpentine interdigital electrode and the serpentine groove 913, the gas dead angle in the serpentine groove 913 can be reduced, the efficiency and stability of the photoionization reaction can be improved, and thus the detection efficiency can be improved.

[0093] It should be noted that, Figures 15 to 17 The number of pairs of the serpentine interdigital electrodes is only an example and does not limit the number of pairs.

[0094] As shown in Figure 17 , the first opening 914 and the second opening 915 are arranged at the lower left corner edge and the upper right corner edge respectively.

[0095] Optionally, the minimum spacing between the first electrode 911 and the second electrode 912 is greater than 5 μm. Here, the minimum spacing refers to the minimum value of the distance between the first electrode 911 and the second electrode 912. In this way, the gap between the first electrode 911 and the second electrode 912 can be larger, so that the to-be-detected gas in the serpentine groove 913 can flow more easily, and it is beneficial to collect as many charged particles generated by the photoionization reaction as possible.

[0096] For example, the minimum spacing between the first electrode 911 and the second electrode 912 can be 6 μm, 7 μm, or 8 μm, etc.

[0097] Optionally, the micro ionization chamber structure 2 further comprises a third pad 92 and a fourth pad 93, the third pad 92 is arranged on and connected with the first electrode 911, and the fourth pad 93 is arranged on and connected with the second electrode 912.

[0098] Exemplarily, the material of the third pad 92 and the fourth pad 93 can be a metal material. For example, the material of the third pad 92 and the fourth pad 93 can include at least one of gold and aluminum.

[0099] As shown in Figure 17 , the third pad 92 and the fourth pad 93 are arranged at the left and right edges, respectively.

[0100] It should be noted that the arrangement positions of the first opening 914, the second opening 915, the third pad 92 and the fourth pad 93 are only as an example, and in other embodiments, the arrangement positions thereof can be adjusted according to actual needs, and the present disclosure does not limit this.

[0101] Referring to Figures 15 to 17 , the second substrate 90 includes a second silicon substrate 901 and a third insulating layer 902, and the third insulating layer 902 is located between the second silicon substrate 901 and the second silicon electrode layer 91. In this way, the second substrate 90 and the second silicon electrode layer 91 facilitate batch production by SOI wafers, which is conducive to further miniaturization of the micro photoionization detector, and can improve production efficiency and reduce production cost.

[0102] Optionally, the material of the second silicon substrate 901 can be high-resistance silicon in an SOI wafer, and the material of the second silicon electrode layer 91 can be low-resistance silicon in an SOI wafer.

[0103] Exemplarily, the material of the third insulating layer 902 can be silicon oxide.

[0104] Exemplarily, the size specifications of the first substrate 10 and the second substrate 90 are the same.

[0105] The present disclosure also provides a preparation method of a micro photoionization detector, which comprises: Firstly, a micro ionization chamber structure is provided.

[0106] Figures 18 to 19 is a structural schematic diagram of a micro ionization chamber structure provided by the present disclosure in a preparation process. Referring to Figure 16 and Figures 18 to 19 , the first step can include the following steps: (1) As shown in Figure 18 , an SOI wafer is provided.

[0107] The SOI wafer comprises a second silicon substrate 901, a third insulating layer 902 and a second silicon electrode material layer 91' stacked in sequence.

[0108] (2) As shown in FIG. 2, a third pad 92 and a fourth pad 93 are formed on the second silicon electrode material layer 91'. Figure 19

[0109] Exemplarily, a layer of metal material can be deposited on the second silicon electrode material layer 91' first, and then the metal material is etched to form the third pad 92 and the fourth pad 93.

[0110] (3) As shown in FIG. 3, the second silicon electrode material layer 91' is etched to form a first electrode 911 and a second electrode 912. Figure 16 Figure 17 Figure 19

[0111] Exemplarily, the DRIE process can be used to etch the second silicon electrode material layer 91' to form the first electrode 911 and the second electrode 912, the first electrode 911 and the second electrode 912 are serpentine interdigital electrodes, and a serpentine groove 913 is formed between the first electrode 911 and the second electrode 912, and the first electrode 911 and the second electrode 912 are respectively provided with a first opening 914 and a second opening 915 at both ends of the serpentine groove 913.

[0112] The micro ionization chamber structure can be obtained through the above steps (1) to (3).

[0113] Secondly, the micro ionization chamber structure is stacked on the light emitting side of the vacuum ultraviolet light source chip to obtain a micro photoionization detector.

[0114] It should be noted that the structure, material, thickness and projection position relationship of each film layer in the preparation method embodiment, as well as the type of the first gas and the gas pressure range can be referred to the foregoing structure embodiment, and the detailed description is omitted here.

[0115] The above only describes optional embodiments of the present disclosure, and does not limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.​​​​

Claims

1. A vacuum ultraviolet light source chip, used in a photoionization detector, characterized in that: It includes a first substrate, a first silicon electrode layer, a dielectric barrier layer and an ultraviolet light transparent cover plate; The first silicon electrode layer is provided on the first substrate, and the first silicon electrode layer includes a first excitation electrode and a second excitation electrode that are spaced apart; At least a portion of the dielectric barrier layer covers the first excitation electrode and the second excitation electrode; The UV-transparent cover plate is arranged on a side of the dielectric barrier layer away from the first silicon electrode layer, a gas cavity is formed between the UV-transparent cover plate and the first silicon electrode layer, and the gas cavity is filled with a first gas; The first gas is used to be excited to radiate ultraviolet light, and the dielectric barrier layer is used to isolate the first gas from the first excitation electrode and the second excitation electrode.

2. The vacuum ultraviolet light source chip according to claim 1, characterized in that: The first excitation electrode and the second excitation electrode are interdigitated electrodes.

3. The vacuum ultraviolet light source chip according to claim 2, characterized in that: The first silicon electrode layer further includes a first connecting portion, a second connecting portion, an isolation portion, and a peripheral portion. The first connecting portion is connected to the first excitation electrode, and the second connecting portion is connected to the second excitation electrode. The first connecting portion and the second connecting portion are used to introduce an external electrical signal. The isolating portion is located at the periphery of the first excitation electrode and the second excitation electrode. The peripheral portion is located at the periphery of the first connecting portion, the second connecting portion, and the isolating portion. Isolation trenches are formed between the first connecting portion and the isolating portion, and between the second connecting portion and the isolating portion. The isolation trenches are filled with a first insulating layer and are leveled by the first insulating layer. The outer contour of the orthographic projection of the UV-transparent cover plate on the first substrate is located inside the sum of the orthographic projections of the isolation portion, the isolation trench, the first connecting portion and the second connecting portion on the first substrate, and intersects with the orthographic projections of the first connecting portion and the second connecting portion on the first substrate.

4. The vacuum ultraviolet light source chip according to any one of claims 1 to 3, characterized in that: The first substrate includes a first silicon substrate and a second insulating layer, wherein the second insulating layer is located between the first silicon substrate and the first silicon electrode layer.

5. The vacuum ultraviolet light source chip according to any one of claims 1 to 3, characterized in that: The vacuum ultraviolet light source chip also includes a stress matching ring, which is arranged between the ultraviolet light transparent cover plate and the dielectric barrier layer to match the thermal expansion coefficient of the ultraviolet light transparent cover plate. The dielectric barrier layer, the stress matching ring and the ultraviolet light transparent cover plate are fixedly connected by alloy solder.

6. The vacuum ultraviolet light source chip according to any one of claims 1 to 3, characterized in that: The gas pressure of the first gas is 10 -2 Pa to 10 4 Pa; The first gas includes at least one of He, Ne, Ar, Kr, Xe, Rn, H2, N2, O2, H2O, CO2, Cl2, CH4, CF4, NH3, F2 and air; or, the first gas includes one of the following excimers: Ar2, Kr2, Xe2, ArF, XeF, XeCl, F2, Ar2Cl, Kr2F and Xe2Cl.

7. The vacuum ultraviolet light source chip according to any one of claims 1 to 3, characterized in that: The gas pressure of the first gas is 10 -8 Pa to 10 4 Pa; The first gas includes at least one of Rb, Cs, Sr, Yb, Hg, Sn, and Th.

8. A method for preparing a vacuum ultraviolet light source chip, wherein the vacuum ultraviolet light source chip is applied to a photoionization detector, characterized in that: include: forming a first silicon electrode layer on a first substrate, wherein the first silicon electrode layer includes a first excitation electrode and a second excitation electrode that are spaced apart; forming a dielectric barrier layer on the first silicon electrode layer, wherein at least a portion of the dielectric barrier layer covers the first excitation electrode and the second excitation electrode; The dielectric barrier layer is fixedly connected to a UV-transparent cover plate, and the UV-transparent cover plate is arranged on a side of the dielectric barrier layer away from the first silicon electrode layer. A gas cavity is formed between the UV-transparent cover plate and the dielectric barrier layer, and the gas cavity is filled with a first gas, wherein the first gas is used to be excited to radiate ultraviolet light, and the dielectric barrier layer is used to isolate the first gas from the first excitation electrode and the second excitation electrode.

9. A miniature photoionization detector, characterized in that: It comprises the vacuum ultraviolet light source chip and a micro ionization chamber structure as claimed in any one of claims 1 to 7, wherein the micro ionization chamber structure is arranged on the light output side of the vacuum ultraviolet light source chip.

10. The micro photoionization detector according to claim 9, characterized in that The micro ionization chamber structure includes a second substrate and a second silicon electrode layer. The second silicon electrode layer is arranged on the second substrate and is located between the ultraviolet light transparent cover and the second substrate. The second silicon electrode layer includes a first electrode and a second electrode arranged at intervals. The first electrode and the second electrode are serpentine interdigitated electrodes. A serpentine groove is formed between the first electrode and the second electrode. The two ends of the serpentine groove are respectively provided with a first opening and a second opening.

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