On-chip Faraday cage

Abstract

The invention discloses a Faraday cage on a chip. The Faraday cage on the chip comprises a substrate layer and a metal layer on the chip, the substrate layer comprises a deep N well, a first N well, a second N well, a first P well and a second P well; the first N well and the second N well of the substrate layer are electrically connected with the deep N well respectively; a deep N well, an N well and a P well are formed on the substrate layer through the ion implantation technology, N-type doping is injected into the N well, and P-type doping is injected into the P well; the metal layer is connected with the first N well, the second N well, the first P well and the second P well of the substrate layer; the through holes between the metal layers are arranged in a staggered manner. According to the invention, bidirectional isolation of noise and electromagnetic interference can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, and in particular to a Faraday cage on a chip. BACKGROUND

[0002] This section is intended to provide background or context to the embodiments of the application recited in the claims. The description herein does not constitute admission that the prior art is prior art nor does it constitute an admission of any description in this section as prior art to an application described herein and / or in another application also owned by the applicant of the present application.

[0003] True random numbers play a crucial role in modern secure encryption systems, and improper design and use of true random number generators can lead to serious security problems. At the same time, the lack of true randomness provided by the random number pool also limits the performance of the entire encryption system, so it is particularly important to design a safe and reliable high-performance TRNG chip.

[0004] A common sub-stable chip Faraday cage chip entropy source structure has the advantages of fast speed and low power consumption, but noise and external electromagnetic interference during chip operation can cause steady-state point drift problems. This instability reduces the entropy rate of the output random sequence.

[0005] According to electromagnetic theory, when a whole piece of metal forms a large cage, due to the metal equipotential body, the voltage on the entire metal is equal, which can effectively isolate the mutual interference between the inside and outside of the cage. Electromagnetic waves inside the cage cannot propagate outward, and electromagnetic waves outside the cage cannot enter the cage. This cage is called a Faraday cage. In order to resist electrical interference of the true random number generator, the main means at present is to realize the Faraday cage structure outside the chip (referred to as off-chip Faraday cage) to achieve the effect of resisting interference, but the internal electromagnetic interference still exists.

[0006] Therefore, there is currently a lack of a structure that directly implements a Faraday cage on a chip (referred to as a chip-on-chip Faraday cage) to achieve noise and electromagnetic interference isolation. SUMMARY

[0007] The embodiments of the present application provide a chip-on-chip Faraday cage, which utilizes metal interconnection layers and corresponding N-wells and P-wells to realize a chip-on-chip Faraday cage for bidirectional noise and electromagnetic interference isolation. The chip-on-chip Faraday cage comprises:

[0008] a substrate layer and a metal interconnection layer on a chip;

[0009] The substrate layer comprises a deep N-well, a first N-well, a second N-well, a first P-well, and a second P-well;

[0010] The first N-well and the second N-well of the substrate layer are electrically connected to the deep N-well, respectively;

[0011] The metal layer is connected with the first N well, the second N well, the first P well and the second P well of the substrate layer.

[0012] The through holes between the metal layers are staggered.

[0013] In the embodiment of the present application, the deep N well, the first N well, the second N well, the first P well and the second P well of the substrate layer and the metal layer on the chip form a Faraday cage protection, so that the external noise and electromagnetic interference first act on the top metal layer, the through holes between the metal layers are staggered, the electromagnetic wave is prevented from leaking from the gap between the through holes, and the shielding protection of the internal circuit of the chip is realized. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0015] Figure 1 It is a structure schematic diagram of the Faraday cage on the chip in the embodiment of the present application (external display),

[0016] Figure 2 It is a structure schematic diagram of the Faraday cage on the chip in the first structure form of the embodiment of the present application (internal display),

[0017] Figure 3 It is a deep N well schematic diagram in the embodiment of the present application,

[0018] Figure 4 It is a structure schematic diagram of the Faraday cage on the chip in the second structure form of the embodiment of the present application (internal display),

[0019] Figure 5 It is a 3D schematic diagram of the staggered through holes between the metal layers. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings. Herein, the schematic embodiments of the present application and the descriptions thereof are used to explain the present application, but not as a limitation on the present application.

[0021] Figure 1 It is a structure schematic diagram of the Faraday cage on the chip in the embodiment of the present application (external display), Figure 2 It is a structure schematic diagram of the Faraday cage on the chip in the first structure form of the embodiment of the present application (internal display), the Faraday cage on the chip comprising: a substrate layer and a metal layer on the chip;

[0022] The substrate layer comprises a deep N well, a first N well, a second N well, a first P well and a second P well;

[0023] The first N well and the second N well of the substrate layer are electrically connected with the deep N well respectively;

[0024] The metal layer is connected with the first N well, the second N well, the first P well and the second P well of the substrate layer;

[0025] The through holes between the metal layers are arranged in a staggered manner.

[0026] In an embodiment, the layout of the top metal layer of the chip is a fine grid or a continuous plate.

[0027] In an embodiment, the deep N well is connected with the high potential of the power supply, and the P substrate in the substrate layer is connected with the ground, so that the top metal layer, the first P well, the P substrate and the second P well are electrically connected to form a first structure form of the on-chip Faraday cage.

[0028] The deep N well is a kind of semiconductor structure, which is usually used in integrated circuit design, especially in metal oxide semiconductor field effect transistor (MOSFET) process. It is a deeper N type region formed in a P type substrate, which mainly functions to reduce substrate noise, provide isolation for devices, and thus improve the performance and stability of the circuit. For example, in a mixed signal integrated circuit, it is used to isolate digital circuits and sensitive analog devices, to prevent the switching noise of digital signals from affecting the normal operation of analog circuits. Figure 3 The deep N well in the embodiment of the present application is shown in the figure, wherein, Figure 3 The left side of the figure does not contain a deep N well, Figure 3 The right side of the figure contains a deep N well. In the traditional CMOS process, the N well is generally used as the substrate of PMOS, and NMOS is directly made on the P type substrate. The entire large substrate of the CMOS process is a lightly doped P type substrate. The DNW technology introduces a deeper N type doped region (called deep N well) in the silicon substrate, which is located in the P type substrate, and then P doping is performed on it to form a P substrate, and then N type heavy doping is performed to form the active area of NMOS. The deep N well can effectively improve the electrical isolation, reduce the parasitic, and reduce the cross-coupling effect, thereby improving the switching speed and overall performance of the device, while reducing the leakage of the substrate. The introduction of the deep N well enhances the anti-interference ability of the integrated circuit, especially in a high noise environment, the deep N well can effectively shield external interference. This is crucial for electromagnetic interference sensitive applications.

[0029] The present application also provides a second structure form of the on-chip Faraday cage, as shown in Figure 4The structure diagram of the on-chip Faraday cage in the second structure form in the embodiment of the present application (internal display) is shown in Figure 2, and the structure of the on-chip Faraday cage in the second structure form is that the first N well and the second N well are connected to the high potential of the power supply voltage, so that the top metal layer, the first N well, the deep N well and the second N well are electrically connected to form the on-chip Faraday cage in the second structure form. The principles of the above two Faraday cages are consistent. In addition, for the twin well process, the triple well process, and the like, the on-chip Faraday cage structure can also be realized by connecting the potentials in a similar manner.

[0030] The above bias voltage can be determined according to actual conditions, for example, 0.9V can be used, which is not limited here.

[0031] In an embodiment, the deep N well and the inner well with different doping concentrations or different types form a nested well structure, and the inner well is connected to the deep N well through a preset electrical connection mode.

[0032] In which, the inner well with different doping concentrations or different types, and the like, cooperates with the outer well through a specific electrical connection mode, which can further refine the conduction path of electromagnetic interference and enhance the shielding effect. For example, when external electromagnetic interference enters, different inner wells can stepwise attenuate according to the characteristics of the interference frequency, intensity, etc., so that the interference conducted to the internal circuit is greatly reduced.

[0033] In an embodiment, a switching device is integrated in the nested well structure.

[0034] After the switching device such as a transistor is integrated in the nested well structure, the nested well structure can be reconfigured, and the switching device can dynamically adjust the connection mode in the nested well structure or the electrical characteristics in the well according to different electromagnetic environments or circuit operation modes. For example, in a strong electromagnetic interference environment, some areas in the well are connected to form a more compact shielding structure; in a low interference environment, some connections are disconnected to reduce power consumption and the influence on the circuit performance.

[0035] In an embodiment, the metal layer can be connected to the first N well, the second N well, the first P well and the second P well of the substrate layer through metal (such as tungsten) and synthetic materials.

[0036] In the embodiment of the present application, the through holes between the metal layers are staggered, and the metal layers on the chip have multiple layers, Figure 5 The 3D schematic diagram of the staggered through holes between the metal layers is shown in Figure 3, Figure 5 In which, the red row represents one metal layer, and the blue row represents another metal layer. Through staggered arrangement, electromagnetic waves can be prevented from leaking through the gaps between the through holes, thereby achieving shielding protection for the internal circuit of the chip.

[0037] In addition to staggered arrangement, the metal layers can be heterogeneous vias with different shapes, sizes and functions. For example, some vias are used for conventional metal layer electrical connection, some vias are filled with magnetic materials or electromagnetic wave absorbing materials to enhance the shielding effect of specific frequency electromagnetic waves; some vias are designed to be adjustable in size, and the size of the via is dynamically adjusted by micro-electro-mechanical system (MEMS) technology to adapt to different frequency electromagnetic interference. A patent is applied for the heterogeneous via structure and its manufacturing and adjusting method.

[0038] In addition, not only can the metal shielding layer be arranged and connected on the side and bottom of the chip, but also between the metal layers and well structures at different levels inside the chip, a dense three-dimensional connection can be established between the metal layers and well structures at different levels inside the chip by various means such as vertical interconnection (TSV) technology, metal pillars or nanowires. This three-dimensional connection network can more effectively guide and disperse electromagnetic interference and improve shielding efficiency.

[0039] In the embodiments of the present application, a new type of high-conductivity and high-permeability on-chip metal interconnection layer can be used, and metal materials or alloy materials can be used as the metal interconnection shielding layer. For example, new materials such as graphene-metal composite films are used. Compared with traditional metal materials, the conductivity and flexibility are better, and better electromagnetic shielding performance can be provided under the same thickness, and the overall weight and thickness of the chip can be reduced, which meets the design requirements of small and thin chips.

[0040] In the embodiments of the present application, the semiconductor material used for the deep N well can be functionally modified. For example, specific impurities are added to the N-type semiconductor material or a special doping process is used, so that the semiconductor material not only has good electrical properties for conducting electromagnetic interference, but also has certain wave absorbing properties, and part of the electromagnetic interference energy is converted into heat energy or other forms of energy consumption, further improving the shielding efficiency.

[0041] In the embodiments of the present application, the on-chip Faraday cage is a self-adapting deformable Faraday cage, which can be deformed in real time according to the shape of the sensitive circuit area. A micro-electro-mechanical system (MEMS) driving unit is integrated in the cage body. When the shape of the sensitive circuit area changes (such as when part of the circuit is enabled / disabled due to chip function switching), the MEMS unit drives the movable metal parts in the cage structure to adjust the position and change the shape, so as to always closely fit the irregular sensitive circuit area, and realize dynamic and accurate shielding.

[0042] In the embodiments of the present application, the on-chip Faraday cage can be a plurality of independently controllable modular structures. For irregularly shaped sensitive circuit regions, different modules with different shapes, thicknesses, and metal layer layouts can be configured according to the electromagnetic interference characteristics and shielding requirements of different sub-regions. For example, in regions of the circuit where signal processing is complex, fine grid-shaped and slightly thicker modules are used; in relatively simple storage regions, relatively light and thin modules are used, optimizing chip area and cost while ensuring shielding effect.

[0043] In an embodiment, the on-chip Faraday cage uses anisotropic electromagnetic shielding material. For strong interference sources from a specific direction, the high shielding performance direction of the material is aligned with the direction of the interference source. For example, a specially treated magnetic metal film material is used, which has different magnetic permeability and electrical conductivity in different directions in the plane. By precisely controlling the laying direction of the material, the shielding ability for interference from a specific direction can be greatly improved.

[0044] In an embodiment, the on-chip Faraday cage further includes an interference source tracking sensor array disposed on the chip.

[0045] The interference source tracking sensor array can monitor the direction, intensity, and frequency of external interference sources in real time. Based on these monitoring data, the structure parameters (such as thickness, metal layer resistivity, etc.) and working mode of the Faraday cage in the corresponding direction are automatically adjusted by an algorithm. For example, when the direction of the interference source changes, the cage structure is quickly adjusted so that the parts with increased thickness or special layout are always aligned with the interference source, ensuring the optimization of the shielding effect.

[0046] Based on the interference source tracking sensor array, a multi-parameter real-time monitoring system is constructed. This system not only can monitor the location of electromagnetic interference sources, but also can detect the intensity, frequency, polarization direction, and other parameters of electromagnetic interference in real time. By integrating various types of sensors (such as electric field sensors, magnetic field sensors, frequency spectrum sensors, etc.) on the chip and using advanced signal processing algorithms to fuse and analyze sensor data, comprehensive monitoring of electromagnetic interference is achieved.

[0047] Based on the data obtained by the multi-parameter real-time monitoring system, an intelligent feedback control system is used. This system can automatically adjust the relevant parameters of the Faraday cage (such as metal layer voltage, trap structure connection method, shielding material characteristics, etc.) according to the monitored electromagnetic interference, achieving dynamic adaptive shielding of electromagnetic interference. For example, when strong electromagnetic interference of a specific frequency is detected, the system automatically adjusts the voltage distribution of the metal layer to enhance the shielding effect of the interference at that frequency.

[0048] In an embodiment, the first N-well and the second N-well are doped with N-type doping, and the first P-well and the second P-well are doped with P-type doping.

[0049] In an embodiment, the deep N-well is formed in the substrate layer by an ion implantation process.

[0050] In embodiments of the present application, the Faraday cage can be equipped with self-learning capability. Shielding effect data in different electromagnetic interference environments can be recorded, and the relationship between interference characteristics and the best shielding strategy is analyzed through machine learning algorithms. As the use time increases and data accumulates, the system continuously optimizes the adaptive mode for irregular sensitive circuit areas and the shielding strategy for specific direction interference sources, achieving continuous improvement of shielding performance.

[0051] In an embodiment, the on-chip Faraday cage is a three-dimensional wraparound structure, and the chip side and bottom are provided with a metal shielding layer, which is connected to the deep N-well and the top metal layer through a three-dimensional connection structure.

[0052] This three-dimensional wraparound structure can shield electromagnetic interference from all directions, which is of great significance for the application of chips in complex electromagnetic environments.

[0053] An active electromagnetic cancellation system can be integrated in the on-chip Faraday cage. The system includes an interference signal detection module, a signal processing module, and a cancellation signal emission module. The interference signal detection module monitors the strength, frequency, and phase of external electromagnetic interference signals in real time; the signal processing module generates a cancellation signal with opposite phase according to the detected interference signal parameters; and the cancellation signal emission module emits the cancellation signal to mutually cancel the external interference signal, achieving active shielding.

[0054] In an embodiment, an adaptive interference suppression circuit can be combined with the metal layer and well structure of the Faraday cage. The circuit can automatically adjust its working parameters (such as gain, filtering characteristics, etc.) according to the detected type and strength of electromagnetic interference, and suppress and filter the interference signals entering the interior of the Faraday cage. For example, when high-frequency electromagnetic interference is detected, the circuit automatically increases the filtering capability of the high-frequency band, reducing the impact of interference signals on the internal circuits of the chip.

[0055] For different application scenarios, the on-chip Faraday cage is designed to be customized. For example, in the automotive electronics field, considering the complex electromagnetic environment, high temperature, and vibration in the car, the structure and material of the on-chip Faraday cage are optimized to improve its shielding performance in a wide temperature range and high vibration environment. In the field of aerospace, in order to meet the requirements of small size and high reliability of chips, a more compact and robust Faraday cage structure is designed.

[0056] The on-chip Faraday cage is integrated with the radio frequency front-end circuit. In a radio frequency communication chip, the radio frequency front-end is susceptible to electromagnetic interference affecting performance. By integrating the Faraday cage, external electromagnetic interference is effectively shielded, improving the reception and transmission quality of radio frequency signals. At the same time, the electrical connection and layout between the Faraday cage and the radio frequency front-end circuit are optimized to reduce interference between them. The structure, layout method and application patent of the on-chip Faraday cage integrated with the radio frequency front-end are applied.

[0057] The on-chip Faraday cage is integrated with other functional modules of the chip to realize a multifunctional integrated chip. For example, the on-chip Faraday cage is integrated with a power management module to reduce the interference of power supply noise on other parts of the chip; it is integrated with a communication module to improve the stability and anti-interference ability of communication signals. This integrated design can reduce the area and power consumption of the chip and improve the overall performance and competitiveness of the chip.

[0058] In summary of the above embodiments, the on-chip Faraday cage proposed in the embodiments of the present application does not need to form an additional Faraday cage structure after the chip is manufactured, but improves the design of the chip based on its own characteristics. Therefore, no additional process steps are required, and the coupling of radio frequency and switching noise can be effectively reduced, with almost no area and performance overhead for the core circuit. The on-chip Faraday cage can prevent signal leakage of internal noise sources, resulting in a decrease in the theoretical total entropy value of the circuit. The present application can realize noise and electromagnetic interference isolation (i.e., external interference is isolated, and internal electromagnetic or noise disturbance is also prevented from leaking out).

[0059] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only for specific embodiments of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A Faraday cage on a chip, characterized in that: include: The substrate and metal layers on the chip; The substrate layer includes a deep N-well, a first N-well, a second N-well, a first P-well and a second P-well; The first N-well and the second N-well of the substrate layer are electrically connected to the deep N-well respectively; The metal layer is connected to the first N-well, the second N-well, the first P-well and the second P-well of the substrate layer; The through holes between the metal layers are arranged in a staggered manner.

2. The on-chip Faraday cage according to claim 1, wherein: The top metal layer of the chip is laid out as either a fine grid or a continuous plate.

3. The on-chip Faraday cage according to claim 1, wherein: The deep N-well is connected to a high potential of a power supply voltage, and the P-substrate in the substrate layer is connected to the ground, so that the top metal layer, the first P-well, the P-substrate and the second P-well are electrically connected to form a Faraday cage on the chip in a first structural form.

4. The on-chip Faraday cage according to claim 1, wherein: The first N well and the second N well are connected to a high potential of a supply voltage, so that the top metal layer, the first N well, the deep N well and the second N well are electrically connected to form an on-chip Faraday cage of a second structural form.

5. The on-chip Faraday cage according to claim 1, wherein: The deep N-well and inner wells of different doping concentrations or types form a nested well structure, and the inner wells are connected to the deep N-well via a preset electrical connection method.

6. The on-chip Faraday cage according to claim 5, wherein: Switching devices are integrated in the nested well structure.

7. The on-chip Faraday cage according to claim 1, wherein: Also included is an on-chip interference source tracking sensor array.

8. The on-chip Faraday cage according to claim 1, wherein: The on-chip Faraday cage is a three-dimensional surrounding structure. Metal shielding layers are provided on the sides and bottom of the chip. The metal shielding layers are connected to the deep N well and the top metal layer through a three-dimensional connection structure.

9. The on-chip Faraday cage according to claim 1, wherein: The on-chip Faraday cage uses anisotropic electromagnetic shielding material.

10. The on-chip Faraday cage according to claim 1, wherein: The first N-well and the second N-well are injected with N-type dopants, and the first P-well and the second P-well are injected with P-type dopants.

11. The on-chip Faraday cage according to claim 1, wherein: The deep N well is formed in the substrate layer by an ion implantation process.

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