Gate driver system and method of determining fault location in gate driver system

Abstract

A gate driver system and a method of determining a fault location in a gate driver system are provided. The gate driver system includes a plurality of gate drivers each having a fault output node switchable between a fault state indicating that a fault is detected by the respective gate driver and an operating state. A timing device is provided for each gate driver, each timing device configured to switch the common node to the first state in response to a faulty output node of the respective gate driver being set to a faulty state. After a predetermined period of time has elapsed from the trigger event, the common node is released from the first state. Since the predetermined time periods of each timing device (and thus each gate driver) are different from each other, the amount of time between the trigger event and the release of the common node from the first state can be measured to identify a failed gate driver, the present invention enables identification of a failed gate driver using only a single output pin.

Description

TECHNICAL FIELD

[0001] The present invention relates to gate drivers, and in particular to a system and method for identifying a gate driver that has reported a fault. BACKGROUND

[0002] Gate drivers are power amplifiers that accept a low power input from a controller and generate a high current drive input for the gate of a high power transistor (e.g. IGBT or power MOSFET). For example, a motor drive system can comprise six gate drivers, each providing an input to a respective gate of a high power transistor. Typically, the gate drivers comprise a pin for reporting a fault detected by the gate driver (i.e. a fault output node). This pin can report both an internal fault of the gate driver, and / or a fault of the transistor controlled by the gate driver.

[0003] However, in order to reduce the number of I / O pins of the controller, the fault output node of each of the gate drivers is typically connected to a single I / O pin. Therefore, once a fault is detected by any of the gate drivers, the single I / O pin will indicate the presence of a fault, but the identity of the gate driver that reported the fault is lost. In other words, using this connection method, it is difficult to distinguish which gate driver reported the fault, particularly in the case where the fault is triggered by random noise.

[0004] Accordingly, the inventors have identified a need to identify the gate driver that has reported a fault, whilst minimising the number of I / O pins required. SUMMARY

[0005] According to an aspect of the present invention, there is provided a gate driver system. The gate driver system comprises a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a fault detected by the respective gate driver and an operational state. The system further comprises:

[0006] a common node switchable between a first state and a second state;

[0007] a timing device for each of the gate drivers, each timing device connected to the fault output node of the respective gate driver and the common node, each timing device configured to:

[0008] set the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state; and

[0009] release the common node from the first state in response to a predetermined time period elapsing from a triggering event, wherein the predetermined time period of each timing device is different.

[0010] A concept is provided for identifying a fault reporting gate driver in a gate driver system. The gate driver system comprises a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicative of a fault detected by the respective gate driver and an operational state. A timing device is provided for each of the gate drivers, wherein each timing device is configured to switch a common node to a first state in response to the fault output node of the respective gate driver being set to the fault state. The common node is then released from the first state after a predetermined time period has elapsed from a triggering event. Since the predetermined time period of each of the timing devices (and thus of each of the gate drivers) is different, the amount of time between the triggering event and the release of the common node from the first state can be measured to identify the fault reporting gate driver (i.e. the gate driver that switched the common node to the first state). Thus, the proposed concept enables identifying the fault reporting gate driver while using only a single output pin (e.g. connected to the common node).

[0011] In a typical gate driver, all fault output nodes (each fault output node corresponding to one gate driver) are connected to each other at one common node. This is to minimize the number of I / O pins required for reporting a fault. Thus, when one gate driver (or a series of gate drivers) detects a fault, the common node indicates that there is a fault detected by one (or more) of the gate drivers, but does not indicate which gate driver has reported the fault. Identifying the fault reporting gate driver can be used to locate and subsequently correct the cause of the fault.

[0012] Of course, alternatively, each of the fault output nodes can be connected to a different I / O pin. Once one of the gate drivers detects a fault, the corresponding I / O pin will indicate that there is a fault, and the location is determined in a straightforward manner. However, this approach requires a large number of I / O pins.

[0013] The disclosed invention provides a solution to this problem without increasing the number of I / O pins for reporting a fault. In particular, the disclosed invention enables identifying the gate driver that has reported the fault. This is achieved by a timing device associated with each of the gate drivers, which initially sets the common node to a first state and only releases the common node from the first state after a predetermined time period. Thus, when the common node is set to the first state, only an entity observing the common node first becomes aware of the existence of the fault and is able to identify the gate driver that has reported the fault by monitoring the length of time between the triggering event and the release of the common node from the first state.

[0014] That is, since the triggering event and the predetermined length of time associated with each gate driver (provided by the timing device) are known, the common node can be monitored to identify the gate driver associated with the reported fault. Accordingly, the common node can be connected to a single I / O pin for reporting the detection and location of the fault.

[0015] In some embodiments, the first state can be a low state and the second state can be a high state. That is, each timing device can individually set the common node to a low state in response to the fault output node of the respective gate driver being set to the fault state. Then, after the predetermined time period associated with the respective timing device, the common node can be released from the low state (i.e., pulled / switched to the high state).

[0016] Accordingly, a falling edge of the common node can indicate that at least one of the gate drivers has a fault output node that has been set to the fault state. Then, after the predetermined time period from the triggering event, a rising edge of the common node can indicate that a gate driver has a fault output node that has been set to the fault state. In other words, the length of time between the triggering event and the rising edge on the common node will indicate which fault output node has been set to the fault state (and thus provide a clue as to the location of the fault).

[0017] However, in some embodiments, the first state can be a high state and the second state can be a low state. Accordingly, a rising edge of the common node can indicate that at least one of the gate drivers has a fault output node that has been set to the fault state. Then, after the predetermined time period from the triggering event, a falling edge of the common node can indicate that a gate driver has a fault output node that has been set to the fault state. In other words, the length of time between the triggering event and the falling edge on the common node will indicate which fault output node has been set to the fault state (and thus provide a clue as to the location of the fault).

[0018] The system can also include a controller connected to the common node. The controller can be configured to measure the length of time between the triggering event and the common node switching to the second state, and identify the gate driver corresponding to the detected fault based on the measured length of time and the predetermined time period of each respective timing device.

[0019] Accordingly, the controller can identify the gate driver having the faulty output node that has been switched to the fault state by monitoring / measuring / determining the time between the triggering event and the switching of the common node to the second state. That is, the controller can consult a list of predetermined time periods and associated gate drivers and match the time period that has elapsed since the triggering event and the switching of the common node to the second state to the list in order to determine the gate driver associated with the reported fault.

[0020] Of course, other means of providing the identity of the gate driver can be implemented in other embodiments. For example, a sensor output can be provided to indicate the time of the triggering event, followed by the time of the switching of the common node to the second state. A user can then be able to determine which gate driver has reported the fault (from the amount of time from the two sensor outputs).

[0021] The triggering event can be the setting of the common node to the first state, or the setting of the faulty output node of the respective gate driver to the operational state.

[0022] In other words, in some cases, each of the timing devices is configured to delay the associated predetermined time period after the setting of the common node to the first state from it, before releasing the common node from the first state. That is, the timing device holds the common node in the first state until the predetermined time period has elapsed, at which point the common node is released from the first state.

[0023] In other cases, each of the timing devices is configured to delay the associated predetermined time period after the setting of the faulty output node of the associated gate driver to the operational state from the fault state, before releasing the common node from the first state. In other words, the timing device waits for a predetermined amount of time from a reset signal that resets each of the faulty output nodes to the operational state.

[0024] When the triggering event is the setting of the common node to the first state, each of the timing devices can comprise a ramp generator and control logic. The ramp generator can be configured to generate a ramp output voltage in response to the setting of the faulty output node of the respective gate driver to the fault state. The control logic can be configured to set the common node to the first state in response to the setting of the faulty output node of the respective gate driver to the fault state and the ramp output voltage failing to satisfy a first voltage condition, and to release the common node from the first state in response to the ramp output voltage satisfying the first voltage condition.

[0025] That is, after the fault output node is set to the fault state, the ramp generator output increases or decreases in voltage. The control logic monitors the output voltage of the ramp generator and compares the output voltage to the first voltage condition. Depending on the result of the comparison (i.e., whether the output voltage satisfies the first voltage condition), the common node is set to the first state or released from the first state. Once the output voltage satisfies the first condition, the common node is released from the first state.

[0026] Accordingly, each timing device is configured to set the common node to the first state and release the common node from the first state after a predetermined time period from the triggering event (i.e., the common node being set to the first state). The rate at which the rate generator changes its associated output voltage or the first voltage condition can be set to ensure this operation according to the predetermined time period.

[0027] In some embodiments, the ramp generator of each timing device can be configured to generate a respective ramp output voltage such that the respective ramp output voltage satisfies the first voltage condition once the respective predetermined time period of the timing device has elapsed from the triggering event. In this case, the first voltage condition of each timing device can be the same.

[0028] In this case, the ramp generator of each timing device is different in order to ensure that each timing device has a different associated predetermined time period. In practice, it will take a different amount of time for the associated output voltage of each ramp generator to satisfy the first voltage condition.

[0029] Alternatively, the first voltage condition of each timing device can be selected such that the ramp output voltage generated by the respective ramp generator satisfies the respective first voltage condition once the respective predetermined time period of the timing device has elapsed from the triggering event.

[0030] In this case, the first voltage condition of each timing device is different in order to ensure that each timing device has a different associated predetermined time period. In practice, if the same for the ramp generator of each respective timing device, then each ramp generator will require a different amount of time to satisfy the respective voltage condition of each timing device.

[0031] The control logic of each timing device can also be configured to set the common node to the first state in response to the ramp output voltage satisfying a second common voltage condition and the first voltage condition.

[0032] Accordingly, the common node is reset to the first state once the common voltage condition is satisfied. This can be useful to continue to indicate that a fault has been detected. That is, the common node will be set to the first state indicating a fault after being released for indicating the identity of the gate driver reporting the fault.

[0033] In some cases, the ramp generator can comprise a capacitor, a current source, and a switch arranged such that the current source is able to charge the capacitor in response to the fault output node of the respective gate driver being set to the fault state.

[0034] This can provide a simple and inexpensive ramp generator for the purposes of the present application. However, other ramp generator arrangements are possible and will be readily understood by the person skilled in the art.

[0035] The capacitance of the capacitor and / or the amperage of the current source of each ramp generator can be selected such that the respective ramp output voltage meets the first voltage condition once the respective predetermined time period of the timing device has elapsed from the triggering event. In this case, the first voltage condition of each timing device can be the same.

[0036] In practice, the capacitor and / or the current source of the ramp generator are parameters that can be varied to ensure that the output voltage meets the voltage condition after the respective predetermined time period.

[0037] In the case where the triggering event is the fault output node of the respective gate driver being set to the working state, each timing device can comprise a ramp generator and control logic. The ramp generator can be configured to generate a ramp output voltage in response to the fault output node of the respective gate driver being set to the working state. The control logic can be configured to set the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state and the ramp output voltage failing to meet the voltage condition. The control logic can also be configured to release the common node from the first state in response to the ramp output voltage meeting the voltage condition.

[0038] That is, after the fault output node is set to the working state (i.e. the fault output node is reset), the ramp generator outputs an increasing or decreasing voltage. The control logic sets the common node to the first state in response to the fault output node being set to the fault state. The control logic then monitors the output voltage of the ramp generator (once the fault output node is reset) and compares said output voltage to the voltage condition. Once the output voltage meets the first condition, the common node is released from the first state.

[0039] In some embodiments, the ramp generator of each timing device can be configured to generate a respective ramp output voltage such that the respective ramp output voltage meets the voltage condition once the respective predetermined time period of the timing device has elapsed from the triggering event. In this case, the voltage condition of each timing device can be the same.

[0040] Alternatively, the voltage condition of each timing device can be selected such that, once a respective predetermined time period of the timing device has elapsed from a triggering event, the ramp output voltage generated by the respective ramp generator satisfies the respective voltage condition.

[0041] The control logic of each timing device can comprise a comparator configured to compare the ramp output voltage to a reference voltage (a reference voltage based on the voltage condition) and to set the common node to the first state or to release the common node from the first state based on the comparison.

[0042] In some embodiments, the system can further comprise a biasing device configured to bias the common node to the second state. Each timing device can further comprise a switching device connected to the common node, the switching device of each respective timing device being configured to set the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state.

[0043] Due to the action of the biasing device, the common node is switched to the second state as soon as it is released from the first state. At the same time, the switching device of each of the timing devices enables the timing device to pull or switch the common node to the first state. Thus, when none of the switching devices pulls the common node to the first state, the common node will be in the second state. When one or more of the timing devices switches the common node through the respective switching device, the common node will be set to the first state until all of the timing devices enable the common node to be released.

[0044] Additionally, a method for determining a location of a fault in a gate driver system is provided, the gate driver system comprising a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicative of a fault detected by the respective gate driver and an operational state. The method comprises:

[0045] setting the common node to the first state in response to the fault output node of one of the gate drivers being set to the fault state; and

[0046] releasing the common node from the first state in response to a predetermined time period elapsing from a triggering event, the predetermined time period being associated with the gate driver whose output node was set to the fault state, and

[0047] wherein the predetermined time period associated with each gate driver is different. BRIEF DESCRIPTION OF DRAWINGS

[0048] The application will now be described by way of example with reference to the accompanying drawings in which:

[0049] Figure 1is a circuit diagram showing a gate driver system according to a general prior art example;

[0050] Figure 2 is a simplified block diagram of a gate driver system according to an embodiment of the present application;

[0051] Figure 3 is a circuit diagram of a timing device according to an embodiment of the present application;

[0052] Figure 4 is a timing diagram of the circuit of Figure 3

[0053] Figure 5 is a circuit diagram of a gate driver system comprising the timing device of Figure 3

[0054] Figure 6 is a timing diagram of the general concept of the gate driver of Figure 5

[0055] Figure 7 is a timing diagram of a gate driver system according to an embodiment of the present application in case of simultaneous reporting of a fault by a plurality of gate drivers;

[0056] Figure 8 is a circuit diagram of a timing device according to another embodiment of the present application;

[0057] Figure 9 is a timing diagram of the circuit of Figure 8

[0058] Figure 10 is a circuit diagram of a gate driver system comprising the timing device of Figure 8

[0059] is a circuit diagram of a timing device according to a further embodiment of the present application; Figure 11

[0060] is a timing diagram of the circuit of Figure 12 Figure 11

[0061] Figure 13 is a circuit diagram of a timing device of Figure 11

[0062] is a circuit diagram of a timing device of Figure 14 Figure 11

[0063] Figure 15 is a circuit diagram of a timing device of Figure 11 ​​​​​​​​a circuit diagram of a timing device having a third device to adjust an associated predetermined time period;

[0064] Figure 16 is Figure 11 a circuit diagram of a timing device having a fourth device to adjust an associated predetermined time period; and

[0065] Figure 17 is a flowchart of a method for determining a location of a fault in a gate driver system according to an embodiment of the present invention.

[0066] It should be noted that the drawings are schematic and not drawn to scale. The relative dimensions and proportions of parts of these drawings have been exaggerated or minimized for the sake of clarity and convenience in the drawings. DETAILED DESCRIPTION

[0067] To understand the present disclosure, it is important to understand the workings of a typical gate driver system. Figure 1 is a circuit diagram of a gate driver system 1.

[0068] As shown, each gate driver 10a to 10f provides an input to the gate of a respective switch 12a to 12f (e.g. IGBT, GaN transistor or power MOSFET). Each gate driver 10a to 10f also provides the ability to report that a fault has been detected. The fault can for example be an internal fault of the gate driver 10a to 10f, can correspond to a switch 12a to 12f or a component connected to a switch 12a to 12f. In particular, each gate driver 10a to 10f reports the presence of a fault through a fault output node 14a to 14f. The fault output node 14a to 14f can be in an operational state (e.g. high or clear state) indicating that the gate driver has not detected a fault, or in a fault state (e.g. low state) indicating that the respective gate driver has detected a fault.

[0069] Each of the fault output nodes 14a to 14f is typically connected together via a common node 20. Thus, if any of the fault output nodes 14a to 14f is in the fault state, the common node 20 will report that a fault is present. Thus, it will not be possible to tell from the information on the common node 20 which gate driver 10a to 10f detected the fault.

[0070] In particular, each of the gate drivers 10a-f is generally configured to individually pull the common node 20 to a low state (e.g., ground) when they detect a fault. When the common node 20 is biased to a high state (e.g., VDD) by the biasing device 30, if none of the gate drivers 10a-f detect a fault, the common node 20 will be in the high state. This binary system makes it impossible to report which of the gate drivers 10a-f has detected and reported a fault.

[0071] Figure 2 A simplified block diagram illustrating an embodiment of the present application is shown. In particular, Figure 2 A gate driver system 100 is shown that enables identification of a gate driver 10a-c that has reported a fault through one common output node 20.

[0072] Similar to Figure 1 The gate driver system 100 includes a plurality of gate drivers 10a-c. As described above, each gate driver 10a-c has a fault output node 14 that can be switched between a fault state and a working state. Three gate drivers 10a-c are shown, but there can be only two gate drivers, or there can be more than three gate drivers.

[0073] Additionally, each of the gate drivers 10a-c is provided with a timing device 40a-c. Each timing device 40a-c is connected to the fault output node 14a-c of the respective gate driver 10a-c and to the common node 20. That is, each gate driver 10a-c has a timing device 40a-c connected between the fault output node 14a-c of the gate driver 10a-c and the common node 20. For clarity, all of the timing devices 40a-c are connected to the same common node 20.

[0074] Each timing device 40a-c can be implemented separately from the gate drivers 10a-c (e.g., connected to a pin of the gate driver 10a-c that outputs the fault signal as the fault output node 14a-c). Alternatively, one or more components of the timing device 40a-c can be implemented as part of the gate driver 10a-c, with the timing device 40a-c connected to an internal fault node of the gate driver 10a-c as the fault output node 14a-c.

[0075] The common node 20 can be switched between a first state and a second state. In the depicted case, the common node 20 is biased towards the second state by the biasing means 30 and can be switched / pulled to the first state by any of the timing means 40a to 40c. The first state in the depicted embodiment is a low state (i.e. a ground state). The second state in the depicted embodiment is a high state (i.e. VDD). However, the depicted embodiment can be modified such that the first state is a high state and the second state is a low state.

[0076] In some embodiments, the common node 20 can be connected to an I / O pin, enabling a user to monitor, detect and diagnose faults.

[0077] Each timing means 40a to 40c is configured to set the common node 20 to the first state in response to the fault output node 14a to 14c of the respective gate driver 10a to 10c being set to the fault state. In other words, when the gate driver 10a to 10c detects a fault, the fault output node 14a to 14c is set to the fault state. In turn, the timing means 40a to 40c associated with the gate driver 10a to 10c sets the common node 20 to the first state. In the depicted example, this is achieved by closing the switching means 50a to 50c, such that the common node 20 is pulled to the first (i.e. low) state.

[0078] Furthermore, each timing means 40a to 40c is configured to release the common node 20 from the first state in response to a predetermined time period elapsing from a trigger event. In the depicted example, this is achieved by opening the switching means 50a to 50c, such that the common node 20 can be pulled back to the second (i.e. high) state by the biasing means 30. In other words, the timing means 40a to 40c controls the switching means 50a to 50c to remove the short to ground of the common node 20 after a predetermined time period elapses from a trigger event.

[0079] In order to distinguish between the different gate drivers 10a to 10c, the predetermined time period of each timing means 40a to 40c is different. That is, each of the timing means 40a to 40c releases the common node from the first state after a different length of time from the same trigger event.

[0080] For the sake of clarity, the predetermined time period of each timing means 40a to 40c can be a specific length of time, or can be a range of times taking into account tolerances with external components. In any case, the predetermined time periods differ in that they can be distinguished from one another (i.e. if the predetermined time periods are ranges of times, these ranges of times will not overlap).

[0081] For example, if the first gate driver 10a detects a fault, the first timing device 40a can wait 1 second from the triggering event before releasing the common node 20. In the same system, if the second gate driver 10b detects a fault, the second timing device 40b can wait 2 seconds from the triggering event before releasing the common node 20.

[0082] Thus, by monitoring the common node 20 and determining the time between the triggering event and the release of the common node 20 from the first state, the gate driver 10a-c that detected the fault can be determined.

[0083] To this end, the gate driver system 100 can further comprise a controller 60 connected to the common node 20. The controller 60 is configured to measure the length of time between the triggering event and the switching of the common node 20 to the second state. The controller 20 then identifies the gate driver 10a-c corresponding to the detected fault based on the measured length of time and the predetermined time period of each respective timing device 40a-c.

[0084] In some implementations of the invention, the triggering event can be the common node 20 being set to the first state. In this case, the timing devices 40a-c set the common node 20 to the first state, delay for a predetermined time period, and then release the common node 20 from the first state when the respective fault output node 14a-c is set to the fault state. Of course, each timing device 40a-c delays for a different predetermined time period, and thus this delay can be monitored to determine the gate driver 10a-c that reported the fault.

[0085] In other implementations, the triggering event can be the fault output node 14a-c of the respective gate driver 10a-c being set to the working state. In other words, the triggering event is the moment at which the fault output node 14a-c is reset / cleared after being in the fault state. Thus, the triggering event can likewise be the generation of a reset signal. In this case, the timing devices 40a-c delay for a predetermined time period, and then release the common node 20 from the first state when the fault output node 14a-c is set to the working state. Of course, each timing device 40a-c delays for a different predetermined time period, and thus this delay can be monitored to determine the gate driver 10a-c that reported the fault.

[0086] Of course, implementations can have other triggering events that will be apparent to those skilled in the art. For example, the triggering event can be the occurrence of a user signal that starts the delay before the common node 20 is released from the first state.

[0087] Turning to Figure 3Fig. 2 shows a circuit diagram of an exemplary embodiment of a timing device 200 for a gate driver 10a to 10c according to an aspect of the present application. Figure 3 The timing device 200 of Fig. 2 acts upon a trigger event that sets the common node 20 into the first state. That is, Figure 3 The timing device 200 of Fig. 2 first sets the common node 20 into the first state, delays for a predetermined time period, and then releases the common node 20 from the first state. Figure 3 The operation of the timing device 200 of Fig. 2 is also referred to the timing diagram of Fig. 3. Figure 4 The operation of the timing device 200 of Fig. 2 is also referred to the timing diagram of Fig. 3.

[0088] The timing device 200 can be implemented in the gate drivers 10a to 10c. That is, the fault output nodes 14a to 14c of the gate drivers 10a to 10c can be internal, and Figure 3 Many of the components of the timing device 200 of Fig. 2 can be provided in the respective gate drivers 10a to 10c. Of course, each of these components can also be provided separately to the respective gate drivers 10a to 10c, wherein the fault output nodes 14a to 14c are fault output pins of the gate drivers 10a to 10c.

[0089] As shown, the timing device 200 is connected to the fault output pins 14 of the gate drivers 10a to 10c, and to the common node 20. The timing device 200 comprises a ramp generator 210, a control logic 220, and a switching device 230.

[0090] The ramp generator 210 is configured to generate a ramp output voltage in response to the fault output node 14 of the respective gate driver 10a to 10c being set into the fault state.

[0091] In particular, the ramp generator 210 comprises a capacitor 212, a current source 214, and a switch 216 arranged such that the current source 214 can charge the capacitor 212 in response to the fault output node 14 of the respective gate driver 10a to 10c being set into the fault state. Thus, when the fault output node 14 of the gate driver 10a to 10c is in the fault state, the switch 216 of the ramp generator 210 is closed. The current source 214 starts charging the capacitor 212 such that the output voltage rises. The rising output voltage is provided to an input of the control logic 220.

[0092] The current source 214 can be connected in series with the capacitor 212, or can be connected in parallel with the capacitor 212. Furthermore, the current source 214 can in principle also be implemented as a resistor connected to a voltage source.

[0093] The profile of the output voltage of the ramp generator 210 can be selected by a suitable selection of the capacitance of the capacitor 212 and / or the amperage of the current source 214.

[0094] Of course, the depicted ramp generator 210 is merely by way of example, and other topologies of the ramp generator 210 are possible and would readily be implemented. For example, the ramp generator 210 can provide a decreasing voltage output. Likewise, the output voltage of the ramp generator 210 can vary in a substantially linear manner, or can vary in a non-linear manner. The ramp generator 210 only needs to generate a monotonically and predictably varying voltage to provide to the input of the control logic 220.

[0095] The control logic 220 is configured to set the common node 20 to the first state in response to the fault output node 14 of the gate driver 10a-c being set to the fault state and the ramp output voltage failing to satisfy the first voltage condition. In particular, in response to the fault output node 14 being set to the fault state, the control logic 220 closes the switch of the switching device 230 to pull the common node 20 to the low / ground state.

[0096] The control logic 220 is configured to then release the common node 20 from the first state in response to the ramp output voltage satisfying the first voltage condition. In particular, in response to the ramp output voltage satisfying the first voltage condition, the control logic 220 opens the switch of the switching device 230 to release the common node 20 from the low / ground state.

[0097] Additionally, the control logic 220 of the timing device 200 can also be configured to set the common node 20 to the first state in response to the ramp output voltage satisfying a second common voltage condition and the first voltage condition. In particular, in response to the ramp output voltage satisfying the first voltage condition and the second voltage condition, the control logic 220 closes the switch of the switching device 230 to set the common node 20 back to the low / ground state.

[0098] For example, the first voltage condition can be that the output voltage of the ramp generator 210 is 2V, and the second common voltage condition can be that the output voltage of the ramp generator 210 is 2.5V. The ramp generator 210 can have an output voltage that increases linearly by 0.5V per second. Thus, (once the fault output node 14 of the respective gate driver 10a-c is set to the fault state) the common node 20 is set to the first state at 0s. At 4s, the common node 20 is released from the first state. At 5s, the common node 20 is set to the first state. Of course, these parameter values are merely by way of illustrative example.

[0099] In general, the time period t between the common node 20 being set to the first state and being released from the first state (i.e. the predetermined time period of the timing device 200) can be formulated as:

[0100]

[0101] where C is the capacitance of the capacitor 212, I is the amperage of the current source 214, and the first voltage condition is satisfied once the voltage across the capacitor 212 exceeds VREF1.

[0102] As can be seen from [1], the first voltage condition and / or the ramp generator output voltage 210 (e.g. the capacitance of the capacitor 212 and / or the amperage of the current source 214) can be varied in order to set the predetermined time period of the timing device 200. Thus, each timing device 200 of the gate driver system can have one or more different voltage conditions and ramp generator output voltages to ensure that each timing device 200 has a different predetermined time period.

[0103] Figure 4 is Figure 3 a timing diagram of the timing device 200 of

[0104] During normal operation (i.e. when no fault has been detected by the gate driver 10a-c), the fault output node 14 remains in a low (i.e. working) state. Thus, there is no voltage across the capacitor 212. After passing through the logic gates and comparators, the output of the control logic 220 means that the switch 230 is turned off and thus the common node 20 remains in the released state (and thus in the second state due to the biasing device 30). In particular, since the fault output node is low (whereas the first comparator 222 is high), the output of the AND gate 224 is low, and since there is no voltage across the capacitor 212, the output of the second comparator 226 is low. Thus, the output of the OR gate 228 is low.

[0105] Once the fault output node 14 is set to a high (i.e. fault) state, the switch 216 is turned on and the common node 20 is pulled to the first state. This is because the fault output node 14 is in a high state, resulting in a high output of the AND gate 224 (where the first comparator 222 remains in a high state) and a high output of the OR gate 228. At this point, the switch 216 of the ramp generator 210 is closed, and thus the current source 214 starts charging the capacitor 212, such that the voltage output from the ramp generator 210 increases. While the voltage across the capacitor 212 remains below the first voltage threshold VREF1 (i.e. the first voltage condition is not satisfied), the first comparator 222 remains in a high state. While the voltage across the capacitor 212 remains below the second voltage threshold VREF2 (i.e. the second common voltage condition is not satisfied), the second comparator 226 remains low.

[0106] Then, once the voltage across the capacitor 212 exceeds the first voltage threshold VREF1 (i.e. the first voltage condition is met), the output of the first comparator 222 falls to a low level. The output of the AND gate 224 thus becomes low, and the output of the OR gate 228 also becomes low. The switch of the switching means 230 is thus opened, releasing the common node 20 from the first state. This should occur after a predetermined period of time (t) has elapsed since the fault output node 14 was set to the high (i.e. fault) state. Likewise, the second comparator 226 remains low while the voltage across the capacitor 212 remains below the second voltage threshold VREF2 (i.e. the second common voltage condition is not met).

[0107] Finally, once the voltage across the capacitor 212 exceeds the second voltage threshold VREF2 (i.e. the second common voltage condition is met), the output of the second comparator 226 becomes high. The output of the OR gate 228 thus becomes high, pulling the common node 20 to the first low state again.

[0108] The first falling edge of the signal present on the common node 20 should thus substantially match the predetermined period of time between the first rising edge of the signal present on the common node 20 and the first falling edge of the signal present on the common node 20.

[0109] Figure 5 A circuit diagram of a gate driver system according to an embodiment of the application is depicted, the gate driver system comprising a timing device 200a-c as Figure 3 depicted.

[0110] Each gate driver has an associated timing device 200a-c connected between the respective fault output pin and the common node 20. The common node 20 is biased to the high state (i.e. the second state) by a (shared) biasing means. When any of the fault output pins is set to the fault state, the respective timing device 200a-c will operate as described above.

[0111] Of course, each timing device 200a-c corresponds to a different predetermined period of time due to having a different first voltage condition or ramp generator output voltage profile as described above. This is indicated by the different reference numerals of the timing devices 200a-c. Figure 6, which represents the signal on the common node 20 when the first timing device 200a, the second timing device 200b, or the third timing device 200c is associated with a faulty output node set to a fault state. As can be seen, there is a difference between the time when the common node 20 is set to a low state and the time when the common node 20 is released from the low state to the high state (indicated as t1 to t3). By monitoring this time delay, the timing device 200a to 200c responsible for the signal on the common node 20 (and therefore the gate driver 10a to 10c reporting the fault) can be identified.

[0112] Assuming that more than one gate driver detects a fault at the same time, the common node 20 will be switched / pulled to the first state by more than one timing device 200a to 200c at the same time. Figure 7 , in which three timing devices 200a to 200c simultaneously switch the common node 20 to the first state.

[0113] In this case, the timing devices 200a to 200b configured with shorter predetermined time periods (e.g., t1 and t2) release the common node 20 from the first state. However, the common node 20 will remain in the first state because the timing device 200c with the longest predetermined time period (e.g., t3) will continue to pull the common node 20 to the first state. Therefore, only the gate driver with the longest predetermined time period will be able to be identified on the common node 20. This is Figure 7 As can be seen in FIG. 2 , the common node 20 returns to the second state only when all the timing devices 200 a to 200 c release the common node 20 from the first state.

[0114] However, in practice this should not be a problem as faults will likely need to be addressed one by one. Thus, once the issue that triggered the fault on the gate driver associated with the longest predetermined time period is resolved, the gate driver associated with the second longest predetermined time period will be identified.

[0115] Finally, if Figure 7 As shown, and according to Figure 6 As shown in the depicted circuit diagram, once the voltage output of the ramp generator satisfies the second common voltage condition, the common node 20 will be pulled / switched back to the first state.

[0116] Move to Figure 8 1 , there is shown a circuit diagram of an exemplary embodiment of a timing device 300 for gate drivers 10 a to 10 c according to another aspect of the present invention. Figure 8 The timing device 300 operates according to a trigger event, which is to set the fault output node 14 of the corresponding gate driver 10a to 10c to the working state. Figure 8The timing device 300 is configured to initially set the common node 20 to the first state, wait for a reset signal for resetting the faulty output node 14 to the working state, delay for a predetermined period of time, and then release the common node 20 from the first state. Figure 9 The timing diagram is used to illustrate Figure 8 operation.

[0117] Typically, when the fault state of the fault output pin / node 14 of the gate driver 10a to 10c is cleared (to the working state), the reset pin must be set to the (usually low) state for a defined time before being released to another (usually high) state. Therefore, the trigger event can be rewritten as the reset pin being reset to the second state after being set to the first state for a defined time period. Of course, in practice, this causes the fault output pin 14 of the gate driver 10a to 10c to be set to the working state (reset from the fault state), and therefore for simplicity, this can be considered a trigger event. In other words, the time measured between the trigger event and the common node 20 being released to the second state (to identify the gate driver reporting the fault) is the rising edge of the signal on the reset pin to the rising edge of the signal on the common node 20.

[0118] Alternatively, it may be the case that the triggering event and reset is when the reset pin is initially set to a low state, rather than when the reset pin is released to a high state (e.g., Figure 9 In other words, the trigger event is the presence of a falling edge on the reset pin, causing the fault output node / pin 14 to be set to an active state. Thus, the ramp generator 310 output can begin increasing from the time the reset pin is initially pulled to a (normally low) state.

[0119] As shown, the timing device 300 is connected to the fault output nodes 14 of the gate drivers 10a to 10c and the common node 20. The timing device 300 includes a ramp generator 310 and a control logic 320.

[0120] The ramp generator 310 is configured to generate a ramp output voltage in response to the fault output node 14 of the corresponding gate driver 10 a to 10 c being set to an active state.

[0121] Specifically, ramp generator 310 includes a capacitor 312 connected to ground, a first resistor 314 and a second resistor 316 connected in parallel and disposed between a voltage source and capacitor 312 , and a diode 318 that enables current to flow through second resistor 316 and capacitor 312 to ground.

[0122] The output of the ramp generator 310 can be connected to control logic 320 comprising a comparator 322 to control the common node 20 to be in the first state or the second state in dependence on the output of the ramp generator 310. However, as described in relation to Figure 10 the output of the ramp generator 310 can be connected to the bus node, the output of the ramp generator associated with the other gate driver can be connected to the bus node. In this case, the comparator 320 can be a common comparator which can be provided prior to input to the controller 60 for timing measurements, or as part of the controller 60.

[0123] Of course, the depicted ramp generator 310 is merely by way of example, and other topologies of the ramp generator 310 are possible and would readily be implemented. For example, the ramp generator 310 can provide a decreasing voltage output. The output voltage of the ramp generator 310 can vary in a substantially linear manner, or can vary in a non-linear manner. The ramp generator 310 only needs to generate a monotonically and predictably varying output voltage.

[0124] The switch 324 is connected across the capacitor, the switch 324 being controlled based on the state of the fault output node 14. Thus, as shown in the timing diagram of Figure 9 when the fault output node 14 of the gate driver is in the fault state, the switch 324 is closed. This discharges the capacitor 312, and thus pulls the common node 20 to ground (as the voltage across the capacitor 312, and thus the output of the ramp generator 310, no longer satisfies the voltage condition). That is, the voltage across the capacitor 312 falls below VREF, and thus the comparator 322 outputs a low signal. Then, when the fault output node 14 of the gate driver is reset to the operational state, the switch 324 is opened. Thus, the voltage source will charge the capacitor 312 through the first resistor 314 and the second resistor 316.

[0125] The time taken for the voltage across the capacitor 312 to reach VREF (i.e. to satisfy the voltage condition) will depend on the resistances of the first resistor 314 and the second resistor 316 and the capacitance of the capacitor 312. Thus, these values can be selected so as to achieve a desired predetermined time period for the individual timing device 300.

[0126] Figure 10 Circuit diagrams of gate driver systems according to embodiments of the application are depicted, the gate driver systems comprising timing devices 300a to 300c as Figure 8 depicted.

[0127] As shown, the ramp generator of each timing device 300a-c shares a common second resistor 316. Furthermore, the output of each timing device is connected to a bus node 330. In turn, the bus node 330 is connected to a common comparator 320. The comparator 320 is configured to provide a high or low output to the common node 20. The output of the comparator 320 can be connected directly to the common node 20, or can be connected to the gate of a switch of a switching device to control the state of the common node 20. In other words, the comparator compares the voltage on the bus node 330 to a reference voltage VREF, and then sets the common node 20 to a first state or releases the common node 20 from the first state based on the comparison.

[0128] In some embodiments, the comparator 320 can be part of the controller 60. That is, the bus node 330 can be connected to the comparator 320 as part of the controller 60 to measure the time elapsed from a triggering event. However, the comparator 320 can also be provided separately, with the output of the comparator being provided to the controller 60.

[0129] As a brief illustration, if any of the fault output nodes 14a-c enters the fault state, the switch of the associated timing device 300a-c will close. This will pull the bus node 330 to ground by creating a short to ground, while only the respective capacitor associated with the timing device 300a-c will be discharged. As a result, the voltage on the bus node 330 fails to satisfy the voltage condition VREF of the comparator 320, and the common node 20 will be pulled to the first state.

[0130] Then, when the switch of the timing device 300a-c opens (after the fault output node 14a-c is reset to the working state), the associated capacitor will recharge and the voltage on the bus node 330 will gradually increase. Once the voltage on the bus node 330 satisfies the voltage condition VREF of the comparator 320, the common node 20 will be released to the second state.

[0131] Preferably, the second resistor 316 has a much larger resistance than any of the first resistors of the timing devices 300a-c. Thus, the charging time of each of the capacitors can be determined by the respective first resistor.

[0132] Each of the capacitors of the timing devices 300a to 300c can have the same capacitance, while each of the first resistors of the timing devices 300a to 300c has a different resistance, so as to set the rise time of the ramp generator according to the respective predetermined time periods of the timing devices 300a to 300c. Alternatively, each of the first resistors of the timing devices 300a to 300c can have the same resistance, while each of the capacitors of the timing devices 300a to 300c has a different capacitance, so as to set the rise time of the ramp generator according to the respective predetermined time periods of the timing devices 300a to 300c. Of course, the resistance and capacitance values ​​of each of the timing devices 300a to 300c can be varied, but this may be more expensive and complex to implement (and therefore it may be preferable to only vary one of the resistance or capacitance between each timing device).

[0133] Move to Figure 11 , a circuit diagram of another exemplary embodiment of a timing device 400 for a gate driver system is shown. The timing device 400 operates based on a triggering event, which is the resetting of a stored fault indicator associated with the associated gate driver (e.g., via an SR latch 424). That is, the fault indicator is stored after the fault output node 14 of the corresponding gate driver 10a to 10c is set to a fault state. When the stored fault indicator is reset (e.g., to an operational indicator), a triggering event occurs. If the fault output node remains in the fault state when the reset occurs, the fault indicator continues to be stored, and the triggering event does not begin.

[0134] therefore, Figure 11 The timing device 400 initially sets the common node 20 to the first state, waits for a reset signal to reset the fault indicator, delays for a predetermined period of time, and then releases the common node 20 from the first state. Figure 12 The timing diagram is used to illustrate Figure 11 The operation of the timing device 400.

[0135] Figure 11 The timing device 400 can be implemented in / within the gate drivers 10a to 10c (similar to Figure 3 That is, the fault output node 14 of the gate drivers 10a to 10c may be an internal node of the gate drivers 10a to 10c (ie, not an output pin), and Figure 11 Many of the components of the timing device 400 may be provided in the gate drivers 10a to 10c. Of course, each of these components may also be provided separately to the gate drivers 10a to 10c, where the fault output node 14 is an output pin of the gate driver.

[0136] During normal operation of the gate drivers 10a-c, i.e. when no fault has been detected by the gate drivers 10a-c, the output switch of the timing device 400 remains open and thus the output of the timing device 400 does not pull the common node 20 to the first state.

[0137] When the internal fault signal on the fault output node 14 triggers the set of the SR latch 424, the fault indicator is stored such that the output Q of the SR latch 424 is set to high. When the output Q of the SR latch closes the switch 416 of the ramp generator 410, the capacitor 412 of the ramp generator 410 will be discharged. This causes the open-drain switch 430 to close (because the voltage across the capacitor 412 no longer satisfies the voltage condition of the comparator 422) and thus pulls the output of the timing device 400 to the low state (in turn, pulling the common node 20 to the low state).

[0138] When the reset pin 70 is pulled to the low state, a negative edge is generated at the clock input of the D flip-flop 426. Once the reset pin 70 is pulled high again, a positive edge will be generated at the clock input of the D flip-flop 426, the clock goes through '1' to the Q output because the D input of the D-FF 426 is permanently connected to '1'. Thus, as long as the fault output node 14 is also in the working state at that time, the SR latch 424 is prompted to reset, thus removing the fault indicator to the operating indicator.

[0139] When the SR latch 424 is reset, the switch 416 will be opened. The reset of the SR latch 424 also resets the D flip-flop 426.

[0140] Then, once the output voltage of the ramp generator 410 satisfies the voltage condition of the comparator 422 (i.e. once the output voltage exceeds the reference voltage value), the open-drain switch 430 will be opened, thus releasing the output of the timing device 400 from the low state.

[0141] In other words, the depicted timing device 400 comprises a ramp generator 410 configured to generate a ramp output voltage in response to a stored fault indicator being reset when the fault output node 14 of the respective gate driver 10a-c (in this case a node internal to the gate driver 10a-c) is in the working state.

[0142] To this end, the ramp generator 410 comprises a switch 416 which, when closed, discharges the capacitor 412, and a current source 414 which, when the switch 416 is open, charges the capacitor 412. The switch 416 is controlled by internal control logic (e.g. SR latch 424, D flip-flop 426, negative edge delay 428) which opens the switch 416 when a fault is detected by the gate drivers 10a-c, and closes the switch 416 in response to a valid reset signal of the gate drivers 10a-c on the reset pin 70.

[0143] The timing device 400 further comprises output control logic (e.g. comparator 422 and open drain output switch 430) configured to set the common node 20 (i.e. the output pin of the gate drivers 10a-c) to a first state in response to the ramp output voltage failing to satisfy the voltage condition (i.e. when the voltage across the capacitor is less than the threshold voltage VREF). The output control logic further releases the common node 20 from the first state in response to the ramp output voltage satisfying the voltage condition.

[0144] Of course, the components of the ramp generator 410 can be selected such that the output voltage / voltage across the capacitor 412 of the ramp generator 410 satisfies the voltage condition after a predetermined length of time, which differs between the timing devices 400. In particular, the capacitance of the capacitor 412 and / or the amperage of the current source 414 can be selected to satisfy this purpose. Alternatively, the voltage condition implemented by the comparator 422 of the control logic can be selected such that the ramp generator 410 satisfies the voltage condition after a predetermined length of time.

[0145] In the depicted embodiment, the predetermined period of time can be adjusted by the adjustment pin 80. This will thus enable a user to select the predetermined period of time associated with each gate driver 10a-c. In particular, components can be connected to the adjustment pin 80 to select the predetermined period of time.

[0146] In a first implementation, as Figure 13 depicted, the capacitor 412 of the ramp generator 410 can be provided by the adjustment pin 80. That is, instead of the capacitor 412 being an internal component, the adjustment pin 80 can be connected to the current source 414, and an external capacitor 412 can be connected between the adjustment pin 80 and ground.

[0147] In another implementation, as Figure 14As depicted, the reference voltage VREF of the comparator 422 can be provided by a reference current source 440 (which can be consistent between different timing devices) and an external resistor 442 can be connected to the regulation pin 80. Thus, the reference voltage VREF of the comparator 422 can be selected based on the resistance of the external resistor 442.

[0148] Alternatively, as Figure 15 depicted, the reference voltage VREF of the comparator 422 can be provided by a voltage divider 450 regulating the bus voltage VDD. Thus, the reference voltage VREF of the comparator 422 can be individually selected for each timing device 400 by the voltage divider 450 providing different voltage divisions (i.e. having different resistance values). Alternatively, the voltage divider 450 can be selected in place of the voltage source providing the appropriate reference voltage VREF.

[0149] Finally, as Figure 16 depicted, the current source 414 can be implemented as a current mirror 460, wherein the current provided by the current mirror 460 is regulated by an external resistor 462. In this case, the current provided by the current mirror 460 will depend on the resistance of the external resistor 462, which can be selected to provide different currents to each of the timing devices.

[0150] Each of the timing devices 400a to 400e can be implemented in the gate driver system 100 as described above, wherein different timing devices 40a to 40c connected to different respective gate drivers 10a to 10c are associated / configured to have different predetermined time periods.

[0151] Figure 17 A flowchart of a method 500 for determining the location of a fault in a gate driver system according to an embodiment of the application is shown. The gate driver system comprises a plurality of gate drivers as described with reference to Figure 1 and Figure 2 Each gate driver has a fault output node (which can be a fault pin of the gate driver or an internal node of the gate driver) which is switchable between a fault state indicating that a fault is detected by the respective gate driver and an operational state.

[0152] In particular, the step 510 involves setting the common node to a first state in response to the fault output node of one of the gate drivers being set to the fault state. That is, if any of the fault output nodes is set to the fault state, the common node is set to the first state.

[0153] Then, in step 520, the common node is released from the first state in response to a predetermined time period elapsing from the triggering event. The amount of time between the triggering event and the release of the common node (i.e. the predetermined time period) depends on the gate driver that has reported a fault. In other words, the predetermined time period taken to release the common node is associated with the gate driver having a fault output node set to the fault state.

[0154] As each gate driver is associated with a different predetermined time period, the amount of time between the triggering event and the release of the common node can be measured to determine / identify the gate driver that has reported a fault.

[0155] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. An embodiment can be implemented by means of hardware comprising several distinct elements, and by means of a combination of several distinct elements. In a device claim enumerating several means, the enumerated means can be considered selective among the several means described or claimed. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. The word "comprising" is not used as a limitation in the claims. In the claims, the word "including" is used as equivalent to "comprising". The word "a" or "an" preceding an element in a claim does not exclude the presence of a plurality of such elements. It is noted that the claims can be drafted to exclude any optional features since certain features of the embodiments are, optionally, not intended to be essential to an optimal practice.

[0156] The following embodiments are disclosed:

[0157] 1. A gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), each gate driver having a fault output node (14a, 14b, 14c) switchable between a fault state indicative of a fault detected by the respective gate driver and an operational state, the system comprising:

[0158] a common node (20) switchable between a first state and a second state;

[0159] a timing device (40a, 40b, 40c) for each of the gate drivers, each timing device being connected to the fault output node of the respective gate driver and to the common node, each timing device being configured to:

[0160] set the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state; and

[0161] release the common node from the first state in response to a predetermined time period elapsing from a triggering event, wherein the predetermined time period of each timing device is different.

[0162] 2. The system according to embodiment 1, further comprising a controller (60) connected to the common node (20) and configured to:

[0163] measure a length of time between the triggering event and the common node switching to the second state; and

[0164] identify the gate driver (10a, 10b, 10c) corresponding to the detected fault based on the measured length of time and a predetermined time period of each respective timing device (40a, 40b, 40c).

[0165] 3. The system according to embodiment 1 or 2, wherein the triggering event is the common node (20) being set to the first state; or a fault output node (14a, 14b, 14c) of the respective gate driver (10a, 10b, 10c) being set to the operational state.

[0166] 4. The system according to embodiment 1 or 2, wherein the triggering event is the common node (20) being set to the first state, and wherein each timing device (200) comprises:

[0167] a ramp generator (210) configured to generate a ramp output voltage in response to the fault output node (14) of the respective gate driver (10a to 10c) being set to the fault state; and

[0168] control logic (220) configured to:

[0169] set the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state and the ramp output voltage failing to satisfy a first voltage condition; and

[0170] release the common node from the first state in response to the ramp output voltage satisfying the first voltage condition.

[0171] 5. The system according to embodiment 4, wherein the ramp generator (210) of each timing device is configured to generate the respective ramp output voltage such that the respective ramp output voltage satisfies the first voltage condition once the respective predetermined time period of the timing device (200) has elapsed from the triggering event, and wherein the first voltage condition of each timing device is the same.

[0172] 6. The system according to embodiment 4, wherein the first voltage condition of each timing device (200) is selected such that the ramp output voltage generated by the respective ramp generator (210) satisfies the respective first voltage condition once the respective predetermined time period of the timing device has elapsed from the triggering event.

[0173] 7. The system according to any one of embodiments 4 to 6, wherein the control logic (220) of each timing device is further configured to set the common node (20) to the first state in response to the ramp output voltage satisfying the second common voltage condition and the first voltage condition.

[0174] 8. The system according to any one of embodiments 4 to 7, wherein the ramp generator (210) comprises:

[0175] a capacitor (212);

[0176] a current source (214); and

[0177] a switch (216) arranged to enable the current source to charge the capacitor in response to the fault output node (14) of the respective gate driver (10a to 10c) being set to the fault state.

[0178] 9. The system according to embodiment 8, wherein the capacitance of the capacitor (212) and / or the amperage of the current source (214) of each ramp generator (210) is selected such that the respective ramp output voltage satisfies the first voltage condition once a respective predetermined time period of the timing device has elapsed from the triggering event, and wherein the first voltage condition of each timing device is identical.

[0179] 10. The system according to any one of embodiments 1 to 2, wherein the triggering event is the fault output node (14) of the respective gate driver (10a to 10c) being set to the working state, and wherein each timing device (300, 400-1, 400-2, 400-3, 400-4, 400-5) comprises:

[0180] a ramp generator (310, 410) configured to generate a ramp output voltage in response to the fault output node (14) of the respective gate driver (10a to 10c) being set to the working state; and

[0181] control logic (320, 420) configured to:

[0182] set the common node (20) to the first state in response to the fault output node of the respective gate driver being set to the fault state and the ramp output voltage failing to satisfy the voltage condition; and

[0183] release the common node from the first state in response to the ramp output voltage satisfying the voltage condition.

[0184] 11. The system of embodiment 10, wherein the ramp generator (310, 410) of each timing device (300, 400-1, 400-2, 400-3, 400-4, 400-5) is configured to generate a respective ramp output voltage such that the respective ramp output voltage satisfies the voltage condition once a respective predetermined time period of the timing device has elapsed from a triggering event, and wherein the voltage condition of each timing device is the same.

[0185] 12. The system of embodiment 10, wherein the voltage condition of each timing device (300, 400-1, 400-2, 400-3, 400-4, 400-5) is selected such that the ramp output voltage generated by the respective ramp generator (310, 410) satisfies the respective voltage condition once a respective predetermined time period of the timing device has elapsed from a triggering event.

[0186] 13. The system of any one of embodiments 10 to 12, wherein the control logic (320, 420) of each timing device comprises: a comparator (322, 422) configured to:

[0187] compare the ramp output voltage to a reference voltage (VREF), the reference voltage being based on the voltage condition;

[0188] set the common node (20) to the first state or release the common node from the first state based on the comparison.

[0189] 14. The system of any one of embodiments 1 to 13, further comprising: a biasing device (30) configured to bias the common node (20) to the second state, and wherein each timing device (40a, 40b, 40c) further comprises a switching device (50a, 50b, 50c) connected to the common node, the switching device of each respective timing device being configured to:

[0190] set the common node to the first state in response to the fault output node of the respective gate driver being set to the fault state.

[0191] 15. The system of any one of embodiments 1 to 14, wherein the first state is a low state and the second state is a high state.

[0192] 16. A method for determining a location of a fault in a gate driver system (100), the gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), each gate driver having a fault output node (14a, 14b, 14c) switchable between a fault state indicative of a fault detected by the respective gate driver and an operational state, the method comprising:

[0193] setting (510) the common node (20) to a first state in response to the fault output node of one of the gate drivers being set to a fault state; and

[0194] releasing (520) the common node from the first state in response to a predetermined time period elapsing from the triggering event, the predetermined time period being associated with the gate driver for which the fault output node was set to the fault state, and

[0195] wherein the predetermined time period associated with each gate driver is different.

Claims

1. A gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), each gate driver having a fault output node (14a, 14b, 14c) switchable between a fault state and an operating state, the fault state indicating a fault detected by the corresponding gate driver, the gate driver system comprising: a common node (20) capable of switching between a first state and a second state; a timing device (40a, 40b, 40c) for each of the gate drivers, each timing device being connected to a fault output node of the corresponding gate driver and the common node, each timing device being configured to: In response to a fault output node of the corresponding gate driver being set to the fault state, setting the common node to the first state; and The common node is released from the first state in response to a predetermined time period having passed since a triggering event, wherein the predetermined time period for each timing device is different from one another.

2. The gate driver system of claim 1 , further comprising a controller ( 60 ) connected to the common node ( 20 ) and configured to: measuring the length of time between the triggering event and the switching of the common node to the second state; and The gate driver (10a, 10b, 10c) corresponding to the detected fault is identified based on the measured length of time and a predetermined time period of a corresponding timing device (40a, 40b, 40c).

3. The system according to claim 1 or 2, wherein: The trigger event is that the common node (20) is set to the first state; or the fault output node (14a, 14b, 14c) of the corresponding gate driver (10a, 10b, 10c) is set to the operating state.

4. The gate driver system according to any one of claims 1 to 3, wherein: The triggering event is the common node (20) being set to the first state, and wherein each timing device (200) comprises: A ramp generator (210) is configured to generate a ramped output voltage in response to a fault output node (14) of the corresponding gate driver (10a, 10b, 10c) being set to the fault state; and Control logic (220) configured to: setting the common node to the first state in response to the fault output node of the corresponding gate driver being set to a fault state and the ramped output voltage failing to satisfy a first voltage condition; and The common node is released from the first state in response to the ramped output voltage satisfying the first voltage condition.

5. The gate driver system according to claim 4, wherein: The ramp generator (210) of each timing device is configured to generate a corresponding ramped output voltage such that once a corresponding predetermined time period of the timing device (200) has elapsed since the triggering event, the corresponding ramped output voltage satisfies the first voltage condition, and wherein the first voltage condition of each timing device is the same.

6. The gate driver system according to claim 4, wherein: The first voltage condition of each timing device (200) is selected such that once the corresponding predetermined time period of the timing device has elapsed from the triggering event, the ramp output voltage generated by the corresponding ramp generator (210) satisfies the corresponding first voltage condition.

7. The gate driver system according to any one of claims 4 to 6, wherein: The control logic (220) of each timing device is further configured to set the common node (20) to the first state in response to the ramped output voltage satisfying a second common voltage condition and the first voltage condition.

8. The gate driver system according to any one of claims 4 to 7, wherein: The ramp generator (210) comprises: capacitor (212); a current source (214); and A switch (216) is arranged to enable the current source to charge the capacitor in response to a fault output node (14) of the corresponding gate driver (10a, 10b, 10c) being set to the fault state.

9. The gate driver system according to claim 8, wherein: The capacitance of the capacitor (212) and / or the amperage of the current source (214) of each ramp generator (210) is selected such that the respective ramp output voltage satisfies the first voltage condition once a respective predetermined time period of the timing device has elapsed from the triggering event, and wherein the first voltage condition of each timing device is the same.

10. The gate driver system according to any one of claims 1 to 3, wherein: The triggering event is that the fault output node (14) of the corresponding gate driver (10a, 10b, 10c) is set to the working state, and wherein each timing device (300, 400-1, 400-2, 400-3, 400-4, 400-5) comprises: a ramp generator (310, 410) configured to generate a ramped output voltage in response to a fault output node (14) of the corresponding gate driver (10a, 10b, 10c) being set to the operating state; and Control logic (320, 420) configured to: setting the common node (20) to the first state in response to the ramped output voltage failing to satisfy a first voltage condition; and The common node is released from the first state in response to the ramped output voltage satisfying a first voltage condition.

11. The gate driver system according to claim 10, wherein: The ramp generator (310, 410) of each timing device (300, 400-1, 400-2, 400-3, 400-4, 400-5) is configured to generate a corresponding ramp output voltage such that once a corresponding predetermined time period of the timing device has elapsed from the trigger event, the corresponding ramp output voltage satisfies the first voltage condition, and wherein the first voltage condition of each timing device is the same.

12. The gate driver system according to claim 10, wherein: The first voltage condition of each timing device (300, 400-1, 400-2, 400-3, 400-4, 400-5) is selected so that once the corresponding predetermined time period of the timing device has elapsed from the triggering event, the ramp output voltage generated by the corresponding ramp generator (310, 410) meets the corresponding first voltage condition.

13. The gate driver system according to any one of claims 10 to 12, wherein: The control logic (320, 420) of each timing device includes a comparator (322, 422) configured to: comparing the ramped output voltage to a reference voltage, the reference voltage being based on the first voltage condition; Based on the comparison, the common node (20) is set to the first state or released from the first state.

14. The gate driver system according to any one of claims 1 to 13, further comprising biasing means (30) configured to bias the common node (20) to the second state, and wherein, Each timing device (40a, 40b, 40c) further comprises a switching device (50a, 50b, 50c) connected to the common node, the switching device of each timing device being configured to: In response to the fault output node of the corresponding gate driver being set to the fault state, the common node is set to the first state.

15. The gate driver system according to any one of claims 1 to 14, wherein: The first state is a low state, and the second state is a high state.

16. A method for determining a location of a fault in a gate driver system (100), the gate driver system (100) comprising a plurality of gate drivers (10a, 10b, 10c), each gate driver having a fault output node (14a, 14b, 14c) switchable between a fault state and an operational state, the fault state indicating a fault detected by the corresponding gate driver, the method comprising: In response to the fault output node of the corresponding gate driver being set to the fault state, setting (510) the common node (20) to a first state; as well as releasing the common node from the first state in response to a predetermined time period having elapsed from a triggering event, the predetermined time period being associated with a gate driver having a faulty output node set to the faulty state, and The predetermined time period associated with each gate driver is different from one another.

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