A FIR filter circuit structure

Abstract

A FIR filter circuit structure comprises: a channel control unit generates a first control signal and a second control signal according to a filter quantity and an order defined by a user; a routing unit transmits filter data received by a filter data channel unit to a multiply-add unit array based on the first control signal; the multiply-add unit array comprises N multiply-add units, and each multiply-add unit is connected through a data selector; a channel control register unit is connected to a selection port of the data selector, and the channel control register unit controls a data channel of the multiply-add unit array through the data selector based on the second control signal; and a filter result operation unit adds multiply-add results of corresponding multiply-add units to obtain a filter result of a corresponding filter. The application can define a multiply-add unit structure of a filter circuit according to user requirements, and configure a FIR filter circuit with low circuit resource occupation ratio and fast operation speed.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor, and particularly relates to a FIR filter circuit structure. BACKGROUND

[0002] As a signal processing technology, digital filtering technology is an indispensable key technology in the field of communication, and is researched by many scholars due to its wide application in the field of digital signal processing. The digital filtering technology is a method of performing mathematical operations on signals to attenuate or amplify the signals, and the processing object is a digital signal. A device with the digital filtering technology is called a digital filter.

[0003] There are many classifications of digital filters. According to the time domain characteristics of the impulse response of the digital filter, the digital filter can be divided into two types, namely, a finite impulse response filter (FIR) and an infinite impulse response filter (IIR). Among them, the FIR filter is a stable filter with no feedback structure and easy-to-implement hardware, and it also meets the coefficient symmetry, so the filtered signal is not easy to appear phase distortion, and therefore the FIR filter is widely used.

[0004] Specifically, the output of the FIR filter is the convolution of the input signal and a set of weight coefficients (or impulse response). The FIR filter adopts a multiplication and accumulation operation mode for the input digital signal to attenuate the interference signal.

[0005] At present, the structure of the implementation circuit of the FIR digital filter is divided into two types, namely, an FIR filter based on a multiplier structure and an FIR filter based on a distributed algorithm, and an FIR filter structure based on serial multiplication and accumulation has only one multiplication and accumulation unit, and all filtering operations are realized through the multiplication and accumulation unit. The structure has the advantages of simple structure, less occupation of hardware resources, only one multiplication and accumulation unit, and low cost, but has the disadvantage of very low throughput rate, and it takes multiple clock cycles to complete one output operation. The output interval is sometimes limited by the filter order. Although a high-frequency clock can reduce the processing delay, it is still limited by the running speed of the multiplier. The FIR filter structure based on the full-parallel multiplication and accumulation unit realizes the core of completing all multiplication operations in one clock cycle and adding the multiplication operation results to output. The FIR filter with the full-parallel multiplier structure has the advantages of high data throughput rate, and one filter output result can be obtained after one clock cycle. The disadvantage is that the structure is complex, occupies a lot of hardware resources, and has high cost.

[0006] In the use scenario of the filter, the case of using multiple filters at the same time is encountered, such as a multi-band equalizer in the field of audio processing, which divides an audio signal into multiple frequency bands, adjusts the gain or compression of each frequency band separately, and then mixes and outputs. In order to achieve the above function, the multi-band equalizer needs to pass the audio signal through multiple FIR filters to obtain audio signals of different frequencies. The mature FIR filter products on the market can only realize the function of one filter. If multiple different configuration filters need to be implemented at the same time, multiple FIR filters need to be instantiated in the system, which is easy to cause waste of system circuit resources. SUMMARY

[0007] The application provides an FIR filter circuit structure, which can customize the multiply-add unit structure of the filter circuit according to user needs, and configure an FIR filter circuit with low circuit resource occupation ratio and fast operation speed.

[0008] Other purposes and advantages of the application can be further understood from the technical features disclosed in the application.

[0009] In order to achieve one or part or all of the above purposes or other purposes, the application provides an FIR filter circuit structure.

[0010] An FIR filter circuit structure comprises:

[0011] The path control unit generates a first control signal and a second control signal according to the number and order of filters customized by the user;

[0012] The routing unit transmits the filter data received by the filter data channel unit to the multiply-add unit array based on the first control signal;

[0013] The multiply-add unit array comprises N multiply-add units, and each multiply-add unit is connected through a data selector;

[0014] The path control register unit is connected to the selection port of the data selector, and the path control register unit controls the data path of the multiply-add unit array through the data selector based on the second control signal;

[0015] The filter result operation unit adds the multiply-add results of the corresponding multiply-add units to obtain the filter result of the corresponding filter.

[0016] The path control unit is provided with three input signals and three output signals;

[0017] The first input signal is the number of filters customized by the user;

[0018] The second input signal is the order of the filter customized by the user;

[0019] The third input signal is the order of the multiplication-addition unit corresponding to the filter;

[0020] The second input signal and the third input signal are one-dimensional arrays with a length of 128.

[0021] The three-way output signal includes a first control signal, a second control signal, and a test signal.

[0022] The test signal indicates whether the number of filters and the order defined by the user meet the specification of the circuit structure. If not, the test signal outputs corresponding error information.

[0023] The circuit structure further includes:

[0024] a coefficient addressing unit;

[0025] The filter coefficients are loaded into the filter coefficient storage queue of the multiplication-addition unit through the coefficient addressing unit.

[0026] The path control register unit includes N-1 registers;

[0027] The register input end is connected to the path control unit and receives the second control signal generated by the path control unit;

[0028] The register output end is connected to the selection port of the data selector in the multiplication-addition unit array, and the data path of the multiplication-addition unit array is controlled through the data selector;

[0029] The multiplication-addition unit array includes N multiplication-addition units and N-1 data selectors connected to the multiplication-addition units;

[0030] The A port of the data selector receives the corresponding filter data transmitted by the routing unit;

[0031] The B port of the data selector is connected to the filter data output end of the previous multiplication-addition unit;

[0032] The output end of the data selector is connected to the filter data input end of the next multiplication-addition unit;

[0033] The multiplication-addition unit filter coefficient input end is connected to the coefficient addressing unit, receives the corresponding filter coefficient and stores it to the filter coefficient storage queue.

[0034] The filter data channel unit includes 128 filter data channels, and the filter data channels are connected to the input end of the routing unit.

[0035] The multiplication-addition unit includes a filter data storage queue, a filter coefficient storage queue, a multiplier, and an adder.

[0036] The filter data storage queue is used for storing filter data.

[0037] The filter coefficient storage queue is used for storing filter coefficients.

[0038] The user can configure the depth of the filter data storage queue and the filter coefficient storage queue through a register, and the depth of the filter data storage queue and the filter coefficient storage queue is the same.

[0039] The filter data is sequentially written into the filter data storage queue and sequentially read out.

[0040] The filter coefficients are written into the filter coefficient storage queue and circulate in and out.

[0041] The multiply-add unit array comprises 128 multiply-add units and 127 data selectors.

[0042] The depth of the filter coefficient storage queue is not higher than 16.

[0043] Compared with the prior art, the beneficial effects of the present application mainly include:

[0044] The present application provides a FIR filter circuit structure, which can customize the multiply-add unit structure of the filter circuit according to the user's needs, and configure a FIR filter circuit with low circuit resource occupation ratio and fast operation speed.

[0045] In order to make the above and other objects, features and advantages of the present application more apparent and understandable, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0047] Figure 1 A FIR filter circuit structure schematic diagram provided by the embodiment of the present application.

[0048] Figure 2 A multiply-add unit schematic diagram provided by the embodiment of the present application.

[0049] Figure 3 A user-defined FIR filter circuit structure schematic diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0050] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0051] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0052] Example:

[0053] like Figure 1 As shown, an FIR filter circuit structure includes: a path control unit, a routing unit, a filter data channel, a multiply-accumulate unit array, a path control register unit, a coefficient addressing unit, and a filter result calculation unit;

[0054] The path control unit generates a first control signal and a second control signal based on the number and order of filters defined by the user.

[0055] Based on the first control signal, the routing unit transmits the filtered data received by the filtered data channel to the multiply-accumulate unit array accordingly;

[0056] The multiply-accumulate unit array consists of N multiply-accumulate units, and each multiply-accumulate unit is connected to the others through a data selector.

[0057] The path control register unit is connected to the selection port of the data selector, and the path control register unit controls the data path of the multiply-accumulate unit array through the data selector based on the second control signal.

[0058] The filter coefficients are loaded into the filter coefficient storage queue of the multiply-accumulate unit through the coefficient addressing unit;

[0059] The filtering result processing unit adds the multiplication and addition results of the corresponding multiply-add unit to obtain the filtering result of the corresponding filter.

[0060] like Figure 1 As shown, the access control unit is equipped with three input signals and three output signals;

[0061] The first input signal is the number of user-defined filters; the second input signal is the order of the user-defined filters; the third input signal is the order of the multiply-accumulate unit corresponding to the filter; wherein, the second input signal and the third input signal are a one-dimensional array of length 128;

[0062] The three output signals include: a first control signal, a second control signal, and a test signal; the test signal indicates whether the number and order of the user-defined filters meet the specifications of the circuit structure; if not, the test signal outputs the corresponding error information.

[0063] like Figure 1 As shown, the path control register unit has N-1 registers; the register input is connected to the path control unit and receives the second control signal generated by the path control unit; the register output is connected to the selection port of the data selector in the multiply-accumulate unit array and controls the data path of the multiply-accumulate unit array through the data selector.

[0064] Specifically, the multiply-accumulate unit array includes N multiply-accumulate units and N-1 data selectors connected to the multiply-accumulate units; the A port of the data selector receives the corresponding filtered data transmitted by the routing unit; the B port of the data selector is connected to the filtered data output of the previous multiply-accumulate unit; the output of the data selector is connected to the filtered data input of the next multiply-accumulate unit; the filter coefficient input of the multiply-accumulate unit is connected to the coefficient addressing unit, receives the corresponding filter coefficients, and stores them in the filter coefficient storage queue. The filtered data channel unit includes 128 filtered data channels, which are connected to the inputs of the routing units respectively.

[0065] like Figure 2 As shown, the multiply-accumulate unit includes a filter data storage queue, a filter coefficient storage queue, a multiplier, and an adder; the filter data storage queue is used to store filter data; the filter coefficient storage queue is used to store filter coefficients; the user can configure the depth of the filter data storage queue and the filter coefficient storage queue through registers, and the depth of the filter data storage queue and the filter coefficient storage queue are the same.

[0066] In this process, the filtered data is written sequentially into the filtered data storage queue and then read out sequentially; the filter coefficients are written into the filter coefficient storage queue and then cyclically added to and removed from it.

[0067] The multiply-accumulate unit array of this application includes 128 multiply-accumulate units and 127 data selectors; the depth of the filter coefficient storage queue is no more than 16.

[0068] This circuit device has a total of 128 filtered data channels (CH1-CH128), each of which can receive a set of filtered data. Therefore, this circuit device can achieve the filtering effect of up to 128 filters. The 128 filtered data channels enter the routing unit, which routes the filtered data in a specific filtered data channel to a specific data selector (MUX) according to the Routing_ctrl signal output by the path control unit.

[0069] The routing control unit is responsible for planning the data path of the array of multiply-add units according to the number and order of the filters customized by the user. The routing control unit has three groups of input signals and three groups of output signals. The three groups of input signals are: Filter_num, Filter_order, and Mac_order. The Filter_num signal indicates the number of filters to be customized by the user. The Filter_order is a one-dimensional array with a length of 128, and represents the order of the filters. The element at the i-th position in the array represents the total order of the i-th filter. The Mac_order is also a one-dimensional array with a length of 128, and represents the order of the multiply-add units. The element at the i-th position in the array represents the order of the multiply-add unit that implements the i-th filter.

[0070] The three groups of output signals of the routing control unit are: Routing_ctrl, MUX_ctrl, and Error_output. The Routing_ctrl signal contains the routing information between the filter data in the filter data path and the A terminal of the data selector. The MUX_ctrl signal contains the control line information of the data selector. The Error_output signal indicates whether the number and order of the filters customized by the user exceed the upper limit of the circuit device. The circuit device supports a maximum of 128 filters, and the total order of all filters is a maximum of 2048. If the number and order of the filters customized by the user meet the specifications of the circuit device, the value of the Error_output signal is "2'b00". If the number of filters exceeds 128, the value of the Error_output signal is "2'b01". If the total order of the filters exceeds 2048, the value of the Error_output signal is "2'b10".

[0071] For example, the user customizes three filters. The first filter has a total order of 128 and is implemented by an 8-order multiply-add unit. The second filter has a total order of 64 and is implemented by a 16-order multiply-add unit. The third filter has a total order of 30 and is implemented by a 5-order multiply-add unit.

[0072] Therefore, the user needs to define the following RTL code:

[0073] assign Filter_num='d3;

[0074] assign Filter_order=['d128,'d64,'d30,0,0,0,…,0];

[0075] assign Mac_order=['d8,'d16,'d5,0,0,0,…,0];

[0076] After the three groups of input signals enter the path control unit, the path control unit first determines whether the three filters customized by the user meet the circuit device specification. If not, the Error_output outputs the corresponding error information. If yes, the user customizes 3 filters in total, filter 1 has 128 orders, and is operated by 8 order multiplier-adder units. Therefore, filter 1 needs 16 8-order multiplier-adder units to be implemented, the first multiplier-adder unit is MAC1, and the last multiplier-adder unit is MAC16. The filter data in the filter data channel CH1 is routed to the Data end of MAC1, and the data selector B end between MAC1-MAC16 is turned on. Filter 2 has 64 orders in total, and is operated by 16 order multiplier-adder units. Therefore, filter 2 needs 4 16-order multiplier-adder units to be implemented, the first multiplier-adder unit is MAC17, and the last multiplier-adder unit is MAC20. The filter data in the filter data channel CH2 is routed to the A end of the data selector in front of MAC17, the A end of the data selector in front of MAC17 is turned on, and the B end of the data selector between MAC17-MAC20 is turned on. Filter 3 has 30 orders in total, and is operated by 5 order multiplier-adder units. Therefore, filter 3 needs 6 5-order multiplier-adder units to be implemented, the first multiplier-adder unit is MAC21, and the last multiplier-adder unit is MAC26. The filter data in the filter data channel CH3 is routed to the A end of the data selector in front of MAC21, the A end of the data selector in front of MAC21 is turned on, and the B end of the data selector between MAC21-MAC26 is turned on.

[0077] The routing relationship between the above filter data and the data selector A end in the multiplier-adder unit array is written into the routing unit through the Routing_ctrl signal, and the data path information between the above multiplier-adder unit arrays is written into the path control register through the MUX_ctrl signal.

[0078] The filter coefficients are loaded into the Coeff_FIFO of each multiplier-adder unit by the coefficient addressing unit before the circuit device formally performs the filtering operation.

[0079] The multiplication and addition results of each multiplier-adder unit are saved into the corresponding buffer, and the buffer has 128 buffers in total.

[0080] The function of the filter result operation unit is to add the multiplication and addition results of the corresponding multiplier-adder units according to the start multiplier-adder unit and the end multiplier-adder unit of each filter, to obtain the filter result of the corresponding filter. Since the order of all multiplier-adder units of each filter is different, the clock period required for calculating the filter result of each filter is different. The filter result operation unit outputs a specific filter result every specific clock period, and at the same time, the corresponding valid signal is pulled high, indicating that the filter result of the filter is valid.

[0081] For example, a user customizes two filters, the first filter has a total order of 16, which is implemented by a 4-order MAC unit; the second filter has a total order of 12, which is implemented by a 6-order MAC unit.

[0082] The user defines the following RTL code:

[0083] assign Filter_num='d2;

[0084] assign Filter_order=['d16,'d12,0,0,0,0,…,0];

[0085] assign Mac_order=['d4,'d6,0,0,0,0,…,0];

[0086] After the above three groups of input signals enter the path control unit, the path control unit first judges whether the two filters customized by the user meet the circuit device specification. In this embodiment, the specification is met, so the Error_output signal is 0, and the path control unit continues to calculate. Filter 1 has a total of 16 orders, which is operated by a 4-order MAC unit. Therefore, filter 1 needs 4 4-order MAC units to be implemented, the first MAC unit is MAC1, and the last MAC unit is MAC4. The filter data in the filter data channel CH1 is routed to the Data end of MAC1, and the data selector B end between MAC1-MAC4 is turned on. Filter 2 has a total of 12 orders, which is operated by a 6-order MAC unit. Therefore, filter 2 needs 2 6-order MAC units to be implemented, the first MAC unit is MAC5, and the last MAC unit is MAC6. The filter data in the filter data channel CH2 is routed to the A end of the data selector in front of MAC5, the A end of the data selector in front of MAC5 is turned on, and the B end of the data selector between MAC5 and MAC6 is turned on.

[0087] The routing relationship between the above filter data and the data selector A end in the MAC unit array is written to the routing unit through the Routing_ctr1 signal, and the data path information between the above MAC unit array is written to the path control register through the MUX_ctr1 signal.

[0088] As shown in Figure 3 , the MAC unit array defines the depth of Data_FIFO and Coeff_FIFO in MAC1-MAC4 as 4, and defines the depth of Data_FIFO and Coeff_FIFO in MAC5 and MAC6 as 6.

[0089] The routing unit routes the filter data in the filter data channel CH1 to the Data end of MAC1, and routes the filter data in the filter data channel CH2 to the A end of the data selector in front of MAC5.

[0090] The data selector determines the data path between the multiply-add unit arrays according to the path control register value: the data selector between MAC1-MAC4 selects the B end signal, the data selector in front of MAC5 selects the A end signal, and the data selector between MAC5 and MAC6 selects the B end signal.

[0091] The user loads the required filter coefficients into the Coeff_FIFO of the corresponding multiply-add unit through the coefficient addressing unit, and sets the coefficients of filter 1 as a0-a15 and the coefficients of filter 2 as b0-b11. The coefficients a0-a3 are loaded in MAC1; the coefficients a4-a7 are loaded in MAC2; the coefficients a8-a11 are loaded in MAC3; the coefficients a12-a15 are loaded in MAC4; the coefficients b0-b5 are loaded in MAC5; and the coefficients b6-b11 are loaded in MAC6.

[0092] The above circuit device is synthesized, laid out, routed and the like in the FPGA EDA tool to generate a bit stream file; the bit stream file is configured into the FPGA through the configuration circuit of the FPGA, and the filter circuit device in the FPGA starts to work;

[0093] Specifically, the user inputs the filter data of filter 1 into the filter data channel CH1 through the IO of the FPGA, inputs the filter data of filter 2 into the filter data channel CH2 through the IO of the FPGA, and the circuit device starts to perform multiply-add operation.

[0094] The multiply-add results of MAC1-MAC4 are added by the filter result operation unit to obtain the filter result of filter 1. Since the multiply-add units of MAC1-MAC4 are 4 orders, the filter result operation unit outputs one filter result of filter 1 every four clock periods. The multiply-add results of MAC5 and MAC6 are added by the filter result operation unit to obtain the filter result of filter 2. Since the multiply-add units of MAC5 and MAC6 are 6 orders, the filter result operation unit outputs one filter result of filter 2 every six clock periods.

[0095] Through the above process, the filtering effect of two filters can be realized in one filter circuit device, and the multiply-add unit structures of each filter are different.

[0096] In summary, the present application provides a FIR filter circuit structure, which can customize the multiply-add unit structure of the filter circuit according to user needs, and configure a FIR filter circuit with low circuit resource occupation ratio and fast operation speed.

[0097] Some common English names or letters used by the present application for the convenience of clear description are only used for exemplary reference, not for limiting interpretation or specific use, and the protection scope of the present application should not be limited by its possible Chinese translation or specific letter.

[0098] It should also be noted that, in this text, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another, without necessarily requiring or implying any such actual relationship or order between such entities or actions.

Claims

1. A FIR filter circuit structure, characterized by, The circuit structure comprises: a path control unit generating a first control signal and a second control signal according to a filter quantity and an order defined by a user; a routing unit transmitting filter data received by a filter data channel unit to a multiply-add unit array based on the first control signal; the multiply-add unit array comprises N multiply-add units, and each multiply-add unit is connected through a data selector; a path control register unit connected to a selection port of the data selector, the path control register unit controlling a data path of the multiply-add unit array through the data selector based on the second control signal; a filter result operation unit adding multiply-add results of corresponding multiply-add units to obtain filter results of corresponding filters; the multiply-add unit array comprises N multiply-add units and N-1 data selectors connected to the multiply-add units; an A port of the data selector receives corresponding filter data transmitted by the routing unit; a B port of the data selector is connected to a filter data output end of a previous multiply-add unit; an output end of the data selector is connected to a filter data input end of a next multiply-add unit; a filter coefficient input end of the multiply-add unit is connected to a coefficient addressing unit, and receives corresponding filter coefficients and stores the filter coefficients to a filter coefficient storage queue.

2. A FIR filter circuit structure according to claim 1, characterized in that, the path control unit is provided with three input signals and three output signals; a first input signal is a filter quantity defined by the user; a second input signal is a filter order defined by the user; a third input signal is an order of a multiply-add unit corresponding to the filter; wherein the second input signal and the third input signal are a one-dimensional array with a length of 128.

3. A FIR filter circuit structure according to claim 2, characterized in that, the three output signals comprise: a first control signal, a second control signal, and a test signal; the test signal indicates whether the filter quantity and the filter order defined by the user meet the specification of the circuit structure; if not, the test signal outputs corresponding error information.

4. The FIR filter circuit structure according to claim 1, wherein, the circuit structure further comprises: a coefficient addressing unit; filter coefficients are loaded to the filter coefficient storage queue of the multiply-add unit through the coefficient addressing unit.

5. The FIR filter circuit structure according to claim 1, wherein, the path control register unit comprises N-1 registers; a register input end of the register is connected to the path control unit, and receives the second control signal generated by the path control unit; a register output end of the register is connected to a selection port of a data selector in the multiply-add unit array, and controls a data path of the multiply-add unit array through the data selector.

6. The FIR filter circuit structure according to claim 1, wherein, the filter data channel unit comprises 128 filter data channels, and the filter data channels are connected to input ends of the routing unit.

7. The FIR filter circuit structure according to claim 1, wherein, the multiply-add unit comprises a filter data storage queue, a filter coefficient storage queue, a multiplier, and an adder; the filter data storage queue is used for storing filter data; the filter coefficient storage queue is used for storing filter coefficients; a user can configure depths of the filter data storage queue and the filter coefficient storage queue through a register, and the depths of the filter data storage queue and the filter coefficient storage queue are the same.

8. A FIR filter circuit structure according to claim 7, characterized in that, the filter data is sequentially written to the filter data storage queue and sequentially read out. The filter coefficient writing into the filter coefficient storage queue is looped in and out.

9. The FIR filter circuit structure according to claim 1, wherein, The multiply-add unit array includes 128 multiply-add units and 127 data selectors; The depth of the filter coefficient storage queue is not higher than 16.

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