Circuit board

Abstract

A circuit board according to the present disclosure is provided with: a fluororesin layer including a first main surface, a second main surface facing the first main surface, and a first hole penetrating from the first main surface to the second main surface; a first copper layer provided on the first main surface and including a 1A main surface facing the first main surface, a 1B main surface facing the 1A main surface, and a second hole penetrating from the 1A main surface to the 1B main surface and communicating with the first hole; the second copper layer is arranged on the second main surface; and a third copper layer that is provided at least on the inner wall surface of the first hole and electrically connects the first copper layer and the second copper layer, the inner wall surface of the second hole protrudes inward by a protruding length D from the inner wall surface of the first hole, and the percentage of the protruding length D with respect to the average thickness H of the first copper layer is 0.5% or more.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a circuit substrate. This application claims priority based on Japanese Application No. 2023-037172 filed on March 10, 2023, and all the recitations described in the Japanese application are incorporated by reference. BACKGROUND

[0002] In recent years, information communication volume is increasing, and communication in a high frequency band such as a microwave band or a millimeter wave band is becoming popular in devices such as IC cards and mobile phone terminals. For this reason, a printed circuit substrate having excellent high frequency characteristics such as small transmission loss in a high frequency band is required. As a base material for manufacturing such a high frequency printed circuit substrate, a laminate in which a copper layer is laminated on an insulating layer is generally used.

[0003] Since the dielectric constant of a fluorine resin is low, a film in which a fluorine resin such as polytetrafluoroethylene is a main component is used as a material for an insulating layer.

[0004] On the other hand, the surface energy of a fluorine resin is small. For this reason, in a case where a non-electrolytic copper plating layer as a conductive layer is formed on an insulating layer containing a fluorine resin by a non-electrolytic plating process, the adhesion of the fluorine resin layer to the non-electrolytic copper plating layer becomes small. Therefore, in the past, in order to improve the adhesion of the fluorine resin layer to the non-electrolytic copper plating layer, the surface of the fluorine resin layer was roughened by treating it with a solution containing metallic sodium before the non-electrolytic plating process, and thus the fluorine resin layer was made to adhere to the non-electrolytic plating layer by an anchor effect (Patent Literature 1).

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: Japanese Patent Application Publication No. 2003-201571 SUMMARY

[0008] The circuit substrate of the present disclosure includes a fluorine resin layer including a first main surface, a second main surface opposite to the first main surface, and a first hole passing through the first main surface to the second main surface; a first copper layer provided on the first main surface and including a first 1A main surface opposite to the first main surface, a first 1B main surface opposite to the first 1A main surface, and a second hole passing through the first 1A main surface to the first 1B main surface and communicating with the first hole; a second copper layer provided on the second main surface; and a third copper layer provided at least on an inner wall surface of the first hole and electrically connecting the first copper layer and the second copper layer, an inner wall surface of the second hole protruding more inward than an inner wall surface of the first hole by a protrusion length D, and a percentage of the protrusion length D with respect to an average thickness H of the first copper layer being 0.5% or more. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic cross-sectional view of the circuit substrate according to the present embodiment.

[0010] Figure 2 is a plan view of the circuit substrate according to the present embodiment, as viewed from the first main surface toward the second main surface. However, the third copper layer is omitted.

[0011] Figure 3 is another example of a schematic cross-sectional view of the circuit substrate according to the present embodiment.

[0012] Figure 4 is a view for explaining a manufacturing method of the circuit substrate according to the present embodiment.

[0013] Figure 5 is a view for explaining a manufacturing method of the circuit substrate according to the present embodiment.

[0014] Figure 6 is a view for explaining a manufacturing method of the circuit substrate according to the present embodiment.

[0015] Figure 7 is a view for explaining a manufacturing method of the circuit substrate according to the present embodiment.

[0016] Figure 8 is a view for explaining a manufacturing method of the circuit substrate according to the present embodiment.

[0017] Figure 9 is a view for explaining a daisy chain mode of Example 1.

[0018] Figure 10 is a schematic cross-sectional view of the region indicated by A of Figure 9 DETAILED DESCRIPTION

[0019] [Technical Problem to be Solved by the Present Disclosure]

[0020] The related art intends to improve the adhesion of the fluororesin layer to the non-electrolytic copper plating layer by roughening the surface of the fluororesin layer. However, due to the roughening of the surface of the fluororesin layer, the fluororesin layer is damaged, and a part of the surface of the fluororesin layer becomes a state in which it is easy to peel off. Along with this, the non-electrolytic copper plating layer and a part of the fluororesin layer are easy to peel off from the fluororesin in a state in which they are adhered. Thus, there is a possibility that an increase in resistance value, conduction failure, and the like occur, and the reliability of the circuit substrate is reduced.

[0021] Therefore, an object of the present disclosure is to provide a circuit substrate having excellent reliability.

[0022] [Effects of the Present Disclosure]

[0023] ​According to the present disclosure, it is possible to provide a circuit substrate having excellent reliability.

[0024] [Explanation of Embodiments of the Present Disclosure]

[0025] First, an embodiment aspect of the present disclosure is listed to be explained.

[0026] (1) The circuit substrate of the present disclosure has a fluororesin layer including a first main surface, a second main surface opposite to the first main surface, and a first hole passing through the first main surface to the second main surface; a first copper layer provided on the first main surface and including a first 1A main surface opposite to the first main surface, a first 1B main surface opposite to the first 1A main surface, and a second hole passing through the first 1A main surface to the first 1B main surface and communicating with the first hole; a second copper layer provided on the second main surface; and a third copper layer provided at least on an inner wall surface of the first hole and electrically connecting the first copper layer and the second copper layer, the inner wall surface of the second hole protruding more inward than the inner wall surface of the first hole by a protrusion length D, the percentage of the protrusion length D with respect to an average thickness H of the first copper layer being 0.5% or more.

[0027] According to the present disclosure, it is possible to provide a circuit substrate having excellent reliability.

[0028] (2) In the above (1), the protrusion length D can be 0.1 μm or more. According to this, the adhesion of the third copper layer to the inner wall surface of the first hole is improved. Therefore, the reliability of the circuit substrate is further improved.

[0029] (3) In the above (1) or (2), the third copper layer can be provided on a region overlapping the first hole when the circuit substrate is viewed in a direction from the first main surface toward the second main surface and the first 1B main surface, and the percentage of an average thickness T2 of the third copper layer provided on the region overlapping the first hole with respect to an average thickness T1 of the third copper layer provided on the first 1B main surface can be 15% or more.

[0030] According to this, even in the region overlapping the first hole which is not easily formed by non-electrolytic copper plating, the thickness of the third copper layer is ensured, and thus the occurrence of conduction failure is suppressed when the circuit substrate is used. Therefore, the reliability of the circuit substrate is further improved.

[0031] (4) In the above (1) or (2), the third copper layer can be provided in a region overlapping the first hole when the circuit substrate is viewed in a direction from the first main surface toward the second main surface, the third copper layer and the second copper layer are sequentially provided in contact with each other in the region overlapping the first hole when the circuit substrate is viewed in a direction from the first main surface toward the second main surface, and a maximum value B of a distance between two points on an outer edge of a region of the second copper layer in contact with the third copper layer, a distance R from the first main surface of the fluororesin layer to an inner wall surface of the first hole along the first hole, and the protruding length D satisfy the following formula 1.

[0032] {(2D+B) / 2R} x 100 ≥ 5.0 Formula 1

[0033] Accordingly, the third copper layer is less likely to peel off, and the reliability of the circuit substrate is improved.

[0034] (5) In any one of the above (1) to (4), the protruding length D can be 1.0 μm or more. In this case, the adhesion of the third copper layer to the inner wall surface of the first hole is improved.

[0035] (6) In any one of the above (1) to (5), the cross-sectional area of the first hole when cut in a plane parallel to the first main surface can continuously decrease from the first main surface toward the second main surface.

[0036] [Details of Embodiments of the Present Disclosure]

[0037] Hereinafter, specific examples of the circuit substrate of the present disclosure will be described with reference to the drawings. In the drawings of the present disclosure, the same reference numerals denote the same parts or corresponding parts. In addition, the dimensional relationships of length, width, thickness, depth, and the like are appropriately changed for the sake of clarity and simplification of the drawings, and are not necessarily indicative of actual dimensional relationships.

[0038] In the present specification, the expression "A to B" means the upper and lower limits of the range (i.e., A or more and B or less), and in the case where A has no unit and only B has a unit, the unit of A is the same as that of B.

[0039] In the present disclosure, when one or more numerical values ​​are described as the lower limit and the upper limit of a numerical range, combinations of any numerical value described in the lower limit and any numerical value described in the upper limit are also disclosed. For example, when a1, b1, and c1 are described as the lower limit and a2, b2, and c2 are described as the upper limit, the range includes greater than a1 and less than a2, greater than a1 and less than b2, greater than a1 and less than c2, greater than b1 and less than a2, greater than b1 and less than b2, greater than b1 and less than c2, greater than c1 and less than a2, greater than c1 and less than b2, and greater than c1 and less than c2. Among a1, b1, and c1, a1 is the smallest, b1 is the second smallest, and c1 is the largest. Among a2, b2, and c2, a2 ​​is the largest, b2 is the second largest, and c2 is the smallest.

[0040] [Embodiment 1: Circuit Board]

[0041] use Figure 1 、 Figure 2 and Figure 3 A circuit board according to an embodiment of the present disclosure (hereinafter also referred to as “this embodiment”) will be described.

[0042] like Figure 1 As shown, the circuit substrate 1 of the present disclosure includes a fluororesin layer 10. The fluororesin layer 10 includes a first main surface 10a, a second main surface 10b opposite to the first main surface 10a, and a first hole 14 extending from the first main surface 10a to the second main surface 10b. The circuit substrate 1 also includes a copper layer 11. The first copper layer 11 is provided on the first main surface 10a and includes a 1A main surface 11a opposite to the first main surface 10a, a 1B main surface 11b opposite to the 1A main surface 11a, and a second hole 15 extending from the 1A main surface 11a to the 1B main surface 11b and communicating with the first hole 14. The circuit substrate 1 also includes a second copper layer 12. The second copper layer 12 is provided on the second main surface 10b. The circuit substrate 1 also includes a third copper layer 13. The third copper layer 13 is provided at least on the inner wall surface of the first hole 14 and electrically connects the first copper layer 11 to the second copper layer 12. Here, the inner wall surface of the first hole 14 corresponds to the wall surface formed of the fluororesin layer 10 that defines the first hole 14 .

[0043] The inner wall surface of second hole 15 in first copper layer 11 protrudes inwardly by a predetermined protrusion length D (μm) relative to the inner wall surface of first hole 14 in fluororesin layer 10. Here, the inward direction refers to the direction toward the center of the opening of second hole 15 as seen in a cross-section of fluororesin layer 10 taken along a plane parallel to first principal surface 10a. The percentage (D / H) of protrusion length D relative to the average thickness H (μm) of first copper layer 11 × 100 is 0.5% or greater. Here, the inner wall surface of second hole 15 corresponds to the wall surface of first copper layer 11 that defines second hole 15.

[0044] The circuit substrate of the present disclosure is such that the percentage (D / H) x 100 of the protrusion length D with respect to the average thickness H is 0.5% or more, and therefore the third copper layer 13 is hooked to the protruding portion of the first copper layer 11, and the third copper layer 13 is in close contact with the inner wall surface of the first hole 14 of the fluororesin layer 10 due to the stress thereof. For this reason, there is no need to perform the roughening treatment of the inner wall surface of the fluororesin layer in the existing manufacturing process. Thus, peeling of the fluororesin layer due to the roughening of the inner wall surface and the reduction of the adhesion of the inner wall surface to the third copper layer accompanying the same are suppressed. Therefore, in the circuit substrate of the present disclosure, the adhesion of the inner wall surface of the fluororesin layer 10 to the third copper layer 13 is good, the electrical connection of the first copper layer 11 to the second copper layer 12 becomes reliable, the increase of the resistance is suppressed, and excellent reliability is obtained. In addition, since the contact surface of the third copper layer 13 to the inner wall surface of the fluororesin layer 10 is flat, the transmission loss is small.

[0045] Hereinafter, each constituent element of the circuit substrate of the present disclosure will be described.

[0046] <Fluororesin layer>

[0047] As the material of the fluororesin layer 10, polytetrafluoroethylene, tetrafluoroethylene-hexafluoropropylene copolymer, perfluoroalkoxy fluororesin, ethylene-tetrafluoroethylene copolymer, and a mixture thereof can be exemplified. Among them, the dielectric constant and the dielectric loss tangent of polytetrafluoroethylene are low. Therefore, the high frequency characteristics of the circuit substrate using the fluororesin layer 10 composed of polytetrafluoroethylene as the insulating layer are good.

[0048] In order to adjust the physical properties such as thermal expansion, rigidity, and thermal conductivity of the fluororesin layer 10, an inorganic filler can be added to the fluororesin layer 10. As the material of the inorganic filler, silica, titanium oxide, aluminum oxide, magnesium oxide, calcium oxide, talc, barium sulfate, boron nitride, zinc oxide, potassium titanate, glass, mica, and the like can be exemplified. The mass ratio of the inorganic filler with respect to the fluororesin (inorganic filler / fluororesin) can be set to 1.0 or more and 3.0 or less.

[0049] The fluororesin layer 10 includes the first hole 14. The first hole 14 is a through hole that penetrates from the first main surface 10a of the fluororesin layer 10 to the second main surface 10b opposite to the first main surface 10a. The cross section of the first hole 14 when cut along a plane parallel to the first main surface 10a of the fluororesin layer 10 can also be a circular shape.

[0050] The lower limit of the equivalent circle diameter r1 of the opening on the same plane as the first main surface 10a of the first hole 14 can be 25 μm or more, or 50 μm or more. If the equivalent circle diameter r1 is 25 μm or more, when the third copper layer 13 is formed, the plating solution can discharge air in the first hole 14, and a plating layer can be reliably formed on the inner wall surface of the first hole 14, and the first copper layer 11 and the second copper layer 12 can be reliably electrically connected. From the viewpoint of the degree of freedom of circuit design, the upper limit of the equivalent circle diameter r1 can be 400 μm, or 250 μm. The equivalent circle diameter r1 can be 25 μm or more and 400 μm or less, or 50 μm or more and 250 μm or less.

[0051] The lower limit of the equivalent circle diameter r2 of the opening on the same plane as the second main surface 10b of the first hole 14 can be 10 μm, or 25 μm. If the equivalent circle diameter r2 is 10 μm or more, when the third copper layer 13 is formed, the plating solution can discharge air in the first hole 14, and a plating layer can be reliably formed on the inner wall surface of the first hole 14, and the first copper layer 11 and the second copper layer 12 can be reliably electrically connected. From the viewpoint of the degree of freedom of circuit design, the upper limit of the equivalent circle diameter r2 can be 400 μm, or 250 μm. The equivalent circle diameter r2 can be 10 μm or more and 400 μm or less, or 25 μm or more and 250 μm or less.

[0052] The cross-sectional area of the first hole 14 when cut along a plane parallel to the first main surface 10a can continuously decrease from the first main surface 10a toward the second main surface 10b, or can increase, or can be constant.

[0053] From the viewpoint of improving the strength, the lower limit of the average thickness of the fluororesin layer 10 can be 5 μm, or 10 μm. From the viewpoint of improving the flexibility, the upper limit of the average thickness of the fluororesin layer 10 can be 500 μm, or 400 μm. The average thickness of the fluororesin layer 10 can be 5 μm or more and 500 μm or less, or 10 μm or more and 400 μm or less.

[0054] In the present disclosure, the average thickness of the fluororesin layer 10 is obtained by the following procedure. First, the circuit substrate 1 is cut along a plane parallel to the normal line of the first main surface 11a to obtain a cross section. In the cross section, the thickness of the fluororesin layer 10 along the normal line is measured at any three points. The average of the thicknesses at the three points corresponds to the average thickness of the fluororesin layer 10. The measurement of the thickness is performed using a digital microscope (Keyence VHX-7000) based on a cross-sectional image obtained at a magnification of 100 times.

[0055] <First Copper Layer>

[0056] The first copper layer 11 is provided on the first main surface 10a. In the present embodiment, the first copper layer 11 forms a circuit. The first copper layer 11 can also be in contact with the fluororesin layer 10. An adhesive can be used to adhere the fluororesin layer 10 to the first copper layer 11.

[0057] The first copper layer 11 is not particularly limited as long as it is a thin film composed of copper, and sputtered copper, electrolytic copper foil, rolled copper foil, or the like can be used. Alternatively, the first copper layer 11 can be formed by plating on the fluororesin layer 10.

[0058] The first copper layer 11 includes a second hole 15 that communicates with the first hole 14. The second hole 15 is a through hole that penetrates the first copper layer 11 from the first A main surface 11a to the first B main surface 11b. The first A main surface 11a is opposite the first main surface 10a of the fluororesin layer 10. The first B main surface 11b is a surface opposite the first A main surface 11a. The cross section of the second hole 15 when cut by a plane parallel to the first B main surface 11b can also be circular.

[0059] The boundary E1 is the intersection of the inner wall surface of the first hole 14 and the first A main surface 11a, and is the outer edge of the region where the first main surface 10a and the first A main surface 11a are in contact. The inner wall surface of the second hole 15 protrudes a predetermined protrusion length D in the direction toward the interior from the boundary E1. Here, the "direction toward the interior" refers to the direction toward the center from the outer peripheral portion of the second hole 15 in a cross-sectional view of a plane parallel to the first A main surface 11a. The percentage (D / H) x 100 of the protrusion length D with respect to the average thickness H of the first copper layer is 0.5% or more. The protrusion length D is measured, for example, in a cross section obtained by cutting the circuit substrate 1 by a plane passing through the center of the opening (second hole 15) of the first B main surface 11b when the circuit substrate is viewed in a direction from the above-described first main surface toward the above-described second main surface (in the direction of the arrow A in FIG. 1) along a normal line to the first B main surface 11b. The protrusion length D is measured in the same manner even when the cross section is different. Figure 1

[0060] ​In order to improve the adhesion of the third copper layer to the inner wall surface of the first hole 14, the lower limit of the above percentage (D / H) x 100 can be 0.5%, or 10%, or 14.4%, or 30%, or 39.0%, or 40%, or 47.2%, or 70.4%. From the viewpoint of maintaining the shape of the protrusion, the upper limit of the above percentage (D / H) x 100 can be 780%, or 200%, or 100%. The above percentage (D / H) x 100 can be 0.5% or more and 780% or less, or 14.4% or more and 200% or less, or 70.4% or more and 100% or less.

[0061] In order to improve the adhesion of the third copper layer to the inner wall surface of the first hole 14, the lower limit of the protrusion length D can be 0.1 μm, or 1.0 μm, or 1.8 μm, or 5.9 μm, or 8.8 μm. From the viewpoint of maintaining the shape of the protrusion, the upper limit of the protrusion length D can be 15.6 μm, or 13.0 μm, or 11.9 μm. The protrusion length D can be 0.1 μm or more and 15.6 μm or less, or 1.8 μm or more and 13.0 μm or less, or 8.8 μm or more and 11.9 μm or less.

[0062] From the viewpoint of improving the conductivity, the lower limit of the average thickness H of the first copper layer can be 0.1 μm, or 0.4 μm. From the viewpoint of improving the flexibility, the upper limit of the average thickness H of the first copper layer can be 25.0 μm, or 20.0 μm, or 12.5 μm, or 2.0 μm. The average thickness H of the first copper layer can be 0.1 μm or more and 25 μm or less, or 0.4 μm or more and 2.0 μm or less.

[0063] In the present disclosure, the average thickness H of the first copper layer is obtained by the following procedure. First, the circuit substrate 1 is cut along a plane parallel to the normal line of the 1B major surface 11b to obtain a cross section. In the cross section, the thickness of the first copper layer in the direction of the above normal line is measured at three arbitrary points. The average of the thicknesses at the three points corresponds to the average thickness H of the above first copper layer. In the present disclosure, the average thicknesses of the second copper layer, the third copper layer, and the fourth copper layer, each of which will be described below, also mean the average thicknesses of the respective layers in the direction of the above normal line, and the measurement methods thereof are the same. The thickness measurement is performed using a digital microscope (KEYENCE VHX-7000) based on a cross-sectional image obtained at a magnification of 100 times.

[0064] The lower limit of the equivalent circle diameter r3 of the opening on the same plane as the first main surface 11a of the second hole 15 can be 20 μm, or can be 45 μm. If the equivalent circle diameter r3 is 20 μm or more, when the third copper layer 13 is formed, the plating solution can discharge air in the first hole 14, and the plating layer can be reliably formed on the inner wall surface of the first hole 14, and the first copper layer 11 and the second copper layer 12 can be reliably electrically connected. From the viewpoint of the degree of freedom of circuit design, the upper limit of the equivalent circle diameter r3 can be 350 μm, or can be 200 μm. The equivalent circle diameter r3 can be 20 μm or more and 350 μm or less, or can be 45 μm or more and 250 μm or less.

[0065] The range of the size of the equivalent circle diameter of the opening on the same plane as the second main surface 11b of the second hole 15 can be set to the same range of the size of the equivalent circle diameter r3 of the opening on the same plane as the above-described first main surface 11a.

[0066] <Second Copper Layer>

[0067] The second copper layer 12 is provided so as to face the second main surface 10b of the fluororesin layer 10. In the present embodiment, the second copper layer 12 forms a circuit. The second copper layer 12 can also be in contact with the fluororesin layer 10. In addition, another layer can be provided between the fluororesin layer 10 and the second copper layer 12. As the other layer, for example, an adhesive layer for adhering the fluororesin layer 10 and the second copper layer 12 can be cited.

[0068] The second copper layer 12 is not particularly limited as long as it is a thin film composed of copper, and sputtered copper, electrolytic copper foil, rolled copper foil, or the like can be used. In addition, the second copper layer can be formed by plating on the fluororesin layer 10.

[0069] From the viewpoint of improving the electrical conductivity, the lower limit of the average thickness of the second copper layer can be 0.1 μm, or can be 0.4 μm. From the viewpoint of improving the flexibility, the upper limit of the average thickness of the second copper layer can be 25.0 μm, or can be 2.0 μm. The average thickness of the second copper layer can be 0.1 μm or more and 25.0 μm or less, or can be 0.4 μm or more and 2.0 μm or less.

[0070] <Third Copper Layer>

[0071] The third copper layer 13 is provided at least on the inner wall surface of the first hole 14, and electrically connects the first copper layer 11 and the second copper layer 12. In the present embodiment, the third copper layer 13 is a thin layer formed by non-electrolytic copper plating. The third copper layer 13 serves as an adherend when a fourth copper layer to be described below is formed by electroplating.

[0072] In Figure 1In the embodiment, the third copper layer 13 is formed on the inner wall surface of the first hole 14, the surface of the protruding portion of the first copper layer 11 (part of the first main surface 11a), the inner wall surface of the second hole 15, and the exposed surface of the main surface of the second copper layer 12 opposite to the fluororesin layer 10. However, the formation site of the third copper layer 13 is not limited to Figure 1 For example, as long as the third copper layer 13 is formed along the inner wall surface of the first hole 14, the end surface opposite to the first copper layer 11 is in contact with at least a part of the first copper layer 11, and the end surface opposite to the second copper layer 12 is in contact with at least a part of the second copper layer 12.

[0073] In addition, the third copper layer 13 can be provided on the first main surface 11a and the region overlapping the first hole 14 when the circuit substrate 1 is viewed in the direction from the first main surface 10a toward the second main surface 10b. The percentage (T2 / T1) x 100 of the average thickness T2 (μm) of the third copper layer 13B provided in the region overlapping the first hole 14 with respect to the average thickness T1 (μm) of the third copper layer 13A provided on the first main surface 11a can be 15% or more. According to this, even in the region overlapping the first hole 14, which is not easily formed by non-electrolytic copper plating, the third copper layer 13B has a sufficient thickness, and thus the occurrence of conduction failure is suppressed when the circuit substrate is used. The lower limit of (T2 / T1) x 100 can be 15%, or can be 30%. The upper limit of (T2 / T1) x 100 is not particularly limited, and can be, for example, 100% or less. (T2 / T1) x 100 can be 15% or more and 100% or less, or can be 30% or more and 100% or less. Note that the "region overlapping the first hole 14 when the circuit substrate 1 is viewed in the direction from the first main surface 10a toward the second main surface 10b (from the first copper layer 11 side)" refers to Figure 2 In the embodiment, the third copper layer 13 is formed on the inner wall surface of the first hole 14, the surface of the protruding portion of the first copper layer 11 (part of the first main surface 11a), the inner wall surface of the second hole 15, and the exposed surface of the main surface of the second copper layer 12 opposite to the fluororesin layer 10. However, the formation site of the third copper layer 13 is not limited to

[0074] The lower limit of the average thickness T1 can be 0.05 μm or 0.1 μm from the viewpoint of ensuring continuity of the third copper layer and uniformly forming the fourth copper layer to be described later. The upper limit of the average thickness T1 is not particularly limited, but can be 1.0 μm or 0.5 μm, for example, from the viewpoint of reducing cost. The average thickness T1 can be 0.05 μm or more and 1.0 μm or less, or 0.1 μm or more and 0.5 μm or less.

[0075] The lower limit of the average thickness T2 can be 0.05 μm or 0.1 μm from the viewpoint of ensuring continuity of the third copper layer and uniformly forming the fourth copper layer to be described later. The upper limit of the average thickness T2 is not particularly limited, but can be 1.0 μm or 0.5 μm, for example, from the viewpoint of reducing cost. The average thickness T2 can be 0.05 μm or more and 1.0 μm or less, or 0.1 μm or more and 0.5 μm or less.

[0076] The third copper layer 13 is also provided in a region overlapping the first hole 14 when the circuit substrate 1 is viewed in a direction from the first main surface 10a toward the second main surface 10b. In the region overlapping the first hole 14 when the circuit substrate 1 is viewed in a direction from the first main surface 10a toward the second main surface 10b, the third copper layer 13B and the second copper layer 12 are provided in such a manner as to be in contact with each other. The protrusion length D, the distance R (μm) along the inner wall surface of the first hole 14, and the maximum value B (μm) of the distance between two points on the outer edge of the region of the second copper layer 12 in contact with the third copper layer 13B can also satisfy the following relation of Equation 1. The distance R is the distance along the inner wall surface of the first hole 14 from the first main surface 10a to the second main surface 10b of the fluororesin layer 10.

[0077] {(2D+B) / 2R} x 100 ≥ 5.0 Equation 1

[0078] Accordingly, the third copper layer 13 is less likely to peel off, and the reliability of the circuit substrate is improved.

[0079] The lower limit of {(2D+B) / 2R} x 100 can be 5.0, 25, 28.1, 30, or 45 from the viewpoint of improving the reliability of the circuit substrate. The upper limit of {(2D+B) / 2R} x 100 is not particularly limited, but can be 500 from the viewpoint of circuit design freedom and maintaining the protrusion shape. {(2D+B) / 2R} x 100 can be 5.0 or more and 500 or less, 30 or more and 500 or less, or 45 or more and 500 or less.

[0080] The protrusion length D, the distance R along the inner wall surface of the first hole 14, and the maximum value B of the distance between two points on the outer edge of the region of the second copper layer 12 that interfaces with the third copper layer 13B are measured in a cross section obtained by cutting the circuit substrate 1 along a plane parallel to the normal line of the first B main surface 11b and passing through the center of the opening (second hole 15) of the first B main surface 11b when the circuit substrate 1 is viewed from the first B main surface 11b side.

[0081] In the above cross section, the protrusion length D is as described above. As shown in FIG. 6, in the above cross section, the protrusion length D can be measured at each of the fluororesin layer 10 on the right side and the fluororesin layer 10 on the left side. According to the manufacturing process of the present disclosure, the protrusion lengths D on the right and left sides are necessarily substantially the same. Therefore, it is sufficient to measure either one of the protrusion lengths D on the right and left sides. Figure 1

[0082] The outer edge of the region of the first A main surface 11a that contacts the first main surface 10a is the boundary E1. The outer edge of the region of the main surface of the second copper layer 12 that opposes the fluororesin layer 10 that contacts the second main surface 10b is the boundary E2. The distance R corresponds to the length of the line segment that connects E1 and E2. As shown in FIG. 6, in the above cross section, the above line segment can be measured at each of the fluororesin layer 10 on the right side and the fluororesin layer 10 on the left side. According to the manufacturing process of the present disclosure, the distances R on the right and left sides are necessarily substantially the same. Therefore, it is sufficient to measure either one of the distances R on the right and left sides. In a microscopic sense, the inner wall surface of the first hole 14 sometimes has unevenness, but even in such a case, the distance R is set as the length of the line segment that connects the boundary E1 and the boundary E2 as described above. Figure 1

[0083] In the above cross section, the maximum value B corresponds to the distance between the boundary E2 on the right side and the boundary E2 on the left side. When the circuit substrate 1 is viewed in the direction from the first main surface 10a toward the second main surface 10b, the third copper layer 13B that interfaces with the second copper layer can be circular in shape. In this case, the maximum value B corresponds to the diameter of the circular shape.

[0084] <Fourth Copper Layer>

[0085] As shown in FIG. 7, the circuit substrate of the present disclosure can further include a fourth copper layer 18 provided on the third copper layer 13. The third copper layer 13 and the fourth copper layer 18 form a blind hole. By providing the fourth copper layer 18 on the third copper layer 13 after the third copper layer 13 is formed, a blind hole with excellent conductivity can be reliably formed. Figure 3

[0086] ​​​From the viewpoint of suppressing blind hole breakage due to bending of the circuit board or the like, the lower limit of the average thickness of the fourth copper layer can be 5 μm or 10 μm. The upper limit of the average thickness of the fourth copper layer is not particularly limited, but for example, from the viewpoint of thinning of the circuit board and cost reduction, it can be 100 μm or 50 μm. The average thickness of the fourth copper layer can be 5 μm or more and 100 μm or less, or 10 μm or more and 50 μm or less. Here, the average thickness of the fourth copper layer is measured in a region of the fourth copper layer 18 disposed opposite the first 1B main surface 1 lb of the first copper layer 11.

[0087] <Manufacturing method>

[0088] Using Figures 4 to 8 An example of a manufacturing method of the circuit board according to the embodiment will be described. The manufacturing method includes a first step (S1) of preparing a laminate in which the first copper layer 11, the fluororesin layer 10, and the second copper layer 12 are sequentially stacked. The manufacturing method further includes a second step (S2) of forming the second hole 15 in the first copper layer 11 by etching a part of the first copper layer 11, so as to expose the fluororesin layer 10. The manufacturing method further includes a third step (S3) of forming the first hole 14 in the fluororesin layer 10 by removing a part of the fluororesin layer 10 by laser irradiation to an exposed surface of the fluororesin layer 10. The manufacturing method further includes a fourth step (S4) of forming the third copper layer 13 on an inner wall surface of the first hole 14 by non-electrolytic plating. The manufacturing method can further include a fifth step (S5) and a sixth step (S6) after the fourth step. In the fifth step, the fourth copper layer 18 is formed on the third copper layer by electrolytic plating. In the sixth step, a conductive pattern is formed by selectively removing the first copper layer 11 and the second copper layer 12. Figure 4 Figure 5 Figure 6 Figure 6 Figure 7 Figure 8 Figure 8

[0089] <First step>

[0090] In the first step, a laminate in which the first copper layer 11, the fluororesin layer 10, and the second copper layer 12 are sequentially stacked is prepared (S1). Figure 4

[0091] ​​​​​​​​As a method of laminating the first copper layer 11 and the second copper layer 12 to the fluororesin layer 10, there is no particular limitation, and for example, an adhesive method of adhering a sheet-shaped copper layer using an adhesive, a casting method of applying a resin composition that is a material of the fluororesin layer 10 to a sheet-shaped copper layer, a sputtering / plating method of forming a copper layer on a few nm-thick thin conductive layer (seed layer) formed on the fluororesin layer 10 by sputtering or evaporation method, a lamination method of adhering a sheet-shaped copper layer to the fluororesin layer 10 using heat press, and the like can be used.

[0092] <Second Step>

[0093] In the second step, a second hole 15 is formed in the first copper layer 11 by etching a part of the first copper layer 11, so that the fluororesin layer 10 is exposed. Figure 5 ).

[0094] As a method of etching at least a part of the first copper layer 11, for example, a known etching method of forming a resist pattern by photolithography can be listed.

[0095] <Third Step>

[0096] In the third step, a first hole 14 is formed in the fluororesin layer 10 by laser irradiation to an exposed surface of the fluororesin layer 10, so that a part of the fluororesin layer 10 is removed. Figure 6 ). At this time, the first hole 14 is formed to penetrate the fluororesin layer 10. For this reason, a part of a main surface of the second copper layer 12 that opposes the fluororesin layer 10 is exposed.

[0097] The conditions of the laser irradiation can be set to the following conditions, for example.

[0098] Pulse width: 1 to 50 μsec

[0099] Output: 10 to 50 W

[0100] Number of shots: 1 to 30

[0101] Frequency: 100 to 4000 Hz

[0102] Wavelength: 10.6 μm

[0103] The greater the pulse width, the greater the protrusion length D. The greater the number of shots, the greater the protrusion length D. The thinner the thickness of the first copper layer, the more easily the protrusion length D is increased. As a result of intensive studies by the present inventors, it has been newly found that by taking into account the thickness of the first copper layer and forming a prescribed combination of the pulse width and the number of shots within the above conditions, the percentage (D / H) x 100 can be 0.5% or more.

[0104] <Fourth Step>

[0105] In the fourth process, a third copper layer 13 is formed on the inner wall surface of the first hole 14 of the fluororesin layer 10 by non-electrolytic plating. Figure 7

[0106] Non-electrolytic plating is a treatment in which a metal having catalytic activity is deposited by reduction of a catalyst, and can be performed by applying various non-electrolytic plating solutions available on the market.

[0107] The thickness of the third copper layer can be adjusted by the copper concentration, temperature, and treatment time of the non-electrolytic plating solution. The average thickness Tl and the average thickness T2 of the third copper layer can also be adjusted by the copper concentration, temperature, and treatment time of the non-electrolytic plating solution.

[0108] The copper concentration of the non-electrolytic plating solution can be set to 3.0 to 4.0 g / L, for example. The temperature of the non-electrolytic plating solution can be set to 30 to 40°C, for example. The treatment time of the non-electrolytic plating can be set to 5 to 40 minutes, for example.

[0109] By forming the third copper layer using non-electrolytic plating as such, the layering of the third copper layer can be adjusted by the copper concentration, temperature, and treatment time of the non-electrolytic plating solution. This is not only simple, but also makes the layering of the electrolytic plating layer provided on the third copper layer reliable.

[0110] <5th Process>

[0111] In the fifth process, a fourth copper layer 18 is formed on the third copper layer by electrolytic plating. Thus, a blind hole having a sufficient thickness can be formed.

[0112] <6th Process>

[0113] In the sixth process, the first copper layer 11 and the second copper layer 12 are selectively removed to form a conductive pattern. As a method of selectively removing the first copper layer 11 and the second copper layer 12, a publicly known method can be applied. For example, a resist pattern having openings in portions where the first copper layer 11 and the second copper layer 12 are to be removed is formed by photolithography. Then, the first copper layer 11 and the second copper layer 12 exposed in the openings of the resist pattern are dissolved by etching.

[0114] In the conventional manufacturing process, roughening treatment of the inner wall surface of the fluororesin layer is performed before non-electrolytic plating (corresponding to the third process). In the roughening treatment of the inner wall surface, a solution containing metallic sodium is generally used. In order to handle a large amount of metallic sodium, special equipment is required from the viewpoint of safety, and thus there is a technical problem of increased manufacturing cost.

[0115] In the manufacturing method of the circuit substrate of the present embodiment, roughening treatment of the inner wall surface is not required, and thus the manufacturing cost can be reduced.

[0116] ​The circuit substrate obtained by the above production method can suppress peeling of the fluororesin layer caused by roughening of the inner wall surface and a decrease in adhesion of the inner wall surface to the third copper layer accompanying the same. Thus, in the circuit substrate of the present disclosure, the adhesion of the inner wall surface of the fluororesin layer 10 to the third copper layer 13 is good, and the electrical connection of the first copper layer 11 to the second copper layer 12 becomes reliable. In addition, since the contact surface of the third copper layer 13 with the inner wall surface of the fluororesin layer 10 is flat, transmission loss is small.

[0117] Embodiments

[0118] The present embodiment will be further specifically described by examples. However, the present embodiment is not limited by these examples.

[0119] [Example 1: Samples 1 to 9, Samples 1-1 to 1-3]

[0120] [Production of Circuit Substrate]

[0121] A laminate in which a first copper layer, a fluororesin layer (thickness 150 μm), and a second copper layer (thickness 12.5 μm) were sequentially stacked was prepared. The average thickness of the first copper layer used in each sample was as described in the column of "average thickness H" of "first copper layer" of Table 2.

[0122] The first copper layer was subjected to copper etching to form a second hole having a diameter of 125 μm.

[0123] Next, a first hole was formed in the fluororesin layer by removing a part of the fluororesin layer by laser irradiation from the second hole. The laser irradiation conditions are as described in Table 1.

[0124] Next, a third copper layer was formed on the inner wall surface of the first hole of the fluororesin layer, the surface of the protruding portion of the first copper layer (part of the first A main surface 11a), the inner wall surface of the second hole, and the exposed surface of the first B main surface and the main surface of the second copper layer corresponding to the fluororesin layer by non-electrolytic plating. The conditions of the non-electrolytic plating are as described in Table 1.

[0125] Next, a fourth copper layer was formed on the third copper layer by electrolytic plating to obtain the circuit substrate of each sample. In all samples, the average thickness of the fourth copper layer was 20 μm.

[0126] [Table 1]

[0127] Table 1

[0128]

[0129] [Evaluation]

[0130] For each sample circuit board, the protrusion length D (μm), the average thickness T1 (μm) of the third copper layer, the average thickness T2 (μm) of the third copper layer, the distance R (μm), and the maximum value B (μm) were measured. The details of the measurement method are as described in Embodiment 1. The results are shown in Table 2. Furthermore, the values ​​of (D / H) × 100, (T2 / T1) × 100, and {(2D+B) / 2R} × 100 were calculated. The results are shown in Table 2.

[0131] [Table 2]

[0132]

[0133] Thermal Cycling Test

[0134] A heat cycle test was performed using each sample circuit board to measure the failure rate. The specific method is as follows.

[0135] The circuit substrate of each sample was patterned to form Figure 9 and Figure 10 Daisy chain pattern shown. In the daisy chain pattern, the circuit width is 0.5mm, the circuit length is 2.5mm, and the blind via pitch is 2.0mm.

[0136] The conditions for the thermal cycle test were: maintaining at -40°C for 30 minutes, then maintaining at 125°C for 30 minutes, with this cycle forming one cycle and a total of 3000 cycles. "TSE-11-A" (trademark) manufactured by ESPEC was used for the thermal cycle test.

[0137] The resistance values ​​between the circuits were measured before and after the thermal cycle test. The rate of change in the post-test resistance value R2 relative to the pre-test resistance value R1 was calculated as {(R2 - R1) / R1} × 100 (%). A rate of change of 5% or greater, or if the post-test resistivity R2 could not be measured, was considered defective. The defective rates for each sample are shown in Table 2. A defective rate of 10 ppm or less indicates excellent circuit board reliability.

[0138] <Inspection>

[0139] The circuit boards of samples 1 to 9 correspond to the examples. These samples were confirmed to have a defect rate of 10 ppm or less and excellent reliability.

[0140] Samples 1-1 to 1-3 correspond to comparative examples, and the defective rates of these samples exceeded 10 ppm, indicating insufficient reliability.

[0141] [Example 2]

[0142] In Example 2, the relationship between the non-electrolytic copper plating conditions and the percentage of the average thickness T2 of the third copper layer relative to the average thickness Tl (T2 / Tl) x 100 was investigated.

[0143] A laminate in which a first copper layer (thickness 12.5 μm), a fluororesin layer (thickness 150 μm), and a second copper layer (thickness 12.5 μm) were sequentially laminated was prepared.

[0144] Next, the first copper layer was subjected to copper etching to form a second hole having a diameter of 130 μm.

[0145] Next, the fluororesin layer was subjected to laser irradiation from the second hole to form a first hole. The protruding length D was 9 μm.

[0146] Next, a third copper layer was formed on the inner wall surface of the first hole of the fluororesin layer by non-electrolytic plating. The treatment time for non-electrolytic plating was set to 20 minutes. The relationship between the copper concentration of the non-electrolytic plating solution and the temperature of the non-electrolytic plating solution and (T2 / Tl) x 100 is described in Table 3.

[0147] [Table 3]

[0148] Table 3

[0149]

[0150] As confirmed from Table 3, the greater the copper concentration, the greater (T2 / Tl) x 100. In addition, it was confirmed that the lower the treatment temperature, the greater (T2 / Tl) x 100.

[0151] As described above, the embodiments and examples of the present disclosure were explained, but it was also intended from the beginning to appropriately combine the configurations of the above-described embodiments and examples or to make various modifications.

[0152] It should be considered that the embodiments and examples of the present disclosure are illustrative in all respects, rather than restrictive. The scope of the present invention is not shown by the above-described embodiments and examples, but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0153] Explanation of Reference Numerals

[0154] 1 circuit substrate

[0155] 10 fluororesin layer

[0156] 10a first main surface

[0157] 10b second main surface

[0158] 11 first copper layer

[0159] 11a first main surface

[0160] 11b first B main surface

[0161] 12 second copper layer

[0162] 13, 13A, 13B third copper layer

[0163] 14 first hole

[0164] 15 second hole

[0165] 18 fourth copper layer

[0166] 31 back surface circuit

[0167] 32 surface circuit

[0168] 33 blind hole

[0169] 34 resistance measurement terminal

Claims

1. A circuit substrate comprising: a fluororesin layer comprising a first main surface, a second main surface opposite to the first main surface, and a first hole, wherein the first hole penetrates from the first main surface to the second main surface; a first copper layer disposed on the first main surface and comprising a 1A main surface opposite to the first main surface, a 1B main surface opposite to the 1A main surface, and a second hole extending from the 1A main surface to the 1B main surface and communicating with the first hole; a second copper layer, disposed on the second main surface; as well as a third copper layer, which is at least provided on the inner wall surface of the first hole and electrically connects the first copper layer and the second copper layer; The inner wall surface of the second hole protrudes inwardly by a protruding length D than the inner wall surface of the first hole. The percentage of the protrusion length D relative to the average thickness H of the first copper layer is greater than or equal to 0.5%.

2. The circuit substrate according to claim 1, wherein The protrusion length D is greater than or equal to 0.1 μm.

3. The circuit substrate according to claim 1 or 2, wherein: The third copper layer is provided on the 1B main surface and a region overlapping with the first hole when the circuit substrate is viewed from the first main surface toward the second main surface. The percentage of the average thickness T2 of the third copper layer provided in the region overlapping with the first hole relative to the average thickness T1 of the third copper layer provided on the 1B main surface is 15% or more.

4. The circuit substrate according to claim 1 or 2, wherein: The third copper layer is provided in a region overlapping with the first hole when the circuit substrate is viewed from the first main surface toward the second main surface. The third copper layer and the second copper layer are sequentially arranged in contact with each other in a region overlapping the first hole when the circuit substrate is viewed from the first main surface toward the second main surface. The protrusion length D, the distance R along the inner wall surface of the first hole from the first main surface to the second main surface of the fluororesin layer, and the maximum value B of the distance between two points on the outer edge of the region of the second copper layer in contact with the third copper layer satisfy the relationship of the following formula 1: {(2D+B) / 2R}×100≥5.0 Equation 1.

5. The circuit substrate according to any one of claims 1 to 4, wherein The protrusion length D is 1.0 μm or more.

6. The circuit substrate according to any one of claims 1 to 5, wherein A cross-sectional area of ​​the first hole, when cut along a plane parallel to the first main surface, continuously decreases from the first main surface toward the second main surface.

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