Semiconductor die and method of manufacturing semiconductor die

Abstract

A semiconductor die and a method of manufacturing a semiconductor die. The present disclosure relates to a semiconductor die (1) comprising: a semiconductor body (10); an insulating layer (90) on a first side (10.1) of the semiconductor body (10); an adhesion promoter layer (190) on the insulating layer (90); a metallization (30) on the first side (10.1) of the semiconductor body (10), comprising a barrier layer system (130); wherein the adhesion promoter layer (190) is arranged at least in an overlapping region (195) between the insulating layer (90) and the at least one layer (131-133) of the barrier layer system (130).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor die comprising a semiconductor body and a metallization. BACKGROUND

[0002] In the semiconductor body, a device structure, e.g. a transistor structure, can be formed. The metallization on the semiconductor body can allow for wiring of the device structure, wherein an insulating layer can be arranged between the semiconductor body and the metallization. SUMMARY

[0003] In embodiments, the semiconductor die comprises an adhesion promoter layer on the insulating layer and the metallization comprises a barrier layer system. Therein, the adhesion promoter layer can be arranged at least in an overlap region between the insulating layer and at least one layer of the barrier layer system. This can improve the adhesion of the barrier layer system on the insulating layer, e.g. where the insulating layer is structured or has a topology, e.g. in the vicinity of a contact opening.

[0004] The barrier layer system can e.g. reduce or prevent diffusion from an upper layer or layer stack down into the semiconductor body, e.g. of copper atoms in case of a copper metallization. Otherwise, this can e.g. lead to formation of copper silicide by the semiconductor body or polysilicon, e.g. a gate electrode, resulting in e.g. ILD breakdown and device failure. More generally speaking, the improved adhesion of the barrier layer system on the insulating layer can have advantages in view of device reliability.

[0005] Further embodiments and features are provided in dependent claims and throughout the present disclosure. Therein, disclosing separate features independently of a specific claim category, the present disclosure relates to apparatus and device aspects, but also to method and use aspects. If e.g. a die is described to be manufactured in a specific way, this is also a disclosure of the respective manufacturing process and vice versa. Generally speaking, embodiments of the present application aim at providing an additional layer between the insulating layer and the barrier layer system, which additional layer is e.g. at least one of an adhesion promoter layer or an etch stop layer.

[0006] The insulating layer can be arranged on a first side of the semiconductor body, which first side can also be referred to as front side. With the insulating layer arranged on the first side of the semiconductor body and the metallization, a device structure formed in the semiconductor body can have at least one load terminal, e.g. a source terminal, there. A second load terminal, e.g. a drain terminal, can also be arranged at the first side or at a second, vertically opposite side of the semiconductor body.

[0007] The insulating layer can be used as an interlayer dielectric, e.g. defining a contact structure between a metallization and a semiconductor body. It can comprise an oxide layer, e.g. a borophosphosilicate glass (BPSG) layer. In other words, the insulating layer can comprise a doped oxide layer, e.g. in addition to an undoped oxide layer. The insulating layer can have a total thickness of at least 0.2 pm, for example, further lower limits being at least 0.5 pm and / or at most 3 pm.

[0008] The semiconductor body can comprise a semiconductor substrate, e.g. in combination with one or more epitaxial layers thereon. Generally, the semiconductor body can be a silicon (Si) or gallium nitride (GaN) semiconductor body, whereas embodiments of the present application relate to semiconductor dies having a silicon carbide (SiC) semiconductor body. This can allow for high voltages in operation of the device or device structure, such that the above-mentioned diffusion problem can be particularly relevant.

[0009] The load pad formed in the metallization can be connected to a load terminal of the device structure in the semiconductor body. The load terminal connected to the load pad can be a first load terminal arranged at a first side of the semiconductor body, and the device structure can comprise a second load terminal, e.g. at a second, vertically opposite side of the semiconductor body. The device structure can be, for example, a FET having a source terminal / region and a drain terminal / region in the semiconductor body, e.g. a source region at the first side of the semiconductor body and a drain region at its second side. In other words, the load pad in the metallization can be a source pad connected to a source terminal of the device structure.

[0010] In addition to the source and drain regions, the device can comprise a body region to which a gate electrode is capacitively coupled. Additionally, a drift region can be arranged between the body region and the drain region, e.g. made of the same doping type, but having a lower concentration than the drain region. The source and drain regions and the drift region, if present, can be made of a first doping type, the body region being made of a second doping type. In the illustrated embodiment, the first doping type is n-type and the second doping type is p-type.

[0011] The barrier layer system has at least one barrier layer, i.e. can consist of a single barrier layer or a barrier layer stack. The overlap region in which the adhesion promoter layer is arranged in between is formed underneath at least one layer of the barrier layer system, e.g. not necessarily covered by all layers of the barrier layer system. In an example, at least one layer of the barrier layer system can protrude laterally outward from the barrier layer stack, the adhesion promoter layer being arranged only underneath this laterally protruding portion of the laterally protruding layer. However, alternatively, the overlap region can be formed underneath the barrier layer stack (multiple barrier layers), e.g. alternatively or in addition to overlapping with a laterally protruding barrier layer.

[0012] In embodiments, the adhesion promoter layer is an aluminum oxide layer. As discussed in further detail below, this layer can additionally or alternatively serve as an etch stop during fabrication (e.g. in etching steps of the structured barrier layer and / or metal layer). Independent of the specific material / function, the adhesion promoter layer can be a relatively thin layer, having e.g. a thickness of no more than 30 nm, 20 nm or 15 nm. A lower limit can e.g. be 3 nm or 5 nm.

[0013] A contact opening can be formed in the insulating layer. The contact opening can allow for forming an electrical contact between the metallization and an underlying region (e.g. a region in a semiconductor body or a polysilicon electrode (e.g. a gate electrode or a field electrode)). Independent of these details, the overlap region can extend at least on an upper edge of the insulating layer in the vicinity of the contact opening. Considering a first or upper side of the insulating layer facing away from the semiconductor body, the edge can be located at this first or upper side, e.g. laterally adjacent to a flank portion laterally delimiting the contact opening. Arranging the overlap region of the adhesion promoter layer at least on the upper edge can reduce a risk of lift off of the barrier layer or layer system in a geometrically or electrically critical position at the contact opening.

[0014] In embodiments, the (first) adhesion promoter layer extends only underneath the barrier layer system, but not in a coverage region laterally aside of the barrier layer system. The coverage region can be arranged on the insulating layer, e.g. laterally aside of the upper edge with the overlap region. In embodiments, the coverage region laterally aside of the barrier layer system is covered by an additional adhesion promoter layer. The additional adhesion promoter layer can be at least one of the same type (e.g. aluminum oxide) or the same thickness as the first adhesion promoter layer in the overlap portion, but e.g. deposited in a later processing step.

[0015] E.g. after the barrier layer and / or metal layer has been etched back, the first adhesion promoter layer (which can have served as an etch stop) can be removed in the coverage region. Then, an additional adhesion promoter layer can be deposited to cover this coverage region, additionally, it can extend on the metallization. It can improve adhesion of a subsequently deposited inorganic passivation layer system, which can comprise a silicon nitride layer and / or a silicon oxide layer (as discussed in further detail below).

[0016] In an alternative embodiment, the (first) adhesion promoter layer also extends in the coverage area next to the barrier layer system. In other words, the adhesion promoter layer is not removed next to the barrier layer system, it can for example completely cover the first side of the insulating layer. As an example, the area ratio of the coverage area to the overlap area can be at least 5: 1, such that the barrier layer system extends in only a relatively small portion of the first side or upper side of the insulating layer. In the coverage area, the first adhesion promoter layer can be covered by an additional adhesion promoter layer, for example of the same type (e.g. aluminum oxide) and / or thickness as the first adhesion promoter layer. The additional adhesion promoter layer can extend onto the metallization, for example to improve the adhesion of the inorganic passivation layer system, see the description above.

[0017] Generally, an inorganic passivation layer system can be provided on the metallization, which can for example comprise a silicon nitride layer and / or a silicon oxide layer. The silicon nitride layer can be arranged underneath or on the silicon oxide layer. In an embodiment, the silicon oxide layer is arranged on a first silicon nitride layer, wherein a second silicon nitride layer is arranged on the silicon oxide layer, for example directly on the first silicon nitride layer and / or the second silicon nitride layer directly on the silicon oxide layer. The first silicon nitride layer can for example be thinner than the silicon oxide layer and / or the second silicon nitride layer. Independent of these geometric details, the silicon oxide layer can for example be an undoped silicon oxide layer, for example an undoped silicon glass (USG).

[0018] In an embodiment, at least one layer of the barrier layer system or the barrier layer system as a whole extends from the overlap area down into the contact opening. The barrier layer or barrier layer system extending down to the bottom of the contact opening can cover the flanking portion of the insulating layer laterally defining the contact opening. Alternatively or additionally, the barrier layer or layer system can for example completely cover the bottom of the contact hole to form an electrical contact there.

[0019] Generally, the adhesion promoter layer can also extend on the flanking portion of the insulating layer. However, in an embodiment, no adhesion promoter layer is provided on the flanking portion, i.e. the (first) adhesion promoter layer extends only on the first side or upper side of the insulating layer. In other words, the flanking portion can be free of adhesion promoter layer, i.e. no adhesion promoter layer. The flanking portion can remain free during deposition of the adhesion promoter layer, or the adhesion promoter layer can be removed from the flanking portion. For example when the adhesion promoter layer is an isolator like aluminum oxide, no adhesion promoter layer on the flanking portion can for example reduce the electrical resistance in the contact opening.

[0020] In an embodiment, the barrier layer system comprises at least one of a Ti, TiN, TiW or W layer. The barrier layer system can be a layer stack with multiple of these layers, for example a Ti / TiN layer covered by a TiW layer and / or a W layer.

[0021] Generally, the barrier layer system can also be applied in case of aluminum metallization, e.g. in case of an uppermost aluminum layer in which load pads and gate pads and the like can be formed. In embodiments, the metallization comprises a copper layer on the barrier layer system. The copper layer can be part of a copper layer system, e.g. a sputter-deposited copper layer directly on the barrier layer system combined with one or more bath-deposited copper layers on top. Thus, independent of the detailed layer stack, the barrier layer system in combination with the adhesion promoter layer can e.g. reduce or prevent copper diffusion and copper silicide formation.

[0022] In embodiments, at least one layer of the barrier layer system protrudes laterally with respect to a copper layer, e.g. a sputter-deposited copper layer directly on the barrier layer system, between which barrier layer system and the insulating layer the adhesion promoter layer is arranged. At least one layer of the barrier layer system can also protrude laterally with respect to other layers of the barrier layer system. With reference to the barrier layer stack discussed above, the Ti / TiN layer, optionally also the TiW layer, can protrude laterally with respect to the W layer.

[0023] Embodiments relate to a method of manufacturing a semiconductor die, comprising:

[0024] i) forming an insulating layer on a semiconductor body;

[0025] ii) forming an etch stop layer on the insulating layer;

[0026] iii) forming a metal layer on the etch stop layer;

[0027] iv) locally etching away the metal layer, wherein the etch stop layer defines an etch stop on the insulating layer.

[0028] With respect to possible embodiments and features of the semiconductor body and the insulating layer, reference is made to the above description. Providing the etch stop layer in step iv) can e.g. reduce or avoid surface roughening and / or uneven thinning of the insulating layer. Avoiding or reducing such geometric deviations can have advantages in terms of reliability as well as also testing capabilities (with less optical deviations optical inspection can e.g. be simplified).

[0029] Generally, the metal layer etched away in step iv) by means of the etch stop layer can be any metallization layer formed on a first side of the semiconductor body. However, in embodiments, the metal layer locally etched away in step iv) is at least one layer of a barrier layer system. As discussed above, the barrier layer system comprises at least one barrier layer, e.g. a Ti, TiN, TiW or W layer. Further, the barrier layer system can be a stack made of a plurality of these layers, see above description. The at least one layer locally etched away in step iv) can at least be the lowermost layer of the barrier layer system. Optionally, in step iv) the entire barrier layer stack can be locally etched away.

[0030] In embodiments, a copper layer is deposited onto the barrier layer system. The copper layer can be deposited by sputtering, i.e. the sputter-deposited copper layer. This can be used as a seed layer, e.g. for a subsequently applied copper layer system by bath deposition. The bath-deposited copper layer system comprises at least one layer bath-deposited copper layer; in embodiments, it comprises a first bath-deposited copper layer deposited onto the sputter-deposited copper layer and a second bath-deposited copper layer deposited onto the first bath-deposited copper layer.

[0031] wherein the second bath-deposited copper layer can be structured relative to the first bath-deposited copper layer, e.g. with laterally edges shifted inwardly relative to the laterally edges of the first bath-deposited copper layer. Thus, a step can be formed in the bath-deposited copper layer system, wherein the laterally edges of the second bath-deposited copper layer are shifted inwardly.

[0032] In embodiments, at least one layer of the barrier layer system is locally etched away in step iv) before the copper layer is applied by sputtering deposition. The sputter-deposited copper layer can be structured after the bath-deposited copper layer system has been applied, e.g. after the second bath-deposited copper layer has been deposited. However, alternatively, the sputter-deposited copper layer can be used and structured alone, whether or not a bath-deposited copper layer system is subsequently applied. In other words, the sputter-deposited copper layer can be structured before the bath-deposited copper layer system is deposited, or the copper metallization can be sputter-deposited as a whole.

[0033] Independent of the process details discussed in the above paragraphs, the etch stop layer can be an aluminum oxide layer. It can e.g. have a thickness of no more than 30 nm, 20 nm or 15 nm, possible lower limits being e.g. 3 nm or 5 nm. In embodiments, the etch stop layer of step iv) serves as an adhesion promoter layer in the ready-to-use die. In other words, the etch stop layer is at least arranged in an overlap region between the insulating layer and at least one layer of the barrier layer system, see the above description. A portion of the etch stop layer arranged laterally aside, e.g. in the cover region (see above), can remain on the insulating layer or be removed after step iv), see the above alternatives discussed with respect to the ready-to-use device. BRIEF DESCRIPTION OF DRAWINGS

[0034] In the following, the semiconductor die and the manufacturing method are explained in further detail by means of exemplary embodiments. Therein, individual features can also be related in different combinations.

[0035] Figure 1 A cross-sectional view of a semiconductor die comprising a semiconductor body, an insulating layer and a metallization is shown;

[0036] Figure 2 A detailed view of the metallization on the insulating layer as Figure 1 illustrated in

[0037] Figures 3a-3f different steps of manufacturing a semiconductor die with a semiconductor body, an insulating layer and a metallization are illustrated;

[0038] Figure 4 Some manufacturing steps are summarized in a flow chart;

[0039] Figure 5 A schematic cross section of a device formed in the active area of the die is shown. DETAILED DESCRIPTION

[0040] Figure 1 A portion of a semiconductor die 1 is shown in a vertical cross section. The semiconductor die 1 comprises a semiconductor body 10, which in the shown example is a silicon carbide (SiC) semiconductor body 11. On a first side 10.1 of the semiconductor body 10, an insulating layer 90 is arranged (see further details in Figure 2 ). Further, a metallization 30 is formed on the semiconductor body 10, which comprises a barrier layer system 130. On the barrier layer system 130, a copper layer system 230 is arranged, which in the shown example comprises a sputter deposited copper layer 231 and a bath deposited copper layer system 235 with a first bath deposited copper layer 235a and a second bath deposited copper layer 235b.

[0041] In detail, Figure 1 the cross section view is located at a lateral edge 1.1 of the die 1, wherein a passive area 1b is arranged laterally between the lateral edge 1.1 of the die 1 and the active area 1a shown on the right side in Figure 1 In the active area 1a, transistor device cells can be arranged (see details below). In the active area 1a, a load pad 31 can be formed in the metallization, for example a source pad connected to a source terminal of a device or device cell. In the passive area 1b, a gate runner 32 and / or a source runner 33 can be formed in the metallization 30, each runner extending along the active area 1a.

[0042] Figure 2 A detailed view of the metallization 30 with the barrier layer system 130 on the insulating layer 90 is illustrated. On the insulating layer 90, an adhesion promoter layer 190 is arranged, which in the shown example is an aluminum oxide layer 191. In an overlap area 195, the adhesion promoter layer 190 is arranged between the insulating layer and the barrier layer system 130, i.e. at least one layer 131, 132, 133 of the barrier layer system 130. In the shown example, the barrier layer system 130 comprises a first barrier layer 131, which can be a Ti / TiN layer, a second barrier layer 132, which can be a TiW layer and / or a third barrier layer 133, which can be a W layer.

[0043] The adhesion promoter layer 190 in the overlap region 195 can improve the adhesion of the barrier layer system 131 on the insulating layer 90. It is arranged in the vicinity of the contact opening 95 in the insulating layer 90, i.e. on the upper rim 96 in the vicinity of the contact opening 95. In the shown example, the adhesion promoter layer 190 is removed aside from the overlap region 195 in the cover region 196, instead, as referred to in Figure 3f It can extend in the cover region 196, as discussed.

[0044] The contact opening 95 is laterally defined by a flank portion 97 of the insulating layer 90. In the shown example and as viewed in a vertical cross-section, the flank portion 97 has an inclined upper portion and a substantially vertical lower portion. Independently of these details, the adhesion promoter layer 190 is only arranged on the first side 90.1 of the insulating layer 90, i.e. no adhesion promoter or aluminum oxide is provided on the flank portion 97.

[0045] As indicated in Figure 2 The insulating layer 90 can comprise sub-layers 90a, 90b, in the shown example a first sub-layer 90a, e.g. a silicon oxide layer, and a second sub-layer 90b, e.g. a BPSG layer. In total, the shown insulating layer 90 can have a thickness of about 1 pm. The adhesion promoter layer 190 can be significantly thinner, e.g. have a thickness between 3 nm and 15 nm.

[0046] Figures 3a-3f Some steps for manufacturing a semiconductor die with a semiconductor body, an insulating layer and metallization with a barrier layer system are illustrated, which are discussed in Figure 3a The insulating layer 90 has been deposited on the first side 10.1 of the semiconductor body 10 and structured to form the contact opening 95. Further, an etch stop layer 290 has been deposited on the insulating layer 90, in the shown example the etch stop layer 290 is an aluminum oxide layer 191. The etch stop layer 290 is structured such that the flank portion 97 laterally defining the contact opening 95 is not covered by the etch stop layer 290.

[0047] Subsequently, the barrier layer system 130 is deposited, see Figure 3b In the shown example, the barrier layer system 130 comprises a first barrier layer, a second barrier layer and a third barrier layer, further details are referred to the discussion of Figure 2 Initially, after deposition, the barrier layer system 130 completely covers the first side 10.1 of the semiconductor body 10. Figure 3b A subsequent structuring of the barrier layer system 130 by anisotropic plasma etching is illustrated. A mask 138 defines an opening 139 for the etch erosion and the etch stop layer 290 on the insulating layer 90 forms an etch stop.

[0048] After the barrier layer system 130 has been structured, the mask 138 can be removed. Subsequently, further metallization layers, for example a copper layer system, can be deposited. In Figure 3c , a sputter-deposited copper layer 231 has been applied by sputter deposition. It serves as seed layer for subsequent bath deposition, i.e. electroplating deposition of a first bath-deposited copper layer 235a as Figure 3d illustrated in Figure 3e , a second bath-deposited copper layer 235b can be deposited for local thickening of the copper layer system 230, for example in the area of the load pad 31. See Figure 3f , the sputter-deposited copper layer 231 can be removed subsequently.

[0049] Before depositing a passivation system, for example an inorganic hard passivation layer or stack, on the metallization 30, an additional adhesion promoter layer 198, for example an aluminum oxide layer, can be deposited. Alternatively or in addition to the adhesion function, the aluminum oxide layer can for example reduce copper oxidation (for example acting as oxygen barrier). In the cover area 196, i.e. aside from the overlap area 195, the etch stop layer 290 can be removed before depositing the additional adhesion promoter layer 198. Alternatively, the etch stop layer 290 can remain in the cover area 196 and be covered by the additional adhesion promoter layer 198. Irrespective of the detailed process variant, the etch stop layer 290 arranged in the overlap area 195 remains there as adhesion promoter layer 190.

[0050] Figure 4 Some manufacturing steps are summarized in a flow chart. After forming 400 an insulating layer on a semiconductor body, an etch stop layer can be formed 401 on the insulating layer. Then, a metal layer, for example a layer or layer stack of a barrier layer system, is formed 402 on the etch stop layer. When the metal and / or barrier layer is etched away 403 locally, the etch stop layer defines an etch stop. Then, further layer(s) of metallization can be formed 404. Optionally, the etch stop layer in the cover area can be removed 405.

[0051] Figure 5 Possible devices 200 and device structures 20 formed in the active area la of the die 1, for example underneath the load pad 31 (see Figure 1 for comparison) are illustrated. In the semiconductor body 10, for example a SiC semiconductor body 11, a load terminal 21 is formed at the first side 10.1, which in the shown example is a source region 22. At the vertically opposite second side 10.2, a drain region 27 is arranged, wherein a body region 23 is arranged underneath the source region 22 and a drift region 24 is arranged between the body region 23 and the drain region 27.

[0052] A gate region 25 comprising a gate electrode 25.1 and a gate dielectric 25.2 capacitively coupling the gate electrode 25.1 to the body region 23 is arranged in the trench 26. Via a voltage applied to the gate electrode 25.1, the channel formation in the body region 23, and thus the current flow between the source region 22 and the drain region 27, can be controlled. The device 200 can comprise a plurality of device units 201 connected in parallel.

Claims

1. A semiconductor die (1) comprising: a semiconductor body (10); an insulating layer (90) on a first side (10.1) of the semiconductor body (10); an adhesion promoter layer (190) on the insulating layer (90); a metallization (30) on the first side (10.1) of the semiconductor body (10), comprising a barrier layer system (130); wherein the adhesion promoter layer (190) is arranged at least in an overlap region (195) between the insulating layer (90) and at least one layer (131-133) of the barrier layer system (130).

2. The semiconductor die (1) according to claim 1, wherein the adhesion promoter layer (190) is an aluminum oxide layer (191).

3. The semiconductor die (1) according to claim 1 or 2, wherein a contact opening (95) is formed in the insulating layer (90), and the overlap region (195) extends at least over an upper edge (96) of the contact opening (95) on the insulating layer (90).

4. The semiconductor die (1) according to claim 3, wherein the adhesion promoter layer (190) extends only underneath the barrier layer system (130), an overlay region (196) laterally aside of the barrier layer system (130) being covered by an additional adhesion promoter layer (198).

5. The semiconductor die (1) according to claim 3, wherein the adhesion promoter layer (190) extends also in an overlay region (196) of the insulating layer (90) laterally aside of the barrier layer system (130).

6. The semiconductor die according to any one of claims 3 to 5, wherein the at least one layer (131-133) of the barrier layer system (130) extends from the overlap region (195) into the contact opening (95) and covers a flank portion (97) laterally delimiting the contact opening (95), on which flank portion (97) no adhesion promoter layer is provided.

7. The semiconductor die (1) according to any one of the preceding claims, the barrier layer system (130) comprising at least one of a Ti, TiN, TiW or W layer.

8. The semiconductor die (1) according to any one of the preceding claims, the metallization (30) comprising a copper layer (136) on the barrier layer system (130).

9. The semiconductor die (1) according to claim 8, wherein the at least one layer (131-133) of the barrier layer system (130) has a lateral protrusion with respect to the copper layer, the adhesion promoter layer (190) being arranged between the barrier layer system (130) and the insulating layer (90).

10. A method of manufacturing a semiconductor die, comprising the following steps: i) forming (400) an insulating layer (90) on a semiconductor body (10); ii) forming (401) an etch stop layer (290) on the insulating layer (90); iii) forming (402) a metal layer (135) on the etch stop layer (290); iv) etching (403) the metal layer (135) locally away, wherein the etch stop layer (290) defines an etch stop on the insulating layer (90).

11. The method according to claim 10, wherein the metal layer (135) of steps iii) and iv) is at least one layer (131-133) of the barrier layer system (130).

12. The method according to claim 11, wherein a copper layer (136) is deposited onto the barrier layer system (130) by sputtering, wherein a bath-deposited copper layer system (235) is applied onto the sputter-deposited copper layer (136) by bath deposition.

13. The method according to claim 12, wherein step iv) is applied before depositing the copper layer (136) onto the barrier layer system (130).

14. The method for manufacturing a semiconductor die (1) according to any one of claims 10 to 14, wherein the barrier layer system (130) is formed at least in the overlap region (195) after step ii) and before step iii), the etch stop layer (290) is arranged between the insulating layer (90) and the at least one layer (131-133) of the barrier layer system (130) such that the etch stop layer (290) forms the adhesion promoter layer (190).

15. The method for manufacturing a semiconductor die (1) according to claim 14, wherein the etch stop layer (290) is removed (405) from the cover region (196) after step iv).

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