Semiconductor die and method of manufacturing semiconductor die

Abstract

A semiconductor die and a method of manufacturing a semiconductor die. The present disclosure relates to a semiconductor die (1) comprising a silicon carbide (SiC) semiconductor body (11); a passivation system (40) on a first side (11.1) of the SiC semiconductor body (11); the passivation system (40) comprises an inorganic passivation layer system (45) and an organic layer (41) on the inorganic passivation layer system (45), a lateral edge (45. I) of the inorganic passivation layer system (45) is arranged on the SiC semiconductor body (11), the inorganic passivation layer system (45) is laterally retracted below the organic layer (41), and the lateral edge (45. I) of the inorganic passivation layer system (45) is covered by the organic layer (41).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor die comprising a semiconductor body. BACKGROUND

[0002] In embodiments of the present application, the semiconductor body is made of silicon carbide (SiC), which has a relatively wide bandgap, for example, compared to silicon. This can be of interest, for example, for power semiconductor devices in high voltage and / or high current applications. In the semiconductor body, a device structure with a load terminal(s) can be formed, for example, a transistor structure with a source terminal and a drain terminal. For wiring and contacts of the device structure, metallization can be formed on the semiconductor body. SUMMARY

[0003] Examples of the present application are directed to advantageous semiconductor dies.

[0004] In embodiments, the semiconductor die comprises a silicon carbide (SiC) semiconductor body and a passivation system on a first side of the SiC semiconductor body. The passivation system comprises an inorganic passivation layer system and an organic layer, wherein a lateral edge of the inorganic passivation layer system is arranged on the SiC semiconductor body. The organic layer can cover the lateral edge of the inorganic passivation layer system, for example, extending further laterally than the inorganic passivation layer system. In other words, the lateral edge of the inorganic passivation layer system is laterally set back under the organic layer.

[0005] As viewed in a cross-sectional plane perpendicular to the lateral edge of the inorganic passivation layer system, the organic layer can extend on the inorganic passivation layer system on one side of the lateral edge and cover the lateral edge of the inorganic passivation layer system towards the other side, for example, laterally outward (towards the lateral edge of the SiC semiconductor body). The organic layer covering the lateral edge of the inorganic passivation layer system can, for example, reduce or slow down silicon carbide oxidation, for example, of the SiC semiconductor body next to or underneath the inorganic passivation layer system.

[0006] Such oxidation can be triggered or driven by humidity, for example, in combination with an electric field. For example, at the lateral edge of the inorganic passivation layer system located on the SiC semiconductor body, SiC oxidation can introduce mechanical stress and cause delamination risks. By extending the organic layer, for example, an imide layer, over the lateral edge, SiC oxidation at this critical geometry location can be at least delayed.

[0007] Further embodiments and features are provided in the claims and throughout the disclosure. Therein, individual features are disclosed independently of a specific claim category, the disclosure relates to apparatus and device aspects, but also to method and use aspects. If, for example, a die is described to be manufactured in a specific way, this is also a disclosure of the corresponding manufacturing process, and vice versa. Generally, embodiments of the present application aim at providing an organic layer having an overlap (e.g. laterally outward) on a lateral edge of an inorganic layer, i.e. covering a lateral edge of the inorganic layer.

[0008] Generally, when referring to an arrangement of one layer or a lateral edge of the layer "on" another layer or entity, e.g. on a SiC semiconductor body, this does not necessarily imply a direct adjacent arrangement to the layer or entity. In other words, an additional layer can be arranged between the inorganic passivation layer system and the first side of the SiC semiconductor body, e.g. an aluminum oxide layer. For example, only an aluminum oxide layer can be arranged between the inorganic passivation layer system and the first side of the SiC semiconductor body. The additional layer may, for example, serve as an adhesion promoter and / or etch stop layer. It may, for example, have a thickness of not more than 30 nm, 20 nm or 15 nm, possible lower limits being, for example, 3 nm or 5 nm. In other words, to summarize, the arrangement "on" can mean a specific distance, e.g. a relatively small distance of not more than 100 nm, 50 nm, 30 nm, 20 nm or 15 nm, or the arrangement "directly on".

[0009] A lateral edge of the additional layer can be arranged on the SiC semiconductor body, e.g. where a lateral edge of the inorganic passivation layer system is arranged. Alternatively, the additional layer can extend further (e.g. laterally outward) than the inorganic passivation layer system. Independently of these details, a humidity and / or ion contamination can be prevented or slowed down, e.g. by the coverage of the organic layer. However, as an alternative to the additional layer below, the inorganic passivation layer system, i.e. a lateral edge thereof, can also be arranged directly on the SiC semiconductor body. Additionally or as an alternative, the organic layer can be arranged directly on the first side of the semiconductor body next to the inorganic passivation layer system.

[0010] Generally, the SiC semiconductor body can comprise a SiC semiconductor substrate, e.g. in combination with one or more epitaxial SiC layers thereon. The side of the uppermost epitaxial SiC layer facing away from the SiC substrate can be the "first side" of the SiC semiconductor body. Vice versa, the side of the SiC substrate facing away from the epitaxial SiC layer(s) can be the "second side" of the SiC semiconductor body.

[0011] In embodiments, the inorganic passivation layer system laterally recedes under the organic layer by at least 1 pm, further lower limits being for example at least 2 pm or 2.5 pm. Possible upper limits can for example be at most 50 pm, 30 pm or 20 pm. In detail, the respective distance can be taken in a cross-sectional plane perpendicular to the lateral edge of the inorganic passivation layer system, i.e. the distance between the lateral edge of the inorganic passivation layer system and the lateral edge of the organic layer (at the lower end of the organic layer).

[0012] In embodiments, the lateral edge of the inorganic passivation layer system is an outer lateral edge facing the lateral edge of the SiC semiconductor body (while an inner lateral edge can be oriented towards the active region). In the vicinity of the lateral edge of the SiC semiconductor body, an electric field can be present, for example originating from a backside potential which can reach from the backside (second side) to the frontside (first side) at the lateral edge of the SiC semiconductor body and can trigger or drive an oxidation process. The outer lateral edge can for example be the outermost lateral edge of the inorganic passivation layer or system, for example without further elements of the inorganic passivation layer system being arranged further outwards.

[0013] Generally, “outwards” and “outermost” relate to a lateral positioning with respect to the respective lateral edge of the SiC semiconductor body, i.e. meaning closer or closest to this lateral edge. Elements discussed with respect to their relative positioning are for example arranged on the same side of the die’s active region, i.e. at the same lateral edge of the SiC semiconductor body. Therein, similar structures can be arranged at the other lateral edges of the SiC semiconductor body, however, this is not mandatory.

[0014] The outer lateral edge of the inorganic passivation layer system can be offset inwards from the lateral edge of the SiC semiconductor body, for example, as seen in a vertical top view, lying parallel to the lateral edge of the SiC semiconductor body. Laterally outside of the outer lateral edge of the inorganic passivation layer system, the SiC semiconductor body in embodiments without additional layers can be exposed, for example not covered by an inorganic layer, wherein the organic layer can provide coverage at least over the lateral portion.

[0015] The lateral edges of the inorganic passivation layer system, e.g. the outer lateral edges, can be arranged between the lateral edges of the SiC semiconductor body and the active area. In other words, the lateral edges of the inorganic passivation layer system can be arranged in the edge termination region. In the active area, a device structure can be formed in the SiC semiconductor body, including e.g. a first load terminal arranged at a first side of the SiC semiconductor body. Additionally, the device structure can include a second load terminal, e.g. at a vertically opposite second side of the SiC semiconductor body. The device structure can e.g. be a FET having a source terminal / region and a drain terminal / region in the SiC semiconductor body, e.g. a source region at a first side of the SiC semiconductor body and a drain region at its second side. In other words, the load pad in the metallization can be a source pad connected to the source terminal of the device structure.

[0016] In addition to the source and drain regions, the device can include a body region to which a gate electrode is capacitively coupled. Additionally, a drift region can be arranged between the body region and the drain region, e.g. made of the same doping type, but having a lower concentration than the drain region. The source and drain regions and the drift region, if present, can be made of a first doping type, the body region being made of a second doping type. In the illustrated embodiment, the first doping type is n-type and the second doping type is p-type.

[0017] In embodiments, the semiconductor die includes an insulating layer on a first side of the SiC semiconductor body. The insulating layer can e.g. be arranged directly on the first side, i.e. adjacent to the SiC semiconductor body. It can serve as an interlayer dielectric, e.g. defining a contact structure between an above metallization and the underlying semiconductor body. The insulating layer can include an oxide layer, e.g. a borophosphosilicate glass (BPSG) layer. In other words, the insulating layer can e.g. include a doped oxide layer in addition to an undoped oxide layer. The insulating layer can e.g. have a total thickness of at least 0.5 pm and / or at most 3 pm.

[0018] The insulating layer can have an outer lateral edge on the SiC semiconductor body, the outer lateral edge of the insulating layer being inwardly offset from the lateral edge of the SiC semiconductor body. The outer lateral edge of the insulating layer can be covered by the inorganic passivation layer system, such that in other words the outer lateral edges of the inorganic passivation layer system are arranged in a lateral positioning between the lateral edges of the SiC semiconductor body and the outer lateral edges of the insulating layer.

[0019] In embodiments, the outer lateral edge of the insulating layer is inwardly offset from the lateral edge of the inorganic passivation layer system by at least 1 pm, further lower limits being for example at least 2 pm, 3 pm or 4 pm. Possible upper limits can for example be at most 20 pm or 10 pm. In detail, the respective distance can be taken in a cross-sectional plane perpendicular to the lateral edge of the inorganic passivation layer system, i.e. the minimum distance between the lateral edge of the inorganic passivation layer system and the outer lateral edge of the insulating layer.

[0020] In embodiments, the semiconductor die comprises metallization on the first side of the SiC semiconductor body, like the insulating layer discussed above for example being arranged between the SiC semiconductor body and the metallization. In case a FET is formed in the semiconductor body, the load pad can for example be a source pad, as detailed above.

[0021] The passivation system can cover the lateral edge of the load pad, for example extending sideways and onto the load pad. Therein, the passivation system can have an opening on the load pad, for example for later contact in a package or other mounting structure.

[0022] As viewed in a cross-sectional plane perpendicular to the lateral edge of the load pad, the inorganic passivation layer system has an inner lateral end on the load pad. In general, the organic layer can be flush with the inner lateral end of the inorganic passivation layer system on the load pad. However, in embodiments, the organic layer extends further inwardly than the inorganic passivation layer system, i.e. laterally inwardly covering the inner lateral end of the inorganic passivation layer system.

[0023] In embodiments, as viewed in a cross-sectional plane perpendicular to the lateral edge of the load pad, the inorganic passivation layer system extends without interruption between the lateral edge of the load pad and the inner lateral end of the inorganic passivation layer system, i.e. without an interruption. Alternatively, the inorganic passivation layer system can be provided with an interruption on the load pad, for example in lateral positioning between the lateral edge of the load pad and the inner lateral end of the inorganic passivation layer system. Whether or not the inorganic passivation layer system is provided with an interruption, the organic layer can extend without interruption, i.e. without an interruption between the opening on the load pad and the lateral edge of the load pad (and further outwardly towards the lateral edge of the SiC semiconductor body).

[0024] In embodiments, the metallization in the area of the load pad is formed with a step. Laterally outside of the step, e.g. closer to the lateral edge of the SiC semiconductor body or die, the load pad has a first thickness ti. Laterally inside of the step, e.g. at a larger distance from the lateral edge of the SiC semiconductor body or die, the load pad has a second thickness t2. Therein, ti is smaller than t2. In other words, the load pad has a smaller thickness ti in the edge portion of the load pad and a larger thickness in the center portion of the load pad. The latter can have advantages, e.g. in terms of thermal management or mounting and bonding, wherein the smaller thickness in the edge portion can e.g. reduce the topology of a passivation system extending onto the load pad.

[0025] In embodiments, the passivation system extends laterally to an inner lateral position x2 thereof arranged laterally outside of the step. In other words, as viewed in the cross-sectional plane, the passivation system extends laterally onto the load pad, but ends in the edge region thereof, wherein the load pad has a thickness ti. As viewed in the cross-sectional plane, the passivation system covers the lateral edge of the load pad, but does not cover the step.

[0026] In embodiments, the inorganic layer or inorganic layer stack covers the flanks of the step in the load pad. The inorganic layer can be or the inorganic layer stack can comprise a silicon nitride layer and / or a silicon oxide layer. Independently of the specific material, covering the flanks can be advantageous, e.g. in terms of migration or diffusion processes. By way of example, such processes can be driven by an electric field originating from a backside potential reaching to the first side at the lateral edge of the semiconductor body (even when the electric field is reduced in the edge termination region or structure, a residual field strength can remain).

[0027] The flanks covered by the inorganic layer or layer stack shall also be disclosed independently of the overlapping organic layer. In other words, a semiconductor die shall be disclosed comprising: a semiconductor body; a metallization on a first side of the semiconductor body, a load pad being formed in the metallization; wherein the metallization in the area of the load pad is formed with a step, the load pad having a first thickness ti laterally outside of the step and a second thickness t2 laterally inside of the step, wherein ti is smaller than t2, wherein an inorganic layer or layer stack covers the flanks of the step. With regard to possible embodiments and additional features, reference is made to the entire disclosure.

[0028] In embodiments, the metallization comprises a copper layer. The copper layer can be part of a copper layer system, which can e.g. comprise a sputter deposited copper layer and one or more bath deposited copper layers on top. In embodiments, the metallization comprises a first bath deposited copper layer and a second bath deposited copper layer deposited on the first bath deposited copper layer, wherein the second bath deposited copper layer can be structured with respect to the first bath deposited copper layer. In other words, the second bath deposited copper layer can form the step in the load pad.

[0029] For structuring the second-bath-deposited copper layer, a mask can be provided on the first-bath-deposited copper layer prior to depositing the second-bath-deposited copper layer. Stairs in the landing pad can be formed at the lateral edge of the second-bath-deposited copper layer, which is displaced inwardly with respect to the lateral edge of the first-bath-deposited copper layer. However, alternatively, the copper layer(s) can be sputter-deposited, whether or not the bath-deposited copper layer system is applied subsequently. In other words, the sputter-deposited copper layer(s) can be combined with the bath-deposited copper layer(s), or the copper metallization can be sputter-deposited as one whole. Further, in case of a sputter-deposited copper metallization, the upper copper layer can be structured with respect to the underlying copper layer to form stairs.

[0030] In summary, all of the copper layers of the metallization, whether sputter-deposited or bath-deposited, can have a thickness of at least 3 pm, for example, with further lower limits of 5 pm or 7 pm, for example. As an example, an upper limit can be 25 pm or 20 pm. Below the lowermost copper layer, for example, a sputter-deposited copper layer, a metallized barrier layer system can be arranged, for example, comprising Ti / TiN layers.

[0031] In embodiments, the inorganic passivation layer system comprises a silicon nitride layer and a silicon oxide layer. The silicon nitride layer can be arranged below or on the silicon oxide layer. In embodiments, the silicon oxide layer is arranged on a first silicon nitride layer, wherein a second silicon nitride layer is arranged on the silicon oxide layer, for example, directly on the first silicon nitride layer and / or the second silicon nitride layer directly on the silicon oxide layer. The first silicon nitride layer can be, for example, thinner than the silicon oxide layer and / or the second silicon nitride layer. Independent of these geometric details, the silicon oxide layer can be, for example, an undoped silicon oxide layer, for example, an undoped silicon glass (USG).

[0032] In embodiments, the semiconductor die comprises a SiC semiconductor body, an insulating layer on a first side of the SiC semiconductor body, and a passivation system with an organic layer, for example, an imide layer, on the insulating layer. The insulating layer can have an outer lateral edge on the SiC semiconductor body, for example, directly on the SiC semiconductor body or with additional layers (for example, aluminum oxide layers, see the description above regarding the arrangement “on”) in between. Independent of these details, the outer lateral edge of the insulating layer can be covered by the organic layer, i.e., the outer lateral edge of the insulating layer is laterally recessed under the organic layer.

[0033] As discussed above for the lateral edges of the inorganic passivation layer system covered by the organic layer, the covering of the outer lateral edges of the insulating layer can for example reduce delamination risks (by slowing down or preventing SiC oxidation at or even below the insulating layer edges). For further details regarding the insulating layer, reference is made to the above description; it can for example comprise an oxide layer (e.g. a BPSG layer) and have a total thickness of at least 0.5 pm and / or at most 3 pm.

[0034] In embodiments, the outer lateral edges of the inorganic passivation layer system are arranged on the insulating layer, i.e. the outer portions of the insulating layer are not covered by the inorganic passivation layer system. Then, the organic layer (e.g. an imide layer) can cover both the outer lateral edges of the inorganic passivation layer system on the insulating layer and the outer lateral edges of the insulating layer on the SiC semiconductor body.

[0035] In embodiments, the organic layer has a thickness of at least 1 pm, further lower limits being for example at least 2 pm, 3 pm, 4 pm or 5 pm. Possible upper limits can for example be not more than 50 pm, 40 pm, 30 pm or 25 pm.

[0036] In embodiments, the organic layer is an imide layer. The imide can for example be a photosensitive polyimide precursor.

[0037] In embodiments, a method of manufacturing a semiconductor die comprises:

[0038] I) forming an inorganic passivation layer system on a first side of a SiC semiconductor body such that lateral edges of the inorganic passivation layer system are arranged on the SiC semiconductor body (e.g. directly on the SiC semiconductor body or with additional layers in between);

[0039] II) forming an organic layer on the inorganic passivation layer system, the organic layer covering the lateral edges of the inorganic passivation layer system.

[0040] For additional embodiments and features, reference is made to the present disclosure as a whole.

[0041] In embodiments, step I) comprises:

[0042] i) depositing the inorganic passivation layer system on the first side of the SiC semiconductor body;

[0043] ii) locally etching away the inorganic passivation layer system to define the lateral edges of the inorganic passivation layer system.

[0044] For step ii), a mask can be deposited on the inorganic passivation layer system. The inorganic passivation layer system can be locally etched away where the mask has openings therethrough, for example at the lateral edges of the SiC semiconductor body and / or on load pads formed in the metallization. Independently of these details, after the inorganic passivation layer system has been locally etched away, the mask can be removed, for example before the organic layer is formed in step II).

[0045] Any of these methods or method steps discussed above can be applied to the manufacture of the semiconductor die discussed above. BRIEF DESCRIPTION OF DRAWINGS

[0046] In the following, the semiconductor die and the manufacturing method are explained in further detail by means of exemplary embodiments. Individual features can also be related in different combinations therewith.

[0047] Figure 1 A cross-sectional view of a semiconductor die comprising a SiC semiconductor body and a passivation system is shown;

[0048] Figure 2 A more detailed view of a passivation system on a SiC semiconductor body is shown;

[0049] Figure 3 A schematic cross-section of a device formed in the active area of a semiconductor die is shown;

[0050] Figure 4a - Figure e illustrates different steps of manufacturing a semiconductor die with a passivation system comprising an inorganic passivation layer system and an organic layer;

[0051] Figure 5 A detailed view of an embodiment of a passivation system on a SiC semiconductor body is shown;

[0052] Figure 6 Some manufacturing steps are summarized in a flow chart;

[0053] Figure 7 A cross-sectional view of a semiconductor die comprising a SiC semiconductor body, an insulating layer and a passivation system is shown. DETAILED DESCRIPTION

[0054] Figure 1A portion of a semiconductor die 1 is shown in the form of a vertical cross section. The semiconductor die 1 comprises a silicon carbide (SiC) semiconductor body 11. On a first side 11.1 of the SiC semiconductor body 11, an insulating layer 90 is arranged. Further, a metallization 30 is formed on the SiC semiconductor body 11, the metallization 30 comprising a barrier layer system 130. On the barrier layer system 130, a copper layer system 230 is arranged, the copper layer system 230 comprising, in the shown example, a sputter deposited copper layer 231 and a bath deposited copper layer system 235 having a first bath deposited copper layer 235a and a second bath deposited copper layer 235b.

[0055] In detail, Figure 1 A cross-sectional view is located at a lateral edge 1.1 of the die 1, wherein a passive area 1b is arranged laterally between the lateral edge 1.1 of the die 1 and Figure 1 an active area 1a shown on the right side in the middle. In the active area 1a, transistor device cells can be arranged (see below in detail). In the active area 1a, load pads 31 can be formed in the metallization 30, e.g. source pads connected to source terminals of devices or device cells. In the passive area 1b, gate runners 32 and / or source runners 33 can be formed in the metallization 30, each extending along the active area 1a.

[0056] On the metallization 30, a passivation system 40 is arranged, the passivation system 40 comprising, in the shown example, an inorganic passivation layer system 45 and an organic layer 41, e.g. an imide layer 42, on the inorganic passivation layer system 45. As discussed in further detail with reference to Figure 4e an additional adhesion promoter layer can be arranged in between (not shown here).

[0057] The shown inorganic passivation layer system 45 comprises a first silicon nitride layer 45.1, a non-doped silicon oxide layer 45.2 directly on the first silicon nitride layer 45.1 and a second silicon nitride layer 45.3 directly on the non-doped silicon oxide layer 45.2. The passivation system 40 covers the gate runners 32 and the source runners 33 and also covers the insulating layer 90 made of doped oxide, e.g. boron phosphor silicon glass, BPSG. In the shown example, an aluminum oxide layer 340 (shown as a line only in Figure 1 is arranged underneath the inorganic passivation layer system 45, i.e. on the insulating layer 90 and also on the metallization 30.

[0058] Figure 1the cross-sectional plane is perpendicular to the lateral edge 31.1 of the load pad 31. The passivation system 40 extends between an outer lateral position xi next to the load pad and an inner lateral position x2 on the load pad 31, i.e. covering the lateral edge 31.1 of the load pad 31. In the shown embodiment, the interruption 60 is provided in at least one layer 41, 42, 45.1-45.3 of the passivation system 40, in this case the interruption 60 intersects the inorganic passivation layer system 45 completely. It is arranged laterally between the lateral edge 31.1 of the load pad 31 and the inner lateral position x2 of the passivation system 40. i

[0059] Figure 2 A more detailed view of the lateral edge 45.i of the inorganic passivation layer system 45 arranged on the SiC semiconductor body 11 is shown, wherein the cross-sectional plane is located perpendicular to this lateral edge 45.i. The lateral edge 45.i of the inorganic passivation layer system 45 is offset inwardly from the lateral edge 11.i of the SiC semiconductor body 11. The organic layer 41, e.g. the imide layer 42 in the shown example, extends further outwardly and covers the lateral edge 45.i of the inorganic passivation layer system 45. Thus, the outer lateral edge 41.i of the organic layer 41 is arranged further outwardly than the lateral edge 45.i of the inorganic passivation layer system 45, i.e. closer to the lateral edge 11.i of the SiC semiconductor body 11.

[0060] In the shown example, the inorganic passivation layer system 45, i.e. the first silicon nitride layer 45.1, and the organic layer 41 are arranged on the first side 11.1 of the SiC semiconductor body 11 directly, respectively, i.e. the inorganic passivation layer system 45 is arranged laterally outside of the insulating layer 90 and the organic layer 41 is arranged laterally outside of the lateral edge 45.i of the inorganic passivation layer system. However, instead, additional layers, e.g. an aluminum oxide layer (see Figure 5 for illustration) can be arranged in between.

[0061] Figure 3 A possible device 200 and device structure 20 is illustrated, which is formed in the active area la of the die 1, e.g. underneath the load pad 31 (see Figure 1 for comparison). In the SiC semiconductor body 11, the load terminal 21 is formed at the first side 11.1, which is the source region 22 in the shown example. At the vertically opposite second side 11.2, the drain region 27 is arranged, wherein the body region 23 is provided underneath the source region 22 and the drift region 24 is arranged between the body region 23 and the drain region 27.

[0062] ​A gate region 25 comprising a gate electrode 25.1 and a gate dielectric 25.2 capacitively coupling the gate electrode 25.1 to the body region 23 is arranged in the trench 26. Via a voltage applied to the gate electrode 25.1, the channel formation in the body region 23 can be controlled and, thus, the current flow between the source region 22 and the drain region 27. The device 200 can comprise a plurality of device units 201 connected in parallel.

[0063] Figure 4a - e illustrates some steps for manufacturing a semiconductor die having a semiconductor body, a metallization, and a passivation system. In Figure 4a , an insulating layer 90 has been deposited on the first side 11.1 of the semiconductor body 11 and a metallization 30 has been formed. Onto the metallization 30, an aluminum oxide layer 230 has been deposited (shown only as a line) and a silicon nitride layer 45.1 and a silicon oxide layer 45.2 have been deposited.

[0064] As shown in Figure 4b , the silicon oxide layer 45.2 can be etched back (not shown in detail here) before the silicon oxide layer 45.2 is covered by the second silicon nitride layer 45.3. In Figure 4b , the inorganic passivation layer system 45 has been deposited but not yet structured. For this purpose, a mask 145 is provided on the inorganic passivation layer system 45. The mask 145 has openings 160 defining the positions where interruptions are to be etched into the inorganic passivation layer system 45. Further, the mask 145 defines the inner and outer lateral ends of the inorganic passivation layer system 45, i.e. the positions where the inorganic passivation layer system 45 is to be opened on the load pad 31.

[0065] Figure 4c The inorganic passivation layer system 45 is illustrated after the etching step, i.e. after the interruptions 60 have been etched into the inorganic passivation layer system 45 and the lateral edges 45.i of the inorganic passivation layer system 45 have been defined. Applying, for example, an anisotropic etching step can leave the inorganic layers 81.1, 81.2, e.g. the stack 80 of inorganic layers 81.1, 81.2, on the flanks 71 of the steps 70.

[0066] In the subsequent step illustrated in Figure 4d , an organic layer 41, e.g. an imide layer 42 in the example shown, has been deposited onto the structured inorganic passivation layer system 45. For the structuring of the organic layer 41, a mask 141 is formed on the organic layer 41. The mask 141 defines lateral edges 41.i in the organic layer 41 and openings 140, see Figure 4e , which is illustrated. In this process step, the organic layer 41 has been etched back and the mask has been removed from the organic layer 41.

[0067] Figure 5 A detailed view of the lateral edge 11.i of the SiC semiconductor body 11 is shown. Figure 5 The embodiment shown in Figure 2 differs from the embodiment shown in

[0068] Figure 6 Some manufacturing steps are summarized in a flow chart. Forming 600 an inorganic passivation layer system on a first side of a SiC semiconductor body can comprise depositing 601 an inorganic passivation layer system on the first side, wherein the inorganic passivation layer system is subsequently etched away 602 locally to define a lateral edge of the inorganic passivation layer system. Subsequently, an organic layer can be formed 610, e.g. by depositing 611 an organic layer and etching it away 612 locally to define openings and a lateral edge.

[0069] Figure 7 An embodiment partly different from the embodiments discussed with reference to Figure 1 In this case, however, the insulating layer 90, the metallization 30 and the passivation system 40 are arranged on the first side 11.1 of the SiC semiconductor body 11 (for further details see the description above). In contrast to Figure 1 The outer lateral edge 45.i of the inorganic passivation layer system 45 is not arranged next to the insulating layer 90, but on the insulating layer 90. Thus, the portion 90a of the insulating layer 90 next to the outer lateral edge 45.i of the inorganic passivation layer system 45, i.e. the portion 90a of the insulating layer 90 between the outer lateral edge 45.i of the inorganic passivation layer system 45 and the outer lateral edge 90.i of the insulating layer 90, is not covered by the inorganic passivation layer system 45.

[0070] The organic layer 41, e.g. the imide layer 42, extends further outwards, i.e. in the direction of the outer lateral edge 1.1 of the die 1, than the inorganic passivation layer system 45 and the insulating layer 90. It covers the outer lateral edge 45.i of the inorganic passivation layer system 45 and also the outer lateral edge 90.i of the insulating layer 90.

Claims

1. A semiconductor die (1) comprising: a silicon carbide (SiC) semiconductor body (11); a passivation system (40) on a first side (11.1) of the SiC semiconductor body (11); the passivation system (40) comprising an inorganic passivation layer system (45) and an organic layer (41) on the inorganic passivation layer system (45), a lateral edge (45.i) of the inorganic passivation layer system (45) being arranged on the SiC semiconductor body (11), wherein the inorganic passivation layer system (45) laterally recedes under the organic layer (41), the lateral edge (45.i) of the inorganic passivation layer system (45) being covered by the organic layer (41).

2. The semiconductor die (1) according to claim 1, wherein the inorganic passivation layer system (45) laterally recedes under the organic layer (41) by at least 1 pm.

3. The semiconductor die (1) according to claim 1 or 2, wherein the lateral edge (45.i) is an outer lateral edge of the inorganic passivation layer system (45), the outer lateral edge of the inorganic passivation layer system (45) being offset inwardly from a lateral edge (11.i) of the SiC semiconductor body (11).

4. The semiconductor die (1) according to claim 3, wherein the lateral edge (45.i) of the inorganic passivation layer system (45) is arranged between the lateral edge (11.i) of the SiC semiconductor body (11) and an active area (1a) of the semiconductor die (1).

5. The semiconductor die (1) according to claim 3 or 4, comprising: an insulating layer (90) on the first side (11.1) of the SiC semiconductor body (11); the insulating layer (90) having an outer lateral edge (90.i) on the SiC semiconductor body (11), wherein the outer lateral edge (90.i) of the insulating layer (90) is offset inwardly from the lateral edge (45.i) of the inorganic passivation layer system (45).

6. The semiconductor die (1) according to claim 5, wherein the outer lateral edge (90.i) of the insulating layer (90) is offset inwardly from the lateral edge (45.i) of the inorganic passivation layer system (45) by at least 1 pm.

7. The semiconductor die (1) according to any one of the preceding claims, comprising: a metallization (30) on the first side (11.1) of the SiC semiconductor body (11), a load pad (31) being formed in the metallization (30); wherein the passivation system (40) covers a lateral edge (31.1) of the load pad (31) and has an opening (41) on the load pad (31).

8. The semiconductor die (1) according to claim 7, wherein the inorganic passivation layer system (45) has an inner lateral end (45.ii) on the load pad (31) as viewed in a cross-sectional plane perpendicular to the lateral edge (31.1) of the load pad (31), the organic layer (41) extending further inwardly than the inorganic passivation layer system (45) and covering the inner lateral end (45.ii) of the inorganic passivation layer system (45).

9. The semiconductor die (1) according to claim 7 or 8 in combination with claim 3 or 4, wherein the inorganic passivation layer system (45) extends without interruption between an inner lateral end (45.ii) of the inorganic passivation layer system (45) and the lateral edge (31.1) of the load pad (31) as viewed in a cross-sectional plane perpendicular to the lateral edge (31.1) of the load pad (31).

10. The semiconductor die (1) according to claim 9, wherein a flow channel (32, 33) is formed next to the load pad (31) in the metallization (30), the inorganic passivation layer system (45) being uninterrupted over the flow channel (32, 33).

11. The semiconductor die (1) according to any one of claims 7 to 10, wherein the metallization (30) in the area of the load pad (31) is formed with a step (70), the load pad (31) having a first thickness ti laterally outside the step (70) and a second thickness t2 laterally inside the step (70), wherein ti is smaller than t2.

12. The semiconductor die (1) according to claim 11, wherein an inorganic layer (81.1, 81.2) or layer stack (80) covers flanks (71) of the step (70).

13. The semiconductor die (1) according to any one of claims 7 to 12, wherein the metallization (30) comprises a copper layer.

14. The semiconductor die (1) according to any one of the preceding claims, wherein the inorganic passivation layer system (45) comprises a silicon nitride layer (45.1, 45.3) and a silicon oxide layer (45.2).

15. A semiconductor die (1) comprising: a silicon carbide (SiC) semiconductor body (11); an insulating layer (90) on a first side (11.1) of the SiC semiconductor body (11); a passivation system (40) on the first side (11.1) of the SiC semiconductor body (11); the insulating layer (90) having an outer lateral edge (90.i) on the SiC semiconductor body (11), the passivation system (40) comprising an organic layer (41) on the insulating layer (90), wherein the insulating layer (90) laterally recedes under the organic layer (41), the outer lateral edge (90.i) of the insulating layer (90) being covered by the organic layer (41).

16. The semiconductor die (1) according to claim 15, the passivation system (40) comprising an inorganic passivation layer system (45), wherein an outer lateral edge (45.i) of the inorganic passivation layer system (45) is arranged on the insulating layer (90).

17. The semiconductor die (1) according to any one of the preceding claims, wherein the organic layer (41) has a thickness of at least 1 pm and / or at most 50 pm.

18. The semiconductor die (1) according to any one of the preceding claims, wherein the organic layer (41) is an imide layer (42).

19. A method of manufacturing a semiconductor die (1), comprising the following steps: a) providing a silicon carbide (SiC) semiconductor body (11), b) providing an insulating layer (90) on a first side (11.1) of the SiC semiconductor body (11), c) providing a passivation system (40) on the first side (11.1) of the SiC semiconductor body (11), d) providing an organic layer (41) on the insulating layer (90), e) providing an inorganic passivation layer system (45) on the organic layer (41), f) laterally receding the insulating layer (90) under the organic layer (41), the outer lateral edge (90.i) of the insulating layer (90) being covered by the organic layer (41). I) forming (600) an inorganic passivation layer system (45) on a first side (11.1) of a silicon carbide (SiC) semiconductor body (11) such that lateral edges (45.i) of the inorganic passivation layer system (45) are arranged on the SiC semiconductor body (11); II) forming (610) an organic layer (41) on the inorganic passivation layer system (45), the organic layer (41) covering the lateral edges (45.i) of the inorganic passivation layer system (45).

20. The method according to claim 19, wherein step I) comprises: i) depositing (601) the inorganic passivation layer system (45) on the first side (11.1) of the SiC semiconductor body (11); ii) locally etching away (602) the inorganic passivation layer system (45) to define the lateral edges (45.i) of the inorganic passivation layer system (45).

21. The method according to claim 20, a mask (145) is applied to step ii), wherein the mask (145) is removed after locally etching away the inorganic passivation layer system (45) and before forming the organic layer (41) in step II).

22. The method according to any one of claims 19 to 21 for manufacturing a semiconductor die (1) according to any one of claims 1 to 18.

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