Super source follower, column parallel analog-to-digital converter and CMOS image sensor

Abstract

The invention provides a super source follower, a column parallel analog-to-digital converter and a CMOS image sensor, so as to enlarge the input level range of the super source follower and improve the driving capability, and is suitable for the field of image processing. The super source follower comprises a first transistor, a grid electrode of the first transistor is connected with an input node, and a source electrode of the first transistor is connected with an output node; the polarity of the second transistor is opposite to that of the first transistor, and the drain electrode of the second transistor is connected with the output node; the first current source is connected with the drain electrode of the first transistor and is used for providing bias current for the first transistor; the second current source is connected with the source electrode of the first transistor and used for providing bias current for the second transistor, and the bias current of the second transistor is configured to be obtained by subtracting the first current source from the second current source; and the bias voltage source is connected between the drain electrode of the first transistor and the grid electrode of the second transistor and is used for providing direct current bias voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, in particular to a super source follower, a column parallel analog to digital converter (ADC) and a complementary metal-oxide-semiconductor (CMOS) image sensor. BACKGROUND

[0002] A ramp (RAMP) generator is a commonly used reference voltage source for a column parallel ADC in a CMOS image sensor, which needs to have strong driving capability, because poor driving performance will introduce stripe noise in the output image. In addition, the synchronous response of a large number of comparators in the column parallel ADC will also produce stripe noise. In view of this, an amplification circuit such as a source follower and a super source follower can be introduced between the RAMP generator and the column unit in the column parallel ADC to reduce or eliminate stripe noise.

[0003] However, the super source follower cannot receive an input signal with a signal amplitude close to the power supply level or the ground level, which will result in too small a swing of the input signal that the super source follower can receive. In addition, the RAMP generator in the column parallel ADC usually also uses a current digital to analog convertor (DAC) topology structure in which the minimum output level corresponds to the ground level or the maximum output level corresponds to the power supply level, so the super source follower cannot be directly connected with the RAMP generator. In view of this, a technical solution is introduced, that is, an additional capacitor is inserted between the RAMP generator and the super source follower to generate a bias voltage.

[0004] However, the introduced additional capacitor will reduce the gain of the super source follower, resulting in attenuation of the output signal of the super source follower, thereby reducing the driving capability of the super source follower. In order to reduce the attenuation phenomenon as much as possible, a large-capacity additional capacitor needs to be used, which will result in too large an area occupied by the additional capacitor. SUMMARY

[0005] The embodiments of the present application provide a super source follower, a column parallel analog to digital converter (ADC) and a CMOS image sensor, so that the level range of the input signal that the super source follower can receive can be expanded, and the driving capability of the super source follower can be improved.

[0006] To achieve the above object, the present application adopts the following technical solutions.

[0007] In a first aspect, a super source follower is provided. The super source follower includes a first transistor, a second transistor opposite to the first transistor in polarity, a first current source, a second current source, and an offset voltage source. A gate of the first transistor is connected to an input node, and a source of the first transistor is connected to an output node. A drain of the second transistor is connected to the output node. The first current source is connected to a drain of the first transistor and configured to provide a bias current to the first transistor. The second current source is connected to the source of the first transistor and configured to provide a bias current to the second transistor, wherein the bias current of the second transistor is configured to be subtracted by the first current source from the second current source. The offset voltage source is connected between the drain of the first transistor and a gate of the second transistor and configured to provide a direct current bias voltage.

[0008] According to the super source follower provided in the first aspect, the offset voltage source is arranged between the drain of the first transistor and the gate of the second transistor, and the offset voltage source provides appropriate bias voltages to the first transistor and the second transistor, so that the first transistor and the second transistor work in normal mode and saturation mode respectively. In this way, the first transistor can receive an input signal with a wide range of levels, for example, the level of the input signal is close to the maximum power supply voltage or the minimum power supply voltage. Therefore, the input signal swing of the super source follower can be expanded, and the driving capability of the super source follower can be improved.

[0009] In addition, in the super source follower, a large-capacity capacitor does not need to be arranged at the gate of the first transistor to reduce the problems of signal attenuation and distortion caused by the change of the gate voltage of the first transistor affected by the input signal swing. Therefore, the gain of the super source follower will not be reduced, the chip area can be saved, and the cost and power consumption can be reduced.

[0010] In addition, the super source follower can also be well adapted to a system with correlated double sampling function, so as to well eliminate or reduce the conversion level between the input signal and the output signal caused by the instability of the production process.

[0011] In some embodiments, the offset voltage source is configured to provide a voltage to the gate of the second transistor, so that when the drain voltage of the first transistor is not high enough as the gate voltage of the second transistor, the second transistor is in saturation mode.

[0012] Therefore, according to the drain voltage of the first transistor, the bias voltage source can provide a higher voltage to the gate voltage of the second transistor, so as to control the second transistor to work stably in the saturation mode. Therefore, the working stability of the super source follower is improved.

[0013] In some embodiments, the first transistor is a P-type metal-oxide-semiconductor (MOS) transistor, and the second transistor is an N-type MOS transistor. When the second transistor is in the saturation mode, the input voltage V IN satisfies the following condition: V IN <(V thn +V dsatn –V thp –V OFS ), where V thn is the threshold voltage of the second transistor, V dsatn is the pinch-off voltage of the second transistor, V thp is the threshold voltage of the first transistor, and V OFS is the bias voltage provided by the bias voltage source. The bias voltage V OFS provided by the bias voltage source satisfies the following condition: V OFS <(V thn +V dsatn –V L,min ), where V L,min is the minimum voltage value in the node coupling the first current source and the bias voltage source, so as to operate the first current source as a constant current source.

[0014] In this way, the minimum level of the input signal that the first transistor can receive can be closer to the minimum power supply voltage, thereby expanding the range of the input signal that the super source follower can receive.

[0015] In some embodiments, the first transistor is an N-type MOS transistor, and the second transistor is a P-type MOS transistor. When the second transistor is in the saturation mode, the input voltage V IN satisfies the following condition: V IN <(V DD –V thp –V dsatp +V thn –V OFS ), where V DD is the power supply voltage of the source of the second transistor, V thp is the threshold voltage of the second transistor, and V dsatpis the pinch-off voltage of the second transistor, V thn is the threshold voltage of the first transistor, V OFS is the bias voltage provided by the bias voltage source. The bias voltage provided by the bias voltage source V OFS satisfies the following condition: V OFS >(V DD –V thp –V dsatp –V L,max ), wherein V L,max is the maximum voltage value in the node coupling the first current source and the bias voltage source to operate the first current source as a constant current source.

[0016] In this way, the maximum level of the input signal that the first transistor can receive can be closer to the maximum power supply voltage, thereby expanding the range of the input signal that the super source follower can receive.

[0017] In some embodiments, the super source follower further comprises: a first switch connected between the gate and the drain of the second transistor; and a second switch connected between the drain of the first transistor and the first current source. The bias voltage source comprises: a first capacitor connected between the first current source and the gate of the second transistor; a bias voltage generator; and a third switch connected between the bias voltage generator and the first current source. In a bias voltage generation mode, the first switch, the second switch and the third switch are configured to be in an ON state, an OFF state and an ON state, respectively, and the input voltage V IN is set to a minimum value or a maximum value, the first capacitor is charged to obtain a bias voltage between the gate of the second transistor and the first current source, wherein the bias voltage is determined by the forward bias voltage of the second transistor and the output voltage of the bias voltage generator. In a voltage buffering mode, the first switch, the second switch and the third switch are configured to be in an OFF state, an ON state and an OFF state, respectively, and the bias voltage of the two terminals of the first capacitor is used to keep the second transistor in a saturation mode and maximize the swing of the input voltage received by the gate of the first transistor.

[0018] In this way, the charging voltage of the two terminals of the first capacitor can be used to realize the function of the bias voltage source. Through the bias voltage generator, a bias voltage can be generated at the node connected to the first capacitor and the first current source, which can cause the first capacitor to only charge a small amount of charge. Therefore, a large enough bias voltage can be obtained at the gate of the second transistor. In this way, the second transistor is in saturation mode. In addition, since the first capacitor does not need to charge too much charge, a small-capacity capacitor can be used to realize it, thereby saving area and cost.

[0019] In some embodiments, the super source follower further comprises: an eighth switch connected between the first current source and the ground; and a ninth switch connected between the gate of the second transistor and the ground. When the first switch and the third switch are closed, and the second switch, the eighth switch and the ninth switch are opened, the bias voltage generator is disconnected, bypassing the first current source and the second transistor, and the super source follower is in a source follower mode.

[0020] Therefore, by controlling the opening or closing of these switches, the super source follower and the source follower can be quickly switched between each other, thereby improving flexibility. The super source follower can be switched to the source follower to improve the noise performance in the high gain mode.

[0021] In some embodiments, the super source follower further comprises: a first switch connected between the gate and the drain of the second transistor. The bias voltage source comprises a first capacitor, a second capacitor, a sixth switch and a seventh switch. One terminal of the first capacitor and one terminal of the second capacitor are connected to the gate of the second transistor, and the other terminal of the first capacitor and the other terminal of the second capacitor are connected to the first current source through the fourth switch and the fifth switch, respectively; the sixth switch is connected in parallel with the two terminals of the first capacitor; and the seventh switch is connected between the second capacitor and the common node of the fifth switch and the ground. In the bias voltage generation mode, the first switch, the sixth switch and the seventh switch are opened, and the fourth switch and the fifth switch are closed, and the second capacitor is charged by the second current source. In the voltage buffer mode, the first switch, the sixth switch and the seventh switch are closed, and the fourth switch and the fifth switch are opened, and the first capacitor is charged by the second capacitor.

[0022] In this way, the charging voltage at both ends of the structure composed of the first capacitor and the second capacitor can be used to realize the function of the bias voltage source. The second capacitor can be charged by the second current source, so a large enough bias voltage can be obtained at the gate of the second transistor. Thus, the second transistor is in saturation mode. In addition, if the bias voltage is too large and affects the normal operation of the super source follower, the second capacitor will be discharged to the first capacitor through the corresponding one or more switches to reduce the bias voltage. In addition, by providing a plurality of small-capacity capacitors in parallel to realize the function of the bias voltage source, the area can be saved, and the circuit design can be more flexible.

[0023] In some embodiments, the super source follower further comprises a ninth switch connected between the gate of the second transistor and ground. When the first switch is closed, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the ninth switch are opened, bypassing the first current source, bypassing the second transistor, the super source follower is in a source follower mode of operation.

[0024] Therefore, by controlling the opening or closing of these switches, the super source follower and the source follower can be quickly switched between each other, thereby improving flexibility. The super source follower can be switched to the source follower to improve the noise performance in the high gain mode.

[0025] In some embodiments, the super source follower further comprises a first switch connected between the gate and the drain of the second transistor, a second switch connected between the drain of the first transistor and the first current source, an eighth switch connected between the first current source and ground, and a ninth switch connected between the gate of the second transistor and ground. The bias voltage source comprises a first capacitor connected between the first current source and the gate of the second transistor, a bias voltage generator, and a third switch connected between the bias voltage generator and the first current source. When the first switch and the third switch are closed, the second switch, the eighth switch, and the ninth switch are opened, the bias voltage generator is disconnected, bypassing the first current source, bypassing the second transistor, and the super source follower is in a source follower mode of operation.

[0026] Therefore, by controlling the opening or closing of these switches, the super source follower and the source follower can be quickly switched between each other, thereby improving flexibility. The super source follower can be switched to the source follower to improve the noise performance in the high gain mode.

[0027] In a second aspect, a column parallel ADC is provided. The column parallel ADC comprises: a plurality of comparators; one or more super source followers described in any of the embodiments of the first aspect. The one or more super source followers are connected between a reference level generator and the plurality of comparators, the comparators being configured to compare a plurality of analog inputs and a buffered reference level.

[0028] In some embodiments, the column parallel ADC comprises one super source follower; an output terminal of the super source follower is connected to reference signal input terminals of all the comparators. That is, all comparators share one super source follower to simplify the circuit topology and reduce area and cost.

[0029] In some embodiments, the column parallel ADC comprises a plurality of super source followers; output terminals of the plurality of super source followers are respectively connected to reference signal input terminals of all the comparators. That is, a plurality of comparators are respectively configured with one super source follower to avoid interference between comparators due to kickback effect, thereby improving image quality.

[0030] In some embodiments, the column parallel ADC works as a single slope ADC in a voltage buffering mode. In this case, the super source follower is configured to implement a bias voltage generation mode for a pixel at the end of a signal slope ADC process of a previous pixel. Therefore, column units of adjacent pixels can complete digital-to-analog conversion in a pipelined manner, thereby saving conversion time and improving analog-to-digital conversion efficiency.

[0031] In a third aspect, a CMOS image sensor is provided. The CMOS image sensor comprises: a pixel array, wherein the pixel array comprises a plurality of pixels, each pixel being configured to output an analog signal corresponding to a state of each pixel; a column parallel ADC described in any of the implementations of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1A is a structural schematic diagram of a CMOS image sensor;

[0033] FIG. 1B is a structural schematic diagram of a column parallel ADC in FIG. 1A

[0034] FIG. 2 is a schematic diagram of different RAMP swing;

[0035] FIG. 3 is a comparative schematic diagram of a ground truth image and a stripe image;

[0036] FIG. 4 is a structural schematic diagram of a source follower;​

[0037] FIG. 5 is a structural schematic diagram of a super source follower;

[0038] FIG. 6 is a schematic diagram of RAMP waveform distortion;

[0039] FIG. 7 is a schematic diagram of a kickback path in a column parallel ADC;

[0040] FIG. 8 is a structural schematic diagram of a super source follower provided by an embodiment of the present application;

[0041] FIG. 9 is a structural schematic diagram of another super source follower provided by an embodiment of the present application;

[0042] FIG. 10 is a structural schematic diagram of still another super source follower provided by an embodiment of the present application;

[0043] FIG. 11 is a structural schematic diagram of still another super source follower provided by an embodiment of the present application;

[0044] FIG. 12 is a structural schematic diagram of still another super source follower provided by an embodiment of the present application;

[0045] FIG. 13 is a structural schematic diagram of a column parallel ADC provided by an embodiment of the present application;

[0046] FIG. 14 is a structural schematic diagram of another column parallel ADC provided by an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the technical solutions provided by the present application, first, technical terms and related technologies involved in the embodiments of the present application are introduced.

[0048] 1. Column parallel analog-to-digital converter (ADC)

[0049] FIG. 1A is a structural schematic diagram of a CMOS image sensor. FIG. 1B is FIG. 1A a structural schematic diagram of a column parallel ADC. As FIG. 1A and FIG. 1BAs shown in Figure 1, the most commonly used ADC architecture in CMOS image sensors consists of a common reference DAC and multiple pairs of comparators and latches for synchronous conversion. In a row-by-row conversion scenario, the number of comparator and latch pairs must be the same as or similar to the horizontal resolution. Therefore, ADCs using this architecture are also called "column-parallel" ADCs.

[0050] 2. Single slope ADC

[0051] An ADC typically includes a ramp generator that serves as a reference DAC, a comparator that compares the DAC output with the analog input, and a counter that measures the time between the DAC output and analog input intersections as the ADC result. For CMOS image sensors, the resolution of the analog voltage corresponding to digital number (DN) 1 is typically changed by varying the amplitude of the ramp waveform.

[0052] FIG. 2 Figure 1 is a diagram showing different RAMP swings that can be used to control ADC resolution. FIG. 2 As shown, in the digital correlated double sampling scenario described below, the RAMP waveform includes two falling slopes. When the ADC's full code (i.e., all digital values ​​are binary 1) corresponds to the maximum level of the pixel, the resolution, also known as "analog gain," is defined as ×1 (or 0dB). When the RAMP swing is reduced to 1 / 2 or 1 / 4, this means that the resolution is also doubled and quadrupled, i.e., ×2 (6dB) and ×4 (12dB), respectively. In the following, to avoid confusion with the DC gain of the comparator, resolution is expressed as "resolution" rather than analog gain.

[0053] 3. Correlated double sampling (CDS)

[0054] CDS is a method for measuring electrical values, such as voltage or current, to eliminate unwanted offsets by taking the difference between two measurements: one under known conditions and one under unknown conditions (i.e., the sum of the known conditions and the measurement object). When using CMOS image sensors, two types of CDS can be performed: analog CDS and digital CDS. Analog CDS generates a differential signal, while digital CDS calculates the difference between two ADC results, one for a known-level sample and one for an unknown-level sample. This is because the known-level sample may include some noise components (e.g., charge injection, clock feedthrough, and thermal noise).

[0055] 4. Streaks

[0056] Banding is a type of distortion that appears as a band in the output image of a CMOS image sensor. When observed, the output level of a pixel varies slightly depending on the output levels of other pixels in the same row. Generally, this phenomenon is caused by interference between columns, which occurs via common signal and power lines. It is also known as "banding noise" or "horizontal smearing." FIG. 3 (a) and (b) in FIG5 show the ground truth image and the stripe image, respectively.

[0057] 5. Auto zero

[0058] Auto-zeroing is a method for eliminating unwanted offset in a differential amplifier by charging a capacitor inserted between the differential amplifier and its input terminals with a charge corresponding to the amplifier's offset. Specifically, by short-circuiting the amplifier's negative input and output terminals, the capacitor is charged before input amplification to a voltage corresponding to the offset and input level at that time. When the connection between the amplifier's negative input and output terminals is disconnected, the output is an amplified value of the input voltage change from before the disconnection, without the offset. If the input voltage is configured to set a known level for CDS during the capacitor's sampling phase, the output corresponds to the amplified difference between the input signal and the known level. In other words, the analog CDS described above is performed simultaneously.

[0059] 6. Source follower (SF) and super source follower (SSF)

[0060] FIG. 4 This is a schematic diagram of the source follower structure. FIG. 4 As shown in (a) in the figure, the source follower is a commonly used buffer amplifier, including a buffer MOS transistor T1 and a bias current source I2. The gain A of the source follower SF Determined by the buffer MOS transistor T1, the transconductance and drain conductance of the buffer MOS transistor T1 are respectively g m and g ds Description (see FIG. 4 The equivalent circuit of the source follower shown in (b)).

[0061] Therefore, the gain of the source follower is A SF The following conditions are met:

[0062] A SF =1 / (1+g ds / g m ).

[0063] Specifically, the back-gate effect should also be considered. This effect is not observed when the substrate and source of the buffer MOS transistor are connected. In this case, the back-gate effect can be ignored, and this connection is easy to implement in a P-type MOS (PMOS) source follower. The output impedance R SF The following conditions are met:

[0064] R SF =1 / (g m +g ds )~1 / g m .

[0065] It can be seen that due to g m Much larger than g ds , so RSF is almost composed of g m The source follower achieves low output impedance.

[0066] As a buffer amplifier with low output impedance, it further provides FIG. 5 The super source follower shown in Figure 1 is a FIG. 5 As shown in (a) of FIG, compared with the source follower, the super source follower includes an additional current source I1 and an additional MOS transistor T2. FIG. 5 In the small signal equivalent circuit shown in (b), the output impedance R SSF The following conditions are met:

[0067] R SSF =1 / {(g m +g ds )×g m2 / g ds +g ds2}~1 / (g m ×g m2 / g ds )~RSF / (g m2 / g ds ).

[0068] As the equation states, the output impedance of the super source follower is much lower than that of the conventional source follower. However, the super source follower has additional limitations in the input signal range to keep the additional MOS transistor T2 in saturation mode. Pch For operation with a threshold voltage V thp and pinch-off voltage V dsatp The input PMOS transistor T1, and the bias current I Nch For operation with a threshold voltage V thn and pinch-off voltage V dsatnthe output voltage V OUT is higher than the input voltage V IN by (V thp + V dsatp ), as shown in the following equation. At the same time, since the drain-source voltage in the saturation mode is higher than the pinch-off voltage, the gate voltage of the additional NMOS transistor T2 in the saturation mode is (V IN + V thp ), which is higher than (V thn + V dsatn ). Therefore, the condition for the input MOS transistor T1 to operate normally satisfies the following conditions:

[0069] V IN + V thp > V thn + V dsatn ,

[0070] V IN > V thn + V dsatn - V thp .

[0071] It can be seen that this restriction is very strict compared to the requirement of the source follower V IN > - V thp (the drain voltage in the saturation mode should be higher than the ground level).

[0072] 7. RAMP generator

[0073] The RAMP generator is a commonly used reference voltage source for column-parallel ADCs in CMOS image sensors, which needs to have strong driving capability, because poor driving performance will introduce stripe noise in the output image. It is well known that the generation mechanism of stripe noise is as follows.

[0074] (1) Load RC disturbance of the RAMP signal line

[0075] Since the input capacitance of each comparator depends on the input voltage of each comparator, the RAMP signal will be disturbed by the response of each comparator. Therefore, even if the input levels are the same, the output encoding of each comparator can be different, depending on whether the input signals received by other columns are large or small.

[0076] FIG. 6 is a schematic diagram of the distortion of the RAMP waveform. As FIG. 6 shown, in the case of a change in capacitance ΔC at time t, the final state of the RAMP signal is shifted by RΔC, where R is the output resistance of the RAMP generator. This shift determines the level of stripe noise. If the counter clock of the single-slope ADC is f clkRΔCf clk .

[0077] (2) Comparator response induced kickback

[0078] Due to the large number of comparators in a column parallel ADC, the synchronous response can induce a strong kickback. The strong kickback can generate fluctuations in the power supply level, ground level, and reference DAC output shared by multiple column cells, and the stripe phenomenon is observed in the output image of the image sensor.

[0079] FIG. 7 is a schematic diagram of a kickback path in a column parallel ADC. As shown in FIG. 7 , the crosstalk capacitance connecting the first stage output of the comparator and the positive input INP and the output resistor of the reference DAC act as a high-pass filter. Therefore, through the high-pass filter, the signal with edges of the first stage output of the comparator is transmitted in the form of a truncated pulse waveform. Since the output terminal of the reference DAC is also connected to other column comparators, the kickback can affect the analog-to-digital conversion results of other columns. This phenomenon is manifested as stripes in the output image. It should be understood that the output-to-input coupling path of the comparator is only an example, and there are other coupling paths in the column parallel ADC, such as an output-to-power line coupling path, an output-to-ground line coupling path, and the like.

[0080] As described above, in terms of the above two cases, the impact of stripe noise becomes greater in the case of poor driving capability, i.e., in the case of a large output resistance of the RAMP generator.

[0081] In view of this, a buffer amplifier similar to a source follower is provided between the RAMP generator and the column cell to effectively reduce the stripe noise. FIG. 5 The super source follower topology shown in is also a well-known buffer amplifier with stronger driving capability. In the bipolar transistor circuit, the input PMOS transistor and the additional NMOS transistor form a transistor pair identical to the reverse Darlington transistor structure, and the transconductance of the transistor pair is significantly higher than that of a single PMOS transistor, which indicates that the driving capability of the buffer amplifier is greatly improved.

[0082] However, the super source follower can not be suitable for an input signal with a highest level of a power supply level or a lowest level of a ground level, because when the input voltage is equal to or close to the ground level, FIG. 5 the additional NMOS transistor shown in may not be able to remain in the saturation mode.

[0083] In addition, since the RAMP generator in the column-parallel ADC usually has a current-DAC topology with the minimum output level corresponding to the ground level or the maximum output level corresponding to the power supply level, it is not possible to directly connect the super source follower with the RAMP generator.

[0084] To solve the problem of limited input signal range, a technical solution is introduced, that is, an additional capacitor is inserted between the output terminal of the RAMP generator and the input terminal of the super source follower, so as to generate a bias voltage for the additional MOS transistor. When the RAMP generator is used to output the minimum required input level, the additional capacitor can be charged to the bias voltage. Therefore, the super source follower can work at the minimum input level.

[0085] However, the additional capacitor reduces the gain of the super source follower, because the voltage swing at the gate of the input PMOS transistor is attenuated due to the change of the input signal at the opposite node of the additional capacitor (i.e. the output signal of the RAMP generator). The attenuation ratio is the ratio of the input capacitance to the ground capacitance at the gate of the PMOS transistor. In order to reduce the attenuation, the capacity of the additional capacitor can be increased, but this will make the additional capacitor occupy a larger chip area.

[0086] To solve the above problems, the embodiments of the present application provide a super source follower. The technical solution in some embodiments of the present application will be described in combination with FIG. 8 to FIG. 14 .

[0087] FIG. 8 is a structural schematic diagram of a super source follower provided by the embodiments of the present application. As FIG. 8 shown, the super source follower includes a first transistor T1, a second transistor T2, a first current source I1, a second current source I2 and a bias voltage source V OFS .

[0088] The gate of the first transistor T1 is connected with an input node V IN , and the source of the first transistor T1 is connected with an output node V OUT .

[0089] The polarity of the second transistor T2 is opposite to that of the first transistor T1, and the drain of the second transistor T2 is connected with the output node V OUT .

[0090] The first current source I1 is connected with the drain of the first transistor T1 and is used to provide a bias current for the first transistor T1.

[0091] The second current source I2 is connected to the source of the first transistor T1 and is configured to provide a bias current to the second transistor T2. The bias current of the second transistor T2 is configured to be the second current source I2 minus the first current source I1.

[0092] The bias voltage source V OFS The bias voltage source V is connected between the drain of the first transistor T1 and the gate of the second transistor T2 and is configured to provide a DC bias voltage.

[0093] In the super source follower provided by the embodiments of the present application, the bias voltage source V OFS The bias voltage source V is connected between the drain of the first transistor T1 and the gate of the second transistor T2. The bias voltage source V OFS The bias voltage source V provides appropriate bias voltages to the first transistor T1 and the second transistor T2, so that the first transistor T1 and the second transistor T2 work in normal mode and saturation mode respectively. In this way, the first transistor T1 can receive an input signal with a wide range of levels, for example, the level of the input signal is close to the maximum power supply voltage or the minimum power supply voltage. Therefore, the input signal swing of the super source follower can be expanded, and the driving capability of the super source follower can be improved.

[0094] In addition, in the super source follower, a large-capacity capacitor does not need to be arranged at the gate of the first transistor T1 to reduce the problems of signal attenuation and distortion caused by the change of the gate voltage of the first transistor T1 affected by the input signal swing. Therefore, the gain of the super source follower will not be reduced, the chip area can be saved, and the cost and power consumption can be reduced.

[0095] In addition, the super source follower can also be well adapted to systems with correlated double sampling function, thereby well eliminating or reducing the conversion level between the input signal and the output signal caused by the instability of the production process.

[0096] In some embodiments, the bias voltage source V OFS The bias voltage source V is configured to provide a voltage to the gate of the second transistor T2, so that when the drain voltage of the first transistor T1 is not high enough as the gate voltage of the second transistor T2, the second transistor T2 is in saturation mode.

[0097] That is, according to the drain voltage of the first transistor T1, the bias voltage source V OFS The bias voltage source V can provide a high voltage to the gate of the second transistor T2, thereby controlling the second transistor T2 to work stably in saturation mode. Therefore, the working stability of the super source follower is improved.

[0098] In some embodiments, as FIG. 8As shown in (a) in FIG. 10, the first transistor T1 can be a PMOS transistor, and the second transistor T2 can be an NMOS transistor.

[0099] When the second transistor T2 is in the saturation mode, the input voltage V IN The following conditions are satisfied:

[0100] V IN +V thp +V OFS >V thn +V dsatn ,

[0101] V IN >V thn +V dsatn –V thp –V OFS .

[0102] Here, V thn is the threshold voltage of the second transistor T2, V dsatn is the pinch-off voltage of the second transistor T2, V thp is the threshold voltage of the first transistor T1, V OFS is the bias voltage provided by the bias voltage source V OFS .

[0103] The gate voltage of the second transistor T2 needs to be kept at a level close to V thn +V dsatn . Therefore, when the minimum drain voltage of the first transistor T1 is V L,min , the bias voltage V OFS provided by the bias voltage source V OFS satisfies the following conditions:

[0104] V OFS +V L,min <V thn +V dsatn ,

[0105] V OFS <V thn +V dsatn –V L,min .

[0106] Here, V L,min is the minimum voltage value in the node coupling the first current source and the bias voltage source V OFS , which can be determined by the pinch-off voltage of the driving transistor in the first current source I1 to operate the first current source I1 as a constant current source.

[0107] Thus, the minimum level of the input signal that the first transistor T1 can receive can be closer to the minimum power supply voltage, thereby expanding the range of the input signal that the super source follower can receive.

[0108] In some other embodiments, as shown in (b) of FIG. 1A, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor. FIG. 8

[0109] When the second transistor T2 is in the saturation mode, the input voltage V IN satisfies the following condition:

[0110] V IN +V thp +V OFS <V DD –V dsatp +V thn ;

[0111] V IN <V DD –V thp –V dsatp +V thn -V OFS .

[0112] Here, V DD is the power supply voltage of the source of the second transistor, V thp is the threshold voltage of the second transistor, V dsatp is the pinch-off voltage of the second transistor, V thn is the threshold voltage of the first transistor, and V OFS is the bias voltage provided by the bias voltage source.

[0113] The bias voltage V OFS provided by the bias voltage source V OFS satisfies the following condition:

[0114] V OFS +V L,max >V DD –V thp -V dsatp ;

[0115] V OFS >V DD –V thp –V dsatp –V L,max .

[0116] Here, V L,max is the power supply voltage of the source of the first current source I1, and V OFS ​the maximum voltage value in the node, which can be determined by the pinch-off voltage of the driving transistor in the first current source I1, to operate the first current source I1 as a constant current source.

[0117] In this way, the maximum level of the input signal that the first transistor T1 can receive can be closer to the maximum power supply voltage, thereby expanding the range of the input signal that the super source follower can receive.

[0118] It should be noted that the embodiments of the present application take MOS transistors as an example for description. In actual application, other discrete devices or integrated devices with amplification function can be used to replace the first transistor T1 and the second transistor T2. The embodiments of the present application are not limited thereto.

[0119] In some embodiments, in combination with FIG. 8 As shown in FIG. 1, the super source follower further includes a first switch S1 and a second switch S2. FIG. 9 The first switch S1 is connected between the gate and the drain of the second transistor T2. The second switch S2 is connected between the drain of the first transistor T1 and the first current source I1.

[0120] The bias voltage source V OFS The bias voltage source V

[0121] The first capacitor C1 is connected between the first current source I1 and the gate of the second transistor T2. The third switch S3 is connected between the bias voltage generator Bias Gen and the first current source I1.

[0122] As shown in (a) of FIG. 2, in the bias voltage generation mode, the first switch S1, the second switch S2 and the third switch S3 are respectively configured to be in an ON state, an OFF state and an ON state, the input voltage V IN is set to the minimum value or the maximum value, the first capacitor C1 is charged (the charging path is shown by the arrowed curve in (a) of FIG. 2), thereby obtaining the bias voltage between the gate of the second transistor T2 and the first current source I1, wherein the bias voltage is determined by the forward bias voltage of the second transistor T2 and the output voltage of the bias voltage generator Bias Gen.

[0123] FIG. 9 In the voltage buffer mode, the first switch S1, the second switch S2 and the third switch S3 are respectively configured to be in an OFF state, an ON state and an OFF state (which is different from the bias voltage generation mode). FIG. 9 In the voltage buffer mode, the first switch S1, the second switch S2 and the third switch S3 are respectively configured to be in an OFF state, an ON state and an OFF state (which is different from the bias voltage generation mode).

[0124] FIG. 9 In the voltage buffer mode, the first switch S1, the second switch S2 and the third switch S3 are respectively configured to be in an OFF state, an ON state and an OFF state (which is different from the bias voltage generation mode).​The bias voltage of the two terminals of the first capacitor C1 is used to keep the second transistor T2 in the saturation mode, and to maximize the swing of the input voltage received at the gate of the first transistor T1 (e.g., to the power supply voltage or to the ground voltage).

[0125] In this way, the charging voltage of the two terminals of the first capacitor C1 can be used to realize FIG. 8 the function of the bias voltage source V OFS . Specifically, by the bias voltage generator Bias Gen, a bias voltage can be generated at the node connecting the first capacitor C1 and the first current source I1, which can cause the first capacitor C1 to only charge a small amount of charge. Therefore, a sufficiently large bias voltage can be obtained at the gate of the second transistor T2. As a result, the second transistor T2 is in the saturation mode.

[0126] In addition, since the first capacitor C1 does not need to charge too much charge, a small-capacity capacitor can be used to realize, thereby saving area and cost.

[0127] FIG. 9 (b) is a circuit schematic diagram of the circuit elements in the super source follower shown in (a). FIG. 9 (b) is a circuit schematic diagram of the circuit elements in the super source follower shown in (a). FIG. 9 As shown in (b), the bias voltage generator Bias Gen includes a third current source I3, a transistor series structure T5, and an output transistor T6.

[0128] The transistor series structure T5 includes a plurality of transistors connected in series by the source and drain and having a diode connection structure. The plurality of transistors can be MOS transistors, for example, NMOS transistors. The output transistor T6 can be a MOS transistor, for example, an NMOS transistor.

[0129] The drain of the NMOS transistor at one end of the NMOS transistor series structure T5 is connected to the third current source I3, the source of the NMOS transistor at the other end of the NMOS transistor series structure T5 is connected to the ground, and the gates of all the NMOS transistors are connected to the third current source I3 and the output NMOS transistor T6. The drain of the output NMOS transistor T6 is connected to the second current source I2, and the source of the output NMOS transistor T6 is connected to the third switch S3.

[0130] When the third switch S3 is turned on, the bias voltage generator Bias Gen provides a bias current through the output NMOS transistor T6, thereby providing a bias voltage to the common node connecting the first capacitor C1 and the first current source II. The bias voltage can affect the amount of charge charged into the first capacitor C1, thereby affecting the gate-source voltage of the second transistor T2, and further affecting the bias voltage of the first transistor T1. When the third switch S3 is turned off, the bias voltage generator Bias Gen is disconnected and no longer provides the bias voltage.

[0131] In combination with (b) in FIG. 9 , the first current source II can be a mirror current source, including a fourth current source I4, a driving transistor T4, and a mirror transistor T3 having a diode-connected structure.

[0132] The driving transistor T4 can be a MOS transistor, for example, an NMOS transistor. The drain of the driving NMOS transistor T4 is connected to the second switch S2.

[0133] The mirror transistor T3 can be a MOS transistor, for example, an NMOS transistor. The gate and drain of the mirror NMOS transistor T3 are both connected to the gate of the driving NMOS transistor T4 and the fourth current source I4.

[0134] Since the driving NMOS transistor T4 and the mirror NMOS transistor T3 form a mirror structure, the drain-source current flowing through the driving NMOS transistor T4 is equal to or proportional to the drain-source current flowing through the mirror NMOS transistor T3, and the drain-source current flowing through the mirror NMOS transistor T3 is the current provided by the fourth current source I4. Therefore, the drain-source current flowing through the driving NMOS transistor T4 is also equal to or proportional to the current provided by the fourth current source I4.

[0135] In some other embodiments, in combination with FIG. 8 As shown in FIG. 10 , the super source follower further includes a first switch S1. The first switch S1 is connected between the gate and drain of the second transistor T2.

[0136] The bias voltage source V OFS includes a first capacitor C1, a second capacitor C2, a sixth switch S6, and a seventh switch S7.

[0137] One terminal of the first capacitor C1 and one terminal of the second capacitor C2 are connected to the gate of the second transistor T2, and the other terminal of the first capacitor C1 and the other terminal of the second capacitor C2 are connected to the first current source II through the fourth switch S4 and the fifth switch S5, respectively.

[0138] The sixth switch S6 is connected in parallel with both terminals of the first capacitor C1. The seventh switch S7 is connected between the common node of the second capacitor C2 and the fifth switch S5 and the ground.

[0139] In the bias voltage generation mode, as shown in (a) of FIG. 6, the first switch S1, the sixth switch S6 and the seventh switch S7 are turned on, the fourth switch S4 and the fifth switch S5 are turned off, and the second capacitor C2 is charged by the second current source I2. FIG. 10

[0140] That is, the charging voltage at both ends of the structure composed of the first capacitor C1 and the second capacitor C2 can be used to realize the function of the bias voltage source V OFS . Specifically, the second capacitor C2 can be charged by the second current source I2, and thus a sufficiently large bias voltage can be obtained at the gate of the second transistor T2. As a result, the second transistor T2 is in saturation mode.

[0141] In the voltage buffer mode, as shown in (b) of FIG. 6, the first switch S1, the sixth switch S6 and the seventh switch S7 are turned off, the fourth switch S4 and the fifth switch S5 are turned on, and the first capacitor C1 is charged by the second capacitor C2. FIG. 10

[0142] In this way, if the bias voltage is too large and affects the normal operation of the super source follower, the second capacitor C2 will be controlled to discharge to the first capacitor C1 through one or more corresponding switches to reduce the bias voltage.

[0143] In addition, by providing a plurality of small-capacity capacitors in parallel to realize the function of the bias voltage source V OFS , the area can be saved, and the circuit design can be more flexible.

[0144] In addition, in order to improve the noise performance in the high-gain mode, the super source follower can be switched to the source follower according to the actual situation, thereby improving the flexibility.

[0145] In a possible implementation, in combination with FIG. 9 , as shown in FIG. 7, the super source follower can further include an eighth switch S8 and a ninth switch S9. FIG. 11 The eighth switch S8 is connected between the first current source I1 and the ground. The ninth switch S9 is connected between the gate of the second transistor T2 and the ground.

[0146]

[0147] ​​​When the first switch S1 and the third switch S3 are closed, and the second switch S2, the eighth switch S8, and the ninth switch S9 are opened, the bias voltage generator Bias Gen is disconnected, bypassing the first current source I1 and the second transistor T2, and the super source follower is in the source follower operation mode. For example, FIG. 11 The super source follower shown in (a) switches to FIG. 11 The source follower shown in (b) in FIG.

[0148] In other words, by controlling the on or off of these switches, it is possible to quickly switch between a super source follower and a source follower, thereby improving flexibility.

[0149] In another possible implementation, combining FIG. 10 ,like FIG. 12 As shown, the super source follower may further include a ninth switch S9. The ninth switch S9 is connected between the gate of the second transistor T2 and the ground.

[0150] When the first switch S1 is closed and the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7 and the ninth switch S9 are opened, the first current source I1 is bypassed and the second transistor T2 is bypassed, and the super source follower is in the source follower working mode. For example, FIG. 12 The super source follower shown in (a) switches to FIG. 12 The source follower shown in (b) in FIG.

[0151] In other words, by controlling the on or off of these switches, it is possible to quickly switch between a super source follower and a source follower, thereby improving flexibility.

[0152] In another possible implementation, combining FIG. 8 ,like FIG. 11 As shown, the super source follower may further include a first switch S1 , a second switch S2 , an eighth switch S8 and a ninth switch S9 .

[0153] The first switch S1 is connected between the gate and drain of the second transistor T2. The second switch S2 is connected between the drain of the first transistor T1 and the first current source I1. The eighth switch S8 is connected between the first current source I1 and ground. The ninth switch S9 is connected between the gate of the second transistor T2 and ground.

[0154] Bias voltage source V OFS It includes a first capacitor C1, a bias voltage generator Bias Gen and a third switch S3.

[0155] The first capacitor C1 is connected between the first current source I1 and the gate of the second transistor T2. The third switch S3 is connected between the bias voltage generator Bias Gen and the first current source I1.

[0156] When the first switch S1 and the third switch S3 are closed, and the second switch S2, the eighth switch S8 and the ninth switch S9 are open, the bias voltage generator Bias Gen is disconnected, bypassing the first current source I1, bypassing the second transistor T2, and the super source follower is in the source follower mode.

[0157] In other words, by controlling the opening or closing of these switches, the super source follower and the source follower can be quickly switched between each other, thereby improving flexibility. For example, the super source follower can be switched to the source follower to improve the noise performance in the high gain mode.

[0158] Embodiments of the present application provide a column parallel analog-to-digital converter (ADC). As shown in FIG. 13 and FIG. 14 , the column parallel ADC includes a plurality of comparators and one or more super source followers as shown in any one of FIG. 8 to FIG. 12 .

[0159] The one or more super source followers are connected between a reference level generator and the plurality of comparators, and the plurality of comparators are configured to compare a plurality of analog inputs and a buffered reference level.

[0160] In some embodiments, in combination with FIG. 9 , as shown in (a) and (b) of FIG. 13 , the column parallel ADC includes one super source follower, and an output terminal of the one super source follower is connected to reference signal input terminals of all comparators. That is, all comparators share the same super source follower, so as to simplify the circuit topology and reduce the area and cost.

[0161] In some other embodiments, in combination with FIG. 9 , as shown in (a) and (b) of FIG. 14 , the column parallel ADC includes a plurality of super source followers, and output terminals of the plurality of super source followers are respectively connected to reference signal input terminals of a plurality of comparators. That is, the plurality of comparators are respectively configured with one super source follower, so as to avoid interference between the comparators due to the kickback effect, thereby improving the image quality.

[0162] In some embodiments, the column-parallel ADC operates as a single-slope ADC in voltage-buffered mode. In this case, a super source follower is used to implement a bias voltage generation mode for each pixel at the end of the previous pixel's signal slope ADC process. Consequently, columns of adjacent pixels can complete digital-to-analog conversion in a pipelined manner, saving conversion time and improving A / D conversion efficiency.

[0163] An embodiment of the present invention provides a CMOS image sensor, comprising a pixel array and FIG. 13 and FIG. 14 The column-parallel ADC shown. The pixel array includes multiple pixels, each of which is configured to output an analog signal corresponding to the state of each pixel. Here, the "state of each pixel" depends on the number of photoelectrons captured by each of the multiple pixels in a single exposure.

[0164] mentioned above FIG. 8 to FIG. 12 The super source follower shown and FIG. 13 and FIG. 14 The column-parallel ADCs shown are only examples, and they may also include devices or circuits not shown in the figures. The embodiments of the present invention are not limited thereto.

[0165] It should be noted that the terms "first" and "second" in this application are intended to distinguish different objects rather than to describe a specific order. In the following, the terms "first" and "second" are used for descriptive purposes only and should not be interpreted as indicating or implying relative importance or implicitly indicating the number of technical features. Therefore, the features defined using "first" and "second" may explicitly or implicitly include one or more features. In the description of the embodiments of the present invention, unless otherwise stated, the term "multiple / a plurality of / the plurality of" refers to two or more.

[0166] The term “if’ as used herein is optionally construed to mean “when” or “in a case where” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” is optionally construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context.

[0167] The phrases “used to,” “applicable to,” or “configured to” as used herein are intended to refer to an open and inclusive language that does not exclude devices used to, applicable to, or configured to perform additional tasks or steps.

[0168] In addition, the terms “including” and “having” and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a list of steps or units is not limited to the listed steps or units, but optionally further includes not listed steps or units, or optionally includes other steps or units inherent to such processes, methods, products, or apparatuses.

[0169] It should be understood that in the present application, the term "at least one" refers to one or more. The term "at least two" refers to two or three or more. The term "and / or" is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, "A and / or B" only describes the relationship between the associated objects, which includes three cases. For example, "A and / or B" refers to three cases: only A, A and B, only B, wherein A and B can be single or multiple. The character " / " generally represents the "or" relationship of the associated objects, and can also represent the "and / or" relationship of the associated objects. "At least one of the following items" or similar expressions refer to any combination of these items, including single items or any combination of multiple items. For example, at least one of a, b or c means: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c can be single or multiple.

[0170] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, i.e., "including, but not limited to". In the specification, terms such as "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with one or more embodiments or one or more examples is included in at least one embodiment or example of the present invention. The schematic representation of the above terms does not necessarily refer to the same one or more embodiments or one or more examples. In addition, the particular features, structures, materials or characteristics can be included in any one or more embodiments or examples using any suitable means. In addition, in the embodiments of the present invention, the terms "optionally", "specifically", "exemplary" or "for example" are used to exemplify, illustrate or explain. Any embodiment or design scheme using the words "optionally," "specifically," "exemplary," or "for example" in the embodiments of the present invention is not necessarily to be interpreted as being preferred or advantageous over other embodiments or designs. On the contrary, the use of words / phrases such as "optionally," "specifically," "exemplary," or "for example" is intended to present the relevant concepts in a specific manner that is easier to understand.

[0171] In the embodiment of the present invention, some characteristics with the same symbol may have different meanings, but these characteristics are related to each other. For example, the bias voltage source and the bias voltage provided by the bias voltage source are represented by the same symbol V OFS indicate, but they have different meanings.

[0172] The circuit structure and business scenarios described in the embodiments of the present application are intended to more clearly explain the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that, with the evolution of circuit structures and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present invention are also applicable to similar technical problems. For example, the super source follower and column-parallel ADC provided by the present invention can also be applied to other fields requiring high-quality analog-to-digital conversion in addition to image processing, and the embodiments of the present invention do not limit this.

[0173] The above description is merely a specific implementation of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions within the technical scope of the present application that can be conceived by those skilled in the art should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be construed as the scope of protection of the claims.

Claims

1. A super source follower, comprising: The super source follower comprises: a first transistor, wherein a gate of the first transistor is connected with an input node, and a source of the first transistor is connected with an output node; a second transistor, wherein a polarity of the second transistor is opposite to that of the first transistor, and a drain of the second transistor is connected with the output node; a first current source connected with a drain of the first transistor and configured to provide a bias current to the first transistor; a second current source connected with the source of the first transistor and configured to provide a bias current to the second transistor, wherein the bias current of the second transistor is configured to be obtained by subtracting the first current source from the second current source; a bias voltage source connected between the drain of the first transistor and a gate of the second transistor and configured to provide a direct current bias voltage.

2. The super source follower of claim 1, wherein, The bias voltage source is configured to provide a voltage to the gate of the second transistor, so that when a drain voltage of the first transistor is not high enough as a gate voltage of the second transistor, the second transistor is in a saturation mode.

3. The super source follower of claim 2, wherein, The first transistor is a P-type metal-oxide-semiconductor (MOS) transistor, and the second transistor is an N-type MOS transistor; when the second transistor is in the saturation mode, the input voltage V IN satisfies the following conditions: V IN (V thn +V dsatn –V thp –V OFS ), wherein V thn is a threshold voltage of the second transistor, V dsatn is a pinch-off voltage of the second transistor, V thp is a threshold voltage of the first transistor, V OFS is the bias voltage provided by the bias voltage source; The bias voltage V provided by the bias voltage source OFS satisfies the following conditions: V OFS <(V thn +V dsatn –V L,min ), wherein V L,min is the minimum voltage value in the node coupling the first current source and the bias voltage source to operate the first current source as a constant current source.

4. The super source follower of claim 2, wherein, The first transistor is an N-type MOS transistor, and the second transistor is a P-type MOS transistor; when the second transistor is in the saturation mode, the input voltage V IN satisfies the following conditions: V IN <(V DD –V thp –V dsatp +V thn –V OFS ), wherein V DD is a power supply voltage of the source of the second transistor, V thp is a threshold voltage of the second transistor, V dsatp is a pinch-off voltage of the second transistor, V thn is a threshold voltage of the first transistor, V OFS is the bias voltage provided by the bias voltage source; The bias voltage V provided by the bias voltage source OFS satisfies the following conditions: V OFS >(V DD –V thp –V dsatp –V L,max ), wherein V L,max is the maximum voltage value in the node coupling the first current source and the bias voltage source to operate the first current source as a constant current source.

5. The super source follower of any one of claims 1 to 4, wherein, The super source follower further comprises: a first switch connected between the gate and the drain of the second transistor; a second switch connected between the drain of the first transistor and the first current source; The bias voltage source comprises: a first capacitor connected between the first current source and the gate of the second transistor; a bias voltage generator; a third switch connected between the bias voltage generator and the first current source, In the bias voltage generation mode, the first switch, the second switch and the third switch are configured to be in an open state, a closed state and an open state respectively, the gate of the first transistor receives an input voltage V IN is set to a minimum value or a maximum value, the first capacitor is charged to obtain a bias voltage between the gate of the second transistor and the first current source, wherein the bias voltage is determined by a forward bias voltage of the second transistor and an output voltage of the bias voltage generator; In a voltage buffer mode, the first switch, the second switch and the third switch are respectively configured to be in an off state, an on state and an off state, a bias voltage of two terminals of the first capacitor is configured to keep the second transistor in a saturation mode, and a swing of the input voltage received by the gate of the first transistor is maximized.

6. The super source follower of claim 5, wherein, The super source follower further comprises: an eighth switch connected between the first current source and a ground; a ninth switch connected between the gate of the second transistor and the ground, wherein when the first switch and the third switch are off, and the second switch, the eighth switch and the ninth switch are on, the bias voltage generator is disconnected, bypassing the first current source and the second transistor, and the super source follower is in a source follower working mode.

7. The super source follower of any one of claims 1 to 4, wherein, The super source follower further comprises: a first switch connected between the gate and the drain of the second transistor; The bias voltage source comprises: a first capacitor; a second capacitor, wherein one terminal of the first capacitor and one terminal of the second capacitor are connected to the gate of the second transistor, and the other terminal of the first capacitor and the other terminal of the second capacitor are connected to the first current source through a fourth switch and a fifth switch, respectively; a sixth switch connected in parallel to the two terminals of the first capacitor; a seventh switch connected between a common node of the second capacitor and the fifth switch and ground, wherein, in a bias voltage generation mode, the first switch, the sixth switch and the seventh switch are turned on, the fourth switch and the fifth switch are turned off, and the second capacitor is charged by the second current source; in a voltage buffer mode, the first switch, the sixth switch and the seventh switch are turned off, the fourth switch and the fifth switch are turned on, and the first capacitor is charged by the second capacitor.

8. The super source follower of claim 7, wherein, The super source follower further comprises: a ninth switch connected between the gate of the second transistor and ground, when the first switch is turned off, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the ninth switch are turned on, bypassing the first current source and bypassing the second transistor, the super source follower is in a source follower working mode.

9. The super source follower of any one of claims 1 to 4, wherein, The super source follower further comprises: a first switch connected between the gate and the drain of the second transistor; a second switch connected between the drain of the first transistor and the first current source; an eighth switch connected between the first current source and ground; a ninth switch connected between the gate of the second transistor and ground; The bias voltage source comprises: a first capacitor connected between the first current source and the gate of the second transistor; a bias voltage generator; a third switch connected between the bias voltage generator and the first current source, wherein, when the first switch and the third switch are turned off, the second switch, the eighth switch and the ninth switch are turned on, the bias voltage generator is disconnected, bypassing the first current source and bypassing the second transistor, the super source follower is in a source follower working mode.

10. A column parallel analog to digital converter (ADC), comprising: The column parallel ADC comprises: a plurality of comparators; one or more super source followers according to any one of claims 1 to 9, wherein the one or more super source followers are connected between a reference level generator and the plurality of comparators, and the comparators are configured to compare a plurality of analog inputs and a buffered reference level.

11. The column parallel ADC of claim 10, wherein, The column parallel ADC comprises one super source follower; an output terminal of the super source follower is connected to a reference signal input terminal of all the comparators.

12. The column parallel ADC of claim 10, wherein, The column parallel ADC comprises a plurality of super source followers, and an output terminal of each of the plurality of super source followers is connected to a reference signal input terminal of all the comparators.

13. The column parallel ADC of any of claims 10-12, wherein, The column parallel ADC works as a single slope ADC in a voltage buffer mode; The super source follower is used to realize a bias voltage generation mode of a pixel at the end of a signal slope ADC process of a previous pixel.

14. A CMOS image sensor, characterized by comprising: The CMOS image sensor includes: a pixel array, wherein the pixel array includes a plurality of pixels, each pixel configured to output an analog signal corresponding to a state of each pixel; The column parallel ADC according to any one of claims 10 to 13.

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