A method of manufacturing a semiconductor probe card

Abstract

The application provides a preparation method of a semiconductor probe card, comprising the following steps: preparing a wafer; performing photoetching and electroplating on the upper surface of a ceramic substrate to form a first copper layer; performing photoetching and electroplating to form a first nickel-cobalt alloy layer; after photoetching, electroplating is performed on the N first nickel-cobalt alloy layers to form a second nickel-cobalt alloy layer, and electroplating is performed on the remaining first nickel-cobalt alloy layers to form a third nickel-cobalt alloy layer; after photoetching, a first gold layer is formed on each of the second nickel-cobalt alloy layer and the third nickel-cobalt alloy layer by electroplating; all photoresist layers are removed to obtain a ceramic sheet; the wafer is placed above the ceramic sheet with the limiting blocks facing downward, and the side surfaces of the N limiting blocks are in abutment with the side surfaces of the N stacked second nickel-cobalt alloy layers and first nickel-cobalt alloy layers; the first gold layer and the second gold layer are bonded; and the silicon substrate of the wafer and the limiting blocks are removed. The preparation method of the semiconductor probe card can realize precise bonding of the wafer and the ceramic sheet, improve product yield, and reduce cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for preparing a semiconductor probe card. Background Technology

[0002] A probe card is a key component used for front-end semiconductor wafer testing, enabling electrical connection between the wafer chip and the testing machine. It consists of multiple probes that test the electrical performance of the wafer chip by contacting it.

[0003] MEMS probe cards are a new type of probe card manufactured using microelectromechanical systems (MEMS) technology. MEMS probes utilize microfabrication techniques to integrate over 100k pins within a single probe card, meeting the testing needs of electronic devices. The probe card consists of a wafer and a ceramic sheet, which are bonded together using a bonding process during fabrication.

[0004] However, existing fabrication processes cannot achieve precise alignment between the ceramic wafer and the wafer during bonding. On one hand, the positioning equipment used for alignment lacks precision, leading to deviations in the positional calibration of the ceramic wafer and the wafer, failing to meet the high-precision alignment standards required for bonding. On the other hand, the skill level of the operators and the adherence to standardized operating procedures also significantly impact alignment accuracy. Inexperienced operators or failure to strictly follow standard procedures can easily introduce additional errors when adjusting the positions of the ceramic wafer and the wafer, affecting alignment accuracy and resulting in inaccurate alignment before bonding. Inaccurate alignment leads to poor bonding, affecting product yield and wasting significant manpower and material resources in upstream processes. This not only impacts production efficiency but also increases production costs and reduces economic benefits. Summary of the Invention

[0005] This invention provides a method for fabricating a semiconductor probe card, which enables precise bonding between wafers and ceramic sheets, improving product yield and reducing costs.

[0006] To address the aforementioned technical problems, this invention provides a method for preparing a semiconductor probe card, comprising the following steps:

[0007] Step 10: Prepare a wafer; the wafer has N limiting blocks and M probes, the limiting blocks and probes are located on two sides of the wafer respectively, and each probe has a second gold layer on its surface; N is an integer greater than or equal to 1, M is an integer greater than or equal to 2, and M is greater than N;

[0008] Step 20: Apply photoresist to the upper surface of the ceramic substrate to form a first photoresist layer; after exposure and development, form M first circuit patterns; electroplate a first copper layer on each first circuit pattern.

[0009] Step 30: Apply photoresist to all first copper layers and the remaining first photoresist layer to form a second photoresist layer; after exposure and development, form a second circuit pattern on each first copper layer; electroplate a first nickel-cobalt alloy layer on each second circuit pattern.

[0010] Step 40: Apply photoresist to all first nickel-cobalt alloy layers and the remaining second photoresist layer to form a third photoresist layer; after exposure and development, form a third circuit pattern on N first nickel-cobalt alloy layers and a fourth circuit pattern on the remaining first nickel-cobalt alloy layers; electroplate a second nickel-cobalt alloy layer on each third circuit pattern and electroplate a third nickel-cobalt alloy layer on each fourth circuit pattern; the orthographic projection of the second nickel-cobalt alloy layer on the ceramic substrate completely coincides with the orthographic projection of the first nickel-cobalt alloy layer on the ceramic substrate; the orthographic projection area of ​​the third nickel-cobalt alloy layer on the ceramic substrate is smaller than the orthographic projection area of ​​the first nickel-cobalt alloy layer on the ceramic substrate; the N second nickel-cobalt alloy layers correspond one-to-one with the N limiting blocks on the wafer;

[0011] Step 50: Apply photoresist to all the second nickel-cobalt alloy layers, the third nickel-cobalt alloy layers, and the retained third photoresist layer to form a fourth photoresist layer; after exposure and development, form a fifth circuit pattern on each of the second and third nickel-cobalt alloy layers; electroplate a first gold layer on each of the fifth circuit patterns.

[0012] Step 60: Remove all photoresist layers to obtain a ceramic wafer;

[0013] Step 70: Place the wafer on top of the ceramic sheet with the probe tip facing upwards and the limiting block facing downwards. Then, make the sides of the N limiting blocks abut against the sides of the N stacked second nickel-cobalt alloy layers and the first nickel-cobalt alloy layers, so that all the second gold layers of the wafer correspond one-to-one with all the first gold layers of the ceramic sheet.

[0014] Step 80: Bond the first gold layer of the ceramic wafer to the second gold layer of the wafer;

[0015] Step 90: Remove the silicon substrate and limiting block from the wafer.

[0016] As a further improvement of the present invention, step 10 specifically includes:

[0017] Step 101: Coat the upper surface of the intermediate product with photoresist to form a sixth photoresist layer; the intermediate product includes a silicon substrate, M probes formed on the silicon substrate, and a fifth photoresist layer located between the probes; after exposure and development, form a sixth circuit pattern on each probe; electroplate a second gold layer on each sixth circuit pattern.

[0018] Step 102: Apply photoresist to the upper surface of all the second gold layers and the retained sixth photoresist layer to form a seventh photoresist layer; after exposure and development, form a seventh circuit pattern next to each of the N probes; electroplate a fourth nickel-cobalt alloy layer on each seventh circuit pattern, and planarize the fourth nickel-cobalt alloy layer to obtain M limiting blocks.

[0019] Step 103: Remove all photoresist layers to obtain a wafer.

[0020] As a further improvement of the present invention, the ratio of N to M is 6 to 8:100.

[0021] As a further improvement of the present invention, the orthographic projection of the first gold layer on the ceramic sheet located on the third nickel-cobalt alloy layer completely coincides with the orthographic projection of the third nickel-cobalt alloy layer on the ceramic sheet.

[0022] As a further improvement of the present invention, all third nickel-cobalt alloy layers are identical in shape and size.

[0023] As a further improvement of the present invention, the thickness of the fourth nickel-cobalt alloy layer is 80-100µm.

[0024] As a further improvement of the present invention, the thickness of the second gold layer is 1±0.5µm.

[0025] As a further improvement of the present invention, the thickness of the first gold layer is 1±0.5µm.

[0026] As a further improvement of the present invention, in step 20, before electroplating, the surface of the first circuit pattern is treated by a plasma surface treatment method; in step 30, before electroplating, the surface of the second circuit pattern is treated by a plasma surface treatment method; in step 40, before electroplating, the surfaces of the third and fourth circuit patterns are treated by a plasma surface treatment method; and in step 50, before electroplating, the surface of the fifth circuit pattern is treated by a plasma surface treatment method.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] This invention provides a method for fabricating a semiconductor probe card. N limiting blocks are formed on a wafer, and N stacked second nickel-cobalt alloy layers and first nickel-cobalt alloy layers adapted to the limiting blocks are formed on a ceramic sheet. When the ceramic sheet is bonded to the wafer, the sides of the N limiting blocks abut against the sides of the N stacked second and first nickel-cobalt alloy layers, providing positioning and achieving precise bonding between the wafer and the ceramic sheet, improving product yield and reducing costs. When fabricating the ceramic sheet, the existing process is used to prepare the first nickel-cobalt alloy layers corresponding to the M probes on the wafer. Second nickel-cobalt alloy layers of the same size as the first nickel-cobalt alloy layers are formed only on the N first nickel-cobalt alloy layers corresponding to the N limiting blocks. The existing process is used to form third nickel-cobalt alloy layers on the other first nickel-cobalt alloy layers, without increasing the process flow. This also provides a suitable thickness for the mounting of the limiting blocks and prevents the nickel-cobalt alloy layers from detaching, further improving product yield. Attached Figure Description

[0029] Figure 1 This is a flowchart of a method for preparing a semiconductor probe card according to an embodiment of the present invention;

[0030] Figure 2 This is a flowchart of step 10 in the method of this embodiment of the invention.

[0031] The figure includes: ceramic substrate 11, first photoresist layer 12, first circuit pattern 121, first copper layer 13, first nickel-cobalt alloy layer 14, second nickel-cobalt alloy layer 15, third nickel-cobalt alloy layer 16, first gold layer 17, silicon substrate 21, probe 22, fifth photoresist layer 23, sixth photoresist layer 24, second gold layer 25, seventh photoresist layer 26, fourth nickel-cobalt alloy layer 27, lower oxide layer 28, upper oxide layer 29, and titanium-copper alloy layer 30. Detailed Implementation

[0032] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] The terms “first,” “second,” “third,” “fourth,” etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order.

[0034] This invention provides a method for preparing a semiconductor probe card, comprising the following steps:

[0035] Step 10: Prepare a wafer. The wafer has N limiting blocks and M probes 22, with the limiting blocks and probes located on opposite sides of the wafer, and each probe 22 has a second gold layer 25 on its surface. N is an integer greater than or equal to 1, M is an integer greater than or equal to 2, and M is greater than N.

[0036] like Figure 2As shown, step 10 specifically includes:

[0037] Step 1001: An upper oxide layer 29 is formed on the upper surface of the silicon substrate 21, and a lower oxide layer 28 is formed on the lower surface of the silicon substrate 21. Photoresist is then applied to the upper surface of the upper oxide layer 29 to form a first photoresist layer.

[0038] Step 1002: Expose and develop the M first preset positions of the photoresist layer to form M first etched positions.

[0039] Step 1003: The upper oxide layer 29 and the silicon substrate 21 directly below each first etch site are etched sequentially to form M tip growth sites; the photoresist layer is removed.

[0040] Step 1004: A titanium-copper alloy layer 30 is formed on the surface of the tip growth site and the upper surface of the upper oxide layer 29 using a sputtering process. Photoresist is then applied to the upper surface of the titanium-copper alloy layer 30 to form a fifth photoresist layer 23. The M second preset positions of the second photoresist layer are exposed and developed to form a needle growth site above each tip growth site.

[0041] Step 1005: A fifth nickel-cobalt alloy layer is formed at M tip growth sites and needle body growth sites using an electroplating process. The fifth nickel-cobalt alloy layer is then planarized to form M probes 22, resulting in an intermediate product.

[0042] Step 101: Photoresist is applied to the upper surface of the intermediate product to form a sixth photoresist layer 24. The intermediate product includes a silicon substrate 21, M probes 22 formed on the silicon substrate 21, and a fifth photoresist layer 23 located between the probes. After exposure and development, a sixth circuit pattern is formed on each probe 22. A second gold layer 25 is electroplated on each sixth circuit pattern. Preferably, the thickness of the second gold layer 25 is 1 ± 0.5 µm.

[0043] Step 102: Photoresist is applied to the upper surfaces of all the second gold layers 25 and the retained sixth photoresist layer 24 to form a seventh photoresist layer 26. After exposure and development of the seventh photoresist layer 26 and the sixth photoresist layer 24, seventh circuit patterns are formed next to the N probes 22. A fourth nickel-cobalt alloy layer 27 is electroplated on each seventh circuit pattern, and the fourth nickel-cobalt alloy layer 27 is planarized to obtain M limiting blocks.

[0044] Preferably, the thickness of the fourth nickel-cobalt alloy layer 27 is 80-100µm, that is, the thickness of the limiting block is 80-100µm. If the limiting block is too thick, it will warp and affect the product quality; if it is too thin, it will not be able to abut against the sides of the second nickel-cobalt alloy layer 15 and the first nickel-cobalt alloy layer 14 stacked on the ceramic sheet, thus affecting the positioning function.

[0045] Step 103: Remove all photoresist layers to obtain a wafer.

[0046] like Figure 1 As shown, in step 20, photoresist is coated on the upper surface of the ceramic substrate 11 to form a first photoresist layer 12. After exposure and development, M first circuit patterns 121 are formed. A first copper layer 13 is electroplated on each first circuit pattern.

[0047] Preferably, before electroplating, the surface of the first circuit pattern 121 is treated with a plasma surface treatment method. This removes residual photoresist from the surface of the first circuit pattern, changing its hydrophobicity to hydrophilicity. This facilitates the subsequent deposition of the first copper layer and enhances the adhesion between the first copper layer and the ceramic substrate 11.

[0048] Step 30: Photoresist is applied to all the first copper layers 13 and the retained first photoresist layer 12 to form a second photoresist layer. After exposure and development of the second photoresist layer, a second circuit pattern is formed on each first copper layer 13. A first nickel-cobalt alloy layer 14 is electroplated on each second circuit pattern.

[0049] Preferably, before electroplating, the surface of the second circuit pattern is treated with a plasma surface treatment method. This removes residual photoresist from the surface of the second circuit pattern, changing its hydrophobicity to hydrophilicity. This facilitates the subsequent deposition of the first nickel-cobalt alloy layer 14 and enhances the adhesion between the first nickel-cobalt alloy layer 14 and the first copper layer.

[0050] Step 40: Photoresist is applied to all the first nickel-cobalt alloy layers 14 and the remaining second photoresist layer to form a third photoresist layer. After exposure and development of the third photoresist layer, a third circuit pattern is formed on N first nickel-cobalt alloy layers 14, and a fourth circuit pattern is formed on the remaining first nickel-cobalt alloy layers 14. A second nickel-cobalt alloy layer 15 is electroplated on each third circuit pattern, and a third nickel-cobalt alloy layer 16 is electroplated on each fourth circuit pattern. Preferably, the ratio of N to M is 6 to 8:100.

[0051] Preferably, before electroplating, the surfaces of the third and fourth circuit patterns are treated using a plasma surface treatment method. This removes residual photoresist from the surfaces of the third and fourth circuit patterns, changing their hydrophobicity to hydrophilicity. This facilitates the subsequent deposition of the second nickel-cobalt alloy layer 15 and the third nickel-cobalt alloy layer 16, and enhances the adhesion between the first nickel-cobalt alloy layer 14 and the second nickel-cobalt alloy layer 15, and between the first nickel-cobalt alloy layer 14 and the third nickel-cobalt alloy layer 16.

[0052] The orthographic projection of the second nickel-cobalt alloy layer 15 onto the ceramic substrate completely coincides with the orthographic projection of the first nickel-cobalt alloy layer 14 onto the ceramic substrate, meaning the second nickel-cobalt alloy layer 15 and the first nickel-cobalt alloy layer 14 are the same size and shape. Each of the N second nickel-cobalt alloy layers 15 corresponds one-to-one with the N limiting blocks on the wafer during bonding. The orthographic projection area of ​​the third nickel-cobalt alloy layer 16 onto the ceramic substrate is smaller than the orthographic projection area of ​​the first nickel-cobalt alloy layer 14 onto the ceramic substrate. All third nickel-cobalt alloy layers 16 are the same size.

[0053] Step 50: Photoresist is applied to all the second nickel-cobalt alloy layers 15, the third nickel-cobalt alloy layer 16, and the retained third photoresist layer to form a fourth photoresist layer. After exposure and development of the fourth photoresist layer, a fifth circuit pattern is formed on each of the second nickel-cobalt alloy layers 15 and the third nickel-cobalt alloy layer 16. A first gold layer 17 is electroplated on each fifth circuit pattern.

[0054] Preferably, before electroplating, the surface of the fifth circuit pattern is treated with a plasma surface treatment method. This removes residual photoresist from the surface of the fifth circuit pattern, changing its hydrophobicity to hydrophilicity. This facilitates the subsequent deposition of the first gold layer 17 and enhances the adhesion between the second nickel-cobalt alloy layer 15 and the first gold layer 17, and between the third nickel-cobalt alloy layer 16 and the first gold layer 17.

[0055] Preferably, the orthographic projection of the first gold layer 17 on the ceramic sheet on the third nickel-cobalt alloy layer 16 completely coincides with the orthographic projection of the third nickel-cobalt alloy layer 16 on the ceramic sheet, that is, the first gold layer 17 and the third nickel-cobalt alloy layer 16 are the same size. Preferably, all first gold layers 17 are the same size.

[0056] Preferably, the thickness of the first gold layer 17 is 1 ± 0.5 µm.

[0057] Step 60: Remove all photoresist layers to obtain a ceramic wafer.

[0058] Step 70: Place the wafer on top of the ceramic sheet, flip the wafer so that the probe tip is facing up and the limiting block is facing down, and make the sides of the N limiting blocks abut against the sides of the N stacked second nickel-cobalt alloy layers 15 and the first nickel-cobalt alloy layers 14, so that all the second gold layers 25 of the wafer correspond one-to-one with all the first gold layers 17 of the ceramic sheet.

[0059] Step 80: The first gold layer 17 of the ceramic sheet and the second gold layer 25 of the wafer are bonded together using an adhesive.

[0060] Step 90: Remove the silicon substrate 21 and the limiting block from the wafer.

[0061] Specifically, the product obtained in step 80 is placed in the Wet Station equipment for the Lift-Off process, and is soaked in sulfuric acid solution to cause the titanium-copper alloy layer 30 to undergo a chemical reaction and fall off, thereby automatically separating the silicon substrate 21, the upper oxide layer 29, the lower oxide layer 28 and the limiting block from the probe 22.

[0062] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor probe card, characterized in that, Includes the following steps: Step 10: Prepare a wafer; the wafer has N limiting blocks and M probes (22), the limiting blocks and probes are located on two sides of the wafer respectively, and each probe (22) has a second gold layer (25) on its surface; N is an integer greater than or equal to 1, M is an integer greater than or equal to 2, and M is greater than N; Step 20: Photoresist is applied to the upper surface of the ceramic substrate (11) to form a first photoresist layer (12); after exposure and development, M first circuit patterns (121) are formed; a first copper layer (13) is electroplated on each first circuit pattern. Step 30: Apply photoresist to all the first copper layers (13) and the retained first photoresist layer (12) to form a second photoresist layer; after exposure and development, form a second circuit pattern on each first copper layer (13); electroplate a first nickel-cobalt alloy layer (14) on each second circuit pattern. Step 40: Photoresist is applied to all the first nickel-cobalt alloy layers (14) and the remaining second photoresist layer to form a third photoresist layer; after exposure and development, a third circuit pattern is formed on N first nickel-cobalt alloy layers (14), and a fourth circuit pattern is formed on the remaining first nickel-cobalt alloy layers (14); a second nickel-cobalt alloy layer (15) is electroplated on each third circuit pattern, and a third nickel-cobalt alloy layer (16) is electroplated on each fourth circuit pattern; the orthographic projection of the second nickel-cobalt alloy layer (15) on the ceramic substrate completely coincides with the orthographic projection of the first nickel-cobalt alloy layer (14) on the ceramic substrate; the orthographic projection area of ​​the third nickel-cobalt alloy layer (16) on the ceramic substrate is smaller than the orthographic projection area of ​​the first nickel-cobalt alloy layer (14) on the ceramic substrate; the N second nickel-cobalt alloy layers (15) correspond one-to-one with the N limiting blocks on the wafer; Step 50: Apply photoresist to all the second nickel-cobalt alloy layers (15), the third nickel-cobalt alloy layers (16) and the retained third photoresist layer to form a fourth photoresist layer; after exposure and development, form a fifth circuit pattern on each of the second nickel-cobalt alloy layers (15) and the third nickel-cobalt alloy layers (16); electroplate a first gold layer (17) on each of the fifth circuit patterns. Step 60: Remove all photoresist layers to obtain a ceramic wafer; Step 70: Place the wafer on top of the ceramic sheet with the probe tip facing up and the limiting block facing down, and make the sides of the N limiting blocks abut against the sides of the N stacked second nickel-cobalt alloy layers (15) and the first nickel-cobalt alloy layers (14), so that all the second gold layers (25) of the wafer correspond one-to-one with all the first gold layers (17) of the ceramic sheet. Step 80: Bond the first gold layer (17) of the ceramic sheet to the second gold layer (25) of the wafer; Step 90: Remove the silicon substrate and limiting block from the wafer.

2. The method for preparing a semiconductor probe card according to claim 1, characterized in that, Step 10 specifically includes: Step 101: Photoresist is applied to the upper surface of the intermediate product to form a sixth photoresist layer (24); the intermediate product includes a silicon substrate (21), M probes (22) formed on the silicon substrate (21), and a fifth photoresist layer (23) located between the probes; after exposure and development, a sixth circuit pattern is formed on each probe (22); a second gold layer (25) is electroplated on each sixth circuit pattern. Step 102: Photoresist is applied to the upper surface of all the second gold layers (25) and the retained sixth photoresist layer to form a seventh photoresist layer (26); after exposure and development, a seventh circuit pattern is formed next to N probes (22); a fourth nickel-cobalt alloy layer (27) is electroplated on each seventh circuit pattern, and the fourth nickel-cobalt alloy layer (27) is planarized to obtain M limiting blocks; Step 103: Remove all photoresist layers to obtain a wafer.

3. The method for preparing a semiconductor probe card according to claim 1, characterized in that, The ratio of N to M is 6 to 8:

100.

4. The method for preparing a semiconductor probe card according to claim 1, characterized in that, The orthographic projection of the first gold layer (17) on the ceramic sheet located on the third nickel-cobalt alloy layer (16) is completely coincident with the orthographic projection of the third nickel-cobalt alloy layer (16) on the ceramic sheet.

5. The method for preparing a semiconductor probe card according to claim 1, characterized in that, All the third nickel-cobalt alloy layers (16) are the same in shape and size.

6. The method for preparing a semiconductor probe card according to claim 2, characterized in that, The thickness of the fourth nickel-cobalt alloy layer (27) is 80–100 µm.

7. The method for preparing a semiconductor probe card according to claim 2, characterized in that, The thickness of the second gold layer (25) is 1 ± 0.5 µm.

8. The method for preparing a semiconductor probe card according to claim 1, characterized in that, The thickness of the first gold layer (17) is 1 ± 0.5 µm.

9. The method for preparing a semiconductor probe card according to claim 1, characterized in that, In step 20, before electroplating, the surface of the first circuit pattern (121) is treated by plasma surface treatment method; in step 30, before electroplating, the surface of the second circuit pattern is treated by plasma surface treatment method. In step 40, before electroplating, the surfaces of the third and fourth circuit patterns are treated using a plasma surface treatment method; in step 50, before electroplating, the surface of the fifth circuit pattern is treated using a plasma surface treatment method.

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