Manufacturing process of ultraviolet imaging CMOS image sensor
By fabricating Ga2O3 thin films on CMOS image sensors, the problems of poor ultraviolet response and high cost are solved, achieving highly integrated ultraviolet imaging that is compatible with traditional CMOS processes.
Patent Information
- Application Number
- CN202510826980.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-19
- Publication Date
- 2025-10-28
AI Technical Summary
Existing CMOS image sensors have limited spectral response range in the ultraviolet band, resulting in extremely poor ultraviolet response. Furthermore, existing ultraviolet imaging solutions are costly, have low integration, and poor compatibility with traditional CMOS technologies.
A Ga2O3 thin film is formed above the photosensitive area of a silicon-based CMOS image sensor. An ultraviolet light absorption layer is prepared by etching, magnetron sputtering and patterning processes to achieve heterogeneous integration of Ga2O3 and CMOS.
It achieves highly integrated ultraviolet imaging, reduces costs, is fully compatible with CMOS processes, and improves ultraviolet light absorption performance.
Smart Images
Figure CN120857656A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, specifically a manufacturing process for an ultraviolet imaging CMOS image sensor. Background Technology
[0002] CMOS image sensors are widely used not only in consumer electronics products such as small digital cameras, mobile phone cameras, and portable camcorders, but also in automotive, surveillance, security, and robot vision fields. Traditional 4T pixel structures, such as... Figure 1 As shown, it consists of four core transistors forming a complete signal chain: the transfer transistor (TG) controls the transfer of photogenerated charge from the photodiode to the floating diffusion node (FD); the reset transistor (RST) is responsible for the potential initialization of the FD node; the source follower (SF) converts the charge into a voltage signal; and the row select transistor (RS) implements the row addressing function. Silicon-based photodiodes, as the photosensitive core, typically employ a pn junction or pinned photodiode (PPD) structure, separating photogenerated electron-hole pairs through the electric field in the depletion region. The advantages of this structure are: suppression of fixed-mode noise through correlated double sampling (CDS); reduced dark current due to the PPD structure; and full compatibility with CMOS processes.
[0003] However, its spectral response range is limited by the intrinsic properties of silicon, exhibiting effective absorption only in the 400-800 nm wavelength range, with a fundamental deficiency in the ultraviolet band. The optical properties of silicon result in extremely poor ultraviolet response, specifically manifested as follows:
[0004] 1. Shallow absorption depth: The penetration depth of ultraviolet light (200-400nm) in silicon is only 10-20nm (e.g., the absorption depth of 300nm ultraviolet light is about 15nm), which causes photogenerated carriers to be generated in extremely thin areas of the surface. They are easily recombinated by surface states and spatially separated from the depletion region (usually located at a submicron depth), resulting in a charge collection efficiency of <20%.
[0005] 2. High reflectivity loss: Silicon has a reflectivity of >40% for ultraviolet light (<30% for visible light).
[0006] Currently, the main solutions for ultraviolet imaging are as follows:
[0007] 1. InGaAs photodiode array sensor: This type of sensor can effectively absorb ultraviolet light, but its manufacturing process is complex, the cost is high, and the integration is low, making it difficult to be compatible with traditional CMOS technology.
[0008] 2. Ultraviolet fiber optic array: This type of technology usually requires a special fiber optic array to guide ultraviolet light, which not only increases the complexity of the system, but also leads to higher costs and lower integration.
[0009] 3. Gallium nitride (GaN) material sensors: Although GaN material has good ultraviolet light absorption capability, its growth and integration process is complex and has poor compatibility with silicon-based CMOS technology.
[0010] The common problems with the above-mentioned existing technologies are their high cost, low integration, and poor compatibility with traditional CMOS technology, which limit their application in the field of large-scale, low-cost ultraviolet imaging. Summary of the Invention
[0011] This invention addresses the shortcomings of existing technologies by providing a manufacturing process for an ultraviolet imaging CMOS image sensor.
[0012] A manufacturing process for an ultraviolet imaging CMOS image sensor includes the following steps:
[0013] Step 1. Form a back-end dielectric layer above the photosensitive area of a silicon-based CMOS image sensor;
[0014] Step 2. Etch away the back dielectric layer to expose the photosensitive area;
[0015] Step 3. Deposit a Ga2O3 thin film over the exposed photosensitive area using magnetron sputtering technology to form an ultraviolet light absorbing layer;
[0016] Step 4. Pattern the Ga2O3 film to ensure that Ga2O3 material is retained only above the photosensitive area;
[0017] Step 5. Perform post-processing and cleaning to remove photoresist and clean surface residues to ensure the Ga2O3 film surface is clean.
[0018] The etching step employs dry etching using a mixed gas of SF6 and O2; during the magnetron sputtering process, a mixed gas of O2 and Ar is used, with the sputtering power set in the range of 150-250W and the sputtering temperature maintained between 200℃ and 350℃; and in the patterning process, reactive ion etching (RIE) is used, employing a mixed gas of Cl2 and CF4 for etching.
[0019] The beneficial effects of this invention are:
[0020] 1. Heterogeneous integration of Ga2O3 and Si: The heterogeneous integration scheme of Ga2O3 and silicon materials proposed in this invention can effectively solve the problem of ultraviolet imaging and is fully compatible with CMOS back-end processes, avoiding the high cost and low integration of traditional ultraviolet imaging devices.
[0021] 2. Low-temperature compatible fabrication process: Ga2O3 thin films are prepared using low-temperature magnetron sputtering and other techniques, ensuring compatibility with CMOS devices while maintaining the material's ultraviolet light absorption performance.
[0022] 3. High integration and high efficiency: By integrating Ga2O3 with CMOS through back-end processes, ultraviolet imaging can be achieved without reducing the integration level of CIS, which greatly improves the performance of image sensors. Attached Figure Description
[0023] Figure 1 This is a traditional 4T pixel structure diagram;
[0024] Figure 2 This is a SEM image obtained after etching the back dielectric layer in an embodiment of this application;
[0025] Figure 3 This is a structural diagram of the CMOS image sensor obtained in the embodiments of this application;
[0026] Figure 4 for Figure 3 The diagram shows the working principle of the sensor. Detailed Implementation
[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0028] This application provides a manufacturing process for an ultraviolet imaging CMOS image sensor, which mainly integrates Ga2O3 material and silicon-based CMOS image sensor through back-end processes to achieve ultraviolet light imaging function.
[0029] This technical solution involves the following key process steps:
[0030] 1. Etching the back dielectric layer
[0031] In the back-end processes of traditional CMOS image sensors, a back-end dielectric layer is typically applied over the photosensitive area. To ensure that the Ga2O3 material can directly contact the CIS photosensitive area, the back-end dielectric layer must first be removed.
[0032] Etching steps:
[0033] First, a suitable etching process needs to be selected to remove the subsequent dielectric material. Commonly used etching methods are dry etching (RIE, Reactive Ion Etching) or wet etching (such as HF solution etching). In this embodiment, dry etching is recommended because it allows for precise control of the etching depth and avoids contamination that may be introduced by liquid etching.
[0034] Process conditions: The gas used is a mixture of SF6 (sulfur hexafluoride) and O2. The specific gas flow rate ratio can be adjusted according to the etching rate and selectivity requirements; typically, the SF6 flow rate is set to 50-100 sccm, and the O2 flow rate to 10-30 sccm. Power: The RF power is typically set to 100-300W to ensure sufficient etching energy. Pressure: The etching chamber pressure is typically maintained within the range of 10-20 mTorr to ensure good etching uniformity. Etching time: The etching time is controlled according to the thickness of the dielectric layer; after etching, the downstream dielectric layer of the photosensitive area is completely removed, providing a suitable substrate for the deposition of the Ga2O3 thin film. The SEM image after etching is shown below. Figure 2 As shown.
[0035] 2. Preparation of Ga2O3 thin films
[0036] After removing the back-end dielectric layer, the next step is to prepare a Ga2O3 thin film using magnetron sputtering. Ga2O3 has a wide band gap (4.9 eV) and is suitable for ultraviolet light absorption, so Ga2O3 was chosen as the ultraviolet light absorbing layer.
[0037] Magnetron sputtering process:
[0038] Gas environment: A mixture of oxygen (O2) and argon (Ar) is used as the sputtering gas. Argon is used for ionization during the sputtering process, and oxygen is used for oxidation to form a Ga2O3 thin film. Typically, the flow rate ratio of argon to oxygen is 3:1. Argon flow rate: 40-60 sccm, oxygen flow rate: 10-20 sccm.
[0039] Sputtering power: Sputtering power has a significant impact on the deposition rate and quality of Ga2O3 films. A power setting within the range of 150-250W ensures uniform deposition of the Ga2O3 film and achieves good film quality.
[0040] Sputtering temperature: To ensure good film formation properties, the temperature is maintained between 200°C and 350°C during sputtering. Lower temperatures help ensure compatibility with CMOS substrates while avoiding potential crystal structure changes caused by high temperatures.
[0041] Sputtering time: Depending on the required Ga2O3 film thickness (usually tens to hundreds of nanometers), the sputtering time is set to 20-60 minutes.
[0042] After sputtering, the Ga2O3 film will uniformly cover the photosensitive area, forming an ultraviolet light absorption layer.
[0043] 3. Patterning and etching of Ga2O3 thin films
[0044] After the Ga2O3 thin film deposition is completed, the next step is to pattern the Ga2O3 thin film to ensure that only the Ga2O3 material is retained above the photosensitive area, while the Ga2O3 film in other areas is removed.
[0045] Patterning steps:
[0046] Photolithography process: First, photoresist is coated onto the surface of a Ga2O3 thin film, followed by exposure and development. During exposure, ultraviolet or deep ultraviolet light is used to irradiate the photoresist, and the pattern of the photosensitive area is transferred onto the photoresist through a mask. After development, the photoresist remains in the photosensitive area, while the photoresist in other areas is removed.
[0047] Ga2O3 Etching: After photoresist patterning, dry etching is used to remove the unprotected Ga2O3 film. Due to the poor selectivity of Ga2O3 to wet etching, reactive ion etching (RIE) is used for dry etching. A mixed gas of chlorine (Cl2) and fluorine (CF4) is used for etching to ensure high selective removal of Ga2O3. Further, the gas flow rates are: chlorine (Cl2): 20-30 sccm, fluorine (CF4): 10-15 sccm. Etching power: The etching power is set to 100-200 W to ensure high selective removal of Ga2O3. Pressure: Maintained within the pressure range of 20-40 mTorr to ensure etching uniformity and high selectivity.
[0048] After etching, the Ga2O3 film will be patterned, with only the photosensitive areas retaining the Ga2O3 material, while the Ga2O3 film in other areas will be removed.
[0049] 4. Post-treatment and cleaning
[0050] Finally, after the Ga2O3 thin film patterning and etching are completed, necessary cleaning and post-processing are performed. Photoresist is removed, and surface residues are cleaned to ensure the Ga2O3 thin film surface is clean and free of contamination, providing good surface quality for subsequent processes. The final device structure schematic diagram is shown below. Figure 3 As shown, the photosensitive area of a silicon-based CMOS image sensor includes a photodiode and a color filter array, and further includes a microlens array formed on a Ga2O3 thin film to improve light collection efficiency.
[0051] The n-Si / Ga2O3 junction in the CMOS image sensor obtained using the above process exhibits a type I bandgap arrangement. Figure 4The electron concentration in n-Si is higher than that in Ga2O3. Due to the electron concentration gradient, electrons diffuse from n-Si to Ga2O3, thus forming an internal electric field at the interface from n-Si to Ga2O3. Under ultraviolet irradiation, photogenerated carriers are generated in Ga2O3, and the photogenerated electron-hole pairs are separated due to the internal electric field. The photogenerated electrons are transported to the n-Si layer and can then be collected in the FD (Flush Deposition) via TG (Transfer Thermoelectric) control. Its readout principle is completely consistent with that of conventional CIS (Computer Integrated Circuit).
[0052] The above description is a preferred embodiment of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A manufacturing process for an ultraviolet imaging CMOS image sensor, characterized in that, Includes the following steps: Step 1. Form a back-end dielectric layer above the photosensitive area of a silicon-based CMOS image sensor; Step 2. Etch away the back dielectric layer to expose the photosensitive area; Step 3. Deposit a Ga2O3 thin film over the exposed photosensitive area using magnetron sputtering to form an ultraviolet light absorbing layer; Step 4. Pattern the Ga2O3 film to ensure that Ga2O3 material is retained only above the photosensitive area; Step 5. Perform post-processing and cleaning to remove photoresist and clean surface residues to ensure the Ga2O3 film surface is clean; The etching step employs dry etching using a mixed gas of SF6 and O2; during the magnetron sputtering process, a mixed gas of O2 and Ar is used, with the sputtering power set in the range of 150-250W and the sputtering temperature maintained between 200°C and 350°C; and in the patterning process, a reactive ion etching process is used, employing a mixed gas of Cl2 and CF4 for etching.
2. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 1, characterized in that, In the etching step of the back-end dielectric layer, the gas flow rate ratio for dry etching is set as follows: SF6 flow rate is set to 50-100 sccm, O2 flow rate is set to 10-30 sccm, RF power is set to 100-300W, and the etching chamber pressure is maintained within the range of 10-20 mTorr.
3. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 1 or 2, characterized in that, During the magnetron sputtering process, the Ar flow rate is 40-60 sccm, the O2 flow rate is 10-20 sccm, and the sputtering time is set to 20-60 minutes.
4. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 3, characterized in that, The sputtering temperature of the Ga2O3 thin film is controlled between 200°C and 300°C.
5. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 1, characterized in that, In the patterning process, after the photoresist is coated, it is exposed and developed. During exposure, ultraviolet light or deep ultraviolet light is used to irradiate the photoresist.
6. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 1, characterized in that, In the reactive ion etching process, the flow rate of Cl2 is 20-30 sccm, the flow rate of CF4 is 10-15 sccm, the etching power is set to 100-200W, and the etching chamber pressure is maintained at 20-40 mTorr.
7. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 5 or 6, characterized in that, The post-processing and cleaning steps include removing photoresist and cleaning surface residues using deionized water or organic solvents.
8. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 1, characterized in that, The thickness of the Ga2O3 film is from tens of nanometers to hundreds of nanometers.
9. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 8, characterized in that, The photosensitive area of the silicon-based CMOS image sensor includes a photodiode and a color filter array.
10. The manufacturing process of the ultraviolet imaging CMOS image sensor according to claim 8 or 9, characterized in that, The manufacturing process also includes forming a microlens array on the Ga2O3 thin film to improve light collection efficiency.