SiC mosfet hard switching loss calculation method and testing device of TNPC circuit

Abstract

The application discloses a SiC MOSFET hard switching loss calculation method and a testing device of a TNPC circuit, and the disclosed SiC MOSFET hard switching loss calculation method of the TNPC circuit comprises the following steps: controlling the channel turn-off of a current calibration device by applying an off pulse signal to a current measured device in the TNPC circuit, and acquiring the current off voltage characteristic parameter of the current measured device in the off process; controlling the channel turn-on of the calibration device by applying an on pulse signal to the current measured device, and acquiring the current on voltage characteristic parameter of the current measured device in the on process; acquiring a hard switching loss calculation model; and substituting the current off voltage characteristic parameter and the current on voltage characteristic parameter into the hard switching loss calculation model for calculation to obtain the hard switching loss of the current measured device. The application has a small change on the TNPC circuit, and effectively reduces the complexity of the TNPC circuit.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of electronic circuits, in particular to a SiC MOSFET hard switching loss calculation method and testing device of a TNPC circuit. BACKGROUND

[0002] The T-type neutral point clamped (TNPC) topology has become the core architecture of medium and high power systems such as photovoltaic inverters and uninterruptible power supplies due to its low device stress, high waveform quality and superior EMI characteristics.

[0003] With the emergence and application of SiC MOSFET power devices, the switching frequency and power density of the TNPC circuit gradually increase, and the generated hard switching loss also increases. The TNPC circuit contains multiple sets of complementary switching tubes. The existing hard switching loss measurement method directly monitors the voltage and current waveforms of the devices in the TNPC circuit during the switching process, and calculates the integral of the voltage and current product to quantify the loss. However, the above method requires the installation of multiple probes in the TNPC circuit to simultaneously monitor the voltage and current of each device in the TNPC circuit, which greatly changes the TNPC circuit, resulting in a relatively complex hard switching loss measurement process. SUMMARY

[0004] The main purpose of the present application is to provide a SiC MOSFET hard switching loss calculation method and testing device of a TNPC circuit, which aims to solve the technical problem that the existing technology greatly changes the TNPC circuit, thereby causing a relatively complex hard switching loss measurement process.

[0005] To achieve the above purpose, the application provides a SiC MOSFET hard switching loss calculation method of a TNPC circuit, which comprises:

[0006] By applying an off pulse signal to the current measured device in the TNPC circuit to control the channel off of the current measured device, and obtaining the current off voltage characteristic parameter of the current measured device during the off process, the current measured device is the SiC MOSFET required to be measured in the TNPC circuit;

[0007] By applying an on pulse signal to the current measured device to control the channel on of the current measured device, and obtaining the current on voltage characteristic parameter of the current measured device during the on process;

[0008] obtain a hard switching loss calculation model, the hard switching loss calculation model being constructed in advance based on a turn-off voltage characteristic parameter of a calibration device in a hard turn-off period and a turn-on voltage characteristic parameter in a hard turn-on period, the hard switching loss calculation model representing a mapping relationship between the turn-off voltage characteristic parameter and a hard switching loss and a mapping relationship between the turn-on voltage characteristic parameter and the hard switching loss, the calibration device being a SiC MOSFET in the TNPC circuit for which the hard switching loss calculation model is constructed;

[0009] substitute the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter into the hard switching loss calculation model to obtain the hard switching loss of the current device under test.

[0010] In an embodiment, before the step of obtaining the hard switching loss calculation model, the method further comprises:

[0011] obtaining a turn-off voltage characteristic parameter of the calibration device in a turn-off process;

[0012] obtaining a turn-on voltage characteristic parameter of the calibration device in a turn-on process;

[0013] determining a hard turn-off period of the calibration device and a hard turn-on period of the calibration device;

[0014] determining a hard turn-off loss calculation model of the calibration device in the hard turn-off period according to the turn-off voltage characteristic parameter;

[0015] determining a hard turn-on loss calculation model of the calibration device in the hard turn-on period according to the turn-on voltage characteristic parameter;

[0016] determining a hard switching loss calculation model according to the hard turn-off loss calculation model and the hard turn-on loss calculation model.

[0017] In an embodiment, the hard turn-off period is composed of a voltage rising period and a current falling period, and the step of determining the hard turn-off loss calculation model of the calibration device in the hard turn-off period according to the turn-off voltage characteristic parameter comprises:

[0018] determining a first hard turn-off loss calculation model of the calibration device in the voltage rising period according to the turn-off voltage characteristic parameter;

[0019] determining a second hard turn-off loss calculation model of the calibration device in the current falling period according to the turn-off voltage characteristic parameter;

[0020] determining a hard turn-off loss calculation model of the calibration device according to the first hard turn-off loss calculation model and the second hard turn-off loss calculation model.

[0021] In an embodiment, the voltage rising period is constituted by the time when the voltage of the calibration device starts to rise to the time when the preset SiC MOSFET voltage value in the TNPC circuit is zero, and the step of determining the first hard-off loss calculation model of the calibration device in the voltage rising period according to the off voltage characteristic parameter comprises:

[0022] calculating the deviation between the time when the preset SiC MOSFET voltage value is zero and the time when the voltage starts to rise, to obtain the length of the voltage rising period;

[0023] determining the voltage value of the calibration device at the time when the preset SiC MOSFET voltage value is zero according to the off voltage characteristic parameter;

[0024] determining the first hard-off loss model of the calibration device in the voltage rising period by the voltage value of the calibration device at the time when the preset SiC MOSFET voltage value is zero and the length of the voltage rising period, and the first hard-off loss calculation model is:

[0025]

[0026] In the formula, is the hard-off loss of the calibration device in the voltage rising period, is the voltage value of the calibration device at the time when the preset SiC MOSFET voltage value is zero, is the load current value, is the length of the voltage rising period, is the loss coefficient.

[0027] In an embodiment, the current falling period is constituted by the time when the preset SiC MOSFET voltage value is zero to the time when the current of the calibration device falls to zero, and the step of determining the second hard-off loss calculation model of the calibration device in the current falling period according to the off voltage characteristic parameter comprises:

[0028] calculating the deviation between the time when the current falls to zero and the time when the preset SiC MOSFET voltage value is zero, to obtain the length of the current falling period;

[0029] determining the second hard-off loss model of the calibration device in the current falling period by the voltage value of the calibration device at the time when the preset SiC MOSFET voltage value is zero, the length of the voltage rising period and the length of the current falling period, and the second hard-off loss calculation model is:

[0030]

[0031] wherein, is the hard turn-off loss of the calibration device in the voltage rising period, is the voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero, is the load current value, is the duration of the voltage rising period, is the duration of the current falling period, is the loss coefficient;

[0032] The step of determining the hard turn-off loss calculation model of the calibration device according to the first hard turn-off loss calculation model and the second hard turn-off loss calculation model comprises:

[0033] combining the first hard turn-off loss calculation model and the second hard turn-off loss calculation model to obtain the hard turn-off loss calculation model of the calibration device, wherein the hard turn-off loss calculation model is:

[0034]

[0035] wherein, is the hard turn-off loss of the calibration device, is the hard turn-off loss of the calibration device in the voltage rising period, is the hard turn-off loss of the calibration device in the current falling period.

[0036] In an embodiment, the hard turn-on period is composed of a current rising period and a voltage falling period, and the step of determining the hard turn-on loss calculation model of the calibration device in the hard turn-on period according to the turn-on voltage characteristic parameter comprises:

[0037] determining a first hard turn-on loss calculation model of the calibration device in the current rising period according to the turn-on voltage characteristic parameter;

[0038] determining a second hard turn-on loss calculation model of the calibration device in the voltage falling period according to the turn-on voltage characteristic parameter;

[0039] determining the hard turn-on loss calculation model of the calibration device according to the first hard turn-on loss calculation model and the second hard turn-on loss calculation model.

[0040] In an embodiment, the current rising period is composed of the moment when the voltage of the calibration device starts to fall to the moment when the current of the calibration device rises to the load current, and the step of determining the first hard turn-on loss calculation model of the calibration device in the current rising period according to the turn-on voltage characteristic parameter comprises:

[0041] a deviation between the time when the current rises to the load current and the time when the voltage starts to drop is calculated to obtain a length of the current rising period;

[0042] a voltage value of the calibration device at the time when the current rises to the load current is determined according to the turn-on voltage characteristic parameter;

[0043] a first hard turn-on loss calculation model of the calibration device in the current rising period is determined through the voltage value of the calibration device at the time when the voltage starts to drop, the voltage value of the calibration device at the time when the current rises to the load current and the length of the current rising period, and the first hard turn-on loss calculation model is:

[0044]

[0045] wherein, is a hard turn-on loss of the calibration device in the current rising period, is the voltage value of the calibration device at the time when the voltage starts to drop, is the voltage value of the calibration device at the time when the current rises to the load current, is the load current value, is the length of the current rising period.

[0046] In an embodiment, the voltage dropping period is composed of the time when the current rises to the load current to the time when the voltage of the calibration device drops to zero, and the step of determining a second hard turn-on loss calculation model of the calibration device in the voltage dropping period according to the turn-on voltage characteristic parameter comprises:

[0047] a deviation between the time when the voltage drops to zero and the time when the current rises to the load current is calculated to obtain a length of the voltage dropping period;

[0048] a charge amount of junction capacitance charging and discharging of a normally-off SiC MOSFET other than the calibration device in the TNPC circuit in the voltage dropping period is determined, the normally-off SiC MOSFET being a SiC MOSFET whose channel is in a closed state in the hard turn-off period and the hard turn-on period;

[0049] a voltage value of the calibration device at the time when the current rises to the load current is determined according to the turn-on voltage characteristic parameter;

[0050] a second hard turn-on loss calculation model of the calibration device in the voltage dropping period is determined through the charge amount of the junction capacitance charging and discharging, the voltage value of the calibration device at the time when the current rises to the load current and the length of the voltage dropping period, and the second hard turn-on loss calculation model is:

[0051]

[0052] wherein, is the hard turn-on loss of the calibration device in the voltage falling period, is the charge amount of the junction capacitance charge-discharge of the normally-off SiC MOSFET outside the calibration device in the voltage falling period, is the voltage value of the calibration device at the moment when the current rises to the load current, is the load current value, is the duration of the voltage falling period;

[0053] The step of determining the hard turn-on loss calculation model of the calibration device according to the first hard turn-on loss calculation model and the second hard turn-on loss calculation model comprises:

[0054] combining the first hard turn-on loss calculation model and the second hard turn-on loss calculation model to obtain the hard turn-on loss calculation model of the calibration device, and the hard turn-on loss calculation model is:

[0055]

[0056] wherein, is the hard turn-on loss of the calibration device, is the hard turn-on loss of the calibration device in the current rising period, is the hard turn-on loss of the calibration device in the voltage falling period.

[0057] In addition, in order to achieve the above-mentioned purpose, the application further provides a test device, which is connected with the TNPC circuit, and the test device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the SiC MOSFET hard switching loss calculation method of the TNPC circuit.

[0058] In an embodiment, the TNPC circuit comprises a power supply, a first direct current capacitor, a second direct current capacitor, a load, and a plurality of SiC MOSFETs, wherein the SiC MOSFETs comprise a first SiC MOSFET, a second SiC MOSFET, a third SiC MOSFET, and a fourth SiC MOSFET.

[0059] The drain of the first SiC MOSFET is connected with the positive electrode of the power supply and the first end of the first direct current capacitor, respectively, and the source of the first SiC MOSFET is connected with the drain of the third SiC MOSFET, the drain of the fourth SiC MOSFET, and the load, respectively.

[0060] The source of the third SiC MOSFET is connected with the source of the second SiC MOSFET, and the drain of the second SiC MOSFET is connected with the second end of the first DC capacitor and the first end of the second DC capacitor respectively;

[0061] The source of the fourth SiC MOSFET is connected with the second end of the second DC capacitor and the negative electrode of the power supply respectively;

[0062] The gate of the first SiC MOSFET, the gate of the second SiC MOSFET, the gate of the third SiC MOSFET and the gate of the fourth SiC MOSFET are connected with the test device.

[0063] The one or more technical solutions provided in the application have at least the following technical effects:

[0064] The application controls the channel turn-off of the current measured device by applying the turn-off pulse signal to the current calibration device in the TNPC circuit, and obtains the current turn-off voltage characteristic parameter of the current measured device in the turn-off process. The current measured device is the SiC MOSFET required to be measured in the TNPC circuit. The application controls the channel turn-on of the calibration device by applying the turn-on pulse signal to the current measured device, and obtains the current turn-on voltage characteristic parameter of the current measured device in the turn-on process. The hard switching loss calculation model is constructed based on the turn-off voltage characteristic parameter of the calibration device in the hard turn-off period and the turn-on voltage characteristic parameter in the hard turn-on period, and represents the mapping relationship between the turn-off voltage characteristic parameter and the hard switching loss and the mapping relationship between the turn-on voltage characteristic parameter and the hard switching loss. The calibration device is the SiC MOSFET in the TNPC circuit for constructing the hard switching loss calculation model. The current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter are substituted into the hard switching loss calculation model for calculation to obtain the hard switching loss of the calibration device. The application constructs the hard switching loss calculation model in advance based on the turn-off voltage characteristic parameter of the calibration device in the hard turn-off period and the turn-on voltage characteristic parameter in the hard turn-on period. In the current scenario, the current turn-off voltage characteristic parameter of the current measured device in the turn-off process and the current turn-on voltage characteristic parameter in the turn-on process are monitored, and the hard switching loss of the current measured device can be calculated based on the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter through the hard switching loss calculation model. Compared with the prior art, the hard switching loss of the application is realized by monitoring the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter of the current measured device, without the need to install multiple probes in the TNPC circuit to measure the current of each device, and the modification of the TNPC circuit is small, which effectively reduces the complexity of the TNPC circuit. BRIEF DESCRIPTION OF DRAWINGS

[0065] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0066] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings required to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0067] Figure 1 Flowchart of the first embodiment of the SiC MOSFET hard switching loss calculation method of the TNPC circuit of the present application;

[0068] Figure 2 Circuit schematic diagram of the TNPC circuit of the present application;

[0069] Figure 3 Flowchart of the second embodiment of the SiC MOSFET hard switching loss calculation method of the TNPC circuit of the present application;

[0070] Figure 4 First equivalent circuit schematic diagram of the TNPC circuit of the present application;

[0071] Figure 5 Second equivalent circuit schematic diagram of the TNPC circuit of the present application;

[0072] Figure 6 Simplified waveform diagram of the hard turn-off process of the present application;

[0073] Figure 7 Flowchart of the third embodiment of the SiC MOSFET hard switching loss calculation method of the TNPC circuit of the present application;

[0074] Figure 8 Simplified waveform diagram of the hard turn-off process of the present application;

[0075] Figure 9 Structure schematic diagram of the test device of the present application.

[0076] The object implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0077] It should be understood that the specific embodiments described herein are merely intended to explain the technical solutions of the present application, and are not used to limit the present application.

[0078] For better understanding of the technical solutions of the present application, the following will be described in detail in combination with the drawings of the specification and specific embodiments.

[0079] The main solution of the embodiment of the present application is: applying an off pulse signal to the current device under test in the TNPC circuit to control the channel off of the current device under test, and obtaining the current off voltage characteristic parameter of the current device under test in the off process, the current device under test being a SiC MOSFET required to be measured in the TNPC circuit; applying an on pulse signal to the current device under test to control the channel on of the calibration device, and obtaining the current on voltage characteristic parameter of the current device under test in the on process; obtaining a hard switching loss calculation model, the hard switching loss calculation model being constructed based on the off voltage characteristic parameter of the calibration device in the hard off period and the on voltage characteristic parameter of the calibration device in the hard on period, representing the mapping relationship between the off voltage characteristic parameter and the hard switching loss and the mapping relationship between the on voltage characteristic parameter and the hard switching loss, the calibration device being a SiC MOSFET for constructing the hard switching loss calculation model in the TNPC circuit; and substituting the current off voltage characteristic parameter and the current on voltage characteristic parameter into the hard switching loss calculation model to calculate the hard switching loss of the current device under test.

[0080] The prior art makes great changes to the TNPC circuit, resulting in a complex measurement process of the hard switching loss.

[0081] The present application provides a solution, which constructs a hard switching loss calculation model based on the off voltage characteristic parameter of the calibration device in the hard off period and the on voltage characteristic parameter of the calibration device in the hard on period in advance, and in the current scenario, monitors the current off voltage characteristic parameter of the current device under test in the off process and the current on voltage characteristic parameter of the current device under test in the on process, and calculates the hard switching loss of the current device under test based on the current off voltage characteristic parameter and the current on voltage characteristic parameter through the hard switching loss calculation model. Compared with the prior art, the hard switching loss of the present application is realized by monitoring the current off voltage characteristic parameter and the current on voltage characteristic parameter of the current device under test, without the need to install multiple probes in the TNPC circuit to measure the current of each device, and the changes to the TNPC circuit are small, effectively reducing the complexity of the TNPC circuit.

[0082] It should be noted that the execution subject of the present embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device, a test device, etc. capable of realizing the above functions. The present embodiment and the following embodiments will be described below taking the test device as an example.

[0083] Based on this, the embodiment of the present application provides a SiC MOSFET hard switching loss calculation method of a TNPC circuit, referring to Figure 1 , Figure 1 FIG. 1 is a flowchart of a first embodiment of the SiC MOSFET hard switching loss calculation method of the TNPC circuit of the present application.

[0084] In the embodiment, the SiC MOSFET hard switching loss calculation method of the TNPC circuit comprises steps S10-S40:

[0085] Step S10, the channel turn-off of the current measured device is controlled by applying a turn-off pulse signal to the current measured device in the TNPC circuit, and the current turn-off voltage characteristic parameter of the current measured device in the turn-off process is obtained.

[0086] The current measured device is the SiC MOSFET required to be measured in the TNPC circuit.

[0087] Step S20, the channel turn-on of the current measured device is controlled by applying a turn-on pulse signal to the current measured device, and the current turn-on voltage characteristic parameter of the current measured device in the turn-on process is obtained.

[0088] For the convenience of description, the embodiment and the following embodiments are described with reference to Figure 2 , but the present scheme is not limited thereto. Figure 2 FIG. 2 is a circuit schematic diagram of the TNPC circuit of the present application. Figure 2 In FIG. 2, the TNPC circuit comprises a power supply Vdc, a first direct current capacitor C1, a second direct current capacitor C2, a load and a plurality of SiC MOSFETs. The SiC MOSFETs comprise a first SiC MOSFET , a second SiC MOSFET , a third SiC MOSFET and a fourth SiC MOSFET . The drain of the first SiC MOSFET is connected to the positive electrode of the power supply Vdc and the first end of the first direct current capacitor C1, respectively, the source of the first SiC MOSFET is connected to the drain of the third SiC MOSFET , the drain of the fourth SiC MOSFET and the load ; the source of the third SiC MOSFET is connected to the source of the second SiC MOSFET , and the source of the second SiC MOSFET the drain of the fourth SiC MOSFET is connected with the second end of the first DC capacitor C1 and the first end of the second DC capacitor C2 respectively. the source of the second SiC MOSFET is connected with the second end of the second DC capacitor C2 and the negative pole of the power supply Vdc respectively.

[0089] Although Figure 2 not shown in the figure, it is to be noted that the gate of the first SiC MOSFET , the gate of the second SiC MOSFET , the gate of the third SiC MOSFET and the gate of the fourth SiC MOSFET are connected with the testing device.

[0090] It is to be understood that the power supply Vdc can be a DC power supply, and the load may be an inductor.

[0091] It is to be noted that the above-mentioned SiC MOSFET can be a power switch tube made of silicon carbide material. Compared with the traditional silicon device, the above-mentioned SiC MOSFET can withstand higher voltage and temperature, has lower conduction loss and faster switching speed. The conduction loss is the power loss of the SiC MOSFET in the conduction state due to its limited conduction resistance, which is proportional to the square of the current.

[0092] In an ideal case, the first DC capacitor C1 and the second DC capacitor C2 divide the DC bus voltage of the power supply Vdc equally. The first SiC MOSFET and the fourth SiC MOSFET are connected in series to the DC bus, the source of the second SiC MOSFET is connected with the source of the third SiC MOSFET , that is, the second SiC MOSFET and the third SiC MOSFET are connected through the common source connection mode, one end of which is connected to the voltage midpoint of the DC bus, and the other end is connected to the bridge arm midpoint of the first SiC MOSFET and the fourth SiC MOSFET . By controlling the first SiC MOSFET , the second SiC MOSFET , the third SiC MOSFET and the fourth SiC MOSFET to be turned on and off alternately, the functions of rectification and inversion can be realized.

[0093] It should be noted that the current device to be tested can be a SiC MOSFET required to measure the hard switching loss in the TNPC circuit, which can be selected by the user from a plurality of SiC MOSFETs in the TNPC circuit according to the requirement.

[0094] The switching loss can be the energy loss of the SiC MOSFET due to the simultaneous existence of voltage and current on the device during the transition from the on state to the off state or from the off state to the on state. The hard switching loss can be a large switching loss due to the high values of voltage and current at the same time during the on or off instant of the SiC MOSFET.

[0095] It can be understood that the two ends of each SiC MOSFET (i.e. the source and drain of the SiC MOSFET) can be connected to a probe for collecting electrical data (such as voltage data and current data) at the two ends of each SiC MOSFET. The test device can be connected to each probe, or each probe can be integrated in the test device, which is not limited in the embodiment.

[0096] It should be noted that the off voltage characteristic parameter can be the voltage data generated by the SiC MOSFET during the off process, which can include the voltage waveform of the voltage varying with time, the amplitude of the voltage at different times, etc.

[0097] It can be understood that the on voltage characteristic parameter can be the voltage data generated by the SiC MOSFET during the on process, which can include the switching characteristic curve of the voltage varying with time, the amplitude of the voltage at different times, etc.

[0098] In a specific implementation, the test device can receive a test instruction, which can contain SiC MOSFET information required to be tested. The test device responds to the test instruction, takes the SiC MOSFET corresponding to the test instruction as the current device to be tested, applies an off pulse signal to the gate of the current device to be tested to control the channel of the current device to be tested to be off, and then obtains the current off voltage characteristic parameter of the current device to be tested in real time during the off process. After detecting that the channel of the current device to be tested is completely off, the test device can apply an on pulse signal to the current device to be tested to control the channel of the current device to be tested to be on, and then obtain the current on voltage characteristic parameter of the current device to be tested in real time during the on process.

[0099] Step S30, obtaining a hard switching loss calculation model.

[0100] The hard switching loss calculation model is constructed in advance based on a turn-off voltage characteristic parameter of a calibration device in a hard turn-off period and a turn-on voltage characteristic parameter in a hard turn-on period. The hard switching loss calculation model represents a mapping relationship between the turn-off voltage characteristic parameter and the hard switching loss and a mapping relationship between the turn-on voltage characteristic parameter and the hard switching loss. The calibration device is a SiC MOSFET in the TNPC circuit for which the hard switching loss calculation model is constructed.

[0101] In a specific implementation, a test environment can be constructed in advance. In the test environment, each SiC MOSFET can be selected as a calibration device for hard switching loss measurement at a time. The test device can apply a turn-off pulse signal to the calibration device to control the channel turn-off of the calibration device, obtain a turn-off voltage characteristic parameter of the calibration device in the turn-off process, then apply a turn-on pulse signal to the calibration device to control the channel turn-on of the calibration device after the calibration device is completely turned off, obtain a turn-on voltage characteristic parameter of the calibration device in the turn-on process, determine a switching characteristic curve of the calibration device by using the turn-off voltage characteristic parameter and the turn-on voltage characteristic parameter, deduce a current waveform by using the switching characteristic curve, and then calculate the hard switching loss of the calibration device based on the current and the voltage. The hard switching loss calculation model representing the mapping relationship between the turn-off voltage characteristic parameter and the hard switching loss and the mapping relationship between the turn-on voltage characteristic parameter and the hard switching loss is constructed by data fitting through multiple tests.

[0102] In a feasible implementation, before step S30, the following steps are included: obtaining a turn-off voltage characteristic parameter of the calibration device in a turn-off process; obtaining a turn-on voltage characteristic parameter of the calibration device in a turn-on process; determining a hard turn-off period of the calibration device and a hard turn-on period of the calibration device; determining a hard turn-off loss calculation model of the calibration device in the hard turn-off period according to the turn-off voltage characteristic parameter; determining a hard turn-on loss calculation model of the calibration device in the hard turn-on period according to the turn-on voltage characteristic parameter; and determining a hard switching loss calculation model according to the hard turn-off loss calculation model and the hard turn-on loss calculation model.

[0103] It should be noted that the hard turn-off period can be a period in which the calibration device is in the turn-off process. The length of the hard turn-off period is the length of the turn-off process. The hard turn-on period can be a period in which the calibration device is in the turn-on process. The length of the hard turn-on period is the length of the turn-on process.

[0104] In a specific implementation, the test device can infer the current waveform of the calibration device in the turn-off process according to the turn-off voltage characteristic parameter of the calibration device, and calculate a hard turn-off loss calculation model of the calibration device within a hard turn-off period based on the turn-off voltage characteristic parameter and the current waveform, the hard turn-off loss calculation model representing the mapping relationship between the turn-off voltage characteristic parameter and the hard switching loss. The test device can infer the current waveform of the calibration device in the turn-on process according to the turn-on voltage characteristic parameter of the calibration device, and calculate a hard turn-on loss calculation model of the calibration device within a hard turn-on period based on the turn-on voltage characteristic parameter and the current waveform, the hard turn-on loss calculation model representing the mapping relationship between the turn-on voltage characteristic parameter and the hard switching loss.

[0105] In step S40, the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter are both substituted into the hard switching loss calculation model for calculation to obtain the hard switching loss of the current measured device.

[0106] In a specific implementation, after determining the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter of the current measured device, the test device can call the pre-constructed hard switching loss calculation model to calculate the corresponding hard switching loss based on the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter through the hard switching loss calculation model.

[0107] The embodiment controls the channel turn-off of the current measured device by applying an off pulse signal to the current calibration device in the TNPC circuit, and obtains the current turn-off voltage characteristic parameter of the current measured device in the turn-off process, and the current measured device is a SiC MOSFET required to be measured in the TNPC circuit; the channel turn-on of the calibration device is controlled by applying an on pulse signal to the current measured device, and the current turn-on voltage characteristic parameter of the current measured device in the turn-on process is obtained; a hard switching loss calculation model is obtained, the hard switching loss calculation model is constructed based on the turn-off voltage characteristic parameter of the calibration device in the hard turn-off period and the turn-on voltage characteristic parameter in the hard turn-on period, and represents the mapping relationship between the turn-off voltage characteristic parameter and the hard switching loss and the mapping relationship between the turn-on voltage characteristic parameter and the hard switching loss, and the calibration device is a SiC MOSFET for constructing the hard switching loss calculation model in the TNPC circuit; the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter are substituted into the hard switching loss calculation model for calculation, and the hard switching loss of the calibration device is obtained. In the current scenario, the current turn-off voltage characteristic parameter of the current measured device in the turn-off process and the current turn-on voltage characteristic parameter in the turn-on process are monitored, and the hard switching loss of the current measured device can be calculated based on the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter by the hard switching loss calculation model. Compared with the prior art, the hard switching loss of the embodiment is realized by monitoring the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter of the current measured device, without the need to install multiple probes in the TNPC circuit to measure the current of each device, and the complexity of the TNPC circuit is effectively reduced.

[0108] Based on the first embodiment of the present application, the second embodiment of the present application is proposed. In the second embodiment of the present application, the same or similar contents as the above first embodiment can be referred to the above introduction, and will not be described in detail. On this basis, please refer to Figure 3 , Figure 3 The flowchart of the second embodiment of the SiC MOSFET hard switching loss calculation method of the TNPC circuit of the present application is shown.

[0109] In the embodiment, the hard turn-off period is composed of a voltage rising period and a current falling period, and the step of determining the hard turn-off loss calculation model of the calibration device in the hard turn-off period according to the turn-off voltage characteristic parameter includes steps S301-S303:

[0110] Step S301, determining a first hard turn-off loss calculation model of the calibration device in the voltage rising period according to the turn-off voltage characteristic parameter.

[0111] It should be noted that the voltage rising period can be a period in which the voltage across the calibration device rises.

[0112] In a specific implementation, the test device can calculate a first hard-off loss calculation model based on the off-voltage characteristic parameter when the calibration device is in the voltage rising period, the first hard-off loss calculation model representing a mapping relationship between the off-voltage characteristic parameter and the hard-off loss of the calibration device in the voltage rising period.

[0113] In a feasible implementation, the voltage rising period is composed of a voltage start rising time of the calibration device to a time when a preset SiC MOSFET voltage value in the TNPC circuit is zero, and step S301 includes steps S3011-S3013.

[0114] Step S3011 calculates a deviation between the time when the preset SiC MOSFET voltage value is zero and the voltage start rising time, to obtain a length of the voltage rising period.

[0115] It should be noted that the preset SiC MOSFET can be a pre-designated SiC MOSFET in each SiC MOSFET. When the calibration device is the first SiC MOSFET , the preset SiC MOSFET is the third SiC MOSFET , when the calibration device is the second SiC MOSFET , the preset SiC MOSFET is the fourth SiC MOSFET , when the calibration device is the third SiC MOSFET , the preset SiC MOSFET is the first SiC MOSFET , when the calibration device is the fourth SiC MOSFET , the preset SiC MOSFET is the second SiC MOSFET .

[0116] In a specific implementation, a period composed of a voltage start rising time of the calibration device to a time when a preset SiC MOSFET voltage value is zero can be taken as the voltage rising period, and the test device can obtain the length of the voltage rising period by calculating a deviation between the time when the preset SiC MOSFET voltage value is zero and the voltage start rising time.

[0117] Step S3012 determines a voltage value of the calibration device at the time when the preset SiC MOSFET voltage value is zero according to the off-voltage characteristic parameter.

[0118] In a specific implementation, the test device can extract the voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero from the off voltage characteristic parameter.

[0119] In step S3013, the first hard-off loss model of the calibration device in the voltage rising period is determined by the voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero and the length of the voltage rising period.

[0120] The first hard-off loss calculation model is:

[0121]

[0122] In the formula, is the hard-off loss of the calibration device in the voltage rising period, is the voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero, is the load current value, is the length of the voltage rising period, is the loss coefficient.

[0123] It should be noted that, Figure 2 The TNPC circuit shown has four modes. When the calibration device is the first SiC MOSFET , the TNPC circuit is in the first mode; when the calibration device is the third SiC MOSFET , the TNPC circuit is in the second mode; when the calibration device is the fourth SiC MOSFET , the TNPC circuit is in the third mode; and when the calibration device is the second SiC MOSFET , the TNPC circuit is in the fourth mode. The first mode and the third mode are complementary inverter operating conditions, the voltage and current directions are the same, the second mode and the fourth mode are complementary rectifier operating conditions, the voltage and current directions are opposite. The equivalent circuits and circuit commutation modes of the two complementary modes have symmetry, the switching characteristics of the calibration device are the same, and the switching loss calculation processes are similar. The difference is that the elements involved in commutation are different, so this embodiment can take one of them for switching loss expression analysis.

[0124] Taking the first mode as an example, the hard switching loss test mode is that the test device applies an on pulse signal to the second SiC MOSFET all the time, so that the second SiC MOSFET is in the on state during the test period, and applies an off pulse signal to the third SiC MOSFET and the fourth SiC MOSFET all the time, so that the third SiC MOSFET and the fourth SiC MOSFET is in an off state during the test, the first SiC MOSFET (i.e., the calibration device) is respectively sent an off pulse signal and an on pulse signal, and corresponding off voltage characteristic parameters and on voltage parameters are acquired, so as to determine a hard switching loss calculation model.

[0125] Taking the second mode as an example, the manner of the hard switching loss test is that the test device applies the on pulse signal to the second SiC MOSFET all the time, so that the second SiC MOSFET is in an on state during the test, the first SiC MOSFET and the fourth SiC MOSFET are respectively applied with the off pulse signal all the time, so that the first SiC MOSFET and the fourth SiC MOSFET are in an off state during the test, the third SiC MOSFET (i.e., the calibration device) is respectively sent an off pulse signal and an on pulse signal, and corresponding off voltage characteristic parameters and on voltage parameters are acquired, so as to determine a hard switching loss calculation model.

[0126] Specifically, for the first mode and the third mode, the embodiment takes the first mode as an example for description. Referring to Figure 4 , Figure 4 is a first equivalent circuit schematic diagram of the TNPC circuit. Figure 4 In the first mode, the drain of the first SiC MOSFET is connected with a first end of a first inductor L1, and a second end of the first inductor L1 is respectively connected with a positive electrode of a power supply Vdc and a first end of a first direct current capacitor C1. The source of the first SiC MOSFET is connected with the drain of the third SiC MOSFET , the drain of the fourth SiC MOSFET , and a first end of a load. The source of the third SiC MOSFET is connected with the source of the second SiC MOSFET , and the drain of the second SiC MOSFET is respectively connected with a second end of the first direct current capacitor C1, a first end of a second direct current capacitor C2, and a second end of the load. The source of the first SiC MOSFET is connected with the first end of the second inductor L2, and the second end of the second inductor L2 is connected with the second end of the second DC capacitor C2 and the negative electrode of the power supply Vdc respectively.

[0127] The first inductor L1 and the second inductor L2 can simulate the parasitic inductance on the printed circuit board (PCB) line.

[0128] Exemplarily, by Figure 4 The hard-off process of the first mode in the voltage rising period is described, and the first SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET The voltage of the third SiC MOSFET

[0129] Before : The first SiC MOSFET channel is turned on, is 0, and the load current completely flows through the first SiC MOSFET channel. The power supply Vdc charges the load , and the load current reaches a specified value at , which can be a pre-configured value, such as 33.3A.

[0130] During to : The first SiC MOSFET channel begins to turn off. The load current is divided into three parts. One part flows through the first SiC MOSFET channel and charges the junction capacitance of the first SiC MOSFET , increases; one part flows through the junction capacitance of the second SiC MOSFET and the third SiC MOSFET , at which time the junction capacitance of the third SiC MOSFET discharges, decreases; and the other part flows through the fourth SiC MOSFET​ The junction capacitance of the fourth SiC MOSFET at this time Junction capacitance discharge, Reduce. In At that moment, the third SiC MOSFET The junction capacitance is completely discharged. When the current decreases to 0, due to the presence of parasitic inductance in the line, when the rate of change of the current flowing through the first inductor L1 is high, an induced voltage is generated in the first inductor L1, causing... Slightly higher than the half bus voltage.

[0131] Specifically, this embodiment will use the second mode as an example to illustrate the second and fourth modes. (Refer to...) Figure 5 , Figure 5 This is the schematic diagram of the second equivalent circuit of the TNPC circuit in this application. Figure 5 In the middle, the first SiC MOSFET The drain of each inductor is connected to the first terminal of the first inductor L1 and the load, respectively. The first terminal is connected, and the second terminal of the first inductor L1 is connected to the positive terminal of the power supply Vdc and the first terminal of the first DC capacitor C1, respectively. The first SiC MOSFET The source of each is connected to the third SiC MOSFET. The drain of the fourth SiC MOSFET drain and load The second terminal is connected; the third SiC MOSFET The source of the second SiC MOSFET The source connection of the second SiC MOSFET The drain of the fourth SiC MOSFET is connected to the second terminal of the first DC capacitor C1 and the first terminal of the second DC capacitor C2, respectively. The source of the capacitor is connected to the first terminal of the second inductor L2, and the second terminal of the second inductor L2 is connected to the second terminal of the second DC capacitor C2 and the negative terminal of the power supply Vdc.

[0132] For example, by Figure 5 Hard turn-off process for the second mode (i.e., the third SiC MOSFET) (For calibration devices) will be explained, and the third SiC MOSFET will be used as an example. The voltage begins to rise at the time when First SiC MOSFET The voltage value at time zero is First SiC MOSFET The voltage across the terminals is Second SiC MOSFET The voltage across the two terminals is , the third SiC MOSFET The voltage across the two terminals is , the fourth SiC MOSFET The voltage across the two terminals is The description is as follows.

[0133] Before : the third SiC MOSFET channel is turned on, 0, and the load current completely flows through the second SiC MOSFET channel and the third SiC MOSFET channel. The DC power supplies the load with a charging current, and the load current reaches a specified value (such as 33.3 A) at .

[0134] During to : the third SiC MOSFET channel starts to turn off. The load current is divided into three parts. One part still flows through the second SiC MOSFET channel and the third SiC MOSFET channel, and charges the junction capacitance of the third SiC MOSFET , which increases; one part flows through the junction capacitance of the first SiC MOSFET , and the junction capacitance of the first SiC MOSFET discharges, decreases; and the other part flows through the junction capacitance of the fourth SiC MOSFET , and the junction capacitance of the fourth SiC MOSFET charges, increases. At , the junction capacitance of the first SiC MOSFET is completely discharged, decreases to 0, and due to the existence of the line parasitic inductance, an induced voltage is generated on the first inductor L1 when the current changes at a high rate, so that is slightly higher than the half bus voltage.

[0135] Further, the simplified waveform diagram of the hard turn-off process can be obtained by analyzing the circuit commutation process of the switching process and combining the switching characteristic curve of the calibrated device. Referring to Figure 6 , Figure 6 is the simplified waveform diagram of the hard turn-off process of the present application, Figure 6 describes the voltages in each period in the hard turn-off process ) and current ( ) over time. In combination Figure 6 with the hard turn-off analysis process of the voltage rising period above, taking the first modality as an example (i.e. the first SiC MOSFET as the reference device), the voltage of the first SiC MOSFET starts to rise at , and the voltage of the third SiC MOSFET becomes zero at The determination process of the first hard turn-off loss calculation model is described.

[0136] During to , the voltage of the first SiC MOSFET increases linearly; the current of the first SiC MOSFET is equal to the load current minus the discharge current of both the junction capacitance of the third SiC MOSFET and the junction capacitance of the fourth SiC MOSFET , which shows an exponential decay trend.

[0137] The voltage fitting function during to is:

[0138]

[0139] In the formula, is the voltage value of the first SiC MOSFET during to , is the duration of the voltage rising period (i.e. the difference between and ), is the time when the voltage of the first SiC MOSFET starts to rise, is the time when the voltage of the third SiC MOSFET becomes zero. is the voltage value of the first SiC MOSFET at = , is the time, ≤ < .

[0140] In the first modality, can be approximated as the time when the voltage starts to rise to 5% of the half bus voltage.

[0141] to The current fitting function during

[0142]

[0143] wherein, is the first SiC MOSFET at to The current value during is the hard-off coefficient, is the loss coefficient, is the time, ≤ < .

[0144] The current of the first SiC MOSFET at the moment = and the moment satisfies the following expression respectively:

[0145]

[0146] wherein, is the current value of the first SiC MOSFET at the moment = 0, is the load current, is the current value of the first SiC MOSFET at the moment = , is = the current value of the first SiC MOSFET at the moment is the duration of the voltage rising period, is the current value of the first SiC MOSFET during to , is the moment when the voltage of the first SiC MOSFET begins to rise, is the moment when the voltage of the third SiC MOSFET is zero, is the time, ≤ < , This refers to the amount of charge generated by the junction capacitance of a normally off SiC MOSFET (excluding calibration devices) during the voltage rise period.

[0147] in:

[0148] The aforementioned calibrated device is the first SiC MOSFET. At that time, the amount of charge discharged from the junction capacitance is That is, the third SiC MOSFET Junction capacitance and fourth SiC MOSFET The sum of the discharge charge of the junction capacitance during the voltage rise period;

[0149] The aforementioned calibrated device is the second SiC MOSFET. At that time, the amount of charge charged and discharged from the junction capacitance is That is, the first SiC MOSFET Junction capacitance and fourth SiC MOSFET The sum of the charge and discharge charges of the junction capacitance during the voltage rise period;

[0150] The aforementioned calibrated device is the third SiC MOSFET. At that time, the amount of charge charged and discharged from the junction capacitance is That is, the junction capacitance of the first SiC MOSFET S1 and the fourth SiC MOSFET The sum of the charge and discharge charges of the junction capacitance during the voltage rise period;

[0151] The aforementioned calibrated device is the fourth SiC MOSFET. At that time, the amount of charge discharged from the junction capacitance is That is, the junction capacitance of the first SiC MOSFET S1 and the second SiC MOSFET The sum of the discharge charge of the junction capacitance during the voltage rise period.

[0152] Through the above =0 time, = At that moment, the first SiC MOSFET The hard-turn-off coefficient and loss coefficient can be calculated from the expression satisfied by the current.

[0153] exist At that moment, the first SiC MOSFET The current value is approximately equal to the load current. The loss factor and hard-turn-off factor can be determined by... Figure 6 The current characteristic curve of the current changing with time is determined.

[0154] based on to The voltage fitting function and the current fitting function during the period can be derived as The loss expression during the period is:

[0155]

[0156] wherein, is the first SiC MOSFET During the period the hard turn-off loss, is the first SiC MOSFET During the period the voltage value, is the first SiC MOSFET During the period the current value, is the first SiC MOSFET At the moment the voltage value, is the load current value, is the duration of the voltage rising period (i.e., the difference between and ), is the loss coefficient, is the moment when the voltage starts to rise, is the third SiC MOSFET the voltage value is zero, is the time, ≤ < .

[0157] It should be noted that for other modalities, the hard turn-off loss model during the voltage rising period can be determined in the same way as the first mode, and the expression obtained is similar, which will not be repeated here. Based on the above-mentioned first mode expression, by replacing the first SiC MOSFET with the calibration device, replacing V 1_2 with the voltage value of the calibration device at the moment when the voltage value of the preset SiC MOSFET is zero, the first hard turn-off loss model of the calibration device during the voltage rising period can be obtained.

[0158] Step S302, according to the turn-off voltage characteristic parameter, determining a second hard turn-off loss calculation model of the calibration device during the current falling period.

[0159] ​​​​In a specific implementation, the test device can calculate a second hard turn-off loss calculation model based on the turn-off voltage characteristic parameter during the current drop period of the calibration device, the second hard turn-off loss calculation model representing a mapping relationship between the turn-off voltage characteristic parameter and the hard turn-off loss of the calibration device during the current drop period.

[0160] Step S303: determining the hard turn-off loss calculation model of the calibration device according to the first hard turn-off loss calculation model and the second hard turn-off loss calculation model.

[0161] In a feasible implementation, the current drop period is composed of the time point when the preset SiC MOSFET voltage value is zero and the time point when the current of the calibration device drops to zero, and step S302 includes steps S3021-S3022.

[0162] Step S3021: calculating a deviation between the time point when the current drops to zero and the time point when the preset SiC MOSFET voltage value is zero to obtain a length of the current drop period.

[0163] In a specific implementation, a period composed of the time point when the preset SiC MOSFET voltage value is zero and the time point when the current drops to zero can be regarded as the current drop period, and the test device can obtain the length of the current drop period by calculating the deviation between the time point when the current drops to zero and the time point when the preset SiC MOSFET voltage value is zero.

[0164] Step S3022: determining a second hard turn-off loss model of the calibration device during the current drop period based on the voltage value of the calibration device at the time point when the preset SiC MOSFET voltage value is zero, the length of the voltage rise period, and the length of the current drop period.

[0165] The second hard turn-off loss calculation model is:

[0166]

[0167] In the formula, is the hard turn-off loss of the calibration device during the current drop period, is the voltage value of the calibration device at the time point when the preset SiC MOSFET voltage value is zero, is the load current value, is the length of the voltage rise period, is the length of the current drop period, is a loss coefficient.

[0168] Correspondingly, step S303 includes:

[0169] The first hard-off loss calculation model and the second hard-off loss calculation model are combined to obtain a hard-off loss calculation model of the calibration device.

[0170] The hard-off loss calculation model is:

[0171]

[0172] In the formula, is a hard-off loss of the calibration device, is a hard-off loss of the calibration device in the voltage rising period, is a hard-off loss of the calibration device in the current falling period.

[0173] Exemplarily, based on the hard-off process of the first mode in the voltage rising period, the hard-off process of the first mode in the current falling period is continued to be described by Figure 4 The hard-off process of the first mode in the current falling period is described with the moment when the voltage value of the third SiC MOSFET is zero as and the moment when the current of the first SiC MOSFET falls to zero as .

[0174] During to : the current of the first SiC MOSFET channel gradually decreases to 0. The body diode of the third SiC MOSFET is turned on, and the current flowing through the third SiC MOSFET gradually increases to the load current. At the same time, due to the high current change rate, an induced voltage is generated on the first inductor L1, so that the voltage of the first SiC MOSFET is slightly higher than the half bus voltage.

[0175] After : the load current is completely transferred to the channel of the second SiC MOSFET and the body diode of the third SiC MOSFET . The junction capacitance of the first SiC MOSFET , the junction capacitance of the fourth SiC MOSFET , the first inductor L1, the second inductor L2, and the package lead inductance of each SiC MOSFET resonate at a high resonance frequency. At the resonance frequency, the equivalent impedance of the circuit presents a capacitive characteristic, and the current phase of the first SiC MOSFET leads the voltage phase of the third SiC MOSFET by 90°.

[0176] Exemplarily, based on the above-mentioned second mode of hard turn-off process in the voltage rising period, it is continued to be described by taking the first SiC MOSFET as an example Figure 5 The hard turn-off process of the second mode in the current falling period is described, and the voltage value of the first SiC MOSFET is zero at the moment , and the current of the first SiC MOSFET falls to zero at the moment .

[0177] During to : the current of the channel of the third SiC MOSFET gradually decreases to 0. The body diode of the first SiC MOSFET is turned on, and the current flowing through the first SiC MOSFET gradually increases to the load current. At the same time, due to the high current change rate, an induced voltage is generated on the first inductor L1, which is slightly higher than the half bus voltage.

[0178] After : the load current is completely transferred to the body diode of the first SiC MOSFET . The junction capacitance of the third SiC MOSFET , the junction capacitance of the fourth SiC MOSFET , the first inductor L1, the second inductor L2 and the package lead inductance of each SiC MOSFET resonate at a high resonance frequency. At the resonance frequency, the equivalent impedance of the circuit presents a capacitive characteristic, and the current phase of the third SiC MOSFET leads the phase by 90°.

[0179] Further, in combination with Figure 6 and the above-mentioned hard turn-off analysis process in the current falling period, it is continued to be described by taking the first SiC MOSFET as an example (i.e. the first SiC MOSFET is the rated device), the voltage value of the third SiC MOSFET is zero at the moment , and the current of the first SiC MOSFET falls to zero at the moment .

[0180] During to , is approximately equal to ; the current of the first SiC MOSFET ​The current of the first SiC MOSFET decreases linearly at a greater rate of change to 0.

[0181] to The voltage fitting function during the period is:

[0182]

[0183] wherein, is the voltage of the first SiC MOSFET at to The voltage value during the period, is the voltage of the first SiC MOSFET at = The voltage value at the moment, is the voltage of the third SiC MOSFET at the moment when the voltage value is zero, is the moment when the current of the first SiC MOSFET drops to zero, is the time, ≤ < .

[0184] to The current fitting function during the period is:

[0185]

[0186] wherein, is the current of the first SiC MOSFET at to The current value during the period, is the current of the first SiC MOSFET at = The current value at the moment, is the length of the current drop period (i.e. the difference between and ), is the voltage of the third SiC MOSFET at the moment when the voltage value is zero, is the moment when the current of the first SiC MOSFET drops to zero, is the time, < ≤ .

[0187] Based on to The voltage fitting function and the current fitting function during the period can be derived to The loss expression during the period is:

[0188]

[0189] wherein, is the first SiC MOSFET During to the hard-off loss during the period, is the first SiC MOSFET During to the voltage value during the period, is the first SiC MOSFET During to the current value during the period, is the first SiC MOSFET During =the voltage value at the moment, is the load current value, is the duration of the voltage rising period, is the duration of the current falling period (i.e., the difference between and ), is time,

[0190] It should be noted that for other modalities, the hard-off loss model during the current falling period can be determined in the same manner as the first modality, and the obtained expression is similar, which will not be repeated here. Based on the above-mentioned first modality expression, by replacing the first SiC MOSFET with the calibration device, and replacing with the voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero, the second hard-off loss model of the calibration device during the current falling period can be obtained.

[0191] Further, by adding the expression of the first hard-off loss model and the expression of the second hard-off loss model, the hard-off loss calculation model of the calibration device can be obtained.

[0192] ​​​The embodiment determines a first hard-off loss calculation model of the calibration device in the voltage rising period according to the off voltage characteristic parameter, determines a second hard-off loss calculation model of the calibration device in the current falling period according to the off voltage characteristic parameter, and determines the hard-off loss calculation model of the calibration device according to the first hard-off loss calculation model and the second hard-off loss calculation model, so that the hard-off loss calculation model can reflect the hard-off loss of the calibration device in different periods, and the precision of the hard-off loss calculation model is effectively improved.

[0193] Based on the first embodiment and the second embodiment of the present application, the third embodiment of the present application is proposed. In the third embodiment of the present application, the same or similar contents as the above first embodiment and the second embodiment can be referred to the above introduction, and will not be described in detail. On this basis, please refer to Figure 7 , Figure 7 The flowchart of the third embodiment of the SiC MOSFET hard switching loss calculation method of the TNPC circuit of the present application is shown.

[0194] In the embodiment, the hard-on period is composed of a current rising period and a voltage falling period, and the step of determining the hard-on loss calculation model of the calibration device in the hard-on period according to the on voltage characteristic parameter includes steps S401-S403:

[0195] In step S401, the first hard-on loss calculation model of the calibration device in the current rising period is determined according to the on voltage characteristic parameter.

[0196] It should be noted that the above-mentioned current rising period can be the on period of the calibration device, and the period of current rising.

[0197] In a specific implementation, the test device can calculate the first hard-on loss calculation model based on the on voltage characteristic parameter when the calibration device is in the current rising period, and the first hard-on loss calculation model represents the mapping relationship between the on voltage characteristic parameter and the hard-on loss of the calibration device in the current rising period.

[0198] In a feasible implementation, the current rising period is composed of the moment when the voltage of the calibration device starts to fall and the moment when the current of the calibration device rises to the load current, and step S401 includes steps S4011-S4013:

[0199] In step S4011, the deviation between the moment when the current rises to the load current and the moment when the voltage starts to fall is calculated to obtain the length of the current rising period.

[0200] In a specific implementation, the starting moment can be the moment when the voltage of the calibration device starts to drop, and the ending moment can be the moment when the current of the calibration device rises to the load current. The test device can obtain the duration of the current rise period by calculating the deviation between the moment when the current of the calibration device rises to the load current and the moment when the voltage of the calibration device starts to drop.

[0201] In step S4012, the voltage value of the calibration device at the moment when the voltage starts to drop and the voltage value of the calibration device at the moment when the current rises to the load current are determined according to the turn-on voltage characteristic parameter.

[0202] In a specific implementation, the test device can extract the voltage value of the calibration device at the moment when the voltage starts to drop and the voltage value of the calibration device at the moment when the current rises to the load current from the turn-on voltage characteristic parameter.

[0203] In step S4013, a first hard turn-on loss calculation model of the calibration device in the current rise period is determined by the voltage value of the calibration device at the moment when the voltage starts to drop, the voltage value of the calibration device at the moment when the current rises to the load current, and the duration of the current rise period.

[0204] The first hard turn-on loss calculation model is as follows:

[0205]

[0206] In the formula, Vth is the threshold voltage of the calibration device, Vd is the voltage value of the calibration device at the moment when the voltage starts to drop, Vr is the voltage value of the calibration device at the moment when the current rises to the load current, I is the load current value, and T is the duration of the current rise period. is the hard turn-on loss of the calibration device in the current rise period, is the voltage value of the calibration device at the moment when the voltage starts to drop, is the voltage value of the calibration device at the moment when the current rises to the load current, is the load current value, is the duration of the current rise period.

[0207] For example, by Figure 4 the hard turn-on process of the first mode (i.e., the first SiC MOSFET is the calibration device) is described, and the voltage of the first SiC MOSFET starts to drop at , the current of the first SiC MOSFET rises to the load current at , the voltage across the first SiC MOSFET is , the voltage across the second SiC MOSFET is , and the voltage across the third SiC MOSFET is , fourth SiC MOSFET The voltage across is explained.

[0208] Before : load current flows through the body diode of the second SiC MOSFET channel and the third SiC MOSFET . is the half bus voltage, the current of the first SiC MOSFET is 0.

[0209] During to : the channel of the first SiC MOSFET is turned on, and the load current starts to migrate from the body diode of the third SiC MOSFET to the channel of the first SiC MOSFET . Due to the high rate of change of the current flowing through the first inductor L1, the first SiC MOSFET , the second SiC MOSFET , the third SiC MOSFET , an induced voltage is generated on the package lead inductance of the first inductor L1, the second SiC MOSFET , and the third SiC MOSFET , which causes to decrease. At the same time, due to the appearance of the induced voltage and the change of , causes to increase, a small part of the current will flow through the fourth SiC MOSFET , charging the junction capacitance Cds4 of the fourth SiC MOSFET . At the moment of , the current flowing through the body diode of the third SiC MOSFET is all migrated to the channel of the first SiC MOSFET , and the current of the third SiC MOSFET is 0; at this time, there is still a small amount of current flowing from the upper half bridge arm into the fourth SiC MOSFET , but because the rate of change of the voltage of is low at this time, the charging current of the junction capacitance of the fourth SiC MOSFET can be ignored, so the current of the first SiC MOSFET is approximately equal to the load current.

[0210] Exemplarily, by Figure 5The hard-on process of the second mode (i.e., the third SiC MOSFET ) is described, and the voltage of the third SiC MOSFET begins to decrease at the moment , the current of the third SiC MOSFET rises to the load current at the moment , the voltage across the first SiC MOSFET is , the voltage across the second SiC MOSFET is , the voltage across the third SiC MOSFET is , and the voltage across the fourth SiC MOSFET is .

[0211] Before : the load current flows through the body diode of the first SiC MOSFET . is the half bus voltage, and the current of the third SiC MOSFET is 0.

[0212] During to : the channel of the third SiC MOSFET opens, and the load current begins to migrate from the body diode of the first SiC MOSFET to the channel of the third SiC MOSFET . Due to the high rate of change of the current flowing through the first inductor L1, the first SiC MOSFET , the second SiC MOSFET , and the third SiC MOSFET , an induced voltage is generated on the package lead inductance of the first inductor L1, the first SiC MOSFET , and the package lead inductance of the second SiC MOSFET , causing to decrease. At the same time, due to the appearance of the induced voltage and the change of , causes to decrease, and the discharge of the junction capacitance of the fourth SiC MOSFET generates a small current flowing through the third SiC MOSFET . At the moment , the load current is completely migrated to the channel of the third SiC MOSFET , and the first SiC MOSFET The current of the third SiC MOSFET is 0, at this time there is still a small amount of current flowing from the lower half-bridge arm into the third SiC MOSFET , but at this time The voltage rate of change of the fourth SiC MOSFET is low, and the charging current of the junction capacitance of the fourth SiC MOSFET is negligible, so the current of the third SiC MOSFET is approximately equal to the load current.

[0213] Further, the hard switching process can be simplified by analyzing the circuit commutation process of the switching process, and combining the switching characteristic curve of the calibrated device to obtain a simplified waveform diagram of the hard switching process, referring to Figure 8 , Figure 8 The simplified waveform diagram of the hard switching process of the present application is Figure 8 The voltage (V) and current (I) trends over time in each period of the hard switching process are described. In combination with Figure 8 and based on the hard switching analysis process of the current rising period above, the above first mode is taken as an example (i.e. the first SiC MOSFET is the calibrated device), and the voltage of the first SiC MOSFET begins to decline at , and the current of the first SiC MOSFET rises to the load current at The determination process of the first hard switching loss calculation model is described.

[0214] During to , the current of the first SiC MOSFET begins to linearly increase from 0; the first inductor L1, the second inductor L2, and the packaging lead inductance of the third SiC MOSFET induce an induced voltage, causing to almost linearly decrease.

[0215] The voltage fitting function during to

[0216]

[0217] In the formula, is the voltage value of the first SiC MOSFET during to , and is the duration of the current rising period (i.e. the difference between and . the voltage of the first SiC MOSFET starts to decrease, the current of the first SiC MOSFET rises to the load current. the voltage value of the first SiC MOSFET at the moment, the voltage value of the first SiC MOSFET at the moment, the voltage value of the first SiC MOSFET at the moment, the time, ≤ < .

[0218] According to the magnetic flux conservation principle, the integral of the parasitic inductance voltage on the closed loop with respect to time within a period of time is equal to the product of the parasitic inductance and the change in inductance current. According to this, the length of time of the current rise period is solved by simultaneous equations. For the closed loop composed of the first DC capacitor C1, the first inductor L1, the first SiC MOSFET , the second SiC MOSFET , and the third SiC MOSFET , the expressions involved are as follows within the time period to :

[0219]

[0220] wherein, is the half bus voltage, is the voltage value of the first SiC MOSFET during to , is the first inductor, is the parasitic inductance of a single power device, is the resonant frequency of the circuit during hard turn-off, is the junction capacitance of the power device participating in resonance.

[0221] is the value of the parasitic inductance. When the above-mentioned device is the first SiC MOSFET , is the sum of the parasitic inductance of the PCB line of the half-bridge arm of the TNPC circuit, the parasitic inductance of the second SiC MOSFET , and the parasitic inductance of the third SiC MOSFET ; when the above-mentioned device is the second SiC MOSFET , Parasitic inductance of the PCB traces of the lower half-bridge arm of the TNPC circuit, and the third SiC MOSFET Parasitic inductance and the fourth SiC MOSFET The sum of parasitic inductances; in the above-mentioned calibrated device is the third SiC MOSFET. hour, Parasitic inductance of the upper half-bridge arm PCB circuit of the TNPC circuit, and the first SiC MOSFET Parasitic inductance and the second SiC MOSFET The sum of parasitic inductances; in the above-mentioned calibrated device is the fourth SiC MOSFET. hour, Parasitic inductance of the PCB traces of the lower half-bridge arm of the TNPC circuit, and the second SiC MOSFET Parasitic inductance and third SiC MOSFET The sum of parasitic inductance.

[0222] to The current fitting function during this period is:

[0223]

[0224] In the formula, The first SiC MOSFET exist to Current value during the period, This is the load current value. The duration of the current rise period (i.e.) and (difference between them) The first SiC MOSFET The moment when the voltage begins to drop, The first SiC MOSFET The moment when the current rises to the load current is, For time, ≤ < .

[0225] based on to The voltage and current fitting functions during the period can be obtained to The loss expression during the period is:

[0226]

[0227] In the formula, for the first SiC MOSFET during to the hard turn-on loss, for the first SiC MOSFET during to the voltage value, for the first SiC MOSFET during to the current value, for the first SiC MOSFET at the voltage value, for the first SiC MOSFET at the voltage value, for the load current value, for the duration of the current rise period (i.e. the difference between and for the first SiC MOSFET at which the voltage begins to decrease, for the first SiC MOSFET at which the current rises to the load current, for the time, ≤ < .

[0228] It should be noted that for other modalities, the hard turn-on loss model in the current rise period can be determined in the same way as the first modality, and the expression obtained is similar, which will not be repeated here. Based on the above-mentioned first modality expression, by replacing the first SiC MOSFET with the calibrated device, replacing with the voltage value of the calibrated device at which the voltage begins to decrease, and replacing with the voltage value of the calibrated device at which the current rises to the load current, the first hard turn-on loss model of the calibrated device in the current rise period can be obtained.

[0229] Step S402, determining a second hard turn-on loss calculation model of the calibrated device in the period formed by the voltage drop period according to the turn-on voltage characteristic parameter.

[0230] In a specific implementation, the test device can calculate a second hard turn-on loss calculation model based on the turn-on voltage characteristic parameter during the voltage drop period of the calibration device, the second hard turn-on loss calculation model representing a mapping relationship between the turn-on voltage characteristic parameter and the hard turn-on loss of the calibration device during the voltage drop period.

[0231] In step S403, a hard turn-on loss calculation model of the calibration device is determined according to the first hard turn-on loss calculation model and the second hard turn-on loss calculation model.

[0232] In a feasible implementation, the voltage drop period is composed of a time point when the current rises to the load current and a time point when the voltage of the calibration device drops to zero, and step S402 includes steps S4021-S4024.

[0233] In step S4021, a deviation between the time point when the voltage drops to zero and the time point when the current rises to the load current is calculated to obtain a duration of the voltage drop period.

[0234] In a specific implementation, a period composed of a time point when the current rises to the load current and a time point when the voltage drops to zero can be regarded as the voltage drop period, and the test device can obtain the duration of the voltage drop period by calculating the deviation between the time point when the voltage drops to zero and the time point when the current rises to the load current.

[0235] In step S4022, a charge amount of junction capacitance charging and discharging of a normally-off SiC MOSFET other than the calibration device in the TNPC circuit during the voltage drop period is determined.

[0236] The normally-off SiC MOSFET is a SiC MOSFET whose channel is in a closed state during the hard turn-off period and the hard turn-on period.

[0237] In step S4023, a voltage value of the calibration device at the time point when the current rises to the load current is determined according to the turn-on voltage characteristic parameter.

[0238] In step S4024, a second hard turn-on loss calculation model of the calibration device during the voltage drop period is determined by the charge amount of the junction capacitance charging and discharging, the voltage value of the calibration device at the time point when the current rises to the load current, and the duration of the voltage drop period.

[0239] The second hard turn-on loss calculation model is:

[0240]

[0241] In the formula, is the hard turn-on loss of the calibration device during the voltage drop period. This refers to the amount of charge charged and discharged from the junction capacitance of a normally off SiC MOSFET (excluding calibration devices) during the voltage drop period. To calibrate the voltage value of the device when the current rises to the load current, This is the load current value. This represents the duration of the voltage drop period.

[0242] Accordingly, step S403 includes:

[0243] The hard turn-on loss calculation model of the calibration device is obtained by combining the first hard turn-on loss calculation model with the second hard turn-on loss calculation model.

[0244] The hard-turn-on loss calculation model is as follows:

[0245]

[0246] In the formula, To calibrate the hard-turn-on loss of the device, To calibrate the hard-turn-on loss of the device during the current rise period. This is to calibrate the hard-turn-on loss of the device during the voltage drop period.

[0247] For example, based on the hard-switching process of the first mode during the current rise period, the process continues through... Figure 4 The hard-turn-on process of the first mode during the voltage drop period is explained, using the first SiC MOSFET as an example. The current rises to the load current at the moment when With the first SiC MOSFET The moment the voltage drops to zero is Please provide an explanation.

[0248] The voltage drop period includes a first voltage drop period and a second voltage drop period, with the first SiC MOSFET... The reverse recovery time is To explain, the first voltage drop period is caused by to The time period is composed of the second voltage drop period, which is composed of... to Composition.

[0249] exist arrive Period: Third SiC MOSFET When the body diode switches from the on to the off state, a reverse recovery current is generated. This first voltage drop period can also be called the reverse recovery period. This reverse recovery current flows through the first SiC MOSFET together with the load current. During this period The body diode of the first SiC MOSFET

[0250] At to During this period: the junction capacitance of the first SiC MOSFET is discharged through the channel of the first SiC MOSFET , and the voltage decreases. The junction capacitance of the third SiC MOSFET and the junction capacitance of the fourth SiC MOSFET are charged, and the voltage increases. Due to the existence of the charging current of the junction capacitance of the third SiC MOSFET and the junction capacitance of the fourth SiC MOSFET , the current of the first SiC MOSFET is higher than the load current. At , the voltage of the first SiC MOSFET decreases to 0.

[0251] After : the power supply continues to charge the load . The junction capacitance of the third SiC MOSFET , the junction capacitance of the fourth SiC MOSFET , the first inductor L1, the second inductor L2, and the package lead inductance of each SiC MOSFET resonate together. Due to the high resonance frequency, the circuit is close to pure inductance. Therefore, the phase of the current of the first SiC MOSFET leads the current phase by 90°.

[0252] Exemplarily, based on the above-mentioned hard-on process of the second mode during the current rising period, the hard-on process of the second mode during the voltage decreasing period is described, and the moment when the current of the third SiC MOSFET Figure 5 rises to the load current is , the moment when the reverse recovery of the third SiC MOSFET occurs is , and the moment when the voltage of the third SiC MOSFET decreases to zero is .

[0253] During to : the body diode of the first SiC MOSFET is switched from the on state to the off state, which generates a reverse recovery current, and the reverse recovery current and the load current flow through the third SiC MOSFET​​ channel, during which is substantially maintained.

[0254] in to during: the junction capacitance of the third SiC MOSFET is discharged through the channel of the third SiC MOSFET , the voltage of the third SiC MOSFET decreases. The junction capacitance of the first SiC MOSFET is charged, the voltage of the first SiC MOSFET increases; the junction capacitance of the fourth SiC MOSFET is discharged, the voltage of the fourth SiC MOSFET decreases. Due to the existence of the charge and discharge currents of the junction capacitance of the first SiC MOSFET and the junction capacitance of the fourth SiC MOSFET , the current of the third SiC MOSFET is higher than the load current. At , the voltage of the third SiC MOSFET

[0255] decreases to 0. after , the power supply continues to charge the load. The junction capacitance of the first SiC MOSFET , the junction capacitance of the fourth SiC MOSFET , the first inductor L1, the second inductor L2 and the package lead inductance of each SiC MOSFET resonate, due to the high resonance frequency, the circuit is close to pure inductance. Therefore, the phase of the current of the third SiC MOSFET leads the phase of the current of the third SiC MOSFET

[0256] Further, in combination with Figure 8 and the hard turn-on analysis process of the voltage drop period above, taking the first mode above as an example (i.e. the first SiC MOSFET is the rated device), taking the reverse recovery time of the first SiC MOSFET as , taking the time when the voltage of the first SiC MOSFET drops to zero as , the determination process of the second hard turn-on loss calculation model is described.

[0257] During to , the body diode of the third SiC MOSFET generates a reverse recovery current in the turn-off process, causing the current of the first SiC MOSFET to increase. is maintained the voltage value of the moment. The first SiC MOSFET reverse recovery time .

[0258] During the period from to , the charging current of the junction capacitance of the third SiC MOSFET and the junction capacitance of the fourth SiC MOSFET flows through the channel of the first SiC MOSFET together with the load current. Almost linearly decreases. Since the reverse recovery current is small, only the charging current of the junction capacitance is considered. According to the actual waveform, it can be seen that the current of the first SiC MOSFET in this stage is approximately equal to the load current plus a half-period sine wave.

[0259] During the period from , the current fitting function is:

[0260]

[0261]

[0262] wherein, is the current value of the first SiC MOSFET during the period from to , is the duration of the voltage drop period (i.e. the difference between and , is the moment when the voltage of the first SiC MOSFET drops to zero, is the load current value, is the current coefficient, is the sine wave period, is the sum of the charging charge of the junction capacitance of the third SiC MOSFET and the junction capacitance of the fourth SiC MOSFET in the voltage drop period, < ≤ .

[0263] In order to compensate for the neglected reverse recovery current and reduce the number of undetermined coefficients in the fitting function, a 3rd power function is selected as the voltage fitting function. The voltage fitting function passes through the points (0, ) and ( , 0), and can be obtained to The voltage fitting function during this period is:

[0264]

[0265] In the formula, The first SiC MOSFET exist to Voltage value during the period for First SiC MOSFET voltage value, The duration of the voltage drop period (i.e. and (difference between them) The first SiC MOSFET When the current rises to the load current, The first SiC MOSFET When the voltage drops to zero, < ≤ .

[0266] based on to The voltage and current fitting functions during the period can be obtained to The loss expression during the period is:

[0267]

[0268] In the formula, The first SiC MOSFET exist to Hard activation losses during the period The first SiC MOSFET exist to Voltage value during the period The first SiC MOSFET exist to Current value during the period, For the third SiC MOSFET Junction capacitance and fourth SiC MOSFET The sum of the charging charge during the voltage drop period of the junction capacitance. The first SiC MOSFET exist Voltage value at time, is a load current value, is a duration of the voltage falling period (i.e. is a difference between , is a time when the current of the first SiC MOSFET rises to the load current, is a time when the voltage of the first SiC MOSFET falls to zero, ≤ .

[0269] It should be noted that the hard turn-on loss model in the voltage falling period can be determined in the same way as the first mode of analysis for other modes, and the obtained expression is similar, which is not described here. Based on the above-mentioned first mode of expression, by replacing the first SiC MOSFET with the calibration device, replacing with the voltage value of the calibration device at the time when the current rises to the load current, and replacing (i.e. the sum of the charging charge of the junction capacitance of the third SiC MOSFET and the junction capacitance of the fourth SiC MOSFET in the voltage falling period) with (i.e. the charge amount of the junction capacitance charging and discharging of the always-off SiC MOSFET other than the calibration device in the voltage falling period), the second hard turn-on loss model of the calibration device in the voltage falling period can be obtained.

[0270] Wherein:

[0271] When the above-mentioned calibration device is the first SiC MOSFET , the charge amount of the junction capacitance charging is , that is, the sum of the charging charge of the junction capacitance of the third SiC MOSFET and the junction capacitance of the fourth SiC MOSFET in the voltage falling period;

[0272] When the above-mentioned calibration device is the second SiC MOSFET , the charge amount of the junction capacitance charging and discharging is , that is, the sum of the charging and discharging charge of the junction capacitance of the first SiC MOSFET and the junction capacitance of the fourth SiC MOSFET in the voltage falling period;

[0273] When the above-mentioned calibration device is the third SiC MOSFET , the charge amount of the junction capacitance charging and discharging is​ the sum of the charge amount of the junction capacitance of the first SiC MOSFET and the junction capacitance of the fourth SiC MOSFET during the voltage drop period;

[0274] When the calibration device is the fourth SiC MOSFET , the charge amount of the junction capacitance is the sum of the charge amount of the junction capacitance of the first SiC MOSFET and the junction capacitance of the second SiC MOSFET during the voltage drop period.

[0275] Further, by adding the expression of the first hard turn-on loss model and the expression of the second hard turn-on loss model, the hard turn-on loss calculation model of the calibration device can be obtained.

[0276] In this embodiment, the first hard turn-on loss calculation model of the calibration device during the current rise period is determined according to the turn-on voltage characteristic parameter; the second hard turn-on loss calculation model of the calibration device during the voltage drop period is determined according to the turn-on voltage characteristic parameter; and the hard turn-on loss calculation model of the calibration device is determined according to the first hard turn-on loss calculation model and the second hard turn-on loss calculation model, so that the hard turn-on loss calculation model can reflect the hard turn-on loss of the calibration device in different periods, and the accuracy of the hard turn-on loss calculation model is effectively improved.

[0277] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the SiC MOSFET hard switching loss calculation method of the TNPC circuit of the present application. More forms of simple transformation based on this technical concept are within the protection scope of the present application.

[0278] The present application provides a test device, which is connected with the TNPC circuit, and the test device comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program is configured to implement the steps of the SiC MOSFET hard switching loss calculation method of the TNPC circuit.

[0279] As shown in Figure 2 , the TNPC circuit comprises a power supply Vdc, a first direct current capacitor C1, a second direct current capacitor C2, a load and a plurality of SiC MOSFETs. The SiC MOSFETs comprise a first SiC MOSFET , a second SiC MOSFET , a third SiC MOSFET and a fourth SiC MOSFET a first SiC MOSFET a drain of the first SiC MOSFET a source of the first SiC MOSFET a drain of the third SiC MOSFET a drain of the fourth SiC MOSFET a load a source of the third SiC MOSFET a source of the second SiC MOSFET a drain of the second SiC MOSFET a source of the fourth SiC MOSFET

[0280] Although not shown in Figure 2 , it should be noted that a gate of the first SiC MOSFET , a gate of the second SiC MOSFET , a gate of the third SiC MOSFET , and a gate of the fourth SiC MOSFET are connected to a test device.

[0281] Reference is made below to Figure 9 , Figure 9 a structural diagram of the test device of the present application. The test device in the embodiments of the present application can include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), and vehicle-mounted terminals (e.g., vehicle-mounted navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 9 The test device shown is merely an example and should not impose any limitation on the functions and use range of the embodiments of the present application.

[0282] As shown in Figure 9As shown, the test device can include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. Various programs and data required for operation of the test device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other by a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the test device to communicate wirelessly or by wire with other devices to exchange data. Although a device having various systems is shown in the figure, it should be understood that all of the systems shown are not required to be implemented or possessed. More or fewer systems can be alternatively implemented or possessed.

[0283] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by a communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0284] The test device provided by the present application adopts the SiC MOSFET hard switching loss calculation method of the TNPC circuit in the above-mentioned embodiments, which can solve the technical problem that the prior art makes great changes to the TNPC circuit, and further causes the hard switching loss measurement process to be relatively complex. Compared with the prior art, the beneficial effects of the test device provided by the present application are the same as those of the SiC MOSFET hard switching loss calculation method of the TNPC circuit provided by the above-mentioned embodiments, and other technical features in the test device are the same as those disclosed in the previous embodiment method, which will not be repeated here.

[0285] It should be understood that aspects of the application can be implemented in hardware, software, firmware or a combination thereof. In the description of the embodiments above, specific features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0286] The above description is only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for calculating SiC MOSFET hard switching losses of a TNPC circuit, characterized by, The method comprises: controlling channel turn-off of a current device under test in a TNPC circuit by applying a turn-off pulse signal to the current device under test, and obtaining a current turn-off voltage characteristic parameter of the current device under test in a turn-off process, the current device under test being a SiC MOSFET required to be measured in the TNPC circuit; controlling channel turn-on of the current device under test by applying a turn-on pulse signal to the current device under test, and obtaining a current turn-on voltage characteristic parameter of the current device under test in a turn-on process; obtaining a hard switching loss calculation model, the hard switching loss calculation model being constructed in advance based on a turn-off voltage characteristic parameter of a calibration device in a hard turn-off period and a turn-on voltage characteristic parameter of the calibration device in a hard turn-on period, the hard switching loss calculation model representing a mapping relationship between the turn-off voltage characteristic parameter and a hard switching loss and a mapping relationship between the turn-on voltage characteristic parameter and the hard switching loss, the calibration device being a SiC MOSFET used to construct the hard switching loss calculation model in the TNPC circuit; substituting the current turn-off voltage characteristic parameter and the current turn-on voltage characteristic parameter into the hard switching loss calculation model to obtain a hard switching loss of the current device under test; before the step of obtaining the hard switching loss calculation model, the method further comprises: obtaining a turn-off voltage characteristic parameter of the calibration device in a turn-off process; obtaining a turn-on voltage characteristic parameter of the calibration device in a turn-on process; determining a hard turn-off period of the calibration device and a hard turn-on period of the calibration device; determining a hard turn-off loss calculation model of the calibration device in the hard turn-off period according to the turn-off voltage characteristic parameter; determining a hard turn-on loss calculation model of the calibration device in the hard turn-on period according to the turn-on voltage characteristic parameter; determining a hard switching loss calculation model according to the hard turn-off loss calculation model and the hard turn-on loss calculation model.

2. The method of SiC MOSFET hard switching loss calculation for TNPC circuit of claim 1, wherein, the hard turn-off period is composed of a voltage rising period and a current falling period, the step of determining the hard turn-off loss calculation model of the calibration device in the hard turn-off period according to the turn-off voltage characteristic parameter comprises: determining a first hard turn-off loss calculation model of the calibration device in the voltage rising period according to the turn-off voltage characteristic parameter; determining a second hard turn-off loss calculation model of the calibration device in the current falling period according to the turn-off voltage characteristic parameter; determining the hard turn-off loss calculation model of the calibration device according to the first hard turn-off loss calculation model and the second hard turn-off loss calculation model.

3. The method of SiC MOSFET hard switching loss calculation for TNPC circuit of claim 2, wherein, the voltage rising period is composed of a voltage start rising time of the calibration device to a time when a preset SiC MOSFET voltage value in the TNPC circuit is zero, the step of determining the first hard turn-off loss calculation model of the calibration device in the voltage rising period according to the turn-off voltage characteristic parameter comprises: calculating a deviation between the time when the preset SiC MOSFET voltage value is zero and the voltage start rising time to obtain a length of the voltage rising period; determining a voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero according to the turn-off voltage characteristic parameter; determining a first hard turn-off loss model of the calibration device in the voltage rising period through the voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero and the length of the voltage rising period, and the first hard turn-off loss calculation model is: In the formula, is the hard-off loss of the device in the voltage rising period, is the voltage value of the device at the moment when the preset SiC MOSFET voltage value is zero, is the load current value, is the duration of the voltage rising period, is the loss coefficient.

4. The method for calculating SiC MOSFET hard switching losses in the TNPC circuit as described in claim 3, characterized in that, The current falling period is composed of the moment when the preset SiC MOSFET voltage value is zero to the moment when the current of the calibration device falls to zero, and the step of determining a second hard turn-off loss calculation model of the calibration device in the current falling period according to the turn-off voltage characteristic parameter comprises: calculating a deviation between the moment when the current falls to zero and the moment when the preset SiC MOSFET voltage value is zero to obtain the length of the current falling period; determining a second hard turn-off loss model of the calibration device in the current falling period through the voltage value of the calibration device at the moment when the preset SiC MOSFET voltage value is zero, the length of the voltage rising period and the length of the current falling period, and the second hard turn-off loss calculation model is: In the formula, is the hard-off loss of the device in the current drop period, is the voltage value of the device at the moment when the preset SiC MOSFET voltage value is zero, is the load current value, is the duration of the voltage rise period, is the duration of the current drop period, is the loss coefficient; The step of determining a hard turn-off loss calculation model of the calibration device according to the first hard turn-off loss calculation model and the second hard turn-off loss calculation model comprises: combining the first hard turn-off loss calculation model and the second hard turn-off loss calculation model to obtain the hard turn-off loss calculation model of the calibration device, and the hard turn-off loss calculation model is: wherein is the hard-off loss of the device under calibration, is the hard-off loss of the device under calibration during the voltage rise period, is the hard-off loss of the device under calibration during the current fall period.

5. The method of SiC MOSFET hard switching loss calculation for TNPC circuit according to any one of claims 1 to 4, characterized in that, The hard turn-on period is composed of a current rising period and a voltage falling period, and the step of determining a hard turn-on loss calculation model of the calibration device in the hard turn-on period according to the turn-on voltage characteristic parameter comprises: determining a first hard turn-on loss calculation model of the calibration device in the current rising period according to the turn-on voltage characteristic parameter; determining a second hard turn-on loss calculation model of the calibration device in the voltage falling period according to the turn-on voltage characteristic parameter; determining a hard turn-on loss calculation model of the calibration device according to the first hard turn-on loss calculation model and the second hard turn-on loss calculation model.

6. The method of SiC MOSFET hard switching loss calculation for TNPC circuit of claim 5, wherein, The current rising period is composed of the moment when the voltage of the calibration device starts to fall to the moment when the current of the calibration device rises to the load current, and the step of determining a first hard turn-on loss calculation model of the calibration device in the current rising period according to the turn-on voltage characteristic parameter comprises: calculating a deviation between the moment when the current rises to the load current and the moment when the voltage starts to fall to obtain the length of the current rising period; determining a voltage value of the calibration device at the moment when the voltage starts to fall and a voltage value of the calibration device at the moment when the current rises to the load current according to the turn-on voltage characteristic parameter; A first hard turn-on loss calculation model of the calibration device in the current rising period is determined by a voltage value of the calibration device at the voltage start dropping moment, a voltage value of the calibration device at the current rising to load current moment, and a length of the current rising period, and the first hard turn-on loss calculation model is: wherein, is the voltage value at the moment when the voltage starts to decrease, is the voltage value at the moment when the voltage starts to decrease, is the voltage value at the moment when the current rises to the load current, is the load current value, is the duration of the current rise period.

7. The method of SiC MOSFET hard switching loss calculation for TNPC circuit of claim 6, wherein, The voltage dropping period is composed of the current rising to load current moment to the voltage of the calibration device dropping to zero moment, and the step of determining a second hard turn-on loss calculation model of the calibration device in the voltage dropping period according to the turn-on voltage characteristic parameter includes: calculating a deviation between the voltage dropping to zero moment and the current rising to load current moment to obtain the length of the voltage dropping period; determining a charge amount of the junction capacitor charging and discharging of a normally-off SiC MOSFET other than the calibration device in the TNPC circuit in the voltage dropping period, the normally-off SiC MOSFET being a SiC MOSFET with a channel in a closed state in the hard turn-off period and the hard turn-on period; determining a voltage value of the calibration device at the current rising to load current moment according to the turn-on voltage characteristic parameter; determining a second hard turn-on loss calculation model of the calibration device in the voltage dropping period by the charge amount of the junction capacitor charging and discharging, the voltage value of the calibration device at the current rising to load current moment, and the length of the voltage dropping period, and the second hard turn-on loss calculation model is: wherein, is the hard turn-on loss of the device during the voltage falling period, is the amount of charge of the junction capacitance of the off-state SiC MOSFET outside the device during the voltage falling period, is the voltage value of the device at the moment when the current rises to the load current, is the load current value, is the duration of the voltage falling period; The step of determining a hard turn-on loss calculation model of the calibration device according to the first hard turn-on loss calculation model and the second hard turn-on loss calculation model includes: combining the first hard turn-on loss calculation model and the second hard turn-on loss calculation model to obtain the hard turn-on loss calculation model of the calibration device, and the hard turn-on loss calculation model is: wherein is the hard turn-on loss of the device under calibration, is the hard turn-on loss of the device under calibration during the current rise period, is the hard turn-on loss of the device under calibration during the voltage fall period.

8. A test device, characterized by The test device is connected with the TNPC circuit, and the test device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the SiC MOSFET hard switching loss calculation method of the TNPC circuit according to any one of claims 1 to 7.

9. The test device of claim 8, wherein, The TNPC circuit includes a power supply, a first direct current capacitor, a second direct current capacitor, a load, and a plurality of SiC MOSFETs, including a first SiC MOSFET, a second SiC MOSFET, a third SiC MOSFET, and a fourth SiC MOSFET; The drain of the first SiC MOSFET is connected with the positive electrode of the power supply and the first end of the first direct current capacitor, respectively, and the source of the first SiC MOSFET is connected with the drain of the third SiC MOSFET, the drain of the fourth SiC MOSFET, and the load, respectively; The source of the third SiC MOSFET is connected with the source of the second SiC MOSFET, and the drain of the second SiC MOSFET is connected with the second end of the first direct current capacitor and the first end of the second direct current capacitor respectively; The source of the fourth SiC MOSFET is connected with the second end of the second direct current capacitor and the negative electrode of the power supply respectively; The gate of the first SiC MOSFET, the gate of the second SiC MOSFET, the gate of the third SiC MOSFET and the gate of the fourth SiC MOSFET are connected with the testing device.

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