Anti-radiation DICE flip-flop based on dual-mode redundancy and adaptive bias

Abstract

The application relates to an anti-radiation DICE trigger circuit based on dual-mode redundancy and adaptive biasing, which is designed with dual-mode redundancy at the circuit level for reset or set circuit, and further proposes an adaptive biasing technology on the basis of the dual-mode redundancy design, and the trigger is reinforced at the circuit design level, helps solve the problem that a traditional DICE trigger reset / set signal is sensitive to SET pulses, and significantly improves the reliability of the trigger in an extreme radiation environment. And the circuit can perceive that it is disturbed by radiation, and immediately make a local and slight adjustment to accelerate recovery, instead of completely passively relying on the self-recovery capability. And the error pulse (Error) generated is a valuable diagnostic signal, which can be used by the system top layer to record the soft error occurrence rate, locate the sensitive unit, and realize predictive health management.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and relates to an anti-radiation DICE flip-flop based on dual-mode redundancy and adaptive bias. BACKGROUND

[0002] As a core storage component of space electronic systems, the reliability of static random access memory (SRAM) directly determines the safe operation of the spacecraft. High-energy particles (such as protons and heavy ions) in the space radiation environment can cause single event effects (SEE: the essence is the ionization interaction of high-energy particles and semiconductor materials), among which single event upset (SEU: the data in the storage unit or latch is flipped due to the incident particles) can cause the unexpected flipping of the logic state of the SRAM storage unit, and further cause system function abnormalities or even failures.

[0003] To improve the anti-SEU capability of SRAM, in the circuit-level hardening scheme, the dual interlocked storage unit (DICE) flip-flop has become a research hotspot in the field of anti-radiation storage technology due to its symmetrical structure and relatively simple device quantity. However, a large number of experiments and simulation results on resettable DICE structure flip-flops show that when heavy ions are incident into the reset circuit of the flip-flop, the originally cut-off reset signal may be momentarily turned on. This causes the flip-flop state to be "incorrectly" reset to a low level, ultimately triggering the SEU effect of the flip-flop. At the same time, the same problem exists in flip-flops with a set bit and flip-flops with both reset and set bits; in addition, although the existing improved DICE flip-flops (such as DICE-FF+DSET, HF-FF, SEDR-FF, etc.) can improve the anti-radiation capability, they generally have problems such as large area overhead (such as MSFF-MC, which has an area of 4.2 times that of the traditional DICE), high power consumption (such as SETTOFF, which has a power consumption of 2.4 times that of the traditional DICE), or significant increase in delay (such as DAD-FF, which has a delay increase of 47%), making it difficult to meet the dual requirements of high performance and high reliability of space electronic equipment.

[0004] Therefore, there is an urgent need for a flip-flop design scheme that can significantly improve the anti-SEU capability while ensuring low area, low power consumption, and low delay. SUMMARY

[0005] In view of the problems existing in the above-mentioned traditional method, the application proposes an anti-radiation DICE flip-flop based on dual-mode redundancy and adaptive bias, which can solve the problem of the reset / set signal of the traditional DICE flip-flop being sensitive to SET pulses, and significantly improve the reliability of the flip-flop in extreme radiation environments.

[0006] To achieve the above-mentioned purpose, the embodiments of the application adopt the following technical solutions:

[0007] A kind of anti-radiation DICE trigger circuit based on dual-mode redundancy and adaptive biasing, comprising:

[0008] Dual-mode redundancy unit, for two independent and identical redundant paths are adopted to input external control signal, generate two internal control signals;Two internal control signals are jointly connected to the corresponding input end of DICE latch unit;External control signal is external reset signal or external set signal;Corresponding internal control signal is internal reset signal or internal set signal.

[0009] Adaptive biasing unit, for real-time monitoring the logic state consistency of two internal control signals, output Error signal;If the first internal control signal is generated by the redundant path of reinforcement, according to Error signal and the second internal control signal, control signal Ctrl_P is generated after being processed by NAND logic;Error signal is inverted after being processed by NAND logic with the second internal control signal, and control signal Ctrl_N is generated;According to control signal Ctrl_P and control signal Ctrl_N, input external control signal is repaired to the correct direction by auxiliary transistor;Wherein, when two internal control signals are same, Error signal is low;When particle bombardment causes transient pulse in any redundant path and makes two internal control signals inconsistent, Error signal is high.

[0010] DICE latch unit, for realizing stable storage of input signal, can tolerate single node transient disturbance, and keep storage state unchanged.

[0011] In one embodiment, the dual-mode redundancy unit includes two completely independent and identical redundant paths;Wherein the redundant path is composed of a PMOS tube and an NMOS tube inverter circuit.

[0012] The input end of two redundant paths is connected with the corresponding input end of DICE latch unit;The output end of the first redundant path is connected with one input end of adaptive biasing unit and the output end of adaptive biasing unit;The output end of the second redundant path is connected with the input end of adaptive biasing unit.

[0013] In one embodiment, the adaptive biasing unit includes: inconsistency detection module, intelligent control logic module and auxiliary biasing module.

[0014] Inconsistency detection module, for real-time monitoring the logic state consistency of two internal control signals by using XOR gate, output Error signal.

[0015] The intelligent control logic module is configured to generate a control signal Ctrl_P by an AND gate according to the Error signal and a second internal control signal, and generate a control signal Ctrl_N by an OR gate according to the Error signal and the second internal control signal.

[0016] The auxiliary biasing module is connected in parallel with the first redundant path, and includes a serial connection of an auxiliary PMOS transistor and an auxiliary NMOS transistor. The serial connection point of the auxiliary PMOS transistor and the auxiliary NMOS transistor is connected to an output terminal of the first redundant path. The auxiliary biasing module is configured to control the auxiliary PMOS transistor and the auxiliary NMOS transistor to repair the external input signal in a correct direction according to the control signal Ctrl_P and the control signal Ctrl_N, respectively.

[0017] In an embodiment, the inconsistency detection module includes an XOR gate.

[0018] The two input terminals of the XOR gate are respectively connected to output terminals of the two redundant paths. The output terminal of the XOR gate is connected to an input terminal of the intelligent control logic module.

[0019] In an embodiment, the intelligent control logic module includes an AND gate, an inverter, and an OR gate.

[0020] The two input terminals of the AND gate are respectively connected to an output terminal of the inconsistency detection module and an output terminal of the second redundant path. The output terminal of the AND gate is connected to a gate of the auxiliary PMOS transistor of the auxiliary biasing module.

[0021] The input terminal of the inverter is connected to the output terminal of the inconsistency detection module. The output terminal of the inverter is connected to one input terminal of the OR gate. The other input terminal of the OR gate is connected to the output terminal of the second redundant path. The output terminal of the OR gate is connected to a gate of the auxiliary NMOS transistor of the auxiliary biasing module.

[0022] The above technical solution has the following advantages and beneficial effects:

[0023] The above anti-radiation DICE flip-flop circuit based on dual-mode redundancy and adaptive biasing has the following advantages and beneficial effects: The above anti-radiation DICE flip-flop circuit based on dual-mode redundancy and adaptive biasing has the following advantages and beneficial effects: The circuit is designed with dual-mode redundancy at the circuit level for the reset or set circuit, and further proposes an adaptive biasing technology on the basis of the dual-mode redundancy design. The flip-flop is reinforced at the circuit design level, which helps to solve the problem that the traditional DICE flip-flop reset / set signal is sensitive to SET pulses, significantly improves the reliability of the flip-flop in an extreme radiation environment, and enables the circuit to perceive that it has been disturbed by radiation and immediately make a local and minor adjustment to accelerate recovery, rather than passively relying on self-recovery capability. The error pulse (Error) generated is a valuable diagnostic signal, which can be used by the system top layer to record the soft error rate, locate sensitive units, and achieve predictive health management. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a radiation-resistant DICE trigger circuit based on dual-mode redundancy and adaptive bias in one embodiment.

[0026] Figure 2 This is a schematic diagram of a DICE trigger circuit in the prior art.

[0027] Figure 3 This is a schematic diagram of a DICE trigger circuit in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0030] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0031] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] In one embodiment, such as Figure 1As shown, a radiation-hardened DICE flip-flop circuit based on dual-mode redundancy and adaptive biasing is provided, comprising a DICE latch unit 10, a dual-mode redundancy unit 20, and an adaptive biasing unit 30.

[0033] The dual-mode redundancy unit 20 is configured to generate two internal control signals by adopting two completely independent and identical redundancy paths for an input external control signal, and to input the two internal control signals into corresponding input terminals of the DICE latch unit 10; the external control signal is an external reset signal or an external set signal; and the corresponding internal control signal is an internal reset signal or an internal set signal.

[0034] Specifically, the external control signal is taken as an external reset signal as an example for illustration.

[0035] The present application completely reengineers the reset input path of the conventional DICE flip-flop. Figure 2 In the conventional DICE flip-flop, the reset signal R is generated by an input reset signal RD through an inverter; as shown in FIG. 1. Figure 3 As shown, the input reset signal RD is no longer directly generated into a reset signal, but through two completely independent and identical redundancy paths for generating the reset signal. Redundancy path 1: receiving the input external reset signal RD, and generating an internal reset signal R1 through an inverter. Redundancy path 2: also receiving the input external reset signal RD, and generating an internal reset signal R2 through another independent inverter. The two redundancy paths are completely symmetrical in circuit structure, and the device size and load are completely matched. The internal reset signals R1 and R2 are jointly input into the subsequent DICE latch unit.

[0036] The adaptive biasing unit 30 is configured to monitor the logic state consistency of the two internal control signals in real time, and output an Error signal; when the redundancy path for generating the first internal control signal is to be hardened, a control signal Ctrl_P is generated by performing NAND logic processing on the Error signal and the second internal control signal; a control signal Ctrl_N is generated by performing NOR logic processing on the Error signal through an inverter and the second internal control signal; the input external control signal is repaired in the correct direction through an auxiliary transistor according to the control signal Ctrl_P and the control signal Ctrl_N; wherein, when the two internal control signals are the same, the Error signal is low; and when particle bombardment causes transient pulses in any redundancy path and makes the two internal control signals inconsistent, the Error signal is a high-level pulse.

[0037] Specifically, the application further introduces adaptive biasing technology on the basis of dual-mode redundancy. Adaptive biasing is a dynamic and intelligent circuit technology that can detect abnormal state of a circuit node (such as a transient pulse caused by radiation) in real time and automatically apply a temporary and directionally correct compensation current to accelerate the recovery of the node voltage to the normal logic level, thereby suppressing the propagation of error pulses and realizing the upgrade from "passive protection" to "active response". Taking the inverter on the internal reset signal R1 path as an example, the path for generating internal reset signals R1 and R2 from the input external reset signal RD through two inverters is modified as shown in the figure. Figure 1

[0038] Figure 1 The figure is the principle diagram of reinforcing the first path, and if the second path is reinforced, the Error signal and the first internal control signal are connected according to the adaptive biasing circuit.

[0039] The DICE latch unit 10 is used to realize stable storage of the input signal and can keep the storage state unchanged when a single node is subjected to transient disturbance.

[0040] Specifically, the DICE latch itself has the characteristics that when only one internal node is subjected to state change due to disturbance, the redundant node can restore it to the correct state through cross feedback mechanism. The reinforcement principle is that when a high-energy particle is incident on the drain of the PMOS tube of one of the redundant paths (for example, redundant path 1) and generates a SET pulse, only the abnormal pulse will appear on the internal reset signal R1, and the internal reset signal R2 remains stable. The abnormal internal reset signal R1 pulse will try to reset the latch, which may cause the voltage of a node (such as node D7) in the latch to change transiently. However, due to the presence of another correct internal reset signal R2 and the self-restoration capability of the internal node of the DICE structure, this local and single-point disturbance will be quickly corrected and will not propagate to the output end Q, thereby ensuring the stability of the flip-flop storage state. Only when both the redundant paths for generating the internal reset signals R1 and R2 are hit by particles and generate SET pulses, the reinforcement will fail, and the probability of this is very low. Compared with the single reset input path of the resettable DICE flip-flop, the probability of data flip caused by SET effect has been greatly reduced.

[0041] ​The above anti-radiation DICE trigger circuit based on dual-mode redundancy and adaptive biasing has a dual-mode redundancy design at the circuit level for the reset or set circuit, and further proposes an adaptive biasing technology on the basis of the dual-mode redundancy design, which reinforces the trigger at the circuit design level, helps to solve the problem that the traditional DICE trigger reset / set signal is sensitive to SET pulses, and significantly improves the reliability of the trigger in an extreme radiation environment. And it can make the circuit perceive that it has been disturbed by radiation, and immediately make local and minor adjustments to speed up recovery, rather than completely passively rely on self-recovery capability. And the error pulse (Error) generated is a valuable diagnostic signal, which can be used by the system top to record soft error rate, locate sensitive units, and achieve predictive health management.

[0042] In one embodiment, the dual-mode redundancy unit 20 includes two completely independent and identical redundancy paths; wherein the redundancy path is composed of an inverter circuit of a PMOS tube and an NMOS tube.

[0043] The input ends of the two redundancy paths are connected with the corresponding input ends of the DICE latch unit 10; the output end of the first redundancy path is connected with an input end of the adaptive biasing unit 30 and the output end of the adaptive biasing unit 30; the output end of the second redundancy path is connected with the input end of the adaptive biasing unit 30.

[0044] In one embodiment, the adaptive biasing unit 30 includes an inconsistency detection module, an intelligent control logic module, and an auxiliary biasing module.

[0045] The inconsistency detection module is used to monitor the logic state consistency of the two internal control signals in real time by using an XOR gate, and outputs an Error signal.

[0046] The intelligent control logic module is used to generate a control signal Ctrl_P by an AND gate according to the Error signal and the second internal control signal; and generate a control signal Ctrl_N by an OR gate after the Error signal is inverted and the second internal control signal is processed.

[0047] The auxiliary biasing module is connected in parallel with the first redundancy path, and includes a series connection of an auxiliary PMOS tube and an auxiliary NMOS tube, and the series connection point of the auxiliary PMOS tube and the auxiliary NMOS tube is connected with the output end of the first redundancy path; and is used to control the auxiliary PMOS tube and the auxiliary NMOS tube to repair the external input signal to the correct direction according to the control signal Ctrl_P and the control signal Ctrl_N respectively.

[0048] Specifically, the auxiliary biasing module includes an auxiliary PMOS transistor (P_extra) and an auxiliary NMOS transistor (N_extra) connected in parallel at the output node of the first redundant path, and the auxiliary PMOS transistor and the auxiliary NMOS transistor are connected in series. The source of the P_extra is connected to a power supply voltage, the drain of the P_extra is connected to the output end of the first redundant path (the node outputting the internal reset signal R1 of the first redundant path), and the gate of the P_extra is controlled by a control signal Ctrl_P. When the control signal Ctrl_P is low (0), the P_extra is turned on to provide an additional pull-up current. The source of the N_extra is connected to a ground, the drain of the N_extra is connected to the output end of the first redundant path (the node outputting the internal reset signal R1 of the first redundant path), and the gate of the N_extra is controlled by a control signal Ctrl_N. When the control signal Ctrl_N is high (1), the N_extra is turned on to provide an additional pull-down current.

[0049] The adaptive biasing technique uses pulses (Ctrl_N, Ctrl_P) to temporarily increase the drive current of the transistors in the affected path. This can accelerate the recovery process of the disturbed node, further shorten the width of the possible glitch, and thus reduce the probability of its impact on the subsequent circuit. This design makes the circuit no longer passively wait for recovery, but actively intervene, shortens the duration of the error state, and reduces the sensitive time window. Moreover, the pulse signal (Error) can be output to the top-level error management unit for error counting and recording, providing more fine-grained data for system health management. The inverter on the path generating the internal reset signal R2 is hardened in a completely symmetrical structure.

[0050] In one embodiment, the inconsistency detection module includes an XOR gate; two inputs of the XOR gate are connected to the output ends of the two redundant paths, respectively; and an output of the XOR gate is connected to an input of the intelligent control logic module.

[0051] Specifically, the inconsistency detection module is composed of an XOR gate, and two input ends of the XOR gate receive the output internal reset signals R1 and R2 of the two redundant reset paths, respectively. Function: Real-time monitoring of the logic state consistency of the internal reset signals R1 and R2; output low (0) when the two signal states are the same; output a high level pulse (Error) when particle bombardment causes transient pulses in any path and makes the signal states inconsistent.

[0052] In one embodiment, the intelligent control logic module includes an NAND gate, an inverter, and an NOR gate; two inputs of the NAND gate are connected to the output end of the inconsistency detection module and the output end of the second redundant path, respectively; and the output end of the NAND gate is connected to the gate of the auxiliary PMOS transistor of the auxiliary biasing module.

[0053] The input of the inverter is connected to the output of the inconsistency detection module. The output of the inverter is connected to one input of the NOR gate. The other input of the NOR gate is connected to the output of the second redundant path. The output of the NOR gate is connected to the gate of the auxiliary NMOS transistor of the auxiliary bias module.

[0054] Specifically, such as Figure 1 As shown, the NAND gate receives the Error signal and the internal reset signal R2, generating the control signal Ctrl_P for the auxiliary PMOS transistor. The logical relationship is: Ctrl_P = !(Error&R2), that is, Error and R2 are ANDed and then NOTed. Error is inverterized to generate !Error, which is then combined with R2 through a circuit consisting of two PMOS transistors connected in series to generate the control signal Ctrl_N for the auxiliary NMOS transistor. The logical relationship is: Ctrl_N = Error&(!R2). This design ensures that the auxiliary transistor is activated only when an error is detected and recovery in a specific direction is required.

[0055] The working process of the anti-radiation DICE trigger circuit based on dual-mode redundancy and adaptive bias, taking the reset circuit as an example: When the internal reset signal R1 is disturbed and its level flips: If the correct internal reset signal R2=1 (high level), it means that the disturbed node should also be at a high level. At this time, the control logic will only activate the auxiliary PMOS transistor (P_extra). When the PMOS transistor is turned on, it will inject the power supply current into the disturbed node, pulling its voltage towards the high level (1); If the correct internal reset signal R2=0 (low level), it means that the disturbed node should also be at a low level. At this time, the control logic will only activate the auxiliary NMOS transistor (N_extra). When the NMOS transistor is turned on, it will provide a discharge path to ground for the disturbed node, pulling its voltage towards the low level (0).

[0056] It is worth noting that the trigger in the radiation-resistant DICE trigger circuit based on dual-mode redundancy and adaptive bias proposed in this application can be not only a reset trigger, but also a set trigger and a trigger that can be set and reset at the same time.

[0057] The specific implementation scheme of the anti-radiation DICE trigger circuit based on dual-mode redundancy and adaptive bias is applied to a trigger with both setting and resetting: for the trigger with both setting and resetting functions, two independent and functionally symmetrical control paths are contained inside: a reset control path and a set control path. The technical solution of the present application needs to independently and completely reinforce the two paths. Reset path reinforcement: the external input reset signal RD is divided into two completely independent internal reset signals R1 and R2 (the specific implementation is the same as described above). Set path reinforcement: the external input set signal SD is also divided into two completely independent internal set signals S1 and S2. The circuit redundancy structure and the connection mode with the DICE latch unit are completely the same as and symmetrical with the implementation scheme of the internal reset signal R1 / R2 path; application of adaptive bias technology: adaptive bias technology also needs to be independently applied to the two control paths. Reset path adaptive bias: a set of inconsistent detection and intelligent response circuits is established for internal reset signals R1 and R2 (with internal reset signal R2 as the correct reference, the path generating internal reset signal R1 is corrected). Set path adaptive bias: similarly, another set of independent and completely symmetrical inconsistent detection and intelligent response circuits is established for internal set signals S1 and S2 (with internal set signal S2 as the correct reference, the path generating internal set signal S1 is corrected). The two adaptive bias circuits work in parallel and do not interfere with each other, and respectively guarantee the reliability of their own signal paths.

[0058] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present disclosure.

[0059] The above embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be pointed out that for ordinary skilled persons in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the protection scope of the present application.

Claims

1. A radiation-resistant DICE trigger circuit based on dual-mode redundancy and adaptive bias, characterized in that, include: The dual-mode redundancy unit is used to generate two internal control signals by using two independent and identical redundant paths for the input external control signal; the two internal control signals are connected to the corresponding input terminals of the DICE latch unit; the external control signal is an external reset signal or an external set signal; the corresponding internal control signal is an internal reset signal or an internal set signal. An adaptive bias unit is used to monitor the consistency of the logic states of two internal control signals in real time and output an Error signal. If a redundant path for the first internal control signal is reinforced, a control signal Ctrl_P is generated after AND-NOT logic processing based on the Error signal and the second internal control signal. The Error signal is then passed through an inverter and combined with the second internal control signal through OR-NOT logic processing to generate a control signal Ctrl_N. Based on the control signals Ctrl_P and Ctrl_N, an auxiliary transistor is used to correct the input external control signal. When the two internal control signals are the same, the Error signal is low; when particle bombardment causes a transient pulse in any redundant path, resulting in inconsistent states of the two internal control signals, the Error signal is high. The DICE latch unit is used to achieve stable storage of input signals and can maintain the stored state while tolerating transient disturbances of a single node.

2. The radiation-resistant DICE trigger circuit based on dual-mode redundancy and adaptive bias according to claim 1, characterized in that, The dual-mode redundancy unit includes two completely independent and identical redundant paths; wherein the redundant path is an inverter circuit composed of a PMOS transistor and an NMOS transistor. The input terminals of the two redundant paths are connected to the corresponding input terminals of the DICE latch unit; the output terminal of the first redundant path is connected to one input terminal of the adaptive bias unit and the output terminal of the adaptive bias unit; the output terminal of the second redundant path is connected to the input terminal of the adaptive bias unit.

3. The radiation-resistant DICE trigger circuit based on dual-mode redundancy and adaptive bias according to claim 1, characterized in that, The adaptive bias unit includes: an inconsistency detection module, an intelligent control logic module, and an auxiliary bias module; The inconsistency detection module is used to monitor the consistency of the logical states of the two internal control signals in real time using an XOR gate and output an Error signal. The intelligent control logic module is used to generate a control signal Ctrl_P by passing the Error signal and the second internal control signal through a NAND gate; and to generate a control signal Ctrl_N by passing the Error signal through an inverter and then passing it through a NOR logic with the second internal control signal. The auxiliary bias module is connected in parallel with the first redundant path and includes an auxiliary PMOS transistor and an auxiliary NMOS transistor connected in series. The series connection point of the auxiliary PMOS transistor and the auxiliary NMOS transistor is connected to the output terminal of the first redundant path. It is used to control the auxiliary PMOS transistor and the auxiliary NMOS transistor to correct the external control signal in the correct direction according to the control signal Ctrl_P and the control signal Ctrl_N, respectively.

4. The radiation-resistant DICE trigger circuit based on dual-mode redundancy and adaptive bias according to claim 3, characterized in that, The inconsistency detection module includes an XOR gate; The two inputs of the XOR gate are connected to the outputs of the two redundant paths, respectively; the output of the XOR gate is connected to the input of the intelligent control logic module.

5. The radiation-resistant DICE trigger circuit based on dual-mode redundancy and adaptive bias according to claim 3, characterized in that, The intelligent control logic module includes a NAND gate, an inverter, and a NOR gate; The two input terminals of the NAND gate are connected to the output terminal of the inconsistency detection module and the output terminal of the second redundant path, respectively, and the output terminal of the NAND gate is connected to the gate of the auxiliary PMOS transistor of the auxiliary bias module. The input terminal of the inverter is connected to the output terminal of the inconsistency detection module, the output terminal of the inverter is connected to one input terminal of the NOR gate, the other input terminal of the NOR gate is connected to the output terminal of the second redundant path, and the output terminal of the NOR gate is connected to the gate of the auxiliary NMOS transistor of the auxiliary bias module.

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