Low-distortion pulse generator

Abstract

The application provides a low-distortion pulse generator, comprising: a transistor MP1, the S pole of the transistor MP1 is used for connecting a high-voltage power supply end, and the D pole is used for connecting a transducer; a first level converter, which is used for driving the G pole of the transistor MP1 to realize the application of a voltage pulse with a rising edge to the transducer; a transistor MN1, the S pole of the transistor MN1 is used for grounding, and the D pole is used for connecting the transducer; a second level converter, which is used for driving the G pole of the transistor MN1 to realize the application of a voltage pulse with a falling edge to the transducer; and a level converter, which is used for adjusting the voltage difference VGS between the gate and the source of the transistor to realize the time adjustment of the rising edge or the falling edge of the voltage pulse. The application adjusts the voltage difference VGS between the gate and the source of the transistor through the level converter to realize the time adjustment of the rising edge or the falling edge of the voltage pulse, thereby adjusting the size of the different edge rates and reducing the waveform distortion.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of medical ultrasound imaging, in particular, to a low-distortion pulse generator. BACKGROUND

[0002] In the field of ultrasound imaging, ultrasound harmonic imaging (UHI) is an ultrasound imaging technique based on the principle of nonlinear acoustics. By receiving the harmonic signals generated by the tissue or contrast agent (usually multiples of the frequency of the incident ultrasound wave), a higher quality image is provided.

[0003] Considering the imaging advantages brought by harmonic imaging, mainstream ultrasound imaging systems will support the function of harmonic imaging. These imaging systems will be connected to a one-dimensional array using a long wire, usually 8 to 128 array elements. The transmitter is usually integrated in the host of the ultrasound imaging, so it can provide sufficient area and power consumption. However, in a large-scale two-dimensional transducer array, the number of transducer elements usually exceeds one thousand or even ten thousand, and each transducer element needs a corresponding transmitter driver. Therefore, the area and power consumption are very limited, and how to realize a low-distortion transmitter under the limitation of limited area and power consumption is a great challenge. In addition, due to the process deviation in the semiconductor process manufacturing process and the temperature change in the chip working process, the performance of the transmitters in different channels will be different, thereby affecting the final imaging quality.

[0004] The core of ultrasound harmonic imaging is to receive the harmonic signals generated by the target medium (such as tissue or contrast agent), rather than the harmonic signals from the transmitter itself. If the transmitter circuit introduces too much nonlinear distortion when generating the fundamental wave signal, these pseudo-harmonic signals will mix into the received signal, reducing the image quality. Therefore, there is an urgent need for a low-distortion transmitter circuit. SUMMARY

[0005] In view of the defects in the prior art, the purpose of the present application is to provide a low-distortion pulse generator.

[0006] The low-distortion pulse generator provided by the present application comprises:

[0007] A transistor MP1, the S pole of the transistor MP1 is used to connect a high-voltage power supply end, and the D pole is used to connect a transducer;

[0008] A first level converter is used to drive the G pole of the transistor MP1 to apply a voltage pulse with a rising edge to the transducer;

[0009] A transistor MN1, the S pole of the transistor MN1 is used to ground, and the D pole is used to connect a transducer;

[0010] a second level converter for driving the G terminal of the transistor MN1 to achieve a voltage pulse with a falling edge applied to the transducer;

[0011] the level converter is configured to adjust the voltage difference VGS between the G and S terminals of the transistor to achieve a time adjustment of the rising edge or the falling edge of the voltage pulse.

[0012] Preferably, further comprising:

[0013] a transistor MN2, the S terminal of which is configured to be connected to a low-voltage power supply terminal, and the D terminal of which is configured to be connected to the transducer;

[0014] a third level converter for driving the G terminal of the transistor MN2 to achieve a voltage pulse with a falling edge applied to the transducer;

[0015] a transistor MP2, the S terminal of which is configured to be connected to ground, and the D terminal of which is configured to be connected to the transducer;

[0016] a fourth level converter for driving the G terminal of the transistor MP2 to achieve a voltage pulse with a rising edge applied to the transducer.

[0017] Preferably, further comprising:

[0018] a diode D1, the positive terminal of which is configured to be connected to the transducer, and the negative terminal of which is configured to be connected to the D terminal of the transistor MN1;

[0019] a diode D2, the negative terminal of which is configured to be connected to the transducer, and the positive terminal of which is configured to be connected to the D terminal of the transistor MP2.

[0020] Preferably, the first level converter comprises:

[0021] an adjustable current source ITRIM1;

[0022] a first two-stage current mirror configured to amplify the current generated by the adjustable current source ITRIM1 by a factor of X1;

[0023] a resistor R3 configured to perform a voltage drop on the amplified current to serve as the VGS of the transistor MP1, VGS being the voltage difference between the G and S terminals.

[0024] Preferably, the first level converter comprises:

[0025] a current source ITRIM1 configured to output a current of a first value;

[0026] a current mirror transistor MN3, the S terminal of which is configured to be connected to a high-voltage source, and the G terminal of which is connected to the D terminal;

[0027] a current mirror transistor

[0028] a current mirror transistor MN4, an S pole of the current mirror transistor MN4 is used for connecting a high voltage source, a G pole is connected to a G pole of a current mirror transistor MN3;

[0029] a current mirror transistor MP3, an S pole of the current mirror transistor MP3 is used for grounding, a D pole is connected to a D pole of the current mirror transistor MN4, a G pole is connected to a D pole;

[0030] a current mirror transistor MP5, an S pole of the current mirror transistor MP5 is used for grounding, a G pole is connected to a G pole of the current mirror transistor MP3;

[0031] a resistor R3, one end of the resistor R3 is used for connecting a high voltage source, the other end is connected to an output port Vout,

[0032] a voltage stabilizing diode D3, which is connected in parallel with the resistor R3;

[0033] a transistor MP4, an S pole of the transistor MP4 is connected to a D pole of the current mirror transistor MP5, a G pole is connected to an input port Vin, a D pole is connected to the other end of the resistor R3;

[0034] a transistor MP6, an S pole of the transistor MP6 is used for grounding, a D pole is connected to an S pole of the transistor MP4;

[0035] a NAND gate, an output end of the NAND gate is connected to a G pole of the transistor MP6, a first input end is used for inputting a TRIM_EN signal, another input end is used for inputting Vin.

[0036] Preferably, the second level shifter comprises:

[0037] an adjustable current source ITRIM2;

[0038] a second two-stage current mirror, used for amplifying a current generated by the adjustable current source ITRIM2 by X2 times;

[0039] a resistor R4, used for voltage drop of the amplified current, as a VGS of the transistor MN1, VGS is a voltage difference between a G pole and an S pole.

[0040] Preferably, the second level shifter comprises:

[0041] a current source ITRIM2, configured to output a current of a second value;

[0042] a current mirror transistor MN5, an S pole of the current mirror transistor MN5 is used for connecting a high voltage source, a G pole is connected to a D pole;

[0043] a current mirror transistor MN6, an S pole of the current mirror transistor MN6 is used for connecting a high voltage source, a G pole is connected to a G pole of a current mirror transistor MN5;

[0044] a current mirror transistor MP7, an S pole of the current mirror transistor MP7 is used for grounding, a D pole is connected to a D pole of the current mirror transistor MN6, a G pole is connected to a D pole;

[0045] a current mirror transistor MP8, an S pole of the current mirror transistor MP8 is used for grounding, a G pole is connected to a G pole of the current mirror transistor MP7;

[0046] a resistance R4, one end of the resistance R4 is used for connecting a high voltage source, the other end is connected to a D pole of the current mirror transistor MP8;

[0047] a transistor MN7, an S pole of the transistor MN7 is connected to a high voltage source, a G pole is used for inputting a TRIM_EN signal, a D pole is connected to the other end of the resistance R4;

[0048] an inverter, an input end of the inverter is used for receiving a signal Vin, an output end of the inverter is used for outputting a signal Vout, a positive pole of a power supply end of the inverter is connected to the other end of the resistance R4, a negative pole of the power supply end of the inverter is grounded.

[0049] Preferably, the first level shifter comprises a constant current circuit; the constant current circuit comprises:

[0050] a resistance voltage dividing network for generating a reference voltage;

[0051] an operational amplifier for making a voltage across a resistance R0 equal to the reference voltage through negative feedback, forming a constant current I;

[0052] a third two-stage current mirror for amplifying the constant current I by X3 times and providing the resistance R3 of the first level shifter.

[0053] Preferably, the constant current circuit comprises:

[0054] a resistance R1, one end of the resistance R1 is connected to a high voltage source;

[0055] a resistance R2, one end of the resistance R2 is connected to the other end of the resistance R1;

[0056] an operational amplifier; a positive input end of the operational amplifier is connected to the other end of the resistance R1;

[0057] a resistance R0, one end of the resistance R0 is connected to an inverting input end of the operational amplifier, the other end of the resistance R0 is grounded;

[0058] a current mirror transistor MN8, an S pole of the current mirror transistor MN8 is used for connecting a high voltage source, a G pole is connected to a D pole;

[0059] a current mirror transistor MN9, an S pole of the current mirror transistor MN9 is connected with a D pole of the current mirror transistor MN9, and a G pole is connected with the D pole;

[0060] a transistor MP14, an S pole of the transistor MP14 is connected with one end of a resistor R0, a G pole is connected with an output end of an operational amplifier, and a D pole is connected with the D pole of the current mirror transistor MN9;

[0061] a current mirror transistor MN10, an S pole of the current mirror transistor MN10 is used for connecting a high-voltage source, and a G pole is connected with the G pole of the current mirror transistor MN8;

[0062] a current mirror transistor MN11, an S pole of the current mirror transistor MN11 is connected with the D pole of the current mirror transistor MN10, and a G pole is connected with the G pole of the current mirror transistor MN9;

[0063] a current mirror transistor MP9, a D pole of the current mirror transistor MP9 is connected with the D pole of the current mirror transistor MN11, and a G pole is connected with the D pole;

[0064] a current mirror transistor MP10, a D pole of the current mirror transistor MP10 is connected with the S pole of the current mirror transistor MP9, a G pole is connected with the D pole, and an S pole is grounded;

[0065] a current mirror transistor MP12, a G pole of the current mirror transistor MP12 is connected with the G pole of the current mirror transistor MP9;

[0066] a current mirror transistor MP13, a G pole of the current mirror transistor MP13 is connected with the G pole of the current mirror transistor MP10, a D pole is connected with the S pole of the current mirror transistor MP12, and an S pole is grounded.

[0067] Preferably, the first level shifter further comprises:

[0068] a resistor R3, one end of the resistor R3 is used for connecting a high-voltage source, and the other end is connected with an output port Vout,

[0069] a voltage stabilizing diode D3, which is connected with the resistor R3 in parallel;

[0070] a transistor MP11, a D pole of the transistor MP11 is connected with the other end of the resistor R3, an S pole is connected with the D pole of the current mirror transistor MP12, and a G pole is used for receiving a signal Vin.

[0071] Compared with the prior art, the present application has the following beneficial effects:

[0072] The present application adjusts the time of rising edge or falling edge of the voltage pulse by adjusting the voltage difference VGS between the gate and the source of the transistor through the level shifter, thereby adjusting the size of the slew rate of different edges and reducing waveform distortion.

[0073] The present application realizes the high-voltage DMOS switch control voltage independent of temperature and semiconductor process deviation through the current stabilizing circuit, and improves the slew rate adjustment efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings. Other features, objects and advantages of the present application will become more apparent through reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings:

[0075] Figure 1 It is a schematic diagram of ideal three-stage pulse with a period of T in the embodiment of the present application;

[0076] Figure 2 It is a schematic diagram of low-distortion pulse generator in the embodiment of the present application;

[0077] Figure 3 It is a circuit diagram of low-to-high current-regulated level shifter in the embodiment of the present application;

[0078] Figure 4 It is a circuit diagram of low-to-high current-regulated level shifter in the embodiment of the present application;

[0079] Figure 5 It is a circuit diagram of current-regulated level shifter in the embodiment of the present application. DETAILED DESCRIPTION

[0080] The present application will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all belong to the protection scope of the present application.

[0081] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0082] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0083] The technical solutions of the present invention and how they solve the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0084] Figure 1 This is a schematic diagram of an ideal three-stage pulse with a period of T in an embodiment of the present invention, as shown below. Figure 1 As shown, it includes two rising edges and two falling edges. An ideal third-order pulse will not have a second harmonic component. In reality, due to the mismatch between the rising and falling edges, a second harmonic component appears in the pulse, causing waveform distortion.

[0085] Therefore, in order to reduce the second harmonic component and waveform distortion, the high-voltage transmitting circuit needs to match the rising and falling edges of the waveform when generating the transmitting pulse.

[0086] Figure 2 This is a schematic diagram of a low-distortion pulse generator in an embodiment of the present invention, as shown below. Figure 2 As shown, the low-distortion pulse generator provided by the present invention includes:

[0087] Transistor MP1, wherein the source (S) terminal of transistor MP1 is used to connect to the high-voltage power supply terminal, and the drain (D) terminal is used to connect to the transducer;

[0088] The first level shifter is used to drive the gate of transistor MP1 to apply a voltage pulse with a rising edge to the transducer.

[0089] A transistor MN1, whose S pole is used for connecting to ground and D pole is used for connecting to the transducer;

[0090] A second level shifter, used for driving the G pole of the transistor MN1 to realize the voltage pulse with falling edge applied to the transducer;

[0091] The level shifter is used for adjusting the voltage difference VGS between the gate and source of the transistor to realize the time adjustment of the rising edge or the falling edge of the voltage pulse.

[0092] A transistor MN2, whose S pole is used for connecting to the low-voltage power supply end and D pole is used for connecting to the transducer;

[0093] A third level shifter, used for driving the G pole of the transistor MN2 to realize the voltage pulse with falling edge applied to the transducer;

[0094] A transistor MP2, whose S pole is used for connecting to ground and D pole is used for connecting to the transducer;

[0095] A fourth level shifter, used for driving the G pole of the transistor MP2 to realize the voltage pulse with rising edge applied to the transducer;

[0096] A diode D1, whose positive pole is used for connecting to the transducer and negative pole is used for connecting to the D pole of the transistor MN1;

[0097] A diode D2, whose negative pole is used for connecting to the transducer and positive pole is used for connecting to the D pole of the transistor MP2.

[0098] As shown in Figure 2 The transistors MP1, MN1, MN2 and MP2 are field effect transistors DMOS. The four high-voltage DMOS are driven by four level shifters. When the high-voltage DMOS is opened, the transmitting circuit charges and discharges the load to generate Figure 1 the three-stage pulse shown in the figure. The charging and discharging current provided by the DMOS determines the size of the rising and falling time in the pulse.

[0099] When the high-voltage DMOS is opened and works in the saturation region, the current passing through is:

[0100] (1)

[0101] Wherein, W / L is the width to length ratio of the MOS, μ is the electron mobility, Cox is the oxide layer capacitance, VG is the gate voltage, VT is the threshold voltage, VS is the source voltage, and VGS is the voltage difference between the gate and source.

[0102] Where, the electron mobility of DMOS, the oxide layer capacitance Cox and the threshold voltage VT will change with the semiconductor manufacturing process and the chip working temperature. In most cases, the load of the high-voltage transmitting circuit is a capacitor, therefore, the pressure swing rate of the output pulse is:

[0103] (2)

[0104] As can be seen from formula (2), the pressure swing rate of the output pulse can be achieved by adjusting the gate and source voltage difference VGS of DMOS. If the VGS of the four DMOS in the middle can be regulated respectively, then the time of the four rising and falling edges of the output pulse can be matched, and the waveform distortion can be effectively reduced. Figure 2

[0105] Figure 3 The circuit diagram of the low-to-high voltage current-regulated level shifter in the embodiment of the present application is shown in FIG. 1, which comprises: Figure 3

[0106] An adjustable current source ITRIM1;

[0107] A first two-stage current mirror for amplifying the current generated by the adjustable current source ITRIM1 by X1 times;

[0108] A resistor R3 for voltage drop of the amplified current, so as to serve as the VGS of the transistor MP1, which is the voltage difference between the gate and the source.

[0109] In the embodiment of the present application, the first two-stage current mirror first amplifies the current by M times, and then amplifies the current by N times. The value of M is any value between 1 and 5, such as 1. The value of N is any value between 40 and 100, such as 50. The value of X1 is M×N.

[0110] More specifically, the first level shifter comprises:

[0111] A current source ITRIM1 configured to output a current of a first value;

[0112] A current mirror transistor MN3, the S pole of which is configured to be connected to a high-voltage source, and the G pole of which is connected to the D pole;

[0113] A current mirror transistor MN4, the S pole of which is configured to be connected to a high-voltage source, and the G pole of which is connected to the G pole of the current mirror transistor MN3;

[0114] A current mirror transistor MP3, the S pole of which is configured to be grounded, the D pole of which is connected to the D pole of the current mirror transistor MN4, and the G pole of which is connected to the D pole;

[0115] ​​a current mirror transistor MP5, the S pole of which is connected to ground, and the G pole of which is connected to the G pole of the current mirror transistor MP3;

[0116] a resistor R3, one end of which is connected to a high voltage source, and the other end of which is connected to an output port Vout,

[0117] a voltage stabilizing diode D3, which is connected in parallel with the resistor R3;

[0118] a transistor MP4, the S pole of which is connected to the D pole of the current mirror transistor MP5, the G pole of which is connected to an input port Vin, and the D pole of which is connected to the other end of the resistor R3;

[0119] a transistor MP6, the S pole of which is connected to ground, and the D pole of which is connected to the S pole of the transistor MP4;

[0120] a NAND gate, the output of which is connected to the G pole of the transistor MP6, the first input of which is used to input a TRIM_EN signal, and the other input of which is used to input Vin.

[0121] In the embodiment of the present application, the high voltage source connected to the S pole of the current mirror transistor MN3 and the S pole of the current mirror transistor MN4 is VDD -- 5V high voltage source. The high voltage source connected to one end of the resistor R3 is VDD — HV high voltage source. The VDD — HV high voltage source can be set to be higher than VDD -- 5V high voltage source, such as a 20V high voltage source, a 40V high voltage source, or a 60V high voltage source.

[0122] In the embodiment of the present application, the adjustable current source ITRIM1 is amplified by two-stage current mirror and provided to the resistor R3, such as 50 times. Figure 3 The Vout in Figure 2 is connected to the gate of the transistor MP1 in Figure 3 . Therefore, the VGS of the transistor MP1 is equal to the voltage across the resistor R3 in

[0123] . By adjusting the current flowing through the resistor R3, the size of VGS can be freely adjusted.

[0124] wherein the TRIM_EN signal is used to turn off the current mirror.

[0125] Figure 4 is the circuit diagram of the low-voltage current-regulated level shifter in the embodiment of the present application, as shown in Figure 4 ,

[0126] The second level shifter comprises:

[0127] Adjustable current source ITRIM2;

[0128] The second two-stage current mirror is used to amplify the current generated by the adjustable current source ITRIM2 by 2 times;

[0129] Resistor R4 is used to reduce the voltage drop of the amplified current, which serves as the VGS of transistor MN1. VGS is the voltage difference between the gate (G) and source (S) terminals.

[0130] In this embodiment of the invention, the second two-stage current mirror first amplifies the current by a factor of M, and then amplifies the current by a factor of N. The value of M is any value between 1 and 5, such as 1. The value of N is any value between 40 and 100, such as 50. The value of X2 is M×N.

[0131] More specifically, the second level converter includes:

[0132] Current source ITRIM2 is configured to output the second value of current;

[0133] The current mirror transistor MN5 has its source (S) connected to a high-voltage source and its gate (G) connected to its drain (D).

[0134] The current mirror transistor MN6 has its source (S) connected to a high-voltage source and its gate (G) connected to the gate (G) of the current mirror transistor MN5.

[0135] The current mirror transistor MP7 has its source (S) terminal grounded, its drain (D) terminal connected to the drain (D) terminal of the current mirror transistor MN6, and its gate (G) terminal connected to the drain (D).

[0136] The current mirror transistor MP8 has its source (S) terminal grounded and its gate (G) terminal connected to the gate (G) terminal of the current mirror transistor MP7.

[0137] Resistor R4, one end of which is connected to a high voltage source, and the other end is connected to the drain of current mirror transistor MP8;

[0138] Transistor MN7, the source (S) of transistor MN7 is connected to a high voltage source, the gate (G) is used to input the TRIM_EN signal, and the drain (D) is connected to the other end of resistor R4;

[0139] An inverter, the input of which is used to receive the signal Vin, the output of which is used to output the signal Vout, the positive terminal of which is connected to the other end of the resistor R4, and the negative terminal is grounded.

[0140] In this embodiment of the invention, the high-voltage source connected to the source of transistor MN7, the source of current mirror transistor MN5, and the source of current mirror transistor MN6 is VDD.-- 5V high voltage source. The high voltage source connected to one end of the resistor R4 is VDD -- 5V high voltage source.

[0141] However, in semiconductor processes, the resistance value of the resistor is greatly affected by process deviation and temperature variation, thus, even Figure 3 and Figure 4 The level shifter shown in FIG. 1 can adjust the size of VGS, and the change of the resistance value will affect the size of the final output waveform swing, thus affecting the waveform distortion. The constant current circuit shown in FIG. 2 can effectively reduce the influence of the change of the resistance value. Figure 5

[0142] Figure 5 The constant current circuit for the current-regulated level shifter in the embodiment of the present application is shown in FIG. 2, which comprises a first level shifter and a constant current circuit. Figure 5 The first level shifter comprises a constant current circuit, and the constant current circuit comprises:

[0143] a resistor voltage dividing network for generating a reference voltage;

[0144] an operational amplifier for making the voltage across the resistor R0 equal to the reference voltage through negative feedback, forming a constant current I;

[0145] a third two-stage current mirror for amplifying the constant current I by X3 times and providing the amplified current to the resistor R3 of the first level shifter.

[0146] In the embodiment of the present application, the third two-stage current mirror first amplifies the current by M times and then amplifies the current by N times, wherein M is any value between 1 and 5, such as 1, and N is any value between 40 and 100, such as 50, and X3 is M×N.

[0147] More specifically, the constant current circuit comprises:

[0148] a resistor R1, one end of which is connected to a high voltage source;

[0149] a resistor R2, one end of which is connected to the other end of the resistor R1;

[0150] an operational amplifier, the positive input terminal of which is connected to the other end of the resistor R1;

[0151] a resistor R0, one end of which is connected to the inverting input terminal of the operational amplifier, and the other end of which is grounded;

[0152] a current mirror transistor MN8, the S pole of which is used to connect to a high voltage source, and the G pole of which is connected to the D pole;

[0153] ​a current mirror transistor MN9, an S pole of the current mirror transistor MN9 is connected with a D pole of the current mirror transistor MN9, and a G pole is connected with the D pole;

[0154] a transistor MP14, an S pole of the transistor MP14 is connected with one end of a resistor R0, a G pole is connected with an output end of an operational amplifier, and a D pole is connected with the D pole of the current mirror transistor MN9;

[0155] a current mirror transistor MN10, an S pole of the current mirror transistor MN10 is used for connecting a high-voltage source, and a G pole is connected with the G pole of the current mirror transistor MN8;

[0156] a current mirror transistor MN11, an S pole of the current mirror transistor MN11 is connected with the D pole of the current mirror transistor MN10, and a G pole is connected with the G pole of the current mirror transistor MN9;

[0157] a current mirror transistor MP9, a D pole of the current mirror transistor MP9 is connected with the D pole of the current mirror transistor MN11, and a G pole is connected with the D pole;

[0158] a current mirror transistor MP10, a D pole of the current mirror transistor MP10 is connected with the S pole of the current mirror transistor MP9, a G pole is connected with the D pole, and an S pole is grounded;

[0159] a current mirror transistor MP12, a G pole of the current mirror transistor MP12 is connected with the G pole of the current mirror transistor MP9;

[0160] a current mirror transistor MP13, a G pole of the current mirror transistor MP13 is connected with the G pole of the current mirror transistor MP10, a D pole is connected with the S pole of the current mirror transistor MP12, and an S pole is grounded.

[0161] In the embodiment of the present application, the high-voltage source connected with the S pole of the current mirror transistor MN8 and the S pole of the current mirror transistor MN10 is VDD -- 5V high-voltage source. One end of the resistor R1 is connected with the high-voltage source VDD -- 5V high-voltage source.

[0162] The first level converter further comprises:

[0163] a resistor R3, one end of the resistor R3 is used for connecting a high-voltage source, and the other end is connected with an output port Vout,

[0164] a voltage stabilizing diode D3, which is connected with the resistor R3 in parallel;

[0165] a transistor MP11, a D pole of the transistor MP11 is connected with the other end of the resistor R3, an S pole is connected with a D pole of the current mirror transistor MP12, and a G pole is used for receiving a signal Vin.

[0166] As shown in Figure 5 The reference voltage Vref is generated by the resistance voltage divider composed of R1 and R2. Through the negative feedback formed by the operational amplifier, the voltage across R0 will be equal to Vref. The current flowing through R0 is provided to the resistance R3 in the level shifter through the current mirror, forming the required voltage drop. By adjusting the ratio N of the current mirror, the VGS driving the DMOS can be adjusted.

[0167] (4)

[0168] As shown in equation 4, if the resistance types of R0 and R3 are the same and can be well matched in the layout, Figure 5 The constant current circuit in equation 5 can provide VGS independent of temperature and process variation.

[0169] In the embodiments of the present application, the time adjustment of the rising edge or the falling edge of the voltage pulse is achieved by adjusting the voltage difference VGS between the gate and the source of the transistor through the level shifter, so that the size of the slew rate of different edges is adjusted, and the waveform distortion is reduced. The high voltage DMOS switch control voltage independent of temperature and semiconductor process variation is achieved through the constant current circuit, and the slew rate adjustment efficiency is improved.

[0170] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the various embodiments can be referred to each other. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0171] The specific embodiments of the present application are described above. It should be understood that the present application is not limited to the specific embodiments described above, and various modifications or changes can be made by those skilled in the art within the scope of the claims, which do not affect the essential content of the present application.

Claims

1. A low-distortion pulse generator, characterized in that, include: Transistor MP1, wherein the source (S) terminal of transistor MP1 is used to connect to the high-voltage power supply terminal, and the drain (D) terminal is used to connect to the transducer; The first level shifter is used to drive the gate of transistor MP1 to apply a voltage pulse with a rising edge to the transducer. Transistor MN1, wherein the source (S) terminal of transistor MN1 is used for grounding and the drain (D) terminal is used for connecting to the transducer; The second level shifter is used to drive the gate of transistor MN1 to apply a voltage pulse with a falling edge to the transducer. The level converter is used to adjust the voltage difference VGS between the gate and source of the transistor to achieve time adjustment of the rising edge or the falling edge of the voltage pulse; The first level converter includes: Adjustable current source ITRIM1; The first two-stage current mirrors are used to amplify the current generated by the adjustable current source ITRIM1 by a factor of X1. Resistor R3 is used to reduce the voltage drop of the amplified current, which serves as the VGS of transistor MP1, where VGS is the voltage difference between the gate (G) and source (S) terminals; the first level shifter includes: Current source ITRIM1 is configured to output the first value of current; The current mirror transistor MN3 is used to connect the source (S) to a high voltage source, the gate (G) to the drain (D), and the drain to one end of the current source ITRIM1. The other end of the current source ITRIM1 is grounded. The current mirror transistor MN4 has its source (S) connected to a high-voltage source and its gate (G) connected to the gate (G) of the current mirror transistor MN3. The current mirror transistor MP3 has its source (S) terminal grounded, its drain (D) terminal connected to the drain (D) terminal of the current mirror transistor MN4, and its gate (G) terminal connected to the drain (D). The current mirror transistor MP5 has its source (S) terminal grounded and its gate (G) terminal connected to the gate (G) terminal of the current mirror transistor MP3. Resistor R3, one end of which is connected to a high-voltage source, and the other end is connected to the output port Vout. Zener diode D3 is connected in parallel with resistor R3; Transistor MP4, the source (S) of transistor MP4 is connected to the drain (D) of current mirror transistor MP5, the gate (G) is connected to the input port Vin, and the drain (D) is connected to the other end of resistor R3; Transistor MP6, wherein the source (S) terminal of transistor MP6 is grounded, and the drain (D) terminal is connected to the source (S) terminal of transistor MP4; The NAND gate has its output connected to the gate (G) of the transistor MP6. Its first input is used to input the TRIM_EN signal, and its other input is used to input Vin. The TRIM_EN signal is used to turn off the current mirror.

2. The low-distortion pulse generator according to claim 1, characterized in that, Also includes: Transistor MN2, wherein the source (S) terminal of transistor MN2 is used to connect to the low-voltage power supply terminal, and the drain (D) terminal is used to connect to the transducer; The third level converter is used to drive the gate of transistor MN2 to apply a voltage pulse with a falling edge to the transducer; Transistor MP2, wherein the source (S) terminal of transistor MP2 is used for grounding and the drain (D) terminal is used for connecting to the transducer; The fourth level shifter is used to drive the gate of transistor MP2 to apply a voltage pulse with a rising edge to the transducer.

3. The low-distortion pulse generator according to claim 1, characterized in that, Also includes: Diode D1, the positive terminal of which is connected to the transducer, and the negative terminal of which is connected to the drain terminal of transistor MN1; Diode D2, the negative terminal of which is connected to the transducer, and the positive terminal of which is connected to the drain terminal of transistor MP2.

4. The low-distortion pulse generator according to claim 1, characterized in that, The second level converter includes: Adjustable current source ITRIM2; The second two-stage current mirror is used to amplify the current generated by the adjustable current source ITRIM2 by 2 times; Resistor R4 is used to reduce the voltage drop of the amplified current, which serves as the VGS of transistor MN1. VGS is the voltage difference between the gate (G) and source (S) terminals.

5. The low-distortion pulse generator according to claim 4, characterized in that, The second level converter includes: Current source ITRIM2 is configured to output the second value of current; The current mirror transistor MN5 has its source (S) connected to a high-voltage source and its gate (G) connected to its drain (D). The current mirror transistor MN6 has its source (S) connected to a high-voltage source and its gate (G) connected to the gate (G) of the current mirror transistor MN5. The current mirror transistor MP7 has its source (S) terminal grounded, its drain (D) terminal connected to the drain (D) terminal of the current mirror transistor MN6, and its gate (G) terminal connected to the drain (D). The current mirror transistor MP8 has its source (S) terminal grounded and its gate (G) terminal connected to the gate (G) terminal of the current mirror transistor MP7. Resistor R4, one end of which is connected to a high voltage source, and the other end is connected to the drain of current mirror transistor MP8; Transistor MN7, the source (S) of transistor MN7 is connected to a high voltage source, the gate (G) is used to input the TRIM_EN signal, and the drain (D) is connected to the other end of resistor R4; An inverter, the input of which is used to receive signal Vin, the output of which is used to output signal Vout, the positive terminal of which is connected to the other end of resistor R4, and the negative terminal is grounded.

6. The low-distortion pulse generator according to claim 1, characterized in that, The first level converter includes a current stabilizing circuit; the current stabilizing circuit includes: A resistor divider network is used to generate a reference voltage; An operational amplifier is used to make the voltage across resistor R0 equal to the reference voltage through negative feedback, thereby forming a constant current I; The third two-stage current mirror is used to amplify the constant current I by 3 times and then provide it to the resistor R3 of the first level converter.

7. The low-distortion pulse generator according to claim 6, characterized in that, The current stabilizing circuit includes: Resistor R1, one end of which is connected to a high-voltage source; Resistor R2, one end of which is connected to the other end of resistor R1; Operational amplifier; the non-inverting input terminal of the operational amplifier is connected to the other end of the resistor R1; Resistor R0, one end of which is connected to the inverting input terminal of the operational amplifier, and the other end is grounded; The current mirror transistor MN8 has its source (S) connected to a high-voltage source and its gate (G) connected to its drain (D). A current mirror transistor MN9, wherein the source (S) of the current mirror transistor MN9 is connected to the drain (D) of the current mirror transistor MN8, and the gate (G) is connected to the drain (D). Transistor MP14, wherein the source (S) of transistor MP14 is connected to one end of resistor R0, the gate (G) is connected to the output terminal of operational amplifier, and the drain (D) is connected to the drain of current mirror transistor MN9; A current mirror transistor MN10, wherein the source (S) of the current mirror transistor MN10 is connected to a high voltage source, and the gate (G) is connected to the gate (G) of the current mirror transistor MN8. A current mirror transistor MN11, wherein the source (S) terminal of the current mirror transistor MN11 is connected to the drain (D) terminal of the current mirror transistor MN10, and the gate (G) terminal is connected to the gate (G) terminal of the current mirror transistor MN9; A current mirror transistor MP9, wherein the drain (D) of the current mirror transistor MP9 is connected to the drain (D) of the current mirror transistor MN11, and the gate (G) is connected to the drain (D). The current mirror transistor MP10 has its drain (D) connected to the source (S) of the current mirror transistor MP9, its gate (G) connected to its drain (D), and its source (S) grounded. A current mirror transistor MP12, wherein the gate of the current mirror transistor MP12 is connected to the gate of the current mirror transistor MP9; The current mirror transistor MP13 has its gate (G) connected to the gate (G) of the current mirror transistor MP10, its drain (D) connected to the source (S) of the current mirror transistor MP12, and its source (S) grounded.

8. The low-distortion pulse generator according to claim 7, characterized in that, The first level converter further includes: Resistor R3, one end of which is connected to a high-voltage source, and the other end is connected to the output port Vout. Zener diode D3 is connected in parallel with resistor R3; Transistor MP11, the drain of transistor MP11 is connected to the other end of resistor R3, the source is connected to the drain of current mirror transistor MP12, and the gate is used to receive signal Vin.

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