Preparation method of high-reliability Trench MOS device
By setting P+ and P++ regions within the P-body region, the avalanche current path is optimized, solving the avalanche problem caused by electric field concentration at the bottom of the trench, and improving the reliability and avalanche capability of the Trench MOS device.
Patent Information
- Application Number
- CN202511086913.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-07
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The electric field is concentrated at the bottom of the trench, which can easily trigger local avalanches, causing a sharp increase in current and making the device prone to burnout.
By providing P+ and P++ regions within the P-body region, the avalanche current path is optimized, the body resistance RB is reduced, and the difficulty of turning on the parasitic transistor is increased. By controlling the depth and concentration of the P-body and P+ regions, the avalanche capability is optimized.
Improve the reliability and avalanche capability of devices under extreme conditions, reduce the difficulty of turning on parasitic transistors, and enhance the stability of devices in high avalanche capability applications.
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Figure CN120916458A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a preparation method of a high-reliability Trench MOS device. BACKGROUND
[0002] Trench MOSFET is a power device which optimizes the performance of traditional planar MOSFET through trench structure. The trench structure is vertically dug into the substrate, allowing denser cell arrangement, which can significantly reduce the on-resistance (Ron) and improve the current handling capability. The trench design shortens the current path and reduces the energy loss during conduction, which is particularly suitable for high-frequency and high-current applications. The gate trench structure reduces the parasitic capacitance (such as Ciss, Coss, Crss) and accelerates the switching speed, thereby reducing the switching loss. Trench MOSFET is mainly used in the low-voltage field (12-200V). DSON gd
[0003] In the process of implementing the present application, the applicant found at least the following problems in the prior art:
[0004] The electric field is concentrated at the bottom of the trench, which easily triggers local avalanche, sharply increases the current, and causes the device to burn out. SUMMARY
[0005] The present application provides a preparation method of a high-reliability Trench MOS device, which is also a preparation method of a Trench MOS (MOSFET) device, to at least solve the problem of electric field concentration at the bottom of the trench, which easily triggers local avalanche, sharply increases the current, and causes the device to burn out.
[0006] To achieve the above purpose, on the one hand, the present application provides a preparation method of a high-reliability Trench MOS device, comprising:
[0007] forming a trench on a wafer on which a substrate and an epitaxial layer above the substrate have been prepared by etching;
[0008] growing a gate oxide layer on the surface of the wafer and the inner surface of the trench;
[0009] forming a gate polysilicon in the trench by polysilicon deposition and etching back, and removing part of the gate oxide layer on the surface of the wafer;
[0010] forming a P-body region on the upper part of the epitaxial layer by boron ion implantation and annealing;
[0011] forming two P+ regions by performing P+ photolithography, boron ion implantation and annealing symmetrically on both sides of the trench in the P-body region;
[0012] In the P-body region and the upper part of the P+ region, source-level N+ lithography, arsenic ion implantation and annealing are performed to form two N+ regions;
[0013] An ILD is deposited on the upper surface of the wafer to form an interlayer dielectric layer;
[0014] Two contact holes are formed by lithography, P++ implantation and annealing are performed to form two P++ regions;
[0015] A front metal is formed by sputtering, a gate electrode and a source electrode are formed by lithography, and a passivation layer is deposited and lithographically formed to form electrode openings;
[0016] The wafer is thinned on the back and the back metal is evaporated to form a drain electrode.
[0017] Further, the trench depth is 0.8 to 2 microns, and the trench width is 0.15 to 1 micron.
[0018] Further, the gate oxide layer has a thickness of 20 to 100 nanometers.
[0019] Further, the number of times and the energy of boron ion implantation in the corresponding steps of forming the P-body region and forming the two P+ regions are the same.
[0020] Further, the formation of the P-body region on the upper part of the epitaxial layer by boron ion implantation and annealing comprises:
[0021] The boron ions are implanted twice, the first implantation energy is 30kev-90Kev, and the dose is 4e12cm -2 The second implantation energy is 90kev-240Kev, and the dose is 4e12cm -2 .
[0022] Further, the formation of the P-body region on the upper part of the epitaxial layer by boron ion implantation and annealing comprises:
[0023] The annealing temperature after boron ion implantation of the P-body region is 1050 to 1100 degrees Celsius, the annealing time is 30 to 60 minutes, and the depth of the P-body region is less than the depth of the trench 303 by at least 0.2 microns.
[0024] Further, the P+ lithography, boron ion implantation and annealing in the P-body region symmetrically located on both sides of the trench form two P+ regions, comprising:
[0025] The boron ions are implanted twice, the first implantation energy is 30kev-90Kev, and the dose is 1e13cm -2 The second implantation energy is 90kev-240Kev, and the dose is 1e13cm -2 .
[0026] Further, P+ photoetching, boron ion implantation and annealing are symmetrically performed on both sides of the trench in the P-body region to form two P+ regions, including:
[0027] The annealing temperature of the P+ region after boron ion implantation is 1000-1050 degrees Celsius, and the annealing time is 0-30 minutes, and the annealing temperature and time of the P+ region are lower than those of the P-body region, the ion concentration of the P+ region is higher than that of the P-body region, and the depth of the P+ region is less than that of the P-body region.
[0028] Further, source-level N+ photoetching, arsenic ion implantation and annealing are performed on the upper part of the P-body region and the P+ region to form two N+ regions, including:
[0029] The arsenic ion implantation energy is 30kev-50Kev, and the dose is 1e15cm -2 -5e15cm -2 .
[0030] Further, source-level N+ photoetching, arsenic ion implantation and annealing are performed on the upper part of the P-body region and the P+ region to form two N+ regions, including:
[0031] The annealing temperature after arsenic ion implantation is 950 degrees Celsius, and the annealing time is 30 minutes.
[0032] The technical scheme has the following beneficial effects: by providing P+ region and P++ region in P-body region, the avalanche current path is optimized, the body resistance R B of the body region is reduced, the difficulty of opening the parasitic triode is increased, the avalanche capability of the device is improved, and the reliability of the device in extreme working condition application is improved. BRIEF DESCRIPTION OF DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.
[0034] Figure 1 is a flow chart of a high-reliability Trench MOS device preparation method according to an embodiment of the present application;
[0035] Figure 2 is a structural schematic diagram of an N-channel Trench MOS device in the prior art with a parasitic BJT marked;
[0036] Figure 3 This is a schematic diagram of a high-reliability Trench MOSFET unit cell structure, one of the embodiments of the present invention;
[0037] Figures 4 to 13 This is a schematic diagram of the process flow for fabricating a high-reliability Trench MOSFET device, which is one embodiment of the present invention. Detailed Implementation
[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] Avalanche energy is a key parameter measuring the energy dissipation capability of a power MOSFET under unclamped inductive switching (UIS) stress, directly affecting the reliability of the device under extreme conditions such as overvoltage, surge, or sudden changes in inductive load. Current-related UIS failures in power DMOS are mainly caused by the turn-on of parasitic BJTs, such as... Figure 2 The N-channel Trench MOSFET structure with parasitic BJT is shown. Inside the power DMOS, there is a parasitic NPN transistor structure. When the device is in avalanche breakdown state, current flows to the source through the P-body region. Due to the body resistance R of the P-body region… B The presence of this resistor causes a voltage drop across the P-body region as current flows laterally, resulting in a higher potential on the trench side of the P-body. This creates a potential difference between the P-body and the N+ source region. When this potential difference reaches the turn-on voltage of the parasitic transistor's BE junction (approximately 0.7V), the parasitic transistor will turn on, causing a sharp increase in current and potentially leading to device burnout. The avalanche resistance of trench MOSFETs is a key indicator of their robustness in practical applications, especially crucial in harsh environments such as automotive electronics and industrial power supplies. The concentrated electric field at the bottom of the trench easily triggers localized avalanche; therefore, for applications requiring high avalanche resistance, this parameter must be carefully considered and optimized during device design.
[0040] To achieve the above objectives, on the one hand, such as Figure 1 As shown, this embodiment of the invention provides a method for fabricating a high-reliability TrenchMOS device, comprising:
[0041] Step S10: On the wafer on which the substrate 301 and the epitaxial layer 302 on the substrate have been prepared, trenches 303 are formed by etching.
[0042] Step S11: A gate oxide layer 304 is grown on the wafer surface and the inner surface of the trench 303;
[0043] Step S12: Gate polysilicon 305 is formed in the trench 303 by polysilicon deposition and etch-back, and the gate oxide layer on the wafer surface is removed.
[0044] Step S13: A P-body region 306 is formed on the upper part of the epitaxial layer 302 by boron ion implantation and annealing;
[0045] Step S14: P+ photolithography, boron ion implantation and annealing are performed symmetrically on both sides of the trench 303 in the P-body region 306 to form two P+ regions 307;
[0046] Step S15: Source-level N+ lithography, arsenic ion implantation and annealing are performed on the upper part of P-body region 306 and P+ region 307 to form two N+ regions 308.
[0047] Step S16: ILD deposition is performed on the upper surface of the wafer to form an interlayer dielectric layer 309;
[0048] Step S17: Two contact holes 310 are formed by photolithography, and two P++ regions 311 are formed by P++ implantation and annealing.
[0049] Step S18: front metal is formed by sputtering, gate electrode and source electrode 312 are formed by photolithography, and passivation layer is deposited and formed by photolithography to form electrode openings;
[0050] Step S19: Thinning and evaporating the back side metal of the wafer to form the drain electrode 313.
[0051] The embodiments of the present invention have the following technical effects: by providing P+ and P++ regions within the P-body region, the avalanche current path is optimized, and the bulk resistance R of the bulk region is reduced. B This increases the difficulty of turning on parasitic transistors, improves the avalanche capability of devices, and enhances the reliability of devices in extreme operating conditions.
[0052] In some embodiments, such as Figure 5 As shown, in Figure 4 On the wafer shown, where a substrate 301 and an epitaxial layer 302 have been fabricated, trenches 303 are formed by etching.
[0053] like Figure 6 As shown, a gate oxide layer 304 is grown on the wafer surface and the inner surface of the trench 303; asFigure 7 As shown, a gate polysilicon 305 is formed in the trench 303 by polysilicon deposition and etch-back, and the gate oxide layer on the wafer surface is removed.
[0054] like Figure 8 As shown, boron ions are implanted and annealed on the upper part of the epitaxial layer 302 to form a P-body region 306. The depth of the P-body region 306 is less than the depth of the trench 303. The depth of the P-body region 306 is the distance from the upper surface of the wafer (source side) to the bottom (or end) of the P-body region 306, and the depth of the trench 303 is the distance from the upper surface of the wafer (source side) to the bottom (or end) of the trench 303.
[0055] like Figure 9 As shown, P+ lithography, boron ion implantation, and annealing are performed symmetrically on both sides of the trench 303 in the P-body region 306 to form two P+ regions 307. The two P+ regions 307 are separated from the trench 303 by the P-body region 306. The depth of the two P+ regions 307 is less than the depth of the P-body region 306. The concentration of the P+ regions 307 is greater than the concentration of the P-body region 306. The depth of the P+ region 307 is the distance from the upper surface of the wafer (on the source side) to the bottom (or end) of the P+ region 307.
[0056] like Figure 10 As shown, source-level N+ lithography, arsenic ion implantation and annealing are performed on the upper part of P-body region 306 and P+ region 307 to form two N+ regions 308, which are symmetrical with respect to the trench 303.
[0057] like Figure 11 As shown, ILD (Inter-Layer Dielectric) deposition is performed on the upper surface of the wafer to form an inter-layer dielectric layer 309;
[0058] like Figure 12As shown, two contact holes 310 are photolithographically formed downwards from the upper surface of the interlayer dielectric layer 309. P++ implantation and annealing are then performed to form two P++ regions 311. The depth of the two contact holes 310 is greater than the depth of the N+ region 308. The two contact holes 310 are symmetrical with respect to the trench 303, and are spaced apart from the trench 303 by the N+ region 308. The two P++ regions 311 are symmetrical with respect to the trench 303, and are spaced apart from the trench 303 by a P-body region 306. The P++ regions 311 are adjacent to the lower surface of the contact holes 310 and the N+ region 308 on the same side. The depth of the contact hole 310 is the distance from the upper surface of the wafer (source side) to the bottom (or end) of the contact hole 310; the depth of the N+ region 308 is the distance from the upper surface of the wafer (source side) to the bottom (or end) of the N+ region 308.
[0059] like Figure 13 As shown, the front metal is formed by sputtering, the gate electrode and source electrode 312 are formed by photolithography, and the passivation layer is deposited and formed by photolithography to form electrode windows;
[0060] like Figure 13 As shown, the back side of the wafer is thinned and the back side metal is evaporated to form the drain electrode 313.
[0061] The final structural schematic diagram of the Trench MOS device is shown below. Figure 3 As shown.
[0062] The embodiments of the present invention have the following technical effects: by providing P+ and P++ regions within the P-body region, and controlling the depth of the P-body region 306 to be less than the depth of the trench 303, the depth of the P+ region 307 to be less than the depth of the P-body region 306, and the concentration of the P+ region 307 to be greater than the concentration of the P-body region 306, the avalanche current path is optimized, and the bulk resistance R of the volume region is reduced. B This increases the difficulty of turning on parasitic transistors, improves the avalanche capability of devices, and enhances the reliability of devices in extreme operating conditions.
[0063] Furthermore, the trench 303 has a depth of 0.8 to 2 micrometers and a width of 0.15 to 1 micrometer.
[0064] In some embodiments, the trench 303 depth of 0.8-2 microns can balance the vertical direction channel length and the depth of the P-body region 306, the depth of the P-body region 306 is at least 0.2 microns less than the depth of the trench 303, and avoid the channel length being too short to cause channel leakage and the channel length being too long to cause channel resistance to increase, ensuring that the breakdown point after the device avalanche breakdown is located at the bottom of the trench. The trench width of 0.15-1 micron can reduce the lateral size of a single trench under the premise of ensuring process realizability such as etching precision, oxide layer uniformity, etc., thereby integrating more trenches in the same chip area, significantly increasing the total channel width, and the greater the total channel width, the lower the on-resistance. Compared with the same size planar MOSFET, the combination of the trench 303 depth of 0.8 to 2 microns and the trench width of 0.15 to 1 micron can reduce the on-resistance by 30%-50%, which is particularly suitable for low-voltage power device scenarios. If the trench width is less than 0.15 microns, it will easily cause serious electric field concentration at the corner of the trench due to the tip effect, resulting in a sharp drop in local breakdown voltage; if the trench width exceeds 1 micron, the device lateral size will increase, reducing the integration level. The width of 0.15-1 micron can weaken the electric field concentration by using a circular arc corner design at the bottom of the trench 303, ensuring the stability of the breakdown voltage, for example, the breakdown voltage fluctuation is less than 5%.
[0065] Further, the gate oxide layer 304 thickness is 20-100 nanometers. In some embodiments, the gate oxide layer 304 thickness of 20-100 nanometers is beneficial for optimizing the gate capacitance to balance the switching speed and driving loss, and enhancing the oxide layer reliability to adapt to long-term work. In some embodiments, the gate oxide layer 304 thickness of 20-100 nanometers cooperates with the trench width of 0.15-1 micron, the trench width of 0.15-1 micron is relatively narrow, and if the oxide layer is too thin, for example, less than 20 nm, the curvature radius at the corner of the trench increases relative to the thickness of the oxide layer, and the electric field concentration effect will be intensified, for example, the corner electric field strength can be 2-3 times that of the planar area, causing the local oxide layer to break down prematurely.
[0066] Furthermore, the number of boron ion implantations and the energy are the same in the corresponding steps of forming the P-body region 306 and forming the two P+ regions 307. Forming the P-body region 306 means forming the P-body region 306 on the epitaxial layer 302 through boron ion implantation and annealing; forming the two P+ regions 307 means symmetrically performing P+ lithography, boron ion implantation, and annealing on both sides of the trench 303 within the P-body region 306 to form two P+ regions 307. It is required that the number of boron ion implantations and the energy are the same in the P+ region steps as in the P-body region steps to ensure that the peak position of the boron ion concentration in the P+ region is consistent with the peak position of the boron ion concentration in the P-body region. Combined with the implantation dosage and annealing process, it is easier to ensure that the concentration in the P+ region is higher than that in the P-body region, and that the depth of the P+ region is less than that of the P-body region.
[0067] Further, the formation of the P-body region 306 on the epitaxial layer 302 by boron ion implantation and annealing includes:
[0068] Boron ions were implanted in two stages. The first implantation energy was 30 keV to 90 keV, and the dose was 4e12cm. -2 The second injection energy was 90 keV to 240 keV, with a dose of 4e12cm. -2 In summary, the combination of boron ion implantation energy and dose with annealing processes in the P-body region can form the P-body region, which determines the threshold voltage of the device.
[0069] Further, the formation of the P-body region 306 on the epitaxial layer 302 by boron ion implantation and annealing includes:
[0070] The boron ion implantation of the P-body region 306 is followed by an annealing temperature of 1050 to 1100 degrees Celsius and an annealing time of 30 to 60 minutes. The depth of the P-body region 306 is at least 0.2 micrometers less than the depth of the trench 303. The depth of the P-body region 306 is the distance from the upper surface of the wafer (source side) to the bottom (or end) of the P-body region 306; the depth of the trench 303 is the distance from the upper surface of the wafer (source side) to the bottom (or end) of the trench 303. This ensures that device breakdown avalanche occurs at the bottom of the trench, away from the P-body region, reducing the lateral current near the P-body region after avalanche breakdown.
[0071] Furthermore, in the P-body region 306, P+ lithography, boron ion implantation, and annealing are performed symmetrically on both sides of the trench 303 to form two P+ regions 307, including:
[0072] The boron ions are implanted twice, the first implantation has an energy of 30 keV to 90 keV and a dose of 1e13 cm -2 The second implantation has an energy of 90 keV to 240 keV and a dose of 1e13 cm -2 The above.
[0073] Further, the P+ region is formed by P+ photolithography, boron ion implantation and annealing symmetrically on both sides of the trench 303 in the P-body region 306, and two P+ regions 307 are formed, including:
[0074] The annealing temperature of the P+ region after boron ion implantation is 1000-1050 degrees Celsius, and the annealing time is 0-30 minutes, and the annealing temperature and time of the P+ region 307 are lower than those of the P-body region 306, the ion concentration of the P+ region 307 is higher than that of the P-body region 306, and the depth of the P+ region 307 is less than that of the P-body region 306. The depth of the P+ region 307 is less than the depth of the P-body region 306, that is, the bottom of the P+ region does not exceed the bottom of the P-body region, so as to ensure that the concentration of the P+ region does not affect the breakdown voltage. Among them, the depth of the P+ region 307 is the distance from the upper surface of the wafer (the source side) to the bottom (or bottom end) of the P+ region 307; the depth of the P-body region 306 is the distance from the upper surface of the wafer (the source side) to the bottom (or bottom end) of the P-body region 306.
[0075] In some embodiments, the annealing temperature of the P+ region after implantation is 1000-1050℃, and the annealing time is 0-30min, and the annealing temperature and time are required to be lower than those of the P-body. The ion concentration of the P+ region is higher than that of the P-body, and the ion concentration of the P+ region is ensured not to affect the concentration of the P-body region near the trench 303, and the depth of the P+ region is ensured to be less than that of the P-body region. The P+ region is spaced apart from the trench by a certain distance, and the distance is as small as possible, which can maximize the reduction of the body resistance R B . Since the P+ region is formed by photolithography, the distance between the P+ region and the trench 303 can be adjusted by controlling the implantation area and the annealing temperature of the P+ region lower than that of the P-body region, so as to ensure that the ion concentration of the P+ region does not affect the concentration of the P-body region near the trench 303.
[0076] Further, the distance between the P+ region and the trench 303 is 50-150 nm. If the distance is less than 50 nm, the P+ concentration will affect the P-body concentration of the sidewall of the trench 303, increasing the threshold voltage. If the distance is greater than 150 nm, the avalanche capability does not achieve the optimal effect.
[0077] Furthermore, source-level N+ lithography, arsenic ion implantation, and annealing are performed on the upper part of the P-body region 306 and the P+ region 307 to form two N+ regions 308, including:
[0078] Arsenic ion implantation energy is 30 keV to 50 keV, and dose is 1e15cm. -2 ~5e15cm -2 .
[0079] Furthermore, source-level N+ lithography, arsenic ion implantation, and annealing are performed on the upper part of the P-body region 306 and the P+ region 307 to form two N+ regions 308, including:
[0080] The annealing temperature after arsenic ion implantation was 950 degrees Celsius, and the annealing time was 30 minutes.
[0081] The technical solutions of the present invention will be described in detail below with reference to specific application examples. For technical details not described in the implementation process, please refer to the relevant descriptions above.
[0082] This invention provides a method for fabricating a highly reliable Trench MOSFET, optimizing the device's avalanche capability and improving its long-term stability in critical applications such as industry, automotive, and energy.
[0083] Figure 3 This is a schematic diagram of a high-reliability Trench MOSFET unit cell structure according to an embodiment of the present invention. Figure 3 In the process, a P+ region is designed within the P-body to provide a current path after avalanche and reduce the volume resistance R of the body region. B To suppress premature turn-on of parasitic transistors, the turn-on current of the parasitic transistors is increased, allowing the device to thermally fail under higher avalanche currents, thus improving the device's avalanche capability. The P+ region depth must be less than the P-body region depth, the P-body region depth must be less than the trench depth, and the bottom of the P-body region must be at least 0.2 μm (micrometers) from the bottom of the trench. Actual spacing may vary depending on product specifications. This design ensures that avalanche breakdown occurs at the bottom of the trench, away from the P-body region, reducing the lateral current near the P-body region after avalanche breakdown and suppressing premature turn-on of the parasitic transistors. A certain distance between the P+ region and the trench, with the smallest possible distance, maximizes the reduction of the body resistance R. B However, it is essential to ensure that the doping in the P+ region does not affect the doping distribution near the channel and does not affect the threshold voltage of the device, so as to optimize the avalanche capability of the device without sacrificing other device parameters.
[0084] To achieve the above objectives, the technical solution adopted by the present invention includes the following steps:
[0085] S21, selecting wafer, forming hard mask layer opening by photoetching, further etching silicon wafer to form trench, and removing hard mask layer;
[0086] S22, growing gate oxide layer;
[0087] S23, depositing and etching back gate polysilicon, and removing surface part of gate oxide layer;
[0088] S24, implanting boron ion into P-body region and annealing to form P-body region;
[0089] S25, P+ photoetching, implanting boron ion and annealing to form P+ region;
[0090] S26, source level N+ photoetching, implanting arsenic ion and annealing;
[0091] S27, depositing ILD;
[0092] S28, photoetching to form contact hole, and implanting P++ and annealing;
[0093] S29, sputtering front metal, photoetching to form gate electrode and source electrode, depositing and photoetching passivation layer to form electrode opening;
[0094] S30, thinning wafer back surface and evaporating back surface metal to form drain electrode.
[0095] In the step S21, the trench depth is 0.8-2 μm, and the trench width is 0.15-1 μm.
[0096] In the step S22, the gate oxide layer thickness is 20-100 nm.
[0097] In the step S24, the boron ion is implanted twice, the first implantation energy is 30 kev-90 kev, and the dose is 4e12 cm -2 In the step S24, the boron ion is implanted twice, the first implantation energy is 30 kev-90 kev, and the dose is 4e12 cm -2 In the step S24, the boron ion is implanted twice, the first implantation energy is 30 kev-90 kev, and the dose is 4e12 cm
[0098] In the step S24, the P-body implantation annealing temperature is 1050-1100 °C, and the annealing time is 30-60 min. The P-body bottom is required to be at least 0.2 um above the trench bottom, to ensure that the device breakdown avalanche occurs at the trench bottom, far away from the P-body region, and to reduce the lateral current near the P-body region after avalanche breakdown.
[0099] In the step S25, the boron ion is implanted twice, the first implantation energy is 30 kev-90 kev, and the dose is 1e13 cm -2The second time of injecting energy is 90kev-240Kev, and the dose is 1e13cm -2 The above.
[0100] In the step S25, the P+ implantation annealing temperature is 1000-1050℃, and the annealing time is 0-30min, which is required to be lower than the annealing temperature and time of the P-body. The ion concentration of the P+ region is higher than that of the P-body, and the ion concentration of the P+ region is ensured not to affect the P-body region concentration near the trench, and the depth of the P+ region is ensured to be less than the depth of the P-body region. The P+ region is spaced apart from the trench by a certain distance, and the distance is as small as possible, which can maximize the reduction of the body resistance R B .
[0101] In the steps S25 and S26, the number of times and energy of P-body implantation and P+ implantation should be consistent, and the number of times of implantation is not limited to 2 times, which can be adjusted according to the channel width requirement.
[0102] In the step S26, the arsenic ion implantation energy is 30kev-50Kev, and the dose is 1e15cm -2 -5e15cm -2 .
[0103] In the step S26, the arsenic ion implantation annealing temperature is 950℃, and the annealing time is 30min.
[0104] The embodiment of the present application has the following technical effects: the embodiment of the present application optimizes the avalanche current path by controlling the trench depth, P-body junction depth and P+ region formation, reduces the body resistance R B , improves the avalanche capability of the device, and improves the reliability of the device in extreme working condition application.
[0105] The following is described by another embodiment, but the present application is not limited to the scope of the described embodiments. As shown in Figures 4 to 13 , the embodiment of the present application provides a preparation method of a high-reliability Trench MOS device, comprising the following steps:
[0106] S41, selecting a wafer with a suitable substrate and epitaxial resistivity, as Figure 4 shown, the 301 region is a substrate, and the 302 region is an epitaxial layer. A hard mask layer is deposited on the wafer, and a hard mask layer window is formed by lithography, and the silicon wafer is further etched to form a trench 303, the trench depth is 1um (micron), and the hard mask layer is removed, as Figure 5 shown.
[0107] S42, grow the sacrificial oxide layer, remove the sacrificial oxide layer, grow the gate oxide layer 304, the thickness of the gate oxide layer is 50 nm, as shown in Figure 6 ;
[0108] S43, gate polysilicon 305 deposition and etching back, remove the surface part of the gate oxide layer, as shown in Figure 7 ;
[0109] S44, P-body 306 region boron ion implantation and annealing, boron ion implantation uses 2 times injection, the first injection energy is 30 Kev, the dose is 6e12 cm -2 , the second injection energy is 90 Kev, the dose is 8e12 cm -2 , the annealing temperature is 1050 DEG C, the annealing time is 60 min, as shown in Figure 8 ;
[0110] S45, P+ lithography, form P+ implantation window, boron ion implantation and annealing, form P+ 307 region. Among them, boron ion implantation uses 2 times injection, the first injection energy is 30 Kev, the dose is 2e13 cm -2 , the second injection energy is 90 Kev, the dose is 3e13 cm -2 , the annealing temperature is 1000 DEG C, the annealing time is 30 min, as shown in Figure 9 ;
[0111] S46, source level N+ lithography window, arsenic ion implantation, the implantation energy is 50 Kev, the dose is 5e15 cm -2 , finally annealing process, the annealing temperature is 950 DEG C, the annealing time is 30 min, form N+ region 308, as shown in Figure 10 ;
[0112] S47, perform ILD 309 deposition, as shown in Figure 11 ;
[0113] S48, etching to form contact hole, form 310 region, and P+ implantation and annealing, form 311 P++ region, as shown in Figure 12 ;
[0114] S49, as shown in Figure 13 , sputtering front metal 312, lithography to form gate electrode and source electrode, passivation layer deposition and etching, the passivation layer is not shown in the schematic diagram;
[0115] S50, wafer back thinning and evaporation back metal 313, form drain electrode.
[0116] It should be understood that the particular order in which the steps of processes presented in the disclosure have been presented makes no limitation as to the scope of the disclosure. Based upon the teachings provided herein, one skilled in the art should appreciate that alternative order explanations of various steps can be implemented to be simultaneously parallel or in some cases possibly performed at different times. Also, the various steps can be reordered and / or "interleaved" with one another such that the ordering presented herein and described is an example only and should not be taken as a restriction of how the steps of the processes presented herein can be implemented. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order presented by the claims.
[0117] In the foregoing detailed description, various features are grouped together in single embodiments for the purpose of streamlining the disclosure. This disclosure is not to be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are expressly recited in each claim. Rather, as the claims below reflect, inventive subject matter lies in fewer than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate preferred embodiment.
[0118] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the claims.
[0119] The foregoing description of one or more embodiments will be provided in the accompanying description. Of course, not all possible combinations of components or method steps are described with regard to the above described embodiments, but one of ordinary skill in the art will recognize that further combinations are possible and are contemplated. Therefore, the embodiments described herein are intended to cover all such modifications and variations as come within the scope of the appended claims. Further, with respect to the use of the term "comprising" in the claims, it is intended to mean that the claimed subject matter includes at least the recited elements, but not excluding others. Further, with respect to the use of the term "or" in the claims, it is intended to mean "either" or "any one of".
[0120] The above detailed description describes the subject matter in the context of specific embodiments. The skilled person will understand that the detailed description is only intended to illustrate the subject matter and is not intended to limit the scope of the subject matter. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the subject matter shall be included in the protection scope of the subject matter.
Claims
1. A method for manufacturing a high-reliability Trench MOS device, characterized in that, The method comprises: forming a trench (303) on a wafer on which a substrate (301) and an epitaxial layer (302) above the substrate have been prepared by etching; growing a gate oxide layer (304) on the surface of the wafer and the inner surface of the trench (303); forming a gate polysilicon (305) in the trench (303) by polysilicon deposition and etching back, and removing the gate oxide layer on the surface of the wafer; forming a P-body region (306) on the upper part of the epitaxial layer (302) by boron ion implantation and annealing; forming two P+ regions (307) by P+ photolithography, boron ion implantation and annealing symmetrically on both sides of the trench (303) in the P-body region (306); forming two N+ regions (308) by source-level N+ photolithography, arsenic ion implantation and annealing on the upper part of the P-body region (306) and the P+ region (307); depositing an ILD on the upper surface of the wafer to form an interlayer dielectric layer (309); forming two contact holes (310) by photolithography, and forming two P++ regions (311) by P++ implantation and annealing; forming a front metal by sputtering, forming a gate electrode and a source electrode (312) by photolithography, depositing a passivation layer and forming an electrode window by photolithography; thinning the back of the wafer and evaporating a back metal to form a drain electrode (313).
2. The method of claim 1, wherein the trench MOS device has a high reliability. The depth of the trench (303) is 0.8 to 2 microns, and the width of the trench is 0.15 to 1 micron.
3. The method of claim 1 or 2, wherein the trench MOS device has a high reliability, and the trench MOS device is a trench MOSFET. The thickness of the gate oxide layer (304) is 20 to 100 nanometers.
4. The method of claim 1, wherein the trench MOS device has a high reliability. The number of times and the energy of the boron ion implantation in the corresponding steps of forming the P-body region (306) and forming the two P+ regions (307) are the same.
5. The method of claim 1, wherein the trench MOS device has a high reliability. The forming of the P-body region (306) on the upper part of the epitaxial layer (302) by boron ion implantation and annealing comprises: Boron ions were implanted in two stages. The first implantation energy was 30 keV to 90 keV, and the dose was 4e12cm. -2 The second injection energy was 90 keV to 240 keV, with a dose of 4e12cm. -2 above.
6. The method of claim 1, wherein the trench MOS device has a high reliability. The forming of the P-body region (306) on the upper part of the epitaxial layer (302) by boron ion implantation and annealing comprises: The annealing temperature after boron ion implantation of the P-body region (306) is 1050 to 1100 degrees Celsius, the annealing time is 30 to 60 minutes, and the depth of the P-body region (306) is at least 0.2 microns less than the depth of the trench (303).
7. The method of claim 1, wherein the trench MOS device has a high reliability. The forming of the two P+ regions (307) by P+ photolithography, boron ion implantation and annealing symmetrically on both sides of the trench (303) in the P-body region (306) comprises: The boron ions are injected twice, the first injection having an energy of 30 keV to 90 keV and a dose of 1e13 cm -2 The second injection has an energy of 90 keV to 240 keV and a dose of 1e13 cm -2 The above.
8. The method of claim 1, wherein the trench MOS device has a high reliability. The forming of the two P+ regions (307) by P+ photolithography, boron ion implantation and annealing symmetrically on both sides of the trench (303) in the P-body region (306) comprises: The annealing temperature after boron ion implantation of the P+ region is 1000 to 1050 degrees Celsius, the annealing time is 0 to 30 minutes, the annealing temperature and the annealing time of the P+ region (307) are lower than those of the P-body region (306), the ion concentration of the P+ region (307) is higher than that of the P-body region (306), and the depth of the P+ region (307) is less than that of the P-body region (306).
9. The method of claim 1, wherein the trench MOS device has a high reliability. In the upper part of the P-body region (306) and the P+ region (307), source-level N+ lithography, arsenic ion implantation and annealing are performed to form two N+ regions (308), including: Arsenic ions are implanted at an energy of 30 keV to 50 keV and a dose of 1e15 cm -2 ~ 5e15 cm -2 .
10. The method of claim 1, wherein the trench MOS device is a high-reliability trench MOS device. In the upper part of the P-body region (306) and the P+ region (307), source-level N+ lithography, arsenic ion implantation and annealing are performed to form two N+ regions (308), including: The annealing temperature after arsenic ion implantation is 950 degrees Celsius, and the annealing time is 30 minutes.