A method for implementing a multi-valued addresser by a dual-gate ferroelectric field effect transistor

Abstract

The application provides a method for realizing a multi-value addresser by a double-gate ferroelectric field effect transistor, relates to the technical field of addressers, and comprises the following steps: preparing a top metal gate, a bottom metal gate, a channel and an MFIS laminated structure to obtain a double-gate ferroelectric field effect transistor structure material; constructing a double-gate ferroelectric field effect transistor structure, entering a pMOS type working mode through the double-gate ferroelectric field effect transistor; controlling and adjusting the voltage of the top metal gate and the bottom metal gate according to the double-gate ferroelectric field effect transistor structure to obtain control and judgment information; and controlling the voltage sum of the top metal gate and the bottom metal gate, performing voltage scanning, obtaining an address point and then obtaining a multi-value addressing function. The application realizes the multi-value addresser function by only using a single double-gate ferroelectric field effect transistor, and greatly saves the occupied space and processing resources.

Description

Technical Field

[0001] This invention proposes a method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor, relating to the field of addresser technology, specifically to the field of implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor. Background Technology

[0002] Multi-valued addressers are addressing circuits or modules capable of handling multiple state inputs, and they are currently widely used in the fields of artificial intelligence and machine learning. Compared to traditional binary logic address matching, multi-valued addressers can carry more information per bit, thereby improving storage density and matching efficiency. Traditional single-valued addressers typically use 16T CMOS cells or 2T-2R cells, while multi-valued addressers use 6T-2ReRAM or 2FeFET-1T cells. These basic units all require multiple transistors, resulting in a large area requirement, which severely limits their high-density integration and cannot meet the needs of the rapid development of artificial intelligence and machine learning. Summary of the Invention

[0003] This invention provides a method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor to solve the above-mentioned problems:

[0004] This invention proposes a method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor, the method comprising:

[0005] A method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor, the method comprising:

[0006] S1. Fabricate the top metal gate 101, bottom metal gate 102, channel 107 and MFIS stacked structure to obtain the dual-gate ferroelectric effect transistor structure material.

[0007] S2. Construct a dual-gate ferroelectric field-effect transistor structure using a dual-gate ferroelectric field-effect transistor structure material, and enter the pMOS type working mode through the dual-gate ferroelectric field-effect transistor.

[0008] S3. Based on the dual-gate ferroelectric field-effect transistor structure, the voltage of the top metal gate 101 and the bottom metal gate 102 is controlled and adjusted to obtain control judgment information.

[0009] S4. By controlling the sum of the voltages of the top metal gate 101 and the bottom metal gate 102, voltage scanning is performed to obtain the addressing point, thereby obtaining the multi-value addressing function.

[0010] Further, S1 includes:

[0011] A channel region and a source / drain region are formed on a Si substrate. The channel region is p-type doped, and the source / drain regions on both sides are n-type doped. Insulating gate dielectric layers 105 and 106 and ferroelectric layers 103 and 104 are deposited sequentially on both sides of the channel region.

[0012] The insulating gate dielectric layers 105 and 106 are obtained by depositing 1-2 nm thick SiO2 using an ALD process.

[0013] The ferroelectric layers 103 and 104 are obtained by depositing 8-10 nm thick HZO using the ALD process and then undergoing rapid thermal annealing at 550 °C for 30 s to form a ferroelectric orthorhombic phase.

[0014] A metal gate with a thickness of 50~100nm is obtained by magnetron sputtering of one of TiN and W on insulating gate dielectric layers 105, 106 and ferroelectric layers 103, 104, and the top metal gate 101 and bottom metal gate 102 are respectively patterned.

[0015] The dual-gate ferroelectric field-effect transistor structure material is obtained by means of a top metal gate 101, a bottom metal gate 102, ferroelectric layers 103 and 104, and insulating gate dielectric layers 105 and 106.

[0016] Further, S2 includes:

[0017] Connect the top metal grid 101, the bottom metal grid 102, the channel 107, and the MFIS stacked structure;

[0018] The MFIS stacked structure is respectively covered above and below the channel 107;

[0019] The top metal grid 101 covers the MFIS stack structure above the channel 107;

[0020] The bottom metal grid 102 covers the underside of the MFIS stacked structure below the channel 107;

[0021] After the connection is completed, a dual-gate ferroelectric field-effect transistor structure is obtained.

[0022] Furthermore, the MFIS stacked structure includes: ferroelectric layers 103 and 104 and insulating gate dielectric layers 105 and 106;

[0023] The insulating gate dielectric layers 105 and 106 are disposed in the middle of the ferroelectric layers 103 and 104 and the channel 107;

[0024] The ferroelectric layers 103 and 104 are disposed in the middle of the top metal gate 101, the bottom metal gate 102 and the insulating gate dielectric layers 105 and 106.

[0025] Furthermore, the ferroelectric layers 103 and 104 are made of HZO material with a thickness of 8-10 nm, the insulating gate dielectric layers 105 and 106 are 1-10 nm thick, the insulating gate dielectric layers 105 and 106 are 1-2 nm thick SiO2, the gate material of the top metal gate 101 and the bottom metal gate 102 is TiN or W, the channel is p-type, and the source and drain regions are n-type heavily doped.

[0026] Further, S3 includes:

[0027] After entering the pMOS operating mode, a write operation is performed on the dual-gate ferroelectric field-effect transistor structure;

[0028] During the write operation, the voltage of the top metal gate 101 and the bottom metal gate 102 is controlled, and control judgment information is obtained by detecting the change of drain current.

[0029] Furthermore, during the write operation, voltage control is applied to the top metal gate 101 and the bottom metal gate 102, and control judgment information is obtained by detecting changes in drain current, including:

[0030] Simultaneously apply write voltage pulses of the same magnitude but opposite polarity to the top metal gate 101 and the bottom metal gate 102 to change the polarization direction of the top metal gate 101 and the bottom metal gate 102, thereby adjusting the channel carrier concentration and threshold voltage.

[0031] During the addressing operation, voltage scans of the same magnitude but opposite polarity are applied to the top metal gate 101 and the bottom metal gate 102. The matching state is determined by detecting changes in the drain current, and matching state determination information is obtained.

[0032] Furthermore, the step of controlling the voltage of the top metal gate 101 and the bottom metal gate 102 during the write operation and obtaining control judgment information by detecting changes in drain current also includes:

[0033] Apply read voltages of opposite polarity to the top metal gate 101 and the bottom metal gate 102;

[0034] When the voltage of the top metal gate 101 is at its negative maximum value and the voltage of the bottom metal gate 102 is at its positive maximum value, the upper half of the channel is closed and the lower half of the channel is open, and the current is output from the lower half of the channel.

[0035] When the absolute value of the read voltage between the top metal gate 101 and the bottom metal gate 102 decreases, the lower half of the channel is turned off;

[0036] When both the upper and lower half of the channel are turned off, the absolute value of the bias voltage of the corresponding top metal gate 101 or bottom metal gate 102 is defined as the address point.

[0037] Increasing the voltage of the top metal gate 101 and decreasing the voltage of the bottom metal gate 102 turns on the upper half of the channel and turns off the lower half of the channel, causing the current to rise again.

[0038] Further, S4 includes:

[0039] During the read operation, the sum of the voltages of the top metal gate 101 and the bottom metal gate 102 is controlled to be zero. A voltage scan is performed on one of the gates, while the other gate is adjusted to meet the symmetry condition, and the changes in current and voltage are tested.

[0040] When the drain current drops to a minimum value, the absolute value of the bias voltage of the top metal gate 101 or the bottom metal gate 102 is determined to be the address point information of the storage state.

[0041] Generate multi-value addressing function based on address point information.

[0042] Furthermore, the function of generating multi-value addressing based on addressing point information includes:

[0043] The addressing points corresponding to different polarization combinations in ferroelectric layers 103 and 104 are obtained at different positions on the voltage scan axis, thereby obtaining multiple addressing points and generating a multi-value addressing function.

[0044] The beneficial effects of this invention are as follows: This invention proposes a method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor. Utilizing the non-volatility and programmability of a single ferroelectric field-effect transistor, combined with the modulation capability of the dual gates on their respective underlying conductive channels, multi-valued addressing characteristics are achieved. This reduces the number of transistors required to implement multi-valued addressing, thereby increasing storage density. Compared to existing 2T-FeFET or 6T-2ReRAM architectures, this invention requires only a single dual-gate FeFET to achieve multi-valued addressing, reducing device area by more than half, lowering power consumption, and increasing integration density. This makes it suitable for high-speed search module integration in high-performance computing and artificial intelligence chips. Attached Figure Description

[0045] Figure 1 This is a 2D structure diagram of a dual-gate ferroelectric field-effect transistor;

[0046] Figure 2 The waveforms of write voltage and address voltage for implementing the addresser function of a dual-gate ferroelectric field-effect transistor;

[0047] Figure 3 This is a schematic diagram of the current output curve of a dual-gate ferroelectric field-effect transistor.

[0048] Figure 4 A schematic diagram illustrating current reading using the programmability of ferroelectric materials to achieve multi-value addressing functionality;

[0049] Figure 5 This diagram illustrates the different states of polarization reversal within the ferroelectric layer corresponding to different addressing voltages.

[0050] Explanation of reference numerals in the attached figures: 101, top metal grid; 102, bottom metal grid; 103, 104, ferroelectric layers; 105, 106, insulating grid dielectric layers; 107, channel. Detailed Implementation

[0051] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0052] One embodiment of the present invention provides a method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor, the method comprising:

[0053] S1. Fabricate the top metal gate 101, bottom metal gate 102, channel 107 and MFIS stacked structure to obtain the dual-gate ferroelectric effect transistor structure material.

[0054] S2. Construct a dual-gate ferroelectric field-effect transistor structure using a dual-gate ferroelectric field-effect transistor structure material, and enter the pMOS type working mode through the dual-gate ferroelectric field-effect transistor.

[0055] S3. Based on the dual-gate ferroelectric field-effect transistor structure, the voltage of the top metal gate 101 and the bottom metal gate 102 is controlled and adjusted to obtain control judgment information.

[0056] S4. By controlling the sum of the voltages of the top metal gate 101 and the bottom metal gate 102, voltage scanning is performed to obtain the addressing point, thereby obtaining the multi-value addressing function.

[0057] The working principle and technical effects of the above technical solution are as follows: Figure 1 This is a schematic diagram of the structure of the dual-gate ferroelectric field-effect transistor of the present invention. The top metal gate 101 and the bottom metal gate 102 respectively cover the MFIS stacked structure above and below the channel 107. The ferroelectric layers 103 and 104 are made of HZO material with a thickness of 8~10nm. The insulating gate dielectric layers 105 and 106 are made of SiO2 with a thickness of 1~2nm. The gate material is TiN or W. The channel is p-type. The source and drain regions are n-type heavily doped to achieve pMOS type operation mode.

[0058] The fabrication method of the dual-gate ferroelectric field-effect transistor of the present invention is as follows: First, a channel region and a source / drain region are formed on a Si substrate. The channel region is p-type doped, and the source / drain regions on both sides are doped with n-type high concentration doping, opposite to that of the channel, to achieve good ohmic contact. Then, an insulating gate dielectric layer and a ferroelectric thin film layer are deposited sequentially on both sides of the channel region—a 1-2 nm thick SiO2 layer is deposited as the insulating gate dielectric layer using an ALD process to suppress interface traps and improve carrier mobility; then, an 8-10 nm thick HZO layer is deposited as the ferroelectric thin film layer using an ALD process, and subjected to 550℃ and 30 s annealing. Rapid thermal annealing (RTA) induces the formation of a ferroelectric orthorhombic phase. Finally, TiN or W is deposited as the metal gate on the insulating gate dielectric layer and the ferroelectric thin film layer using magnetron sputtering, with a thickness of 50-100 nm. The top metal gate (TG) and bottom metal gate (BG) are patterned accordingly. The upper and lower gates, ferroelectric layers, and dielectric layer structures form a metal-ferroelectric-insulator-semiconductor (MFIS) stack structure, corresponding to the upper and lower surfaces of the channel to constitute a dual-gate structure. Finally, metal contacts are deposited and patterned to complete the fabrication of the source and drain electrodes, thus obtaining the desired structure. Figure 1 The device structure shown.

[0059] like Figure 2 As shown, during the write operation, the present invention applies write voltage pulses of the same magnitude but opposite polarity (e.g., ±3V, pulse width 1μs) to TG and BG simultaneously. By utilizing the programmability and non-volatility of the ferroelectric layer, its polarization direction is changed, thereby adjusting the channel carrier concentration and threshold voltage. During the addressing (reading) operation, voltage scans of equal magnitude but opposite direction are applied to TG and BG (VTG+VBG=0), and the matching state is determined by detecting changes in drain current.

[0060] like Figure 3 As shown, when TG and BG are applied with read voltages in opposite directions, when TG voltage is at its negative maximum value (e.g., -0.5V) and BG voltage is at its positive maximum value (e.g., +0.5V), the upper half of the channel is closed, and the lower half is on, with the device current mainly contributed by the lower channel. As the absolute values ​​of the TG and BG read voltages decrease, the lower half of the channel gradually turns off. When both channels are off (the device current reaches its minimum), the corresponding TG / BG bias voltage is defined as the address point. Further increasing the TG voltage and decreasing the BG voltage turns on the upper half of the channel while keeping the lower half off, and the device current rises again. By adjusting the polarization combination, this address point can be moved to different voltages, realizing multi-value addressing functionality.

[0061] like Figure 4 and Figure 5As shown, this invention establishes different polarization combinations in the ferroelectric layers (P_TG, P_BG) of a dual-gate system by applying write pulses with adjustable amplitude and settable polarity to TG and BG respectively. This alters the carrier modulation effect of the corresponding channels, i.e., changing the carrier concentration in the top and bottom channels causes a corresponding shift in the channel's equivalent threshold voltage. During simultaneous writing to both gates, different polarization combinations lead to a regular migration of the matching point position in the symmetrical search bias mode (VTG+VBG=0). During the read operation, the sum of the voltages of TG and BG is kept zero. A voltage scan is performed on one gate (e.g., TG), while the other gate is adjusted to satisfy the symmetry condition, and the current-voltage change is tested. When the drain current drops to a minimum, the TG / BG bias at this point is determined as the "address point" of the storage state. Different polarization combinations in the ferroelectric layer (e.g., ...) Figure 5 The addressing points (00, 01, 10, 11) are distributed at different positions on the voltage scan axis, thus obtaining multiple addressing points (00, 01, 10, 11), thereby realizing multi-value addressing within a single device. This method can precisely control the number and interval of addressing points by adjusting the amplitude, polarity, and duration of the write pulse to meet different storage density and matching accuracy requirements.

[0062] First, a dual-gate ferroelectric field-effect transistor (FET) structure material is fabricated. A structure containing an MFIS stack is formed through a specific process, where the ferroelectric layer is made of HZO material, which is annealed to form a ferroelectric orthorhombic phase. The insulating gate dielectric layer uses SiO2 to suppress interface traps. The transistor structure is then constructed and put into pMOS mode. During writing, voltage pulses of equal magnitude but opposite polarity are applied to both gates, utilizing the non-volatility of ferroelectric polarization to adjust the channel carrier concentration and threshold voltage. During reading, the sum of the two gate voltages is kept zero during scanning, and the addressing point is determined based on changes in the drain current. By changing the addressing point position through different polarization combinations, multi-valued addressing is achieved.

[0063] Employing a dual-gate MFIS structure and leveraging the programmability and non-volatility of HZO ferroelectric materials, a single device can achieve multi-value addressing, thereby increasing storage density. ALD technology and rapid thermal annealing ensure stable material performance, while symmetrical voltage control improves matching accuracy. Different storage and accuracy requirements can be met by adjusting the write pulse parameters, providing an effective solution for the development of high-density memory devices.

[0064] In one embodiment of the present invention, S1 includes:

[0065] A channel region and a source / drain region are formed on a Si substrate. The channel region is p-type doped, and the source / drain regions on both sides are n-type doped. Insulating gate dielectric layers 105 and 106 and ferroelectric layers 103 and 104 are deposited sequentially on both sides of the channel region.

[0066] The insulating gate dielectric layers 105 and 106 are obtained by depositing 1-2 nm thick SiO2 using an ALD process.

[0067] The ferroelectric layers 103 and 104 are obtained by depositing 8-10 nm thick HZO using the ALD process and then undergoing rapid thermal annealing at 550 °C for 30 s to form a ferroelectric orthorhombic phase.

[0068] A metal gate with a thickness of 50~100nm is obtained by magnetron sputtering of one of TiN and W on insulating gate dielectric layers 105, 106 and ferroelectric layers 103, 104, and the top metal gate 101 and bottom metal gate 102 are respectively patterned.

[0069] The dual-gate ferroelectric field-effect transistor structure material is obtained by means of a top metal gate 101, a bottom metal gate 102, ferroelectric layers 103 and 104, and insulating gate dielectric layers 105 and 106.

[0070] The working principle and technical effects of the above solution are as follows: First, a p-type channel region and an n-type source / drain region are defined on a Si substrate to ensure good ohmic contact. A SiO2 insulating gate dielectric layer and an HZO ferroelectric layer are sequentially deposited using an ALD process. The HZO layer is annealed at a specific temperature to form a ferroelectric orthogonal phase. TiN or W is deposited as a metal gate by magnetron sputtering and patterned, ultimately forming a structure material containing a dual-gate and MFIS stack. The thickness of each layer and process parameters are strictly controlled throughout the process to ensure that each structural layer functions normally and is tightly bonded.

[0071] Precise selection of doping types and process control ensure the electrical characteristics of the source / drain regions and the channel are matched. The SiO2 layer prepared by the ALD process effectively suppresses interface traps and improves carrier mobility; the HZO ferroelectric layer, after optimized annealing, exhibits stable ferroelectric properties. The selection of materials and fabrication process for the metal gate ensures gate conductivity and structural stability, and the high controllability of each process step facilitates mass production.

[0072] In one embodiment of the present invention, S2 includes:

[0073] Connect the top metal grid 101, the bottom metal grid 102, the channel 107, and the MFIS stacked structure;

[0074] The MFIS stacked structure is respectively covered above and below the channel 107;

[0075] The top metal grid 101 covers the MFIS stack structure above the channel 107;

[0076] The bottom metal grid 102 covers the underside of the MFIS stacked structure below the channel 107;

[0077] After the connection is completed, a dual-gate ferroelectric transistor structure is obtained, such as... Figure 1 As shown.

[0078] The working principle and technical effect of the above technical solution are as follows: The prepared MFIS stack is respectively covered above and below the p-type channel. Then, the top metal gate is covered on the upper MFIS stack, and the bottom metal gate is covered on the lower MFIS stack. Through precise structural connection and positioning, a complete double-gate ferroelectric field-effect transistor structure is constructed. This process ensures accurate correspondence between components, good contact between the MFIS stack and the channel and metal gate, and guarantees a smooth charge transport path.

[0079] The rational structural layout allows for independent and coordinated voltage control of the upper and lower sections of the channel via dual gates. Precise coverage and connection methods reduce contact resistance, lower signal loss, and ensure stable operation of the transistor after entering pMOS mode. High structural stability effectively avoids device performance abnormalities caused by component misalignment, thus improving device reliability.

[0080] In one embodiment of the present invention, the MFIS stacked structure includes: ferroelectric layers 103 and 104 and insulating gate dielectric layers 105 and 106;

[0081] The insulating gate dielectric layers 105 and 106 are disposed in the middle of the ferroelectric layers 103 and 104 and the channel 107;

[0082] The ferroelectric layers 103 and 104 are disposed in the middle of the top metal gate 101, the bottom metal gate 102 and the insulating gate dielectric layers 105 and 106.

[0083] The ferroelectric layers 103 and 104 are made of HZO material with a thickness of 8-10 nm. The insulating gate dielectric layers 105 and 106 are 1-10 nm thick and are made of SiO2 with a thickness of 1-2 nm. The gate materials of the top metal gate 101 and the bottom metal gate 102 are TiN or W. The channel is p-type and the source and drain regions are n-type heavily doped.

[0084] The working principle and technical effects of the above technical solution are as follows: The MFIS stack consists of a ferroelectric layer and an insulating gate dielectric layer. The insulating gate dielectric layer is located between the ferroelectric layer and the channel, and the ferroelectric layer is located between the metal gate and the insulating gate dielectric layer. The ferroelectric layer uses HZO material, and its polarization direction can be adjusted by voltage due to its ferroelectric properties. The insulating gate dielectric layer uses SiO2 to block direct charge tunneling and suppress interface traps. The p-type channel and the heavily doped n-type source / drain regions work together to enable the device to operate stably in pMOS mode. The metal gate uses highly conductive TiN or W to ensure effective voltage signal transmission.

[0085] The layered structure achieves the dual functions of ferroelectric control and charge isolation. The SiO2 insulating layer improves the device's insulation performance and carrier mobility, while the non-volatility of the HZO ferroelectric layer enables the device to maintain a polarized state for a long time, reducing energy consumption. The optimized selection of materials and thicknesses for each layer balances the device's electrical performance and structural stability, providing a core structural guarantee for the realization of multi-valued addressing functions. Furthermore, it exhibits good material compatibility and is easy to integrate with existing semiconductor processes.

[0086] In one embodiment of the present invention, S3 includes:

[0087] After entering the pMOS operating mode, a write operation is performed on the dual-gate ferroelectric field-effect transistor structure;

[0088] During the write operation, the voltage of the top metal gate 101 and the bottom metal gate 102 is controlled, and control judgment information is obtained by detecting the change of drain current.

[0089] The working principle and technical effect of the above technical solution are as follows: After the device enters pMOS mode, a voltage control is applied to the dual gate during the write operation. By changing the dual gate voltage, the polarization state of the ferroelectric layer is adjusted, thereby changing the channel carrier concentration and threshold voltage. During the addressing operation, based on the polarization state after writing, a specific voltage is applied to the dual gate. By detecting the change in drain current, the current matching state of the device is determined, thereby obtaining control judgment information.

[0090] Voltage control during write operations enables programmable adjustment of the device's electrical characteristics. Based on the non-volatility of ferroelectric materials, the adjusted state can be stably maintained, reducing energy consumption from repeated writes. Control judgment information is obtained through drain current detection, a method that is intuitive and highly sensitive, quickly and accurately reflecting the device's operating state and improving its efficiency and accuracy.

[0091] In one embodiment of the present invention, during the write operation, voltage control is applied to the top metal gate 101 and the bottom metal gate 102, and control judgment information is obtained by detecting changes in drain current, including:

[0092] Simultaneously apply write voltage pulses of the same magnitude but opposite polarity to the top metal gate 101 and the bottom metal gate 102 to change the polarization direction of the top metal gate 101 and the bottom metal gate 102, thereby adjusting the channel carrier concentration and threshold voltage.

[0093] During the addressing operation, voltages of the same magnitude but opposite polarity are applied to the top metal gate 101 and the bottom metal gate 102. The matching state is determined by detecting changes in the drain current, and matching state determination information is obtained, such as... Figure 2As shown. That is, after changing the write voltage to determine different storage states (such as 00, 01, 10, 11), by applying a symmetrical scan voltage and monitoring the change in drain current, the corresponding minimum point can be obtained on the scan curve. These discrete voltage positions correspond one-to-one with the write state, thereby completing the multi-value addressing function.

[0094] The working principle and technical effect of the above technical solution are as follows: During writing, voltage pulses of the same magnitude but opposite polarity are applied to the dual gates. Utilizing the polarization reversal characteristic of ferroelectric materials, the polarization direction of the dual-gate ferroelectric layer is changed, thereby adjusting the channel carrier concentration and threshold voltage to achieve information storage. During addressing, the same voltage scan with opposite polarity is applied. As the voltage changes, the channel conduction state gradually changes. The upper half-channel and the lower half-channel sequentially undergo conduction and turn-off processes. When both channels are turned off, the drain current is minimal, and the corresponding voltage is the address point. The address point position can be changed by polarization combination.

[0095] The symmetrical voltage pulse design enables more balanced polarization regulation of the dual gates, improving the consistency and stability of the device's electrical characteristic regulation. Addressing points are precisely captured through current variations, ensuring reliable judgment. Furthermore, addressing point regulation based on polarization combinations provides a means to implement multi-value addressing functionality. This operation mode features low power consumption, fast response speed, and optimizable pulse width and voltage parameters, adapting to different application scenarios and enhancing the device's flexibility and practicality.

[0096] In one embodiment of the present invention, the step of voltage control of the top metal gate 101 and the bottom metal gate 102 during the write operation, and obtaining control judgment information by detecting changes in drain current, further includes:

[0097] Apply read voltages of opposite polarity to the top metal gate 101 and the bottom metal gate 102;

[0098] When the voltage of the top metal gate 101 is at its negative maximum value and the voltage of the bottom metal gate 102 is at its positive maximum value, the upper half of the channel is closed and the lower half of the channel is open, and the current is output from the lower half of the channel; the upper half of the channel is the half of the channel closest to the top electrode, and the lower half of the channel is the half of the channel closest to the bottom electrode.

[0099] When the absolute value of the read voltage between the top metal gate 101 and the bottom metal gate 102 decreases, the lower half of the channel is turned off;

[0100] When both the upper and lower half of the channel are turned off, the absolute value of the bias voltage of the corresponding top metal gate 101 or bottom metal gate 102 is defined as the address point.

[0101] Increasing the voltage of the top metal gate 101 and decreasing the voltage of the bottom metal gate 102 turns on the upper half of the channel and turns off the lower half, causing the current to rise again. By adjusting the polarization combination, the address point can be moved to different voltages, achieving multi-value addressing functionality, such as... Figure 3 As shown.

[0102] The working principle and technical effect of the above technical solution are as follows: During the write operation phase, in addition to applying voltage pulses of the same magnitude but opposite polarity, the dynamic control of the channel conduction state is achieved by precisely controlling the difference in read voltage polarity between the top metal gate 101 and the bottom metal gate 102. When the top gate voltage is at its negative maximum value and the bottom gate voltage is at its positive maximum value, the modulation effect of the electric field on the carriers causes the upper half-channel to be depleted and turned off, while the lower half-channel is enriched and turned on. At this time, the device current is mainly contributed by the lower half-channel. As the absolute value of the negative voltage of the top gate decreases and the positive voltage of the bottom gate decreases synchronously, the carrier concentration in the lower half-channel gradually decreases until both channels are turned off due to carrier depletion. At this time, the drain current reaches its minimum value, and the corresponding gate bias voltage is defined as the address point. Continuing to adjust the gate voltage, the top gate voltage increases and the bottom gate voltage decreases, the upper half-channel restarts carrier transport, the lower half-channel remains off, and the device current rises again. By changing the polarization combination of the ferroelectric layer, the position of the addressing point on the voltage axis can be dynamically adjusted.

[0103] Through refined voltage gradient control, step-by-step switching of the channel conduction state is achieved, making address point determination more accurate and repeatable. By utilizing the coordinated adjustment of voltage polarity and amplitude, the variation of channel current can be flexibly controlled, avoiding the address point ambiguity problem caused by single voltage control. Simultaneously, based on the address point migration characteristics of polarization combinations, the implementation path of multi-value addressing is further expanded, enabling a single device to support more storage states, improving storage density and data processing efficiency. The operation process requires no complex external circuitry, reducing device integration difficulty, and the significant current variation facilitates subsequent signal detection and processing, enhancing the stability and reliability of device operation.

[0104] In one embodiment of the present invention, S4 includes:

[0105] During the read operation, the sum of the voltages of the top metal gate 101 and the bottom metal gate 102 is kept to zero. A voltage scan is performed on one gate while the other gate is adjusted to meet symmetry conditions. Changes in current and voltage are tested, such as... Figure 4 As shown;

[0106] When the drain current drops to a minimum value, the absolute value of the bias voltage of the top metal gate 101 or the bottom metal gate 102 is determined to be the address point information of the storage state.

[0107] Generate multi-value addressing function based on address point information.

[0108] The function of generating multi-value addressing based on addressing point information includes:

[0109] Obtain different polarization combinations in ferroelectric layers 103 and 104, such as Figure 5 The addressing points shown are distributed at different positions on the voltage scanning axis, thereby obtaining multiple addressing points and generating a multi-value addressing function.

[0110] The working principle and technical effect of the above solution are as follows: During the read operation, the sum of the dual gate voltages is kept zero. One gate is scanned while the other gate is adjusted synchronously to ensure voltage symmetry. During this process, the relationship between drain current and voltage is tested in real time. When the drain current drops to its minimum value, the corresponding dual-gate bias voltage is the address point for that storage state. Since different polarization combinations of the ferroelectric layer will cause the address points to be distributed at different positions on the voltage scan axis, multiple address points are obtained, ultimately generating a multi-value addressing function.

[0111] The symmetrical voltage scanning mode ensures the stability of the testing environment, reduces the impact of external interference on address point judgment, and improves the accuracy of address point detection. By acquiring multiple address points based on different polarization combinations, multi-value addressing of a single device is achieved, significantly increasing storage density. Furthermore, the address point distribution is controllable, and the address point interval can be optimized by adjusting the polarization combination to meet different storage accuracy requirements, providing an efficient solution for high-density information storage and processing.

[0112] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor, characterized in that, The method includes: S1. The top metal gate (101), bottom metal gate (102), channel (107) and MFIS stacked structure are fabricated to obtain the dual-gate ferroelectric effect transistor structure material. S2. Construct a dual-gate ferroelectric field-effect transistor structure using a dual-gate ferroelectric field-effect transistor structure material, and enter the pMOS type working mode through the dual-gate ferroelectric field-effect transistor. S3. Based on the dual-gate ferroelectric field-effect transistor structure, the voltage of the top metal gate (101) and the bottom metal gate (102) is controlled and adjusted to obtain control judgment information; S4. By controlling the sum of the voltages of the top metal gate (101) and the bottom metal gate (102), voltage scanning is performed to obtain the addressing point, thereby obtaining the multi-value addressing function; Wherein, S3 includes: After entering the pMOS operating mode, a write operation is performed on the dual-gate ferroelectric field-effect transistor structure; During the write operation, the voltage of the top metal gate (101) and the bottom metal gate (102) is controlled, and control judgment information is obtained by detecting the change of drain current. Wherein, S4 includes: During the read operation, the sum of the voltages of the top metal gate (101) and the bottom metal gate (102) is controlled to be zero. A voltage scan is performed on one of the gates, while the other gate is adjusted to meet the symmetry condition. The changes in current and voltage are tested. When the drain current drops to a minimum value, the absolute value of the bias voltage of the top metal gate (101) or the bottom metal gate (102) is determined to be the address point information of the storage state; Generate multi-value addressing function based on address point information.

2. The method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor according to claim 1, characterized in that, S1 includes: A channel region and a source / drain region are formed on a Si substrate. The channel region is p-type doped, and the source / drain regions on both sides are n-type doped. An insulating gate dielectric layer (105, 106) and a ferroelectric layer (103, 104) are deposited sequentially on both sides of the channel region. The insulating gate dielectric layer (105, 106) is obtained by depositing 1~2nm thick SiO2 using the ALD process; The ferroelectric layers (103, 104) are obtained by depositing 8-10 nm thick HZO using the ALD process and then undergoing rapid thermal annealing at 550 °C for 30 s to form a ferroelectric orthorhombic phase. A metal gate with a thickness of 50~100nm is obtained by magnetron sputtering of one of TiN and W on the insulating gate dielectric layer (105, 106) and the ferroelectric layer (103, 104), and the top metal gate (101) and bottom metal gate (102) are respectively patterned. The dual-gate ferroelectric field-effect transistor structure material is obtained by using a top metal gate (101), a bottom metal gate (102), ferroelectric layers (103, 104), and an insulating gate dielectric layer (105, 106).

3. The method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor according to claim 1, characterized in that, S2 includes: The top metal grid (101), bottom metal grid (102), channel (107) and MFIS stacked structure are connected; The MFIS stacked structure is respectively covered above and below the channel (107); The top metal grid (101) is placed over the MFIS stack structure above the channel (107); The bottom metal grid (102) is placed below the MFIS stacked structure below the channel (107); After the connection is completed, a dual-gate ferroelectric field-effect transistor structure is obtained.

4. The method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor according to claim 2, characterized in that, The MFIS stacked structure includes: ferroelectric layers (103, 104) and insulating gate dielectric layers (105, 106). The insulating gate dielectric layer (105, 106) is disposed in the middle part between the ferroelectric layer (103, 104) and the channel (107); The ferroelectric layers (103, 104) are disposed in the middle of the top metal gate (101), the bottom metal gate (102) and the insulating gate dielectric layer (105, 106).

5. The method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor according to claim 4, characterized in that, The ferroelectric layers (103, 104) are made of HZO material with a thickness of 8~10nm, the insulating gate dielectric layers (105, 106) are made of SiO2 with a thickness of 1~2nm, the gate materials of the top metal gate (101) and the bottom metal gate (102) are TiN or W, the channel is p-type, and the source and drain regions are n-type heavily doped.

6. The method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor according to claim 1, characterized in that, During the write operation, voltage control is applied to the top metal gate (101) and the bottom metal gate (102), and control judgment information is obtained by detecting changes in drain current, including: Write voltage pulses of the same magnitude but opposite polarity are applied simultaneously to the top metal gate (101) and the bottom metal gate (102) to change the polarization direction of the top metal gate (101) and the bottom metal gate (102), thereby adjusting the channel carrier concentration and threshold voltage. During the addressing operation, voltage scans of the same magnitude but opposite polarity are applied to the top metal gate (101) and the bottom metal gate (102). The matching state is determined by detecting the change in drain current, and matching state determination information is obtained.

7. The method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor according to claim 1, characterized in that, During the write operation, voltage control is applied to the top metal gate (101) and the bottom metal gate (102), and control judgment information is obtained by detecting changes in drain current. The method also includes: Apply read voltages of opposite polarity to the top metal gate (101) and the bottom metal gate (102); When the voltage of the top metal gate (101) is at its negative maximum value and the voltage of the bottom metal gate (102) is at its positive maximum value, the upper half of the channel is closed and the lower half of the channel is open, and the current is output from the lower half of the channel; When the absolute value of the read voltage between the top metal gate (101) and the bottom metal gate (102) decreases, the lower half of the channel is turned off; When both the upper and lower half of the channel are turned off, the absolute value of the bias voltage of the corresponding top metal gate (101) or bottom metal gate (102) is defined as the address point. Increasing the voltage of the top metal gate (101) and decreasing the voltage of the bottom metal gate (102) turns the upper half of the channel on and turns the lower half of the channel off, causing the current to rise again.

8. The method for implementing a multi-valued addresser using a dual-gate ferroelectric field-effect transistor according to claim 1, characterized in that, The function of generating multi-value addressing based on addressing point information includes: The addressing points corresponding to different polarization combinations in the ferroelectric layers (103, 104) are distributed at different positions on the voltage scan axis, thereby obtaining multiple addressing points and generating a multi-value addressing function.

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