Manufacturing method of double-sided wire-embedded printed circuit board

Abstract

The invention discloses a method for manufacturing a double-sided wire-embedded printed circuit board. The method comprises the following steps of: processing an inner layer; pressing the insulating layer; manufacturing a via hole; the photosensitive insulating layer is pasted on the surface of the plate in a film pasting mode; transferring a circuit pattern to the insulating layer by using a pattern transfer technology, removing unnecessary parts by using development, and then completely curing the insulating layer by using a heating curing mode; a thin copper conduction layer is manufactured on the surface of the plate in a chemical copper deposition or copper sputtering mode; film pasting: pasting a circuit dry film on the surface of the board; transferring the pattern to the dry film again by using a pattern transfer technology; filling the pattern area through electroplating until the insulating layer is fully filled, and forming a wire embedding structure; removing the film; and etching to finally complete the manufacturing of the wire-embedded printed circuit board. According to the wire-embedded circuit board manufactured by the invention, double-sided processing is carried out, a double-sided wire-embedded structure can be manufactured, the production period is shortened, and due to the existence of the core board, the mechanical strength of the board is good, and the board is not easy to warp.

Description

Technical Field

[0001] This invention belongs to the field of printed circuit board manufacturing technology, specifically relating to a method for manufacturing a double-sided embedded wire printed circuit board. Background Technology

[0002] As electronic devices evolve towards higher density and miniaturization, embedded wire substrates, as a key carrier for realizing three-dimensional circuit interconnects, occupy a pivotal position in modern electronics manufacturing. This technology enables complex circuit layouts within limited space, directly determining the performance and market competitiveness of high-end electronic products.

[0003] In existing technology, taking a 4-layer buried wire printed circuit board as an example, its manufacturing process is as follows: Figures 2-1 to 2-10 As shown, specifically: A copper foil is attached to a support plate; a layer of circuit dry film is attached to the copper foil; the circuit pattern is transferred to the dry film using pattern transfer technology, and unwanted parts are removed using development; the pattern area is filled using electroplating; the circuit dry film is removed using a film remover; lamination is performed to form a buried wire structure; other layers of circuit processing are continued according to the conventional printed circuit board process; processing continues until the target number of layers is reached; the completed board is peeled off from the support plate; the copper surface of the buried wire layer is etched away using etching technology to expose the circuit, thus producing the finished buried wire board.

[0004] The above production process has the following problems: The technical purpose of embedded wire substrates is to protect the line width by laminating the insulating layer during semi-additive processing, and to etch away the conductive copper layer from the bottom, while protecting the line width from loss during etching, thus further improving the processing capability of fine lines. However, this processing method can only achieve single-sided embedded wire processing and requires the use of a support board, i.e., using a coreless substrate process, which has certain processing difficulties and cost waste of support board. In addition, the single-sided processing mode has a long processing cycle, and the finished board without a core board is also prone to insufficient support and board warping problems. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing a double-sided embedded wire printed circuit board, which addresses the shortcomings of the prior art. The embedded wire circuit board is processed from both sides, which can create a double-sided embedded wire structure, shorten the production cycle, and the mechanical strength of the board is good due to the presence of the core board, making it less prone to warping.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a method for manufacturing a double-sided embedded wire printed circuit board, comprising the following steps: Inner layer processing: The inner core board is processed using standard printed circuit board (PCB) processes; Insulation layer lamination: The insulation layer is laminated using a lamination process; Through-hole fabrication: Through-holes are fabricated using laser drilling; Insulating layer lamination: A photosensitive insulating layer is applied to the surface of the board using a lamination method; Post-pattern transfer curing: Using pattern transfer technology, the circuit pattern is transferred onto the insulating layer. Unwanted parts are removed using development, and then the insulating layer is completely cured using heat curing. Fabrication of the conductive layer: A thin copper conductive layer is fabricated on the surface of the board using chemical plating or sputtering methods; Film application: Applying a dry film to the surface of the circuit board; Pattern transfer: The pattern is transferred again onto the dry film using pattern transfer technology; unwanted areas are removed using development. Pattern electroplating: Electroplating is used to fill the patterned area until the insulating layer is completely filled, forming a buried wire structure; Film removal: Use film removal solution to remove the dry film from the circuit board; Etching: Using etching technology, the conductive layer on the surface of the insulating layer is removed, and the fabrication of the embedded wire printed circuit board is finally completed.

[0007] The above-mentioned method for manufacturing a double-sided embedded wire printed circuit board uses laser drilling to create vias. The specific process is as follows: A high-resolution camera was used to acquire images of the insulating layer's graphic structure; Enhance the edge contrast of the via using image preprocessing algorithms; An edge detection algorithm is used to identify the contour boundary of the via; Calculate the geometric center coordinates of the through hole profile; Establish the conversion relationship between pixel coordinates and actual physical coordinates; If the position deviation of the through hole exceeds the allowable range, the deviation data is recorded and a position correction command is generated; Perform statistical analysis on the measurement results to evaluate the overall positional accuracy; Construct a dataset containing the precise coordinates of all vias; Laser drilling is used to create through holes.

[0008] The above-mentioned method for manufacturing a double-sided embedded printed circuit board utilizes pattern transfer technology to transfer circuit patterns onto an insulating layer, including: performing pattern transfer processing on the insulating layer using a pre-set pattern transfer control strategy, and forming a predetermined circuit pattern on the surface of the insulating layer using precision photolithography.

[0009] The specific process of pre-setting the graphic transfer control strategy in the above-mentioned method for manufacturing a double-sided embedded wire printed circuit board is as follows: The thickness distribution data of the insulation layer on the surface of the inner core board is obtained, and the thickness is measured point by point on the substrate surface using laser scanning measurement technology to obtain a standardized data matrix of the thickness distribution. Based on the thickness distribution data matrix, a mapping relationship model between the insulating layer and the conductive layer is established using a multilayer perceptron algorithm to obtain a targeted pattern transfer control strategy.

[0010] The above-mentioned method for manufacturing a double-sided embedded wire printed circuit board employs laser scanning measurement technology to perform point-by-point thickness detection on the substrate surface, including: The substrate surface is scanned by a laser beam, the time difference of the laser reflection signal is measured, and the thickness value at each measurement point is calculated. If the detected thickness change exceeds the preset threshold range, an adaptive threshold segmentation algorithm is used to mark and identify the abnormal area; The measured thickness data is normalized to eliminate the influence of systematic errors; Construct a two-dimensional thickness distribution matrix to record the coordinate position and corresponding thickness value of each measurement point; Repeated measurements were performed on the abnormal area to verify the authenticity of the thickness anomaly; Generate a visual image of the thickness distribution, identifying the regions where thickness varies.

[0011] The above-mentioned method for manufacturing a double-sided embedded wire printed circuit board employs a multilayer perceptron algorithm to establish a mapping relationship model between the insulating layer and the conductive layer, including: Collect correlation data between graphic transfer accuracy and changes in material properties from historical manufacturing data; Construct a multi-layer neural network structure and set the input layer to receive thickness distribution data; By using hidden layers to process complex nonlinear mapping relationships, key feature parameters are extracted. The output layer generates prediction results for the optimal combination of process parameters; The backpropagation algorithm is used to train the network weights and optimize the model's prediction accuracy. The generalization ability of the model is evaluated using cross-validation. Analyze the similarity between the current substrate condition and historical data to determine the applicability of the model; Generate personalized process parameter recommendations based on the characteristics of the current substrate.

[0012] The above-mentioned method for manufacturing a double-sided embedded wire printed circuit board uses precision photolithography to form a predetermined circuit pattern on the surface of an insulating layer, including: A photosensitive adhesive layer is coated on the surface of the insulating layer to control the uniformity of the coating thickness; Set the exposure parameters according to the control strategy, including exposure time and light intensity; A latent image pattern is formed by selectively exposing the photosensitive adhesive layer using a photomask. Perform a developing process to remove the unexposed or exposed photosensitive emulsion portions; Detect the sharpness of graphic edges and the accuracy of line width; If the edge sharpness of the image is below the quality standard, adjust the exposure parameters and re-transfer the image; The pattern is transferred onto the insulating layer through an etching process to form the final pattern structure.

[0013] The above-mentioned method for manufacturing a double-sided embedded wire printed circuit board involves using electroplating to fill the patterned area until the insulating layer is completely filled, forming an embedded wire structure. The specific process is as follows: Prepare the chemical plating solution and control the metal ion concentration; Pre-treating the surface of the insulating layer enhances metal adhesion; The substrate is immersed in a chemical plating solution to initiate an autocatalytic reaction; Control the temperature and pH of the plating solution to maintain the stability of the reaction; Real-time monitoring of thickness changes during the deposition process; If the unevenness of the deposition thickness exceeds the preset standard, adjust the plating solution concentration and reaction time parameters; Ultrasonic assistance can be used to improve the density and uniformity of the coating. After the insulation layer is filled, it is cleaned and dried to form a buried wire structure.

[0014] Compared with the prior art, the present invention has the following advantages: 1. Existing technologies involve first fabricating the circuit layer structure and then laminating it with an insulating layer to form a buried wire structure. This invention creates a conductor cavity within the insulating layer and then fills it with electroplating to form the buried wire structure. Existing buried wire circuit board structures utilize a support plate for single-sided lamination on copper foil, followed by removal of the conductive copper layer at the bottom. This invention uses chemical copper or sputtered copper to form a conductive layer on the surface of the insulating layer, and then removes the conductive layer from the front. Existing buried wire circuit board structures, due to the lack of a core board and single-sided lamination, can only produce single-sided buried wire structures, resulting in long production cycles and a tendency for board warping. The buried wire circuit board produced by this invention is processed from both sides, allowing for double-sided buried wire structures, shortening the production cycle, and due to the presence of a core board, the board has good mechanical strength and is less prone to warping.

[0015] 2. Compared with traditional printed circuit board (PCB) processes, the biggest advantage of embedded wire PCBs is that they can use an insulating layer to protect the circuitry, thereby achieving the purpose of creating fine circuitry. In contrast, existing embedded wire PCB processes can only achieve fine circuitry processing on the outermost single layer. The processing method of this invention can be applied not only to the outer layer of the PCB but also to any layer, thereby improving the overall fine circuitry processing capability of the PCB.

[0016] 3. This invention achieves precise control over the preparation process of the insulating layer and the conductive layer, improves the manufacturing precision and consistency of multilayer printed circuit boards, and effectively solves problems such as insufficient pattern transfer precision and uneven via filling in traditional processes, providing technical support for the manufacturing of high-density interconnect printed circuit boards.

[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention; Figures 2-1 to 2-10 This is a flowchart of the manufacturing process in the existing technology; Figures 3-1 to 3-11 This is a flowchart illustrating the manufacturing process of the present invention; Figure 4 This is a structural comparison diagram between products in the prior art and the product of this invention. Detailed Implementation

[0019] like Figure 1 as well as Figures 3-1 to 3-11 As shown, the method for manufacturing a double-sided embedded wire printed circuit board of the present invention includes the following steps: Step S1, Inner Layer Processing: Process the inner core board using conventional printed circuit board processes; Step S2, Insulation Layer Lamination: The insulation layer is laminated using a lamination process; Step S3, Through-hole fabrication: Through-holes are fabricated using laser drilling; In this embodiment, laser drilling is used to create the through hole in step S3. The specific process is as follows: Step S301: Use a high-resolution camera to acquire images of the insulating layer pattern structure; The high-resolution camera is configured with a pixel resolution of no less than 2048×2048, and the lens focal length is selected from a fixed focal length in the range of 25mm to 50mm according to the size of the detection area to ensure that the physical size of a single pixel is controlled within 1 micrometer. Step S302: Enhance the edge contrast of the via using an image preprocessing algorithm; the specific process is as follows: Step S30201: Perform grayscale conversion processing on the acquired original image, converting the RGB color image into an 8-bit grayscale image with a grayscale value range of 0 to 255; the conversion process adopts a weighted average method, in which the weight of the red channel is 0.299, the weight of the green channel is 0.587, and the weight of the blue channel is 0.114, to ensure that the converted grayscale image can maintain the brightness information of the original image; Step S30202: A Gaussian filter is used to suppress noise in the grayscale image. The filter kernel size is set to 3×3 or 5×5, and the standard deviation parameter is adjusted within the range of 0.5 to 2.0 according to the image noise level. The filtering process is implemented through convolution operation. The new grayscale value of each pixel is calculated by its neighboring pixels according to the Gaussian distribution weight, which effectively reduces random noise in the image and electronic noise generated during the acquisition process. Step S30203: Apply histogram equalization algorithm to enhance the overall contrast of the image. The algorithm first counts the number of pixels at each gray level in the image, calculates the cumulative distribution function, and then maps the original gray values ​​to a new gray range. The mapping function is that the new gray value is equal to 255 multiplied by the cumulative probability, which makes the gray distribution of the processed image more uniform and significantly improves the contrast between the via and the background of the insulating layer. Step S30204: Edge enhancement processing is performed using the Laplacian operator. The Laplacian operator kernel is a 3×3 matrix with a central element of 8 and 8 surrounding elements of -1. The edge information in the image is highlighted through convolution operation. After processing, the Laplacian response image is added to the original image to obtain the edge-enhanced image, making the aperture boundary clearer and sharper. Step S303: Use an edge detection algorithm to identify the contour boundary of the via; the specific process is as follows: Step S30301: Apply the Canny edge detection algorithm to extract the edge of the via. The algorithm first uses the Sobel operator to calculate the gradient magnitude and direction of the image. The gradient magnitude represents the edge intensity, and the gradient direction is used for subsequent non-maximum suppression. The Sobel operator contains two 3×3 convolution kernels, one horizontal and one vertical, to detect edges in the horizontal and vertical directions, respectively. Step S30302: Perform non-maximum suppression processing, compare the gradient magnitude of adjacent pixels along the gradient direction, retain local maximum points, suppress non-maximum points, and make the edge lines thinner; during the suppression process, the gradient direction is quantized into four main directions: 0 degrees, 45 degrees, 90 degrees and 135 degrees, and each pixel is compared with two neighboring pixels in its gradient direction. Step S30303: Use dual threshold processing to determine edge pixels; set a high threshold and a low threshold. The high threshold is usually 2 to 3 times the low threshold. Pixels with gradient magnitude higher than the high threshold are directly marked as edge points, and pixels with gradient magnitude lower than the low threshold are marked as non-edge points. Pixels with gradient magnitude between the two thresholds need to be determined as edge points through connectivity analysis. Step S30304: A complete via contour is formed using an edge connection algorithm. The algorithm employs an 8-connected neighborhood search method, starting from a determined edge point and searching for adjacent edge points along the edge direction to connect broken edge segments into a complete closed contour. During the connection process, gaps of no more than 2 pixels are allowed to cross, ensuring the integrity of the via contour. Step S304: Calculate the geometric center coordinates of the through hole profile; The geometric center is determined using a centroid calculation method based on the detected contour boundary point coordinates. The centroid coordinates are obtained by averaging the x and y coordinates of all contour points. During the calculation, the internal region of the contour is traversed pixel by pixel, and the coordinate information of all pixels within the region is collected. Step S305: Establish the transformation relationship between pixel coordinates and actual physical coordinates; the specific process is as follows: Step S451: Camera calibration is performed using a standard calibration board. The calibration board contains circular or square markers of known physical dimensions, and the spacing between the markers is accurate to the sub-micron level. During the calibration process, images of the calibration board are captured at different positions and angles to obtain multiple sets of data on the correspondence between pixel coordinates and physical coordinates. Step S452: Calculate the camera intrinsic parameter matrix and distortion coefficients; the intrinsic parameter matrix includes parameters such as focal length, principal point coordinates, and pixel size, and the distortion coefficients describe the radial and tangential distortion characteristics of the lens; the optimal values ​​of the intrinsic parameter matrix and distortion coefficients are obtained by fitting the calibration data using the least squares method. Step S453: Establish a coordinate transformation mathematical model. The transformation model considers camera intrinsic parameters, distortion correction, and extrinsic parameter transformation to convert the via center coordinates in the pixel coordinate system to the actual position coordinates in the substrate physical coordinate system. The transformation process first performs distortion correction, and then applies the perspective transformation matrix to complete the coordinate system transformation. Step S306: If the position deviation of the through hole exceeds the allowable range, record the deviation data and generate a position correction command; The actual position of the measured through hole is compared with the design position, and the lateral and longitudinal components of the position deviation are calculated. When the Euclidean distance of the deviation exceeds the preset allowable range, the direction and magnitude of the deviation are recorded, and a position correction command containing the correction direction and correction amount is generated. Step S307: Perform statistical analysis on the measurement results and evaluate the overall positional accuracy; Calculate the mean, standard deviation, and maximum deviation of all via position deviations, statistically analyze the histogram of deviation distribution, and evaluate the consistency and reliability of measurement accuracy. The analysis results are used to judge the stability of the detection process and the overall level of insulation layer pattern transfer quality. Step S308: Construct a dataset containing the precise coordinates of all vias; The coordinates of the via center after coordinate transformation are organized into a dataset according to a predetermined format. The dataset includes information such as via number, x-coordinate, y-coordinate, measurement timestamp and quality rating, providing basic data support for subsequent via fabrication. Step S309: Use laser drilling to create a through hole.

[0020] In one embodiment, the image preprocessing process employs adaptive parameter adjustments for different types of insulating layer materials.

[0021] For example, for polyimide insulating layers, due to their low surface reflectivity, the image gain parameter needs to be increased to 1.2 times, while the histogram equalization clipping limit is set to 2.0 to avoid noise amplification caused by over-enhancement. For epoxy resin insulating layers, their high surface smoothness makes them prone to reflection, requiring the use of polarizing filters to reduce reflection interference, and the standard deviation parameter of the Gaussian filter adjusted to 1.5 to ensure that edge information is maintained while suppressing reflection noise.

[0022] Specifically, the dual threshold settings of the edge detection algorithm are dynamically adjusted based on the via size. For vias with diameters ranging from 50 to 100 micrometers, the high threshold is set to the 85th percentile of the gradient magnitude distribution, and the low threshold is set to 0.4 times the high threshold. For vias with diameters ranging from 100 to 200 micrometers, since the edge gradient changes relatively gently, the high threshold is reduced to the 75th percentile of the gradient magnitude distribution, and the low threshold ratio is adjusted to 0.3 times, ensuring that the complete via outline can be detected.

[0023] In one possible implementation, the coordinate transformation process employs a piecewise linear interpolation method to improve transformation accuracy. The detection area is divided into multiple sub-regions, and independent transformation parameters are established for each sub-region, eliminating nonlinear errors over a large field of view.

[0024] For example, a detection area of ​​20mm×20mm is divided into 16 sub-regions of 4×4, and the conversion accuracy of each sub-region can reach 0.5 micrometers, which is about 30% more accurate than the global conversion method.

[0025] It should be noted that the generation of the position correction command takes into account the adjustable range of the manufacturing process. When a via position deviation is detected, the correction command not only includes the numerical information of the deviation, but also suggestions for adjusting subsequent process parameters.

[0026] For example, if the vias are shifted in a certain direction, the instruction includes correction parameters for the photolithography alignment system. If the deviation exhibits a random distribution, it is recommended to adjust the exposure dose or development time parameters to fundamentally improve the positional accuracy of pattern transfer.

[0027] Step S4, Insulating Layer Application: Apply a photosensitive insulating layer to the surface of the board using a film application method; Step S5, Curing after Pattern Transfer: Using pattern transfer technology, the circuit pattern is transferred onto the insulating layer. Unwanted parts are removed using development, and then the insulating layer is completely cured using heat curing. In this embodiment, step S5 uses pattern transfer technology to transfer the circuit pattern onto the insulating layer, including: performing pattern transfer processing on the insulating layer using a pre-set pattern transfer control strategy, and forming a predetermined circuit pattern on the surface of the insulating layer using precision photolithography.

[0028] In this embodiment, the specific process of pre-setting the graphics transfer control strategy is as follows: The thickness distribution data of the insulation layer on the surface of the inner core board is obtained, and the thickness is measured point by point on the substrate surface using laser scanning measurement technology to obtain a standardized data matrix of the thickness distribution. Based on the thickness distribution data matrix, a mapping relationship model between the insulating layer and the conductive layer is established using a multilayer perceptron algorithm to obtain a targeted pattern transfer control strategy.

[0029] In this embodiment, laser scanning measurement technology is used to perform point-by-point thickness detection on the substrate surface, including: Step S501: Scan the substrate surface with a laser beam, measure the time difference of the laser reflection signal, and calculate the thickness value at each measurement point; the specific process is as follows: In step S50101, the laser emitter generates a red laser beam with a wavelength of 635 nanometers and a laser beam power set to 5 milliwatts. The laser beam is focused into a spot with a diameter of 10 micrometers through a precision optical lens group. The laser beam illuminates the substrate surface at a perpendicular angle. When the laser encounters the surface of the insulating layer, a first reflection signal is generated. When it continues to penetrate the insulating layer and reaches the surface of the inner core board, a second reflection signal is generated.

[0030] In step S50102, the photodetector receives two reflected signals and records the time interval Δt between the two reflected signals using a high-precision time measurement circuit. Based on the laser propagation speed v in the insulating layer material, the insulation layer thickness d is calculated using the formula d = v × Δt / 2, where dividing by 2 is because the round-trip path length of the laser is twice the thickness.

[0031] In step S50103, the scanning control device drives the laser beam to scan the substrate surface point by point according to a preset grid path. The scanning step size is set to 50 micrometers to ensure sufficient spatial resolution between adjacent measurement points. The scanning time for each measurement point is 10 milliseconds, which includes the complete cycle of signal acquisition, data processing, and position movement.

[0032] Step S502: If the detected thickness change exceeds the preset threshold range, an adaptive threshold segmentation algorithm is used to mark and identify the abnormal region; the specific process is as follows: Step S50201: Establish a thickness change rate evaluation mechanism, calculate the thickness difference between each measurement point and its eight neighboring points, and trigger the anomaly detection process when the thickness difference exceeds 15% of the standard thickness. The adaptive threshold segmentation algorithm first calculates the mean μ and standard deviation σ of the thickness values ​​in the local area, and then dynamically determines the segmentation threshold T according to the formula T=μ+k×σ, where k is an adjustment coefficient, and the initial value is set to 1.5.

[0033] In step S50202, for measurement points whose thickness values ​​exceed the dynamic threshold T, the algorithm marks them as potential outliers and checks the distribution density of outliers within a 3×3 neighborhood around the point. When the number of outliers in the neighborhood exceeds 5, the entire neighborhood is marked as an outlier region, and the adjustment coefficient k is adjusted to dynamically change between 0.8 and 2.5 to adapt to the thickness variation characteristics of different regions.

[0034] Step S50203: After the abnormal area is marked, the algorithm generates marked data containing the boundary coordinates, area size, and average thickness deviation of the abnormal area, providing accurate location information and anomaly assessment basis for subsequent repeated measurement verification.

[0035] Step S503: Normalize the measured thickness data to eliminate the influence of systematic errors; The original thickness data is normalized using the Z-score standardization method. The thickness value is converted into a standardized value by the formula Z=(X-μ) / σ, where X is the original thickness value, μ is the global mean, and σ is the global standard deviation.

[0036] Step S504: Construct a two-dimensional thickness distribution matrix and record the coordinates and corresponding thickness values ​​of each measurement point; the specific process is as follows: Step S50401: Based on the actual size of the substrate and the scanning step size, create an m×n dimension thickness distribution matrix M, where m and n correspond to the number of measurement points on the substrate in the X and Y axes, respectively. Each element M(i,j) in the matrix contains three attribute values: X coordinate, Y coordinate, and normalized thickness value.

[0037] Step S50402: Establish coordinate mapping relationships and convert the measurement point positions in the physical coordinate system into matrix index positions. Using the coordinate transformation formulas i=floor(x / step_x) and j=floor(y / step_y), the continuous physical coordinates (x, y) are mapped to discrete matrix indices (i, j), where step_x and step_y are the scan steps in the X and Y axes, respectively.

[0038] Step S50403: Mark the location information of abnormal areas in the thickness distribution matrix, and distinguish abnormal measurement points from normal measurement points by setting special identifiers to form a complete data structure containing spatial location, thickness value and abnormal status.

[0039] Step S505: Repeat the measurement and verification of the abnormal area to confirm the authenticity of the thickness anomaly; the specific process is as follows: In step S50501, for the marked abnormal area, the laser scanning device repositions itself to the center of the abnormal area and performs a second scan with higher measurement accuracy. The laser power of the second scan is increased to 8 milliwatts, the scanning step size is reduced to 25 micrometers, and the measurement time is extended to 20 milliseconds to obtain more accurate thickness data.

[0040] Step S50502: Compare the consistency between the initial measurement result and the second measurement result, and calculate the relative error between the two measurements. When the relative error is less than 5%, the existence of the abnormal area is confirmed; when the relative error exceeds 5%, it is determined to be measurement noise or system interference, and the area is removed from the abnormal marker.

[0041] Step S50503: For confirmed abnormal areas, record the abnormality type, severity, and possible causes, and establish an abnormal area database to provide a reference for subsequent process parameter optimization. Abnormality types include three basic types: excessively thin, excessively thick, and uneven thickness. Severity is divided into three levels according to the deviation range: slight, moderate, and severe.

[0042] Step S506: Generate a visual image of the thickness distribution, identifying the range of areas where the thickness varies.

[0043] A pseudo-color image is generated based on the thickness distribution matrix. A color mapping scheme is used to map different thickness values ​​to different colors. The normal thickness range is displayed in green, the thinner areas are displayed in blue, and the thicker areas are displayed in red.

[0044] In one embodiment, during laser scanning measurement, when there is microparticle contamination on the substrate surface, the laser reflection signal will exhibit additional scattering components. In this case, signal filtering techniques are needed to remove the influence of scattering noise. By setting a signal intensity threshold, scattering signals with excessively low intensity are filtered out, retaining the main reflection signal for thickness calculation.

[0045] For example, when the intensity of the reflected signal is detected to be below 70% of the set threshold, the system automatically activates the signal enhancement mode, increases the laser power and extends the signal acquisition time to ensure that reliable thickness measurement data is obtained.

[0046] For example, when dealing with regions with large thickness variation gradients, the adaptive threshold segmentation algorithm needs to dynamically adjust the segmentation parameters based on local features. In the substrate edge region, due to manufacturing process limitations, thickness variations are typically more pronounced than in the central region. The algorithm detects the distance from the measurement point to the substrate edge; when the distance is less than 5 mm, it automatically adjusts the adjustment coefficient k to 2.0, increasing the tolerance for thickness variations in the edge region and avoiding misclassifying normal edge effects as abnormal areas.

[0047] In one possible implementation, the construction of the two-dimensional thickness distribution matrix needs to consider the actual shape and size variations of the substrate. For non-rectangular substrates, a mathematical model of the substrate profile is established to determine the boundary range of the effective measurement area. Elements located outside the substrate profile in the matrix are set to invalid values; only elements within the effective measurement area record the actual thickness data. This approach accurately reflects the true thickness distribution characteristics of the substrate and avoids interference from invalid regions on the overall data analysis.

[0048] Specifically, the repeated measurement verification mechanism for abnormal areas can effectively improve the reliability of measurement results. When the initial scan detects that the thickness value of a certain area deviates significantly from the normal range, the system will automatically trigger the verification process. During the verification process, different scanning parameters and measurement angles are used, and through cross-verification of multi-angle measurement data, measurement errors caused by changes in surface reflection characteristics or local contamination are eliminated.

[0049] For example, if during the verification process a significant difference is found in the measurement results of an anomaly point at different angles, it is determined that the anomaly may be caused by surface contamination rather than a real change in thickness.

[0050] In this embodiment, a multilayer perceptron algorithm is used to establish a mapping relationship model between the insulating layer and the conductive layer, including: Step S507: Collect correlation data between graphic transfer accuracy and material property changes in historical manufacturing data; Extract complete process records containing parameters such as insulation layer thickness, exposure energy, and development time from the production database.

[0051] Step S508: Construct a multi-layer neural network structure and set the input layer to receive thickness distribution data; including: Step S50801: Set the input layer to 12 nodes, corresponding to the measurement values ​​of 12 key areas of the thickness distribution data matrix.

[0052] Step S50802: Configure 3 hidden layers and use ReLU, Sigmoid and Tanh activation functions respectively to process nonlinear features of different dimensions.

[0053] Step S50803: The output layer is designed with 6 nodes, corresponding to key process parameters such as exposure time and developer concentration.

[0054] Step S509: Process complex nonlinear mapping relationships through hidden layers and extract key feature parameters; Step S50901: Extract the spatial gradient features of the thickness distribution in the first hidden layer and calculate the thickness change rate of adjacent regions.

[0055] In step S50902, the second hidden layer combines the material dielectric constant data to establish the correlation weight between thickness fluctuation and dielectric properties.

[0056] In step S50903, the third hidden layer integrates the outputs of the first two layers to generate an intermediate representation containing 32-dimensional feature vectors.

[0057] Step S5010: Generate the prediction results of the optimal combination of process parameters in the output layer; The feature vectors output from the hidden layer are converted into process parameter values, and then the specific values ​​are output through a linear activation function.

[0058] Step S5011: Train network weights using the backpropagation algorithm to optimize model prediction accuracy; Using mean squared error as the loss function, with an initial learning rate of 0.001, the loss value converged to below 0.05 after 500 iterations.

[0059] Step S5012: Evaluate the generalization ability of the model using cross-validation. The dataset was divided into 5 subsets, and the average prediction accuracy reached 92.3%, with a standard deviation of less than 1.8%.

[0060] Step S5013: Analyze the similarity between the current substrate state and historical data to determine the applicability of the model; Calculate the Euclidean distance between the current thickness distribution and historical samples; when the similarity is higher than 85%, directly call the historical parameters; when it is lower than 70%, start the retraining process.

[0061] Step S5014: Generate personalized process parameter suggestions for the current substrate characteristics.

[0062] For example, for substrates with thickness fluctuations within ±3 μm, an optimized combination of an output exposure time of 45 seconds and a developer temperature of 28°C is used.

[0063] In one embodiment, the feature extraction process in step S50901 specifically includes: dividing the 12×12 thickness matrix into 9 4×4 overlapping regions, and calculating the thickness variance of each region as a primary feature.

[0064] Preferably, when the variance of a certain region is detected to exceed 0.5 μm², the weighting coefficient of that region is automatically increased to 1.2 times.

[0065] Understandably, the similarity calculation uses a dynamic weighting method, assigning a weight coefficient of 0.4 to the central region, which has the greatest impact on the accuracy of image transfer, and setting the coefficient for the edge region to 0.1.

[0066] Specifically, when the similarity of the central region reaches 90%, it is still considered applicable even if the overall similarity is 75%.

[0067] In one embodiment, the parameter suggestion generation process in step S5014 includes a security verification mechanism. For example, when the predicted exposure time exceeds the device's upper limit, other parameter values ​​are automatically adjusted proportionally to maintain the total energy. This mechanism ensures that the feasibility of parameter combinations reaches over 99.6%.

[0068] In this embodiment, a predetermined circuit pattern is formed on the surface of the insulating layer using precision photolithography, including: Step S5015: Coat the surface of the insulating layer with a photosensitive adhesive layer, controlling the uniformity of the coating thickness; the specific process is as follows: Step S11: A photosensitive adhesive layer is formed on the surface of the insulating layer using a spin coating process. The spin coating speed parameters are adjusted based on the thickness distribution data matrix of the insulating layer surface. When an area where the thickness variation of the insulating layer exceeds a preset threshold range is detected, a segmented speed control method is adopted. In areas with thinner thickness, the spin coating speed is reduced to 1500 rpm, and in areas with thicker thickness, the spin coating speed is increased to 3000 rpm, ensuring that the uniformity of the photosensitive adhesive layer thickness is controlled within ±0.1 micrometers.

[0069] Step S12: The thickness of the photosensitive adhesive layer is monitored in real time using laser interferometry, and thickness distribution characteristic data is obtained through multi-point sampling. When the standard deviation of the thickness exceeds 0.05 micrometers, a secondary coating compensation procedure is initiated to locally replenish the coating in areas with insufficient thickness, forming a photosensitive adhesive layer structure with uniform thickness.

[0070] Step S5016: Set exposure parameters according to the control strategy, including exposure time and light intensity; the specific process is as follows: Step S501601: Based on the mapping relationship model established by the multilayer perceptron algorithm, the optimal combination of exposure parameters for the current substrate state is determined. The multilayer perceptron algorithm analyzes the correlation pattern between the insulating layer thickness distribution and the pattern transfer accuracy in historical manufacturing data, establishes a neural network structure whose input layer includes thickness distribution feature values ​​and material property parameters, uses the ReLU activation function to process the nonlinear mapping relationship in the hidden layer, and generates optimized values ​​for exposure time and light intensity in the output layer.

[0071] Step S501602: Adjust the spatial distribution settings of the exposure parameters based on the uniformity test results of the photosensitive adhesive layer thickness. For a standard area with a thickness of 2.5 micrometers, set the exposure time to 8 seconds and the light intensity to 25 milliwatts per square centimeter. For areas with a thickness deviation exceeding 0.1 micrometers, adjust the exposure time according to the thickness compensation coefficient: increase the exposure time by 1 second when the thickness increases by 0.05 micrometers, and decrease the exposure time by 1 second when the thickness decreases by 0.05 micrometers.

[0072] Step S501603 establishes a dynamic response relationship between exposure parameters and changes in the properties of the insulating layer material. When the dielectric constant of the insulating layer material changes, the degree of change in the photosensitivity of the photosensitive adhesive is calculated by measuring the dielectric constant shift, and the basic light intensity parameters are adjusted to ensure consistent exposure results under different material property conditions.

[0073] Step S5017: Selectively expose the photosensitive adhesive layer using a photomask to form a latent image pattern; A high-precision alignment device is used to ensure the precise positioning of the mask and the insulating layer pattern structure, with the alignment accuracy controlled within ±0.5 micrometers. Selective exposure processing is performed using an ultraviolet light source.

[0074] Step S5018: Perform development treatment to remove the unexposed or exposed photosensitive adhesive portions; The exposed photosensitive adhesive layer is chemically developed using an alkaline developer. The development time is determined based on the type and thickness of the photosensitive adhesive, resulting in a clear graphic outline structure.

[0075] Step S5019: Detect the sharpness of the graphic edges and the accuracy of the line width; the specific process is as follows: Step S501901 involves measuring the edge sharpness of the developed graphic structure using a high-precision visual inspection device. The visual inspection device employs a high-resolution CCD camera in conjunction with a microscope to acquire the grayscale change curve of the graphic edge and calculate the edge sharpness value as a sharpness evaluation index. The edge sharpness value is determined by measuring the distance corresponding to the change in grayscale from 10% to 90% within the edge transition area; a smaller distance indicates a sharper edge.

[0076] Step S501902 involves using a linewidth measurement algorithm to perform accuracy checks on the critical dimensions of the graphic structure. Linewidth measurement identifies the edge positions of the graphic and calculates the distance between relative edges to obtain the linewidth value, achieving a measurement accuracy of 0.1 micrometers. When the linewidth deviation exceeds ±5% of the design value, the deviation location and value are recorded, and a quality assessment report is generated.

[0077] Step S501903: Establish a graphic quality evaluation system, and form a quality score by combining edge sharpness and line width accuracy data. The quality score adopts a weighted average method, with edge sharpness having a weight of 0.6 and line width accuracy having a weight of 0.4. When the comprehensive score is lower than 85 points, it is judged as unqualified in quality.

[0078] Step S50110: If the edge sharpness of the image is lower than the quality standard, adjust the exposure parameters and re-transfer the image; the specific process is as follows: Step S501101: When the edge sharpness value is greater than 2 micrometers or the line width deviation exceeds ±8%, the parameter adjustment program is initiated. Based on the quality inspection results, the specific reasons for underexposure or overexposure are analyzed. If underexposure is found, the exposure time is increased or the light intensity is increased; if overexposure is found, the exposure parameters are reduced accordingly.

[0079] Step S501102 involves adjusting parameters using an iterative optimization method, with each adjustment controlled within 10% of the original parameter value. The entire process of photosensitive adhesive coating, exposure, and development is then repeated until the image quality meets the standard requirements.

[0080] Step S50111: The pattern is transferred onto the insulating layer through an etching process to form the final pattern structure. The specific process is as follows: Step S501111 involves using dry etching technology to transfer the pattern of the insulating layer. Dry etching removes the insulating layer material not protected by the photosensitive adhesive through plasma chemical reaction. The etching gas is selected according to the type of insulating layer material; for polyimide insulating layers, oxygen plasma is used, and the etching rate is controlled at 50 nanometers per minute.

[0081] Step S501112 involves real-time monitoring of the etching depth and sidewall contour, using optical interferometry to detect the etching progress. The etching process is stopped when the designed depth is reached to avoid pattern deformation caused by over-etching. After etching, residual photoresist is removed to obtain a precise insulating layer pattern structure.

[0082] Step S501113 involves a final quality inspection of the etched pattern structure, measuring the pattern's dimensional accuracy and surface roughness. The pattern's dimensional accuracy must be controlled within ±3% of the design value, and the surface roughness must be less than 50 nanometers to ensure the accuracy requirements of subsequent via fabrication processes.

[0083] In one embodiment, the uniformity of the photosensitive adhesive layer thickness is controlled using a multi-stage spin coating process. First, a pre-coating is performed at a low speed of 1000 rpm to form a base adhesive layer. Then, based on the abnormal area marking results from the insulation layer thickness distribution data matrix, localized touch-up coating is performed in areas with significant thickness deviations. The touch-up coating process uses a micro-dispensing device, with each touch-up volume controlled at 0.01 microliters. Through multiple touch-ups, the required thickness uniformity is achieved.

[0084] For example, when the thickness of a certain area of ​​the insulating layer is 0.2 micrometers thinner than the standard thickness, the photosensitive adhesive coating in that area needs to be thickened by 0.15 micrometers to compensate for the thickness effect in subsequent processes. This localized thickening effect can be achieved by reducing the spin coating speed in that area to 1200 rpm and extending the spin coating time to 45 seconds.

[0085] In one possible implementation, the exposure parameters are dynamically adjusted based on the output of a multilayer perceptron algorithm. The input layer of the multilayer perceptron algorithm contains 12 nodes, corresponding to characteristic parameters such as the mean thickness, standard deviation, maximum deviation, dielectric constant, and coefficient of thermal expansion of the insulating layer. Two hidden layers are configured: the first layer contains 20 nodes, and the second layer contains 15 nodes. The output layer contains 3 nodes, outputting the optimal exposure time, light intensity, and exposure mode selection, respectively.

[0086] Specifically, when the standard deviation of the input insulating layer thickness is 0.08 micrometers and the dielectric constant is 3.2, the multilayer sensor algorithm outputs an exposure time of 9.2 seconds and a light intensity of 28 milliwatts per square centimeter. This combination of parameters enables optimal pattern transfer accuracy under the current substrate conditions, achieving an edge sharpness of 1.2 micrometers.

[0087] It should be noted that the image edge sharpness detection employs a sub-pixel-level edge detection algorithm to improve measurement accuracy. This algorithm analyzes the gray-level gradient changes near the image edge and uses a Gaussian fitting method to determine the precise edge location, achieving a measurement accuracy of 0.05 micrometers. When insufficient edge sharpness is detected, the algorithm can automatically identify whether the problem is caused by underexposure or overexposure and provide corresponding parameter adjustment suggestions.

[0088] Preferably, the etching process employs an inductively coupled plasma etching device, achieving precise control of the etching rate and anisotropy through independent control of the radio frequency (RF) power and bias power. The RF power controls the plasma density, affecting the etching rate, while the bias power controls the ion bombardment energy, affecting the etching directionality. For a pattern structure with a linewidth of 5 micrometers, setting the RF power to 800 watts and the bias power to 200 watts enables the achievement of a high-quality etched profile with a perpendicularity greater than 85 degrees.

[0089] Step S6: Fabricate the conductive layer: Use chemical plating or sputtering copper to fabricate a thin copper conductive layer on the surface of the board; Step S7, Applying the film: Apply the dry film of the circuit board to the surface of the board; Step S8, Pattern Transfer: The pattern is transferred back onto the dry film using pattern transfer technology; unwanted areas are removed using development. Step S9, Pattern Electroplating: Electroplating is used to fill the pattern area until the insulating layer is completely filled, forming a buried wire structure; In this embodiment, step S9 involves using electroplating to fill the patterned area until the insulating layer is completely filled, forming a buried wire structure. The specific process is as follows: Step S901: Prepare the chemical plating solution and control the metal ion concentration; including: Step S90101: Calculate the required molar concentration of metal ions based on the geometry and aspect ratio of the via. By measuring the geometric parameters of the via with a diameter ranging from 50 μm to 200 μm and a depth ranging from 100 μm to 500 μm, the mass transfer rate of metal ions within the via is calculated using the Stokes diffusion equation. This determines that the copper ion concentration needs to be maintained between 0.02 mol / L and 0.08 mol / L, and the nickel ion concentration needs to be controlled between 0.01 mol / L and 0.04 mol / L.

[0090] Step S90102: Prepare the chemical plating solution components containing a reducing agent and a complexing agent. Sodium hypophosphite is used as the main reducing agent, with a concentration set at 0.15 mol / L to 0.25 mol / L. Sodium citrate is added as a complexing agent, with a concentration controlled at 0.1 mol / L to 0.2 mol / L. The complexation reaction stabilizes the metal ions in the solution, preventing hydrolysis and precipitation of the metal ions.

[0091] Step S90103: Adjust the concentration ratio of buffer and stabilizer in the plating solution. Add sodium acetate buffer to maintain the pH value of the solution within the range of 4.5 to 5.5, and add thiourea stabilizer at a concentration of 1 mg / L to 5 mg / L to inhibit the spontaneous decomposition reaction of the plating solution and extend its service life.

[0092] Step S902: Pre-treat the surface of the insulating layer to enhance metal adhesion; including: Step S90201 involves using plasma cleaning to remove organic contaminants from the surface of the insulating layer. In an oxygen plasma environment, the radio frequency power is set to 100W to 300W, and the processing time is 30 to 120 seconds. The active oxygen atoms in the plasma react with the organic molecules in an oxidation reaction, thoroughly removing surface grease and organic residues.

[0093] Step S90202 involves surface roughening treatment to increase surface area and adhesion points. A potassium permanganate solution with a concentration of 2 g / L to 8 g / L is used, and the mixture is treated at 60°C to 80°C for 5 to 15 minutes. This oxidation reaction forms a micro-rough structure on the surface of the insulating layer, increasing the mechanical anchoring effect of the metal coating.

[0094] Step S903: Immerse the substrate in the chemical plating solution to initiate the autocatalytic reaction; The pretreated substrate is vertically immersed in the prepared chemical plating solution to ensure that the vias are completely wetted by the solution. Through the redox reaction between the reducing agent and the metal ions, the metal deposition process begins on the surface of the insulating layer and the inner wall of the vias.

[0095] Step S904: Controlling the temperature and pH of the plating bath to maintain reaction stability; including: Step S90401: Set up a plating bath temperature control system to maintain a constant reaction temperature. Precisely control the plating bath temperature within the range of 75 degrees Celsius to 85 degrees Celsius, with temperature fluctuations not exceeding ±1 degree Celsius. A constant temperature water bath circulation system is used to achieve precise temperature regulation, ensuring the stability of the chemical reaction rate.

[0096] Step S90402: Monitor and adjust the pH value of the plating solution in real time. An online pH sensor is used to continuously monitor the acidity and alkalinity of the plating solution. When the pH value deviates from the set range, sodium hydroxide or hydrochloric acid solution is automatically added to adjust the pH value and maintain it within the optimal reaction range of 4.8 to 5.2.

[0097] Step S905: Real-time monitoring of thickness changes during the deposition process; including: Step S90501: Electrochemical impedance spectroscopy is used to measure the real-time change in coating thickness. By setting a reference electrode and a working electrode on the substrate, the change in electrochemical impedance with the increase of coating thickness is measured, and a linear relationship model between impedance value and coating thickness is established to achieve online monitoring of thickness.

[0098] Step S90502: The uniformity of the coating on the inner wall of the via is detected using optical interferometry. A white light interferometer is used to scan and measure the cross-section of the via. By analyzing the changes in the interference fringes, the coating thickness at different locations is calculated, and two-dimensional mapping data of the thickness distribution is obtained.

[0099] Step S90503: Calculate the uniformity index of the coating thickness distribution. Perform statistical analysis on the measured thickness data, calculate the standard deviation and coefficient of variation of the thickness distribution. When the standard deviation exceeds 15% of the average thickness, it is determined to be a non-uniform thickness distribution.

[0100] Step S906: If the unevenness of the deposition thickness exceeds the preset standard, adjust the plating solution concentration and reaction time parameters; including: Step S90601: Adjust the metal ion concentration according to the degree of thickness distribution deviation. When the coating thickness at the bottom of the via is significantly less than the thickness at the orifice, increase the metal ion concentration by 10% to 20% to improve the metal deposition rate deep within the via and enhance the uniformity of the thickness distribution.

[0101] Step S90602: Optimize reaction time and plating solution circulation parameters. Extend the chemical plating time by 15 to 30 minutes, and simultaneously increase the circulation flow rate of the plating solution. Improve the mass transfer conditions within the pores through forced convection, and promote the diffusion and transport of metal ions to the bottom of the pores.

[0102] Step S907: Improve the density and uniformity of the coating with ultrasonic assistance; including: Step S90701: Set the frequency and power parameters of the ultrasonic generator. Use ultrasonic waves with a frequency of 40kHz to 80kHz and control the power density within the range of 0.5W / cm² to 2.0W / cm². The cavitation effect of the ultrasonic waves promotes micro-stirring of the plating solution within the through-hole.

[0103] Step S90702: Control the time interval and duration of ultrasonic treatment. An intermittent ultrasonic treatment mode is adopted, with each treatment lasting 30 seconds followed by a 10-second pause to avoid damage to the formed coating from excessive ultrasonic energy, while maintaining a uniform mixing state of the plating solution.

[0104] Step S90703: Monitor the effect of ultrasonic treatment on the microstructure of the coating. The grain size and density of the coating are observed using a scanning electron microscope. After ultrasonic treatment, the grain size of the coating is reduced by 20% to 40%, and the coating density is increased by 5% to 15%, significantly improving the mechanical and electrical properties of the coating.

[0105] Step S908: After the insulation layer is filled, it is cleaned and dried to form a buried wire structure.

[0106] In one embodiment, the preparation process of the electroless plating solution requires strict control over the order of addition and mixing of each component. First, deionized water is heated to a preset temperature, then a complexing agent, a buffer, and a metal salt are added sequentially, and finally a reducing agent is added to initiate the chemical reaction. This sequence avoids premature reduction of metal ions, ensuring the stability of the plating solution and the controllability of the reaction.

[0107] Specifically, when the diameter of the via is 100 micrometers and the depth is 300 micrometers, the aspect ratio reaches 3:1. At this point, special attention needs to be paid to the mass transfer efficiency within the via. Increasing the concentration of the complexing agent to 0.18 mol / L can improve the solubility and stability of metal ions. At the same time, appropriately reducing the concentration of the reducing agent to 0.18 mol / L slows down the reaction rate, allowing sufficient time for metal ions to diffuse to the bottom of the via, thus achieving a uniform coating distribution.

[0108] For example, in actual production, when the coating thickness at the top of the via is detected to be 8 micrometers while that at the bottom is only 4 micrometers, it indicates a significant thickness gradient. In this case, ultrasonic-assisted treatment at a frequency of 60 kHz and a power density of 1.2 W / cm², administered intermittently for 20 minutes, can reduce the thickness difference to less than 1 micrometer, significantly improving the uniformity of the coating.

[0109] In one possible implementation, electrochemical impedance spectroscopy (EIS) monitoring employs a three-electrode system, using the coated substrate as the working electrode, a platinum wire as the counter electrode, and a saturated calomel electrode as the reference electrode. By applying a small-amplitude AC voltage signal, the impedance response at different frequencies is measured, establishing a linear relationship between the real part of the impedance and the coating thickness. When the coating thickness increases from 2 micrometers to 10 micrometers, the real part of the impedance exhibits a linear decreasing trend, with a correlation coefficient exceeding 0.98, providing a reliable technical means for real-time thickness monitoring.

[0110] It should be noted that ultrasonic cavitation plays an important role in the electroless plating process. When ultrasound propagates in the plating solution, it generates microbubbles in the negative pressure phase and produces local high temperature and pressure when the bubbles burst in the positive pressure phase. This microscopic mechanical stirring can disrupt the concentration boundary layer within the through-hole, promote the contact between fresh plating solution and the hole wall, and remove gas adsorption on the coating surface, thereby improving the density and adhesion of the coating.

[0111] Step S10, Film Removal: Use film removal solution to remove the dry film from the circuit; Step S11, Etching: Using etching technology, the conductive layer on the surface of the insulating layer is removed, and the fabrication of the embedded wire printed circuit board is finally completed.

[0112] Figure 4 The diagram shows a comparison between the conventional processing method (left) and the processing method of the present invention (right). The embedded wire circuit board produced by the method of the present invention can be processed from both sides, which can create a double-sided embedded wire structure, shorten the production cycle, and because of the presence of the core board, the board has good mechanical strength and is not prone to warping.

[0113] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a double-sided embedded wire printed circuit board, characterized in that, The method includes the following steps: Inner layer processing: The inner core board is processed using standard printed circuit board (PCB) processes; Insulation layer lamination: The insulation layer is laminated using a lamination process; Through-hole fabrication: Through-holes are fabricated using laser drilling; Insulating layer lamination: A photosensitive insulating layer is applied to the surface of the board using a lamination method; Post-pattern transfer curing: Using pattern transfer technology, the circuit pattern is transferred onto the insulating layer. Unwanted parts are removed using development, and then the insulating layer is completely cured using heat curing. Fabrication of the conductive layer: A thin copper conductive layer is fabricated on the surface of the board using chemical plating or sputtering methods; Film application: Applying a dry film to the surface of the circuit board; Pattern transfer: The pattern is transferred again onto the dry film using pattern transfer technology; unwanted areas are removed using development. Pattern electroplating: Electroplating is used to fill the patterned area until the insulating layer is completely filled, forming a buried wire structure; Film removal: Use film removal solution to remove the dry film from the circuit board; Etching: Using etching technology, the conductive layer on the surface of the insulating layer is removed, and the fabrication of the embedded wire printed circuit board is finally completed.

2. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 1, characterized in that: The specific process for creating a through hole using laser drilling is as follows: A high-resolution camera was used to acquire images of the insulating layer's graphic structure; Enhance the edge contrast of the via using image preprocessing algorithms; An edge detection algorithm is used to identify the contour boundary of the via; Calculate the geometric center coordinates of the through hole profile; Establish the conversion relationship between pixel coordinates and actual physical coordinates; If the position deviation of the through hole exceeds the allowable range, the deviation data is recorded and a position correction command is generated; Perform statistical analysis on the measurement results to evaluate the overall positional accuracy; Construct a dataset containing the precise coordinates of all vias; Laser drilling is used to create through holes.

3. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 1, characterized in that: The method of transferring circuit patterns onto an insulating layer using pattern transfer technology includes: performing pattern transfer processing on the insulating layer using a pre-set pattern transfer control strategy, and forming a predetermined circuit pattern on the surface of the insulating layer using precision photolithography.

4. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 3, characterized in that: The specific process of pre-setting the graphics transfer control strategy is as follows: The thickness distribution data of the insulation layer on the surface of the inner core board is obtained, and the thickness is measured point by point on the substrate surface using laser scanning measurement technology to obtain a standardized data matrix of the thickness distribution. Based on the thickness distribution data matrix, a mapping relationship model between the insulating layer and the conductive layer is established using a multilayer perceptron algorithm to obtain a targeted pattern transfer control strategy.

5. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 4, characterized in that: The step of using laser scanning measurement technology to perform point-by-point thickness detection on the substrate surface includes: The substrate surface is scanned by a laser beam, the time difference of the laser reflection signal is measured, and the thickness value at each measurement point is calculated. If the detected thickness change exceeds the preset threshold range, an adaptive threshold segmentation algorithm is used to mark and identify the abnormal area; The measured thickness data is normalized to eliminate the influence of systematic errors; Construct a two-dimensional thickness distribution matrix to record the coordinate position and corresponding thickness value of each measurement point; Repeated measurements were performed on the abnormal area to verify the authenticity of the thickness anomaly; Generate a visual image of the thickness distribution, identifying the regions where thickness varies.

6. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 4, characterized in that: The method of establishing a mapping relationship model between the insulating layer and the conductive layer using a multilayer perceptron algorithm includes: Collect correlation data between graphic transfer accuracy and changes in material properties from historical manufacturing data; Construct a multi-layer neural network structure and set the input layer to receive thickness distribution data; By using hidden layers to process complex nonlinear mapping relationships, key feature parameters are extracted. The output layer generates prediction results for the optimal combination of process parameters; The backpropagation algorithm is used to train the network weights and optimize the model's prediction accuracy. The generalization ability of the model is evaluated using cross-validation. Analyze the similarity between the current substrate condition and historical data to determine the applicability of the model; Generate personalized process parameter recommendations based on the characteristics of the current substrate.

7. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 3, characterized in that: The process of forming a predetermined circuit pattern on the surface of an insulating layer using precision photolithography includes: A photosensitive adhesive layer is coated on the surface of the insulating layer to control the uniformity of the coating thickness; Exposure parameters, including exposure time and light intensity, are set according to the control strategy. A latent image pattern is formed by selectively exposing the photosensitive adhesive layer using a photomask. Perform a developing process to remove the unexposed or exposed photosensitive emulsion portions; Detect the sharpness of graphic edges and the accuracy of line width; If the edge sharpness of the image is below the quality standard, adjust the exposure parameters and re-transfer the image; The pattern is transferred onto the insulating layer through an etching process to form the final pattern structure.

8. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 1, characterized in that: The process of filling the graphic area with electroplating until the insulating layer is completely filled to form a buried wire structure is as follows: Prepare the chemical plating solution and control the metal ion concentration; Pre-treating the surface of the insulating layer enhances metal adhesion; The substrate is immersed in a chemical plating solution to initiate an autocatalytic reaction; Control the temperature and pH of the plating solution to maintain the stability of the reaction; Real-time monitoring of thickness changes during the deposition process; If the unevenness of the deposition thickness exceeds the preset standard, adjust the plating solution concentration and reaction time parameters; Ultrasonic assistance can be used to improve the density and uniformity of the coating. After the insulation layer is filled, it is cleaned and dried to form a buried wire structure.

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