Printed circuit board embedded with electronic device and manufacturing method thereof

Abstract

The invention relates to the technical field of printed circuit boards, and discloses a printed circuit board embedded with an electronic device and a manufacturing method thereof.The manufacturing method of the printed circuit board embedded with the electronic device comprises the steps that an embedded layer, a first dielectric layer and a first stacking layer are stacked together, and a heat dissipation base is arranged in the embedded layer; the first dielectric layer comprises a first PP layer and a first replacement layer, and the first added layer comprises a first circuit layer; laminating the embedded layer, the first dielectric layer and the first added layer to obtain a substrate; processing a first blind hole in the substrate, wherein the first blind hole penetrates through the first circuit layer, the first PP layer and the first replacement layer; the first blind hole is filled with a first conductive part, and the first circuit layer and the electronic device are both connected with the first conductive part. According to the printed circuit board embedded with the electronic device and the manufacturing method of the printed circuit board provided by the invention, the problem that the board is easy to warp after the additional layer is arranged on one side of the embedded layer and lamination is performed in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of printed circuit board technology, and in particular to a printed circuit board with embedded electronic devices and a method for manufacturing the same. Background Technology

[0002] With the continuous development of the electronic communications industry and the automotive electronics industry, the requirements for related printed circuit board products are also getting higher and higher. Printed circuit boards are gradually becoming smaller and more multifunctional, and the requirements for heat dissipation performance of printed circuit boards are also getting higher and higher.

[0003] A printed circuit board with embedded electronic components is a type of printed circuit board in which electronic components (such as chips) are embedded inside. However, this structure has the problem that the heat generated by the electronic components cannot be dissipated in time. If the temperature of the electronic components (such as chips) is too high, it will lead to a decrease in the performance and lifespan of the electronic components. Therefore, it is necessary to strengthen the thermal control of electronic components.

[0004] In related technologies, since electronic devices are generally high-power, after embedding the electronic devices inside the printed circuit board, it is necessary to conduct the electronic devices to the outer layer traces through blind hole filling electroplating. Therefore, an additional layer is set on one side of the embedded layer where the electronic devices are located and then laminated. However, board warping is prone to occur after lamination. Summary of the Invention

[0005] This application provides a printed circuit board with embedded electronic devices and a method for manufacturing the same, which improves the problem of board warping that easily occurs after adding an additional layer on one side of the embedded layer and laminating it in related technologies.

[0006] In a first aspect, embodiments of this application provide a method for manufacturing a printed circuit board with embedded electronic devices, comprising: An embedded layer, a first dielectric layer, and a first augmentation layer are stacked together in sequence. A heat dissipation base is provided inside the embedded layer, and electronic devices are provided on the heat dissipation base. The first dielectric layer includes a first PP layer and a first replacement layer stacked together. The material of the first replacement layer is PI or PTFE. The first augmentation layer includes a first circuit layer. The embedded layer, the first dielectric layer, and the first build-up layer are laminated together to obtain a substrate; A first blind via is formed on the substrate, the first blind via penetrating the first circuit layer, the first PP layer and the first replacement layer, and the electronic device defines the bottom surface of the first blind via; A first conductive portion is filled inside the first blind hole, and both the first circuit layer and the electronic device are connected to the first conductive portion.

[0007] In some embodiments, at least two first PP layers are provided, and the first replacement layer is located between two adjacent first PP layers.

[0008] In some embodiments, two first PP layers are provided, the first replacement layer is located between the two first PP layers, and the two first PP layers are symmetrically arranged about the first replacement layer.

[0009] In some embodiments, the first replacement layer is located between the first PP layer and the first line layer.

[0010] In some embodiments, the process of forming the first blind via on the substrate includes: Etching removes a portion of the first circuit layer to obtain a first opening formed on the first circuit layer; A first connecting hole is machined inside the first window opening, penetrating the first PP layer and the first replacement layer. The first blind hole includes the first window opening and the first connecting hole.

[0011] In some embodiments, the first circuit layer includes a first circuit portion and a second circuit portion disposed at intervals, the first blind via passes through the first circuit portion, and the first circuit portion is connected to the first conductive portion. When the first blind hole is processed on the substrate, a second blind hole is processed on the substrate. The second blind hole is spaced apart from the first blind hole. The second blind hole penetrates the second circuit portion, the first PP layer, and the first replacement layer. The heat sink defines the bottom surface of the second blind hole. When the first blind hole is filled with a first conductive portion, the second blind hole is filled with a second conductive portion. The second circuit portion and the heat sink are both connected to the second conductive portion.

[0012] In some embodiments, after filling the first conductive portion into the first blind via, the method for manufacturing the printed circuit board with embedded electronic devices further includes: A second dielectric layer and a second additional layer are stacked sequentially on the side of the first additional layer away from the first dielectric layer. The second dielectric layer includes a second PP layer and a second replacement layer stacked together. The material of the second replacement layer is PI or PTFE. The second additional layer includes a second circuit layer. A third blind via is fabricated that penetrates the second circuit layer, the second PP layer, and the second replacement layer, with a portion of the first circuit layer defining the bottom surface of the third blind via; A third conductive portion is filled within the third blind via, and both the second circuit layer and the first circuit layer are connected to the third conductive portion.

[0013] Secondly, embodiments of this application provide a printed circuit board with embedded electronic devices, including a substrate. The substrate includes an embedded layer, a first dielectric layer, and a first add-on layer stacked sequentially. A heat sink is disposed inside the embedded layer, and electronic devices are disposed on the heat sink. The first dielectric layer includes a first PP layer and a first replacement layer stacked together. The first replacement layer is made of PI or PTFE. The first add-on layer includes a first circuit layer. A first blind via is disposed on the substrate, penetrating the first circuit layer, the first PP layer, and the first replacement layer. The electronic devices define the bottom surface of the first blind via. A first conductive portion is filled in the first blind via, and both the first circuit layer and the electronic devices are connected to the first conductive portion.

[0014] In some embodiments, at least two first PP layers are provided, and the first replacement layer is located between two adjacent first PP layers.

[0015] Thirdly, embodiments of this application provide a printed circuit board with embedded electronic devices, which is manufactured by the method for manufacturing a printed circuit board with embedded electronic devices as described in the first aspect.

[0016] The method for manufacturing a printed circuit board with embedded electronic devices provided in this application has the following advantages: First, the embedded layer, the first dielectric layer, and the first augmentation layer are stacked sequentially. A heat sink is provided inside the embedded layer, and electronic devices are disposed on the heat sink. The first dielectric layer includes a first PP layer and a first replacement layer stacked together. The material of the first replacement layer is PI or PTFE. The first augmentation layer includes a first circuit layer. Then, the embedded layer, the first dielectric layer, and the first augmentation layer are laminated to obtain a substrate. Next, a first blind via is processed on the substrate. The first blind via penetrates the first circuit layer, the first PP layer, and the first replacement layer. The electronic devices define the bottom surface of the first blind via. A first conductive portion is then filled into the first blind via. Both the first circuit layer and the electronic devices are connected to the first conductive portion. Therefore, while ensuring that the first dielectric layer meets the withstand voltage requirements, the thickness of the first PP layer is relatively small. This solves the problem of board warping caused by excessive shrinkage stress of the first PP layer during the lamination process due to excessive thickness of the first PP layer.

[0017] The advantages of the printed circuit board with embedded electronic devices provided in this application compared to the prior art can be found in the description of the advantages of the manufacturing method of the printed circuit board with embedded electronic devices provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a method for manufacturing a printed circuit board with embedded electronic devices in one embodiment of this application; Figure 2 This is a schematic diagram of the substrate structure in one embodiment of this application; Figure 3 Is Figure 2 The diagram shows a first blind via and a second blind via fabricated on a substrate. Figure 4 Is Figure 3 A schematic diagram showing the first blind hole and the second blind hole filled with the first conductive part and the second conductive part, respectively. Figure 5 Is Figure 4 The schematic diagram of the printed circuit board structure is shown below. The second dielectric layer and the second additive layer are stacked sequentially on the side of the first additive layer away from the first dielectric layer. A third blind hole and a fourth blind hole are processed, and a third conductive part and a fourth conductive part are filled into the third blind hole and the fourth blind hole, respectively. Figure 6 This is a schematic diagram of the structure of a printed circuit board in another embodiment of this application; Figure 7 This is a schematic diagram of the structure of a printed circuit board in another embodiment of this application; Figure 8 This is a schematic diagram of the structure of a printed circuit board in another embodiment of this application.

[0020] The markings in the diagram mean: 100. Substrate; 10. Embedded layer; 11. Heat sink; 12. Electronic components; 20. First dielectric layer; 21. First PP layer; 22. First replacement layer; 30. First additional layer; 31. First line layer; 301. First line section; 302. Second line section; 40. First blind hole; 41. Second blind hole; 50. First conductive part; 51. Second conductive part; 60. Second dielectric layer; 61. Second PP layer; 62. Second replacement layer; 70. Second layer added; 71. Second line layer; 701. Third line section; 702. Fourth line section; 80. Third conductive part; 81. Fourth conductive part. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0025] With the continuous development of the electronic communications industry and the automotive electronics industry, the requirements for related printed circuit board products are also getting higher and higher. Printed circuit boards are gradually becoming smaller and more multifunctional, and the requirements for heat dissipation performance of printed circuit boards are also getting higher and higher.

[0026] A printed circuit board with embedded electronic components is a type of printed circuit board in which electronic components (such as chips) are embedded inside. However, this structure has the problem that the heat generated by the electronic components cannot be dissipated in time. If the temperature of the electronic components (such as chips) is too high, it will lead to a decrease in the performance and lifespan of the electronic components. Therefore, it is necessary to strengthen the thermal control of electronic components.

[0027] In related technologies, since electronic devices are generally high-power, after embedding them inside the printed circuit board, they need to be connected to the outer layer traces through blind via filling electroplating. The application of high-power electronic devices usually requires high voltage resistance. When the electronic devices are connected to the outer layer traces, the dielectric layer thickness usually needs to be increased to meet the high voltage resistance requirements. For example, the voltage resistance of PP (Prepreg) is 1000V / 50μm. If the printed circuit board needs to meet the voltage resistance of 4000V, the thickness of PP needs to be greater than 200μm. The thicker the PP, the greater the stress shrinkage caused by its melting deformation. Therefore, after adding an overlay on one side of the embedded layer where the electronic devices are located and laminating it, board warping is likely to occur due to the stress shrinkage of PP and the asymmetrical structure of the laminated layer.

[0028] Furthermore, when drilling blind vias with thick dielectric layers, the bottom of the blind via is adjacent to the pads of electronic components, which are typically thin (approximately 10 μm). To avoid damaging these pads, laser drilling is the only option for blind vias. Laser drilling of blind vias requires high energy and multiple laser passes due to the thick dielectric layer. Both high energy and multiple laser passes can cause the blind via walls to become concave. This concavity reduces the spacing between blind vias. If horizontal blind vias are designed as closely spaced vias, they may become conductive after plating, or ion migration between them may increase, thus affecting the printed circuit board's resistance to CAF (Conductive Anodic Filament).

[0029] Meanwhile, the pads on the electronic components of printed circuit boards with embedded electronic components are usually small, so the diameter of blind vias is also relatively small. When the dielectric layer is too thick, it will lead to an increase in the aspect ratio of the blind vias. When the blind vias are filled by electroplating after drilling, if pure PP is used to laminate the dielectric layer from the pads on the electronic components to the inner circuit, the PP thickness is more than 200μm, the diameter of the blind vias is designed to be 150μm-200μm, and the aspect ratio of the blind vias is greater than 0.8:1. The aspect ratio of the blind vias exceeds the capacity of the electroplating process, the electroplating solution has poor exchange in the blind vias, and the filling is prone to poor filling.

[0030] In view of this, this application provides a printed circuit board with embedded electronic devices and a method for manufacturing the same. The embedded layer, the first dielectric layer, and the first augmentation layer are stacked sequentially. A heat sink is provided inside the embedded layer, and the electronic devices are disposed on the heat sink. The first dielectric layer includes a first PP layer and a first replacement layer stacked together. The material of the first replacement layer is PI or PTFE. The first augmentation layer includes a first circuit layer. The embedded layer, the first dielectric layer, and the first augmentation layer are then laminated to obtain a substrate. Next, a first blind via is processed on the substrate, penetrating the first circuit layer, the first PP layer, and the first replacement layer. The electronic devices define the bottom surface of the first blind via. A first conductive portion is then filled into the first blind via. Both the first circuit layer and the electronic devices are connected to the first conductive portion. Therefore, while ensuring that the first dielectric layer meets the withstand voltage requirements, the thickness of the first PP layer is relatively small. This solves the problem of board warping caused by excessive shrinkage stress of the first PP layer during lamination due to its excessive thickness.

[0031] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0032] Please refer to Figure 1 and Figure 2 In a first aspect, embodiments of this application provide a method for manufacturing a printed circuit board in which electronic devices 12 are embedded, comprising: S100: The embedded layer 10, the first dielectric layer 20 and the first augmentation layer 30 are stacked together in sequence. The embedded layer 10 has a heat dissipation base 11 inside, and an electronic device 12 is disposed on the heat dissipation base 11. The first dielectric layer 20 includes a first PP layer 21 and a first replacement layer 22 stacked together. The material of the first replacement layer 22 is PI or PTFE. The first augmentation layer 30 includes a first circuit layer 31.

[0033] The embedded layer 10 may include a dielectric layer and a core board. The dielectric layer may be PP, and the core board may be a bare core board or a copper-clad laminate. The embedded layer 10 may have an embedding groove, and a heat sink 11 is disposed in the embedding groove. The heat sink 11 may be a metal block, such as a copper block or an aluminum block, or it may be a ceramic block. The electronic device 12 may be a chip, etc. The heat sink 11 and the electronic device 12 constitute a power component.

[0034] For example, the embedded layer 10 may include a first core board, a dielectric layer (using PP), and a second core board stacked together.

[0035] Material cutting: The first core board, the second core board, and PP (i.e., the dielectric layer) are all cut according to the design dimensions. Drilling: Window alignment reference holes need to be drilled in the first core board, the second core board, and PP.

[0036] Inner layer circuit fabrication: The inner layer circuits of the first and second core boards are fabricated through copper plating, electroplating, film application, exposure, development, and etching.

[0037] Windowing: The areas corresponding to the embedded power components are shaped according to the shape of the heat sink 11 in the first core board, the second core board and PP (i.e., dielectric layer) to embed the power components.

[0038] Pre-overlap: Pre-overlapping to be pressed.

[0039] Embedding: The power components (heat sink 11 and electronic device 12) are placed into the embedding groove formed by the first core board, the second core board, and the PP window in the embedding layer 10. A high-temperature resistant film can be attached to the side of the first core board away from the first reinforcement layer 30 to prevent the power components from falling off, and at the same time to prevent PP glue from overflowing onto the first core board, the second core board, and the heat sink 11 during pressing.

[0040] The first PP layer 21 is made of PP, and the first replacement layer 22 is made of PI (Polyimide) or PTFE (Polytetrafluoroethylene). That is, the first replacement layer 22 can be a PI film, which has excellent thermal stability (temperature range of -269℃ to 400℃). Its molecular structure is not easily thermally degraded or significantly shrinks. Its voltage resistance is 120V / 1μm, that is, the first replacement layer 22 with a thickness of 1 μm can withstand a voltage of 120V without being broken down. When the first replacement layer 22 is made of PTFE, its voltage resistance is 200V / 1μm, that is, a first replacement layer 22 with a thickness of only 20µm is required for a voltage of 4000V.

[0041] In this embodiment, the material of the first replacement layer 22 is PI for illustration.

[0042] For example, if the withstand voltage of the first dielectric layer 20 needs to reach 4000V, then only a 25μm first replacement layer 22 and a 50μm first PP layer 21 are needed, that is, 120V * 25μm = 3000V. The 50μm thick first PP layer 21 has a withstand voltage of 1000V. Therefore, the first dielectric layer 20 after combining the first PP layer 21 and the first replacement layer 22 only needs a thickness of 75μm to meet the requirement of withstanding 4000V high voltage, which reduces the thickness of the first dielectric layer 20. However, if the first dielectric layer 20 uses the first PP layer 21 entirely without the first replacement layer 22, then the thickness of the first dielectric layer 20 needs to reach 200μm.

[0043] The material of the first circuit layer 31 can be copper, aluminum, or silver, etc. The first add-on layer 30 may also include a dielectric layer, and the first circuit layer 31 may be provided with one or more layers. For example, the first add-on layer 30 may be copper foil. The first replacement layer 22 and the first circuit layer 31 may be pressed and fixed before being pressed with the embedded layer 10, and then pressed with the embedded layer 10 after pressing.

[0044] The embedded layer 10, the first dielectric layer 20, and the first augmentation layer 30 can be riveted together.

[0045] S200: The embedded layer 10, the first dielectric layer 20 and the first augmentation layer 30 are pressed together to obtain the substrate 100.

[0046] In this process, after the first PP layer 21 is pressed, melted, and then cured, the embedded layer 10, the first PP layer 21, and the first reinforcement layer 30 are integrated into one unit. At the same time, the dielectric layer of the first PP layer 21 and / or the embedded layer 10 can also provide adhesive to fill the gap between the power component and the core board in the embedded layer 10, as well as the gap between the heat sink base 11 and the electronic device 12, after melting and flowing, so that the power component is stably fixed in the embedded layer 10.

[0047] It is understandable that the molecular structure of the first replacement layer 22 is not prone to thermal degradation or significant shrinkage. Since the first dielectric layer 20 includes the first PP layer 21 and the first replacement layer 22 stacked together, the thickness of the first PP layer 21 can be smaller. Since only the first PP layer 21 will melt and deform during pressing, causing stress, the thickness of the first dielectric layer 20 can be reduced from the original 200μm to 75μm, and the thickness of the first PP layer 21 can be reduced from the original 200μm to 50μm. The smaller the thickness of the single first PP layer 21, the smaller the shrinkage stress during pressing. Therefore, the problem of board warping caused by shrinkage stress during pressing due to the excessive thickness of the first PP layer 21 can be solved by reducing the thickness of the first PP layer 21. S300: Please refer to this as well. Figure 3 A first blind hole 40 is formed on the substrate 100. The first blind hole 40 penetrates the first circuit layer 31, the first PP layer 21 and the first replacement layer 22. The electronic device 12 defines the bottom surface of the first blind hole 40.

[0048] The first blind hole 40 can be formed on the substrate 100 by laser drilling or mechanical drilling. One or more first blind holes 40 can be provided.

[0049] For example, a first blind hole 40 is processed on the substrate 100 by laser drilling. When drilling, it is necessary to control the laser energy and not allow it to penetrate the pads on the electronic device 12. By reducing the thickness of the first dielectric layer 20, the energy and time of laser drilling can be reduced, and the problem of the first blind hole 40 being recessed after drilling can be solved.

[0050] For example, the thickness of the first dielectric layer 20 can be reduced from 200μm to 75μm. After the thickness of the first dielectric layer 20 is reduced, when drilling the first blind hole 40 with a laser, only the 75μm thickness needs to be drilled. In addition, the first replacement layer 22 does not contain fiberglass cloth, and the laser drilling energy is better controlled. Therefore, by using the first replacement layer 22 to replace part of the PP layer, the problem of the first blind hole 40 being concave after drilling due to the excessive thickness of the first dielectric layer 20, which requires high energy, long time and multiple laser drilling, can be improved.

[0051] It is understandable that when the first circuit layer 31 needs to be connected to the core board circuit of the embedded layer 10, blind holes or through holes between the first circuit layer 31 and the core board of the embedded layer 10 can be drilled by laser or mechanical drilling.

[0052] S400: Please refer to this as well. Figure 4 The first conductive part 50 is filled in the first blind hole 40, and the first circuit layer 31 and the electronic device 12 are both connected to the first conductive part 50.

[0053] The first conductive portion 50 can be filled into the first blind via 40 by means of copper plating or electroplating. The material of the first conductive portion 50 can be copper, aluminum, or silver, etc. The material of the first conductive portion 50 can be the same as that of the first circuit layer 31, and the first circuit layer 31 can be thickened at the same time when the first conductive portion 50 is filled into the first blind via 40.

[0054] It is understandable that, since the thickness of the first dielectric layer 20 is relatively small, the problem of poor electroplating filling of the first blind hole 40 caused by the large thickness of the first dielectric layer 20 can be solved.

[0055] For example, after the thickness of the first dielectric layer 20 is reduced, the aspect ratio of the first blind hole 40 is reduced. Taking a hole diameter of 150μm as an example, its aspect ratio is reduced from the original (hole depth 200 / hole diameter 150) 1.33:1 to (hole depth 75 / hole diameter 150) 0.5:1. The reduction in the aspect ratio of the blind hole can meet the requirement of electroplating filling process capability within 0.8:1, thereby improving the problem of poor filling of the first blind hole 40.

[0056] It should be noted that after the first conductive part 50 is filled into the first blind hole 40, the inner layer circuit can be fabricated on the first circuit layer 31 by means of exposure, development and etching, and the quality of the inner layer circuit and the electroplating filling of the first blind hole 40 can be inspected by optical inspection.

[0057] As can be seen from the above, the method for manufacturing a printed circuit board with embedded electronic devices 12 provided in this application embodiment involves first stacking the embedded layer 10, the first dielectric layer 20, and the first augmentation layer 30 together in sequence. A heat sink 11 is disposed inside the embedded layer 10, and the electronic devices 12 are disposed on the heat sink 11. The first dielectric layer 20 includes a first PP layer 21 and a first replacement layer 22 stacked together. The material of the first replacement layer 22 is PI or PTFE. The first augmentation layer 30 includes a first circuit layer 31. Then, the embedded layer 10, the first dielectric layer 20, and the first augmentation layer 30 are pressed together to obtain a substrate 100. A first blind hole 40 is fabricated on the substrate 100. The first blind hole 40 penetrates the first circuit layer 31, the first PP layer 21 and the first replacement layer 22. The electronic device 12 defines the bottom surface of the first blind hole 40. The first conductive part 50 is then filled in the first blind hole 40. The first circuit layer 31 and the electronic device 12 are both connected to the first conductive part 50. Therefore, while ensuring that the first dielectric layer 20 meets the pressure resistance requirements, the thickness of the first PP layer 21 is made smaller. This solves the problem of board warping caused by excessive shrinkage stress of the first PP layer 21 during the lamination process due to excessive thickness of the first PP layer 21.

[0058] It should be noted that the first replacement layer 22 can be made of low-shrinkage PI film (such as biphenyl-type PI). Biphenyl-type PI has a rigid biphenyl structure and strong intermolecular forces, with tightly packed molecular chains that are difficult to ionize and break down by an external electric field. The glass transition temperature (Tg) of biphenyl-type PI can be as high as 350°C or more, and the long-term service temperature exceeds 300°C. Its excellent heat resistance enables it to effectively resist thermal breakdown. The first PP layer 21 is made of high Tg PP to meet the requirements of high pressure resistance.

[0059] As one possible implementation, the first replacement layer 22 is located between the first PP layer 21 and the first line layer 31.

[0060] With this configuration, when the embedded layer 10, the first dielectric layer 20 and the first augmentation layer 30 are stacked together in sequence, a flexible copper-clad laminate including the first replacement layer 22 and the first circuit layer 31 can be used directly, that is, the first replacement layer 22 and the first circuit layer 31 are connected together in advance.

[0061] Optionally, the first circuit layer 31 includes a first circuit portion 301 and a second circuit portion 302 spaced apart, a first blind via 40 passing through the first circuit portion 301, and the first circuit portion 301 being connected to the first conductive portion 50.

[0062] When the first blind hole 40 is processed on the substrate 100, a second blind hole 41 is also processed on the substrate 100. The second blind hole 41 is spaced apart from the first blind hole 40. The second blind hole 41 passes through the second circuit portion 302, the first PP layer 21 and the first replacement layer 22. The heat sink 11 defines the bottom surface of the second blind hole 41. When the first conductive portion 50 is filled in the first blind hole 40, the second conductive portion 51 is filled in the second blind hole 41. The second circuit portion 302 and the heat sink 11 are both connected to the second conductive portion 51.

[0063] With this configuration, not only can the electronic device 12 and the first circuit section 301 be connected and electrically conductive through the first conductive part 50, but the heat sink 11 and the second circuit section 302 can also be connected through the second conductive part 51.

[0064] It should be noted that one or more second blind holes 41 may be provided. The second conductive part 51 can conduct heat from the heat sink 11 to the second circuit part 302 and dissipate it through the second circuit part 302, thereby improving the heat dissipation effect of the printed circuit board in which the electronic components 12 are embedded.

[0065] Optionally, a first blind via 40 is formed on the substrate 100, including: First, a portion of the first circuit layer 31 is etched away to obtain a first opening formed on the first circuit layer 31.

[0066] Then, a first connecting hole is machined in the first window opening, penetrating the first PP layer 21 and the first replacement layer 22. The first blind hole 40 includes the first window opening and the first connecting hole.

[0067] This design can solve the problem that the thickness of the first circuit layer 31 is too large, making it difficult to process the first blind hole 40 on the substrate 100.

[0068] Please refer to this as well. Figure 5 In this embodiment, after filling the first conductive portion 50 into the first blind hole 40, the method for manufacturing a printed circuit board in which the electronic device 12 is embedded further includes: First, a second dielectric layer 60 and a second additive layer 70 are stacked sequentially on the side of the first additive layer 30 away from the first dielectric layer 20. The second dielectric layer 60 includes a second PP layer 61 and a second replacement layer 62 stacked together. The second additive layer 70 includes a second circuit layer 71. The material of the second replacement layer 62 is PI or PTFE.

[0069] The structure and material of the second dielectric layer 60 may be similar to those of the first dielectric layer 20. The structure and material of the second reinforcement layer 70 may be similar to those of the first reinforcement layer 30. The second dielectric layer 60 and the second reinforcement layer 70 are riveted together with the substrate 100.

[0070] Secondly, a third blind via is fabricated that penetrates the second circuit layer 71, the second PP layer 61, and the second replacement layer 62, with a portion of the first circuit layer 31 defining the bottom surface of the third blind via.

[0071] The processing method of the third blind via can be similar to that of the first blind via 40. One or more third blind vias can be provided. When the second circuit layer 71 needs to be connected to the core board circuit of the embedded layer 10, blind vias or through-holes between the second circuit layer 71 and the core board of the embedded layer 10 can also be drilled by laser or mechanical drilling.

[0072] Next, the third conductive part 80 is filled into the third blind hole, and the second circuit layer 71 and the first circuit layer 31 are both connected to the third conductive part 80.

[0073] The method of filling the third blind hole with the third conductive part 80 is similar to the method of filling the first blind hole with the first conductive part 50.

[0074] It is understandable that after the third conductive part 80 is filled in the third blind hole, the outer layer circuit can be fabricated on the second circuit layer 71 by means of exposure, development and etching, and the quality of the outer layer circuit and the electroplating filling of the second blind hole 41 can be inspected by optical inspection.

[0075] By adopting the above solution, the problem of board warping can be avoided in the manufacturing method of multi-layer printed circuit boards with embedded electronic components 12.

[0076] Optionally, the second circuit layer 71 includes a third circuit section 701 and a fourth circuit section 702 spaced apart, a third blind via passing through the third circuit section 701, and the third circuit section 701 being connected to the third conductive section 80.

[0077] When a third blind hole is formed on the substrate 100, a fourth blind hole is formed on the substrate 100. The fourth blind hole is spaced apart from the third blind hole. The fourth blind hole passes through the fourth circuit portion 702, the second PP layer 61, and the second replacement layer 62. The second circuit portion 302 defines the bottom surface of the fourth blind hole. When the third blind hole is filled with a third conductive portion 80, the fourth blind hole is filled with a fourth conductive portion 81. Both the second circuit portion 302 and the fourth circuit portion 702 are connected to the fourth conductive portion 81.

[0078] With this configuration, not only can the third line section 701 and the first line section 301 be connected and electrically connected through the third conductive section 80, but the fourth line section 702 and the second line section 302 can also be connected through the fourth conductive section 81.

[0079] It should be noted that one or more fourth blind vias may be provided. The second conductive part 51 can conduct the heat from the heat sink 11 to the second circuit part 302, and then conduct it through the second circuit part 302 to the fourth circuit part 702 and dissipate it, thereby improving the heat dissipation effect of the printed circuit board in which the electronic components 12 are embedded.

[0080] It is understandable that after the third conductive part 80 is filled into the third blind hole, and the second circuit layer 71 and the first circuit layer 31 are both connected to the third conductive part 80, more dielectric layers and additional layers can be laminated on the second additional layer 70. This is achieved through multiple inner layer circuits and laminations. Finally, processes such as solder resist, character marking, testing, FQC (Final Quality Control, outgoing inspection) and packaging are carried out.

[0081] Solder resist: Solder resist treatment is performed according to conventional manufacturing methods. High-temperature heat dissipation PADs (pads) are not covered with solder resist.

[0082] Characters: Print the characters using the conventional method.

[0083] Test: Open-circuit and short-circuit test on the line.

[0084] FQC: FQC inspects the product.

[0085] Packaging and shipping: Pack and ship the qualified printed circuit boards according to requirements.

[0086] Please refer to Figures 6 to 8 In some embodiments, at least two first PP layers 21 are provided, and a first replacement layer 22 is located between two adjacent first PP layers 21.

[0087] By adopting the above solution, while ensuring that the total thickness of all first PP layers 21 meets the pressure resistance requirements, the thickness of each first PP layer 21 is relatively thin. This solves the problem of board warping caused by excessive shrinkage stress of the first PP layer 21 during the pressing process due to the excessive thickness of a single first PP layer 21.

[0088] Please refer to Figure 6 As one possible implementation, two first PP layers 21 are provided, and a first replacement layer 22 is located between the two first PP layers 21, with the two first PP layers 21 arranged symmetrically about the first replacement layer 22.

[0089] By adopting the above scheme, the first dielectric layer 20 can form a symmetrical structure, which can better balance the shrinkage stress of the two first PP layers 21 and prevent board warping.

[0090] When the first dielectric layer 20 adopts the above structure, the aperture of the first blind via 40 can be set to be relatively large, such as 200μm. The withstand voltage of the first replacement layer 22 is 120V*25μm=3000V, and the withstand voltage of the 50μm thick first PP layer 21 is 1000V, so the withstand voltage is 1000+1000=2000V. The combined thickness of the 25μm thick first replacement layer 22 and the 100μm thick first PP layer 21 is only 125μm, which can meet the requirement of a high voltage of over 4000V. Compared with the first dielectric layer 20, which requires a thickness of 200μm when using pure PP, its thickness is reduced from 200μm to 125μm.

[0091] After the thickness of the first dielectric layer 20 is reduced, when laser drilling the first blind hole 40, only a thickness of 125μm needs to be drilled. This can also improve the problem that the first blind hole 40 is concave after drilling due to the need for high energy, long time and multiple laser drillings caused by the excessive thickness of the first dielectric layer.

[0092] Meanwhile, as the thickness of the first dielectric layer 20 decreases, the aspect ratio of the first blind hole 40 decreases. Taking a hole diameter of 200μm as an example, its aspect ratio decreases from the original (hole depth 200 / hole diameter 200) 1:1 to (hole depth 125 / hole diameter 200) 0.625:1. The decrease in the aspect ratio of the blind hole can meet the requirement of electroplating filling process capability within 0.8:1, thereby improving the problem of poor filling of the first blind hole 40.

[0093] On the other hand, during pressing, only the first PP layer 21 melts and deforms, causing stress. The thickness of the first PP layer 21 is reduced from the original 200μm to two 50μm thick first PP layers 21, with a first replacement layer 22 between the two first PP layers 21. The other two 50μm thick first PP layers 21 melt and flow and shrink on both sides of the first replacement layer 22. The two first PP layers 21 are symmetrically arranged about the first replacement layer 22, and their stress can be offset to a certain extent. The smaller the thickness of a single first PP layer 21, the smaller the shrinkage stress during pressing. Therefore, reducing the thickness of the two single first PP layers 21 can solve the problem of board warping caused by shrinkage stress during pressing due to excessive thickness of a single first PP layer 21.

[0094] For example, two second PP layers 61 are provided, and a second replacement layer 62 is located between the two second PP layers 61, and the two second PP layers 61 are symmetrically arranged about the second replacement layer 62.

[0095] This configuration allows the second dielectric layer 60 to form a symmetrical structure, which can better balance the shrinkage stress of the two second PP layers 61 and prevent board warping.

[0096] When the first dielectric layer 20 and the second dielectric layer 60 adopt the above structure and are made of the same material, the aperture of the first blind hole 40 can be set to be relatively large, such as 200μm. The withstand voltage of the first replacement layer 22 is 120V*25μm=3000V, and the withstand voltage of the 50μm thick first PP layer 21 is 1000V, so the withstand voltage is 1000+1000=2000V. The combined thickness of the 25μm thick first replacement layer 22 and the 100μm thick first PP layer 21 is only 125μm, which can meet the requirement of a high voltage of over 4000V. Compared with the first dielectric layer 20, which requires a thickness of 200μm when made of pure PP, its thickness is reduced from 200μm to 125μm.

[0097] After the thickness of the first dielectric layer 20 is reduced, when laser drilling the first blind hole 40, only a thickness of 125μm needs to be drilled. This can also improve the problem that the first blind hole 40 is concave after drilling due to the need for high energy, long time and multiple laser drillings caused by the excessive thickness of the first dielectric layer.

[0098] Meanwhile, as the thickness of the first dielectric layer 20 decreases, the aspect ratio of the first blind hole 40 decreases. Taking a hole diameter of 200μm as an example, its aspect ratio decreases from the original (hole depth 200 / hole diameter 200) 1:1 to (hole depth 125 / hole diameter 200) 0.625:1. The decrease in the aspect ratio of the blind hole can meet the requirement of electroplating filling process capability within 0.8:1, thereby improving the problem of poor filling of the first blind hole 40.

[0099] On the other hand, during pressing, only the first PP layer 21 melts and deforms, causing stress. The thickness of the first PP layer 21 is reduced from the original 200μm to two 50μm thick first PP layers 21, with a first replacement layer 22 between the two first PP layers 21. The other two 50μm thick first PP layers 21 melt and flow and shrink on both sides of the first replacement layer 22. The two first PP layers 21 are symmetrically arranged about the first replacement layer 22, and their stress can be offset to a certain extent. The smaller the thickness of a single first PP layer 21, the smaller the shrinkage stress during pressing. Therefore, reducing the thickness of a single first PP layer 21 can solve the problem of board warping caused by shrinkage stress during pressing due to excessive thickness of a single first PP layer 21.

[0100] Please refer to Figure 7 As one possible implementation, the first dielectric layer 20 includes a first PP layer 21 and a first replacement layer 22 stacked together. One first PP layer 21 and one first replacement layer 22 are each provided. The first replacement layer 22 is located between the first PP layer 21 and the first line layer 31. Two second PP layers 61 are provided. The second replacement layer 62 is located between the two second PP layers 61, and the two second PP layers 61 are symmetrically arranged about the second replacement layer 62.

[0101] By adopting the above scheme, the second dielectric layer 60 can form a symmetrical structure, which can better balance the shrinkage stress of the two second PP layers 61 and prevent board warping.

[0102] When the first dielectric layer 20 and the second dielectric layer 60 adopt the above structure, the aperture of the first blind hole 40 can be set to 150μm, and the aperture of the second blind hole 41 can be larger than the aperture of the first blind hole 40.

[0103] The first replacement layer 22 and the first circuit layer 31 can be made of flexible copper clad laminate. The first dielectric layer 20 uses a 25μm thick first replacement layer 22 in combination with a 50μm thick first PP layer 21, and the second dielectric layer 60 uses a 25μm thick second replacement layer 62 in combination with two 50μm thick second PP layers 61.

[0104] The withstand voltage of both the first replacement layer 22 and the second replacement layer 62 is 120V*25μm=3000V. The withstand voltage of both the 50μm thick first PP layer 21 and the 50μm thick second PP layer 61 is 1000V, so the withstand voltage is 1000+1000=2000V. The thickness of the second replacement layer 62 (25μm thick) and the second PP layer 61 (100μm thick) is only 125μm, which can meet the requirement of high voltage exceeding 4000V. Compared with the second dielectric layer 60, which uses pure PP and requires a thickness of 200μm, its thickness is reduced from 200μm to 125μm.

[0105] After the thickness of the first dielectric layer 20 and the second dielectric layer 60 is reduced, when laser drilling the first blind hole 40 / second blind hole 41, only a thickness of 75μm / 125μm is needed for drilling. This can also improve the problem that the first blind hole 40 and the second blind hole 41 are concave after drilling due to the excessive thickness of the first dielectric layer 20 and the second dielectric layer 60, which requires high energy, long time and multiple laser drilling.

[0106] Meanwhile, as the thickness of the first dielectric layer 20 and the second dielectric layer 60 is reduced, the aspect ratio of the first blind hole 40 and the second blind hole 41 is reduced, which can meet the requirement of electroplating filling process capability within 0.8:1, thereby improving the problem of poor filling of the first blind hole 40 and the second blind hole 41.

[0107] On the other hand, the smaller the thickness of the first PP layer 21 and the second PP layer 61 during pressing, the smaller the shrinkage stress during pressing. Therefore, reducing the thickness of the first PP layer 21 and the second PP layer 61 can solve the problem of board warping caused by shrinkage stress during pressing due to excessive thickness of the first PP layer 21 and the second PP layer 61.

[0108] Please refer to Figure 8As one possible implementation, two first PP layers 21 are provided, and a first replacement layer 22 is located between the two first PP layers 21, and the two first PP layers 21 are symmetrically arranged about the first PP layers 21; the second dielectric layer 60 includes a second PP layer 61 and a second replacement layer 62 stacked together, and one of each second PP layer 61 and the second replacement layer 62 is provided.

[0109] By adopting the above scheme, the first dielectric layer 20 can form a symmetrical structure, which can better balance the shrinkage stress of the two first PP layers 21 and prevent board warping.

[0110] When the first dielectric layer 20 and the second dielectric layer 60 adopt the above structure, the aperture of the first blind hole 40 can be set to be greater than 150μm, and the aperture of the second blind hole 41 can be 150μm.

[0111] The second replacement layer 62 and the second circuit layer 71 can be made of flexible copper clad laminate. The second dielectric layer 60 uses a 25μm thick first replacement layer 22 in combination with two 50μm thick first PP layers 21, and the second dielectric layer 60 uses a 25μm thick second replacement layer 62 in combination with a 50μm thick second PP layer 61.

[0112] The withstand voltage of both the first replacement layer 22 and the second replacement layer 62 is 120V*25μm=3000V. The withstand voltage of both the 50μm thick first PP layer 21 and the 50μm thick second PP layer 61 is 1000V, so the withstand voltage is 1000+1000=2000V. The thickness of the first replacement layer 22 (25μm thick) and the first PP layer 21 (100μm thick) is only 125μm, which can meet the requirement of high voltage exceeding 4000V. Compared with the first dielectric layer 20, which uses pure PP and requires a thickness of 200μm, its thickness is reduced from 200μm to 125μm.

[0113] After the thickness of the first dielectric layer 20 and the second dielectric layer 60 is reduced, when laser drilling the first blind hole 40 / second blind hole 41, only the thickness of 125μm / 75μm needs to be drilled. This can also improve the problem that the first blind hole 40 and the second blind hole 41 are concave after drilling due to the excessive thickness of the first dielectric layer 20 and the second dielectric layer 60, which requires high energy, long time and multiple laser drilling.

[0114] Meanwhile, as the thickness of the first dielectric layer 20 and the second dielectric layer 60 is reduced, the aspect ratio of the first blind hole 40 and the second blind hole 41 is reduced, which can meet the requirement of electroplating filling process capability within 0.8:1, thereby improving the problem of poor filling of the first blind hole 40 and the second blind hole 41.

[0115] On the other hand, the smaller the thickness of the first PP layer 21 and the second PP layer 61 during pressing, the smaller the shrinkage stress during pressing. Therefore, reducing the thickness of the first PP layer 21 and the second PP layer 61 can solve the problem of board warping caused by shrinkage stress during pressing due to excessive thickness of the first PP layer 21 and the second PP layer 61.

[0116] It should be noted that the thickness of the single-layer first PP layer 21 and the single-layer second PP layer 61 is not limited to 50μm, and can be between 50μm and 100μm. The specific thickness can be designed based on the aperture of the first blind hole 40 and the space of the second blind hole 41, ensuring that the aspect ratio of the first blind hole 40 and the second blind hole 41 is within 0.8:1. The thickness of the first replacement layer 22 and the second replacement layer 62 is not limited to 25μm, and can be less than or greater than 25μm, depending on the pressure resistance requirements and the combined thickness of the first PP layer 21 and the second PP layer 61.

[0117] Secondly, embodiments of this application provide a printed circuit board with an embedded electronic device 12, including a substrate 100. The substrate 100 includes an embedded layer 10, a first dielectric layer 20, and a first addendum layer 30 arranged sequentially and in layers. A heat sink 11 is disposed inside the embedded layer 10, and the electronic device 12 is disposed on the heat sink 11. The first dielectric layer 20 includes a first PP layer 21 and a first replacement layer 22 arranged in layers. The material of the first replacement layer 22 is PI or PTFE. The first addendum layer 30 includes a first circuit layer 31. A first blind via 40 is disposed on the substrate 100. The first blind via 40 penetrates the first circuit layer 31, the first PP layer 21, and the first replacement layer 22. The electronic device 12 defines the bottom surface of the first blind via 40. A first conductive portion 50 is filled in the first blind via 40. The first circuit layer 31 and the electronic device 12 are both connected to the first conductive portion 50.

[0118] The printed circuit board with embedded electronic device 12 provided in this application embodiment includes a substrate 100 comprising a buried layer 10, a first dielectric layer 20, and a first augmentation layer 30 arranged sequentially and in layers. A heat sink 11 is disposed inside the buried layer 10, and the electronic device 12 is disposed on the heat sink 11. The first dielectric layer 20 includes a first PP layer 21 and a first replacement layer 22 arranged in layers. The material of the first replacement layer 22 is PI or PTFE. The first augmentation layer 30 includes a first circuit layer 31. Furthermore, a first blind via 40 is provided on the substrate 100. The hole 40 penetrates the first circuit layer 31, the first PP layer 21, and the first replacement layer 22. The electronic device 12 defines the bottom surface of the first blind hole 40. The first blind hole 40 is filled with a first conductive part 50. The first circuit layer 31 and the electronic device 12 are both connected to the first conductive part 50. Therefore, while ensuring that the first dielectric layer 20 meets the pressure resistance requirements, the thickness of the first PP layer 21 is relatively small. This solves the problem of board warping caused by excessive shrinkage stress of the first PP layer 21 during the pressing process due to excessive thickness of the first PP layer 21.

[0119] Optionally, at least two first PP layers 21 are provided, and the first replacement layer 22 is located between two adjacent first PP layers 21.

[0120] This configuration ensures that the total thickness of all first PP layers 21 meets the pressure resistance requirements, while also making each first PP layer 21 relatively thin. This solves the problem of board warping caused by excessive shrinkage stress of the first PP layer 21 during the pressing process due to the excessive thickness of a single first PP layer 21.

[0121] Thirdly, embodiments of this application provide a printed circuit board with embedded electronic devices 12, which is manufactured by the manufacturing method of the printed circuit board with embedded electronic devices 12 as described in the first aspect.

[0122] The printed circuit board with embedded electronic devices 12 provided in this embodiment of the application first stacks the embedded layer 10, the first dielectric layer 20, and the first augmentation layer 30 together in sequence during processing. A heat sink 11 is disposed inside the embedded layer 10, and the electronic devices 12 are disposed on the heat sink 11. The first dielectric layer 20 includes a first PP layer 21 and a first replacement layer 22 stacked together. The material of the first replacement layer 22 is PI or PTFE. The first augmentation layer 30 includes a first circuit layer 31. Then, the embedded layer 10, the first dielectric layer 20, and the first augmentation layer 30 are pressed together to obtain a substrate 100. Then, on the substrate... A first blind hole 40 is machined on the 100. The first blind hole 40 penetrates the first circuit layer 31, the first PP layer 21 and the first replacement layer 22. The electronic device 12 defines the bottom surface of the first blind hole 40. The first conductive part 50 is then filled in the first blind hole 40. The first circuit layer 31 and the electronic device 12 are both connected to the first conductive part 50. Therefore, while ensuring that the first dielectric layer 20 meets the pressure resistance requirements, the thickness of the first PP layer 21 is small. This solves the problem of board warping caused by excessive shrinkage stress of the first PP layer 21 during the pressing process due to excessive thickness of the first PP layer 21.

[0123] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for manufacturing a printed circuit board with embedded electronic components, characterized in that, include: An embedded layer, a first dielectric layer, and a first augmentation layer are stacked together in sequence. A heat dissipation base is provided inside the embedded layer, and electronic devices are provided on the heat dissipation base. The first dielectric layer includes a first PP layer and a first replacement layer stacked together. The material of the first replacement layer is PI or PTFE. The first augmentation layer includes a first circuit layer. The embedded layer, the first dielectric layer, and the first build-up layer are laminated together to obtain a substrate; A first blind via is formed on the substrate, the first blind via penetrating the first circuit layer, the first PP layer and the first replacement layer, and the electronic device defines the bottom surface of the first blind via; A first conductive portion is filled inside the first blind hole, and both the first circuit layer and the electronic device are connected to the first conductive portion.

2. The method for manufacturing a printed circuit board with embedded electronic devices according to claim 1, characterized in that, At least two first PP layers are provided, and the first replacement layer is located between two adjacent first PP layers.

3. The method for manufacturing a printed circuit board with embedded electronic components according to claim 2, characterized in that, Two first PP layers are provided, and the first replacement layer is located between the two first PP layers, and the two first PP layers are symmetrically arranged about the first replacement layer.

4. The method for manufacturing a printed circuit board with embedded electronic components according to claim 1, characterized in that, The first replacement layer is located between the first PP layer and the first line layer.

5. The method for manufacturing a printed circuit board with embedded electronic devices according to claim 1, characterized in that, The process of forming the first blind hole on the substrate includes: Etching removes a portion of the first circuit layer to obtain a first opening formed on the first circuit layer; A first connecting hole is machined inside the first window opening, penetrating the first PP layer and the first replacement layer. The first blind hole includes the first window opening and the first connecting hole.

6. The method for manufacturing a printed circuit board with embedded electronic devices according to claim 1, characterized in that, The first circuit layer includes a first circuit portion and a second circuit portion that are spaced apart. The first blind via passes through the first circuit portion, and the first circuit portion is connected to the first conductive portion. When the first blind hole is processed on the substrate, a second blind hole is processed on the substrate. The second blind hole is spaced apart from the first blind hole. The second blind hole penetrates the second circuit portion, the first PP layer, and the first replacement layer. The heat sink defines the bottom surface of the second blind hole. When the first blind hole is filled with a first conductive portion, the second blind hole is filled with a second conductive portion. The second circuit portion and the heat sink are both connected to the second conductive portion.

7. The method for manufacturing a printed circuit board with embedded electronic devices according to any one of claims 1 to 6, characterized in that, After filling the first conductive portion into the first blind hole, the method for manufacturing the printed circuit board with embedded electronic devices further includes: A second dielectric layer and a second additional layer are stacked sequentially on the side of the first additional layer away from the first dielectric layer. The second dielectric layer includes a second PP layer and a second replacement layer stacked together. The material of the second replacement layer is PI or PTFE. The second additional layer includes a second circuit layer. A third blind via is fabricated that penetrates the second circuit layer, the second PP layer, and the second replacement layer, with a portion of the first circuit layer defining the bottom surface of the third blind via; A third conductive portion is filled within the third blind via, and both the second circuit layer and the first circuit layer are connected to the third conductive portion.

8. A printed circuit board with embedded electronic components, characterized in that, The system includes a substrate comprising a buried layer, a first dielectric layer, and a first add-on layer stacked sequentially. A heat sink is disposed within the buried layer, and electronic devices are disposed on the heat sink. The first dielectric layer comprises a first polypropylene (PP) layer and a first replacement layer stacked together. The first replacement layer is made of PI or PTFE. The first add-on layer comprises a first circuit layer. A first blind via is disposed on the substrate, penetrating the first circuit layer, the first PP layer, and the first replacement layer. The electronic devices define the bottom surface of the first blind via. The first blind via is filled with a first conductive portion, and both the first circuit layer and the electronic devices are connected to the first conductive portion.

9. The printed circuit board with embedded electronic devices according to claim 8, characterized in that, At least two first PP layers are provided, and the first replacement layer is located between two adjacent first PP layers.

10. A printed circuit board with embedded electronic components, characterized in that, The printed circuit board with embedded electronic devices is manufactured by the method for manufacturing a printed circuit board with embedded electronic devices as described in any one of claims 1 to 7.

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