Data gating using scan enable pins

Abstract

The invention relates to data gating using scan enable pins. The present disclosure provides an integrated circuit (100) comprising a storage element (102) and a control circuit (106, 110). The control circuit is configured to: in response to a scan enable control, select between a functional data input and a scan data input for use as an input to the memory element; selectively disabling the back-and-forth switching of the output of the storage element by gating a clock signal provided to the storage element in response to a clock enable control; and selecting an input of the storage element as the scan data input when the clock enable control indicates that the output of the storage element is to be prohibited from switching back and forth.

Description

[0001] This application is a divisional application of the invention patent application with international application number PCT / US2022 / 019219, international application date March 8, 2022, which entered the Chinese national phase on November 27, 2023, with application number 202280038300.1 and invention title "Data Gating Using Scan Enable Pin". Technical Field

[0002] This disclosure relates in general to integrated circuits, and more particularly to power reduction of gated clock circuits in integrated circuits. Background Technology

[0003] To alleviate the testing challenges of integrated circuits (ICs) containing millions of transistors, a scan mode is often implemented, where the IC's flip-flops are daisy-chained, allowing for simple scan chain testing of what would otherwise be a complex state machine. For an overview of scan testing techniques, see, for example, “Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic,” IEEE Transactions on Computers, C-22(1), 46-60; M. Williams and J. Angell (doi:10.1109 / tc.1973.223600).

[0004] Clock gating is often used to reduce the dynamic power consumption of multi-million transistor ICs. In “Clock Gating – A Power Optimization Technique for VLSI Circuits” (J. Shinde et al., 2011 Annual IEEE India Conference, December 16-18, 2011; DOI 10.1109 / INDCON.2011.6139440), the authors investigated various clock gating techniques that can be used to optimize power in VLSI circuits at the RTL level and discussed the various issues involved in applying this power optimization technique at the RTL level. Summary of the Invention

[0005] The embodiments described herein provide an integrated circuit (IC) including a storage element and control circuitry. The control circuitry is configured to: select between a function data input and a scan data input for use as an input to the storage element in response to a scan enable control; selectively disable switching back and forth of the storage element's output by gating a clock signal provided to the storage element in response to a clock enable control; and select the storage element's input as the scan data input when the clock enable control indicates that switching back and forth of the storage element's output will be disabled.

[0006] In some implementations, the storage element includes one or more latches, and when the scan data input is selected, the control circuitry is configured to prevent any of the latches from switching back and forth when the output is disabled, regardless of whether the function data input is being switched. In one exemplary implementation, the control circuitry is configured to prevent the latch from switching back and forth without adding delay to the function data input.

[0007] In the embodiments disclosed in this invention, by selecting the scan data input when the clock enable control indicates that the output will be prohibited from switching back and forth, the control circuit is configured to set the input to the storage element to a constant logic state, regardless of whether the function data input is switching. In another embodiment, the control circuit includes a logic gate configured to set the storage element to scan mode in response to the clock enable control disabling the clock signal.

[0008] In another embodiment, the control circuit includes a logic gate configured to set the input of the storage element to a constant logic state in response to the clock enable control disabling the clock signal. In another embodiment, the storage element includes a latch clocked by the inversion of the clock signal, and the control circuit is configured to set the input of the latch to a constant logic state when the clock enable control indicates that the output will be prohibited from switching back and forth when the scan data input is selected.

[0009] According to the embodiments described herein, a method is also provided in an integrated circuit (IC) that includes at least a memory element. The method includes selecting between a functional data input and a scan data input for use as an input to the memory element in response to a scan enable control. In response to a clock enable control, selectively disabling back-and-forth switching of the output of the memory element by gating a clock signal provided to the memory element. When the clock enable control indicates that back-and-forth switching of the output of the memory element will be disabled, the input of the memory element is selected as the scan data input.

[0010] According to the embodiments described herein, an apparatus including a processor is also provided, the processor including (i) a fetch circuit configured to fetch instructions, and (ii) an execution circuit configured to execute instructions. One or both of the fetch circuit and the execution circuit include a storage element and control circuitry. The control circuitry is configured to: select between a function data input and a scan data input for use as an input to the storage element in response to a scan enable control; selectively disable switching back and forth of the output of the storage element by gating a clock signal provided to the storage element in response to a clock enable control; and select the input of the storage element as the scan data input when the clock enable control indicates that switching back and forth of the output of the storage element will be disabled.

[0011] This disclosure will be more fully understood from the following detailed description of embodiments thereof, taken in conjunction with the accompanying drawings, in which: Attached Figure Description

[0012] Figure 1 This is a block diagram schematically illustrating the structure of an integrated circuit (IC) according to the embodiments described herein;

[0013] Figure 2 This is a block diagram schematically illustrating the structure of a D-type flip-flop (DFF) coupled to a scan circuit and a clock-gated circuit, according to the implementation described herein;

[0014] Figure 3 This is a block diagram schematically illustrating the structure of a computer according to the embodiments described herein;

[0015] Figure 4 This is a flowchart illustrating a method for reducing power consumption using data gating, based on the implementation described herein.

[0016] Figure 5 The diagrams are schematic illustrations of various types of systems that may include any of the circuits, devices, or systems discussed herein, based on the embodiments described herein; and

[0017] Figure 6 This is a block diagram illustrating an exemplary non-transitory computer-readable storage medium according to some implementation schemes, showing storage circuit design information. Detailed Implementation

[0018] Overview

[0019] Typically, complex integrated circuits include memory elements, each configured to store a "logic -1" or "logic -0" value. In this context, the term "memory element" refers to elements such as flip-flops, latches, etc. For example, the embodiments described herein refer to flip-flops, but the techniques disclosed in this invention are applicable to other suitable types of memory elements.

[0020] There are various types of flip-flops, including, for example, clocked flip-flops and non-clocked flip-flops, RS flip-flops, JK flip-flops, T flip-flops, etc. A common type of flip-flop widely used in modern integrated circuits is the D flip-flop (sometimes called a DFF), which includes a D input, a clock input, and an output. A DFF is configured to store a logic value asserted at its D input when the clock input transitions, for example, from logic low to logic high. In the following disclosure, for example, flip-flops and DFFs are sometimes referred to interchangeably.

[0021] To facilitate easy testing of digital integrated circuits, a scan circuit can be added to a group of digital fairings (DFFs) within the integrated circuit. An external tester can instruct the scan circuit to use a scan mode (or scan enable), in which case the group of DFFs should be scanned. The scan circuit is configured to sequentially interconnect (e.g., "daisy-chain") the DFFs in the group in response to the scan mode instruction, such that scan inputs outside the group propagate between the DFFs in the group, from the first DFF to the last DFF, and from the last DFF to the scan-out output of the group of DFFs. (Two modes of integrated circuit operation will be discussed below—one being the scan mode described above, and the other being a functional mode, in which the scan circuit is not active and the DFFs receive functional inputs instead of scan inputs.)

[0022] In the following text, logic low and logic high will be further referred to as low level and high level, respectively; the transition from low to high will be called the rising edge (or "positive edge"), and the transition from high to low will be called the falling edge (or "negative edge"). It should be understood that low level and high level do not necessarily represent voltage levels; for example, in some logic families, low level and high level can indicate the direction of current; furthermore, in some logic families, low level represents a voltage higher than the voltage level represented by high level (e.g., in negative logic).

[0023] A DFF typically consists of a primary latch and a secondary latch. In a positive-edge triggered DFF, when the clock input is low, the primary latch propagates the D input of the DFF to the input of the secondary latch and latches the value of the D input on the rising edge of the clock; when the clock input is high, the secondary latch propagates the output of the primary latch to the DFF output and latches the value of the primary latch on the falling edge of the clock. Conversely, in a negative-edge triggered DFF, the primary latch propagates the input on the high edge of the clock and latches on the negative edge of the clock, while the secondary latch propagates the output of the primary latch on the low edge of the clock and latches the output on the rising edge of the clock. (Note that the primary interrupt latch and the secondary latch can operate in a manner also referred to by those skilled in the art as "master" (i.e., primary) and "slave" (i.e., secondary). Although the primary / secondary terminology is used herein, it is explicitly intended that "primary" and "secondary" be interpreted to encompass these corresponding terms.)

[0024] High-speed, high-density integrated circuits can comprise millions of DFFs (Distributed Clock Factors), and the back-and-forth switching of the clock inputs of these DFFs is a significant factor in the power consumption of the integrated circuit. A common technique for reducing power consumption is clock gating, in which the clock signal is disabled in unused sections of the circuit. Clock gating saves power by pruning the clock tree, but at the cost of adding more logic components to the circuit.

[0025] Typically, when the DFF's clock is disabled, the DFF's clock input is set to logic level, where the primary latch is transparent (i.e., it propagates the D input to the secondary latch) but does not latch the logic value. The secondary latch stores the last value output by the primary latch at the falling edge of the clock (e.g., for a positive-edge triggered DFF, the clock is set low). Therefore, power dissipation is significantly reduced because the secondary latch does not switch back and forth. (Secondary latches typically drive logic circuitry and charge and discharge additional nodes during switching, resulting in significant power dissipation.)

[0026] However, when the primary latch is transparent, it typically switches back and forth on the D input, even if the DFF clock is disabled and the changes in the D input are not visible at the secondary latch output. Therefore, even if the DFF clock is disabled, the switching of the secondary latch can still result in significant power consumption.

[0027] The embodiments described herein provide apparatus and methods that utilize data gating in addition to clock gating of the clock-disabled DFF, to further reduce the power consumption of the clock-disabled DFF. In some embodiments, the control circuitry is configured to direct a constant scan enable input (when no scan is indicated) to the corresponding DFF input in response to a clock disable input, thereby setting the DFF input to a constant logic level. Therefore, when the clock is disabled, both the data input and the clock input are gated, significantly reducing the power consumption of the integrated circuit.

[0028] Furthermore, the control circuitry disclosed in this invention does not add any logic components to the functional data path (e.g., before the functional input of the flip-flop). Therefore, the technology disclosed in this invention does not introduce additional latency and does not reduce the achievable data throughput or clock speed.

[0029] System Description

[0030] Figure 1 This is a block diagram schematically illustrating the structure of an integrated circuit (IC) 100 according to an embodiment described herein. IC 100 may include any suitable type of IC configured to perform any appropriate function, such as a microprocessor, video processor, or any other IC. The IC includes: a set of dual-latch D-type flip-flops (DFFs) 102 sharing a common clock input (designated "clock"); and combinational logic circuitry 104 configured to generate functional inputs for the DFFs 102 in response to data stored in the DFFs (and possibly in response to other inputs). Each DFF includes a clock input ("CLK"), a D input, and a Q output (in this embodiment, the DFF 102 may include other inputs, such as a reset).

[0031] It should be understood that the integrated circuit according to some embodiments may include multiple clock inputs and multiple groups of DFFs, each group of DFFs sharing one of the multiple clock inputs. In some embodiments, IC 100 may include other logic components, such as non-clocked flip-flops, memory, analog circuitry, etc. However, for clarity, the following will refer to embodiments in which IC 100 includes a single clock, and circuitry unrelated to the DFF group, such as memory, analog subsystems, etc., will be ignored.

[0032] according to Figure 1 In the exemplary embodiment shown, IC 100 includes scan circuits 106, each scan circuit being coupled to a corresponding DFF 102 and configured to transmit a functional input (from the output of combinational logic circuit 104) or a scan input to the D input of the DFF in response to a scan enable input.

[0033] DFF 102 are daisy-chained together, such that the scan input of the first DFF is coupled to the SCAN-IN input of IC 100, the scan input of the second DFF is coupled to the Q output of the first DFF, and so on. The Q output of the last DFF is coupled to the SCAN-OUT output of IC 100. (In some implementations, SCAN-IN and / or SCAN-OUT are not inputs / outputs of IC 100; instead, scan-in may be an input from the built-in self-test (BIST) circuitry in IC 100 and / or SCAN-OUT may be an output to the built-in self-test (BIST) circuitry in IC 100.)

[0034] IC 100 also includes a clock disable circuit 108 configured to disable the clock input of DFF 102 that may be inactive. A clock gating circuit 110 is coupled to each DFF 102; this clock gating circuit is configured to disable the clock input of the DFF in response to a clock disable control output from the clock disable circuit 108 (e.g., by applying a constant logic low level to the clock input of the DFF). As described above, this prevents the secondary latches of the DFF 102 from switching back and forth, thereby reducing power consumption.

[0035] according to Figure 1 The exemplary implementation shown employs data gating in addition to clock gating to prevent the primary latch (in addition to the secondary latch) from switching back and forth. (In the following...) Figure 2 An exemplary internal structure of the dual-latch flip-flop 102 is described, showing the primary latch and the primary latch. The scan circuit 106 is configured to send a constant logic level (e.g., low) to the D input of the corresponding DFF in response to a clock disable input. Therefore, the primary latch will not switch, and additional power reduction will be achieved (in an embodiment, in response to a clock disable input, the scan circuit sends a scan enable input to the D input of the DFF, which is a constant low level in functional mode).

[0036] It should be understood that Figure 1 The structure of IC 100 shown and described above is an exemplary embodiment cited for clarity. In alternative embodiments, other structures may be used. For example, a scan circuit may also be used to set the DFF to a known state; other types of flip-flops may be used; and more than one scan chain may be implemented in the IC.

[0037] In this context, the scanning circuit 106 and the clock gating circuit 110 are collectively referred to as the "control circuit" that implements the technology disclosed in this invention; however, in other embodiments, the control circuit that implements the technology disclosed in this invention may use the same... Figure 1Different circuits or different organizations may implement this. In this context, the terms "clock enable input" and "clock disable input" are used interchangeably to refer to signals that control whether the clock is enabled or disabled.

[0038] Figure 2 This is a block diagram schematically illustrating the structure of the DFF 102 coupled to the scan circuit 106 and the clock gate 110 according to the embodiment described herein. This document is based on... Figure 2 The example implementation shown describes the reference in more detail. Figure 1 The DFF 102, scan circuit 106, and clock gate 110 are discussed below. For ease of presentation, they are described below. Figure 2 The logic function of an embodiment of the scan circuit 106 and clock gate 110 in relation to AND and OR gates is shown. However, it should be noted that any suitable circuit structure can be used to implement the shown functionality.

[0039] The DFF 102 includes two latches—a primary latch 202 and a secondary latch 204. When the clock input is low, the primary latch propagates the D input of the DFF to the input of the secondary latch and latches the value of the D input on the rising edge of the clock. When the clock input is high, the secondary latch propagates the output of the primary latch to the output of the DFF and latches the value of the primary latch on the falling edge of the clock.

[0040] The clock input of DFF 102, shared by primary latch 202 and secondary latch 204, is generated by clock gating 110. According to... Figure 2 In the exemplary embodiment shown, the clock gate 110 is an AND gate that propagates the clock input to the DFF clock input when the clock enable input is high, and sets the DFF clock input to low when the clock enable input is low, thereby preventing the secondary latch from switching back and forth.

[0041] The scanning circuit 106 includes: a multiplexer 206 configured to select the source for the D input of the DFF 102; an AND gate 208 configured to gate the scan data; an inverter 209; and an OR gate 210 configured to indicate which source the multiplexer 206 should send to the D input of the DFF 102.

[0042] In scan mode, the scan enable input is high, AND gate 208 outputs scan-in data, and OR gate 210 outputs logic high, causing multiplexer 206 to transmit the output of AND gate 208 to the D input of DFF 102. Therefore, a scan path is configured, and the scan input propagates through the Q output of DFF 102 (and thus to the scan input of the next DFF stage scan circuit, such as...). Figure 1(As shown in the diagram). In functional mode, the scan enable input is low, and if the clock enable input is high, the multiplexer 206 transmits the functional input to the D input of the DFF 202.

[0043] However, in functional mode, if the clock enable is low, OR gate 210 instructs multiplexer 206 to send the output of AND gate 208 to the D input of DFF 102. When the scan enable input is now low, inverter 209 outputs high and AND gate 208 outputs low, the D input of DFF 102 will be low, and thus, regardless of any switching in the functional input, primary latch 202 will not switch back and forth, further reducing power consumption.

[0044] It should be understood that Figure 2 The structures of DFF 102, scan circuit 106, and clock gate 110 shown and described above are referenced by way of example. In alternative embodiments, various suitable structures may be used. For example, a De Morgan equivalent of the gate shown may be used. In some embodiments, the scan enable input and / or clock enable input may be active low. In embodiments, other types of DFFs may be used, and in some embodiments, some or all of the DFFs may be replaced by other types of flip-flops (e.g., T flip-flops).

[0045] In this example, besides trigger 102 Figure 2 Various components (scanning circuit 106 and clock gate 110) serve as control circuitry for performing the technology disclosed in this invention. In alternative embodiments, the control circuitry may have any other suitable configuration.

[0046] Figure 3 This is a block diagram schematically illustrating the structure of a computer 300 according to the embodiments described herein. The computer 300 includes a central processing unit (CPU) 304 and a memory 306. The CPU includes: an instruction fetch circuit 308 configured to fetch and decode instructions (e.g., from memory 306); and an instruction execution circuit 310 configured to execute the decoded instructions.

[0047] Users can interact with computer 300 through a display device and one or more input devices (in this example, the monitor / keyboard / mouse subsystem 312). It should be understood that computer 300 may include multiple CPUs and many other components, including, for example, encryption / decryption units, graphics processors, network interface circuitry, analog circuitry, and wireless interface units.

[0048] The instruction fetch circuit 308 and the instruction execution circuit 310 include multiple flip-flops, such as Figure 1 and Figure 2Trigger 102. According to Figure 3 In the exemplary embodiment shown, CPU 304 includes a scan chain 316 that covers at least some flip-flops in instruction fetch circuitry 308 and instruction execution circuitry 310 (and / or additional logic circuitry that CPU 300 may include). The scan chain includes scan circuitry (e.g., Figure 2 The scan circuit 106 is configured to operate the corresponding flip-flop in scan mode and to set the D input of the flip-flop to a constant logic level, for example by routing the scan enable input to the D input of the flip-flop, when the clock of the corresponding flip-flop is disabled.

[0049] Figure 4 This is a schematic flowchart illustrating a method 400 for reducing power consumption using data gating, according to the embodiment described herein. The flowchart consists of a clock gating system 110 and a scanning circuit 106. Figure 1 The process is executed independently of the other scan circuits and clock gates.

[0050] The flowchart begins at the check-scan-enable stage 402, where the scan circuit checks whether scan-enable is indicated. If so, the flowchart proceeds to the "routing scan to flip-flop" stage 404, where the scan circuit routes the scan-in input to the D input of DFF 102, enters the scan test of DFF, and the flowchart ends.

[0051] If there is no scan enable indication in stage 402, the clock gating and scan circuitry enters the check-clock-enable stage 406 and checks whether the clock of the corresponding DFF is enabled. If it is, the clock gating and scan circuitry enters the functional operation stage 408, where the scan mode is disabled and the clock is not gated, and then the flowchart ends.

[0052] If the clock is not enabled in stage 406, the scan circuit will route the scan input (which is set low in functional mode) to the D input of DFF 102 in the "Route Scan Input to Flip-Flop" stage 410, so that the primary latch of DFF will not switch back and forth. Then, in the "Force Flip-Flop Clock Low" stage, the clock gate 110 sets the clock input of the flip-flop to low, thereby preventing the secondary latch from switching back and forth.

[0053] Therefore, according to Figure 4As shown and described above, the clock gating and scan circuitry is operable to route the scan-in input to the D input of the corresponding flip-flop in response to a scan mode indication (scan enable high); and in response to a clock disable indication (clock enable low), i) force a constant low level at the clock input of the flip-flop to prevent the secondary latch from switching back and forth, and ii) route the scan enable input (which is low in functional mode) to the D input of the flip-flop to prevent the primary latch from switching back and forth.

[0054] Figure 5 This diagram 500 is a schematic illustration of various types of systems that may include any of the circuits, devices, or systems discussed above, according to embodiments described herein. Systems or devices 500 that may utilize one or more of the techniques described herein in combination with or otherwise utilize them can be used in a wide range of fields. For example, system or device 500 may be used as part of the hardware of a system such as a desktop computer 510, a laptop computer 520, a tablet computer 530, a cellular or mobile phone 540, or a television 550 (or a set-top box coupled to a television).

[0055] Similarly, the disclosed components can be used in wearable devices 560, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0056] System or device 500 can also be used in a variety of other contexts. For example, system or device 500 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based services 570. Furthermore, system or device 500 can be implemented in a wide range of dedicated everyday devices, including common household devices 580 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Components can also be implemented in various modes of transportation. For example, system or device 500 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 590.

[0057] Figure 5The applications shown are merely illustrative and are not intended to limit the potential future applications of the disclosed systems or devices. Other illustrative applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0058] Various exemplary circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuits, but also computer-readable storage media that include design information specifying such circuits. Therefore, this disclosure is intended to support claims that cover not only devices including the disclosed circuits, but also storage media specifying circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., integrated circuits) including the disclosed circuits. Claims regarding such storage media are intended to cover entities that, for example, generate circuit designs but do not manufacture those designs themselves.

[0059] Figure 6 This is a block diagram illustrating an exemplary non-transitory computer-readable storage medium for storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 620 is configured to process design information 615 stored on a non-transitory computer-readable medium 610 and manufacture an integrated circuit 830 based on the design information 615.

[0060] Non-transitory computer-readable storage medium 610 may include any of a variety of suitable types of memory devices or storage devices. Non-transitory computer-readable storage medium 610 may be installation media, such as CD-ROM, floppy disk, or magnetic tape devices; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory such as flash memory, magnetic media, such as hard disk drives or optical storage devices; registers, or other similar types of memory elements. Non-transitory computer-readable storage medium 610 may also include other types of non-transitory memory or combinations thereof. Non-transitory computer-readable storage medium 810 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0061] Design information 615 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 615 may be used by semiconductor manufacturing system 620 to manufacture at least a portion of integrated circuit 630. The format of design information 615 can be recognized by at least one semiconductor manufacturing system 620. In some embodiments, design information 615 may also include one or more cell libraries specifying the composition, layout, or both of integrated circuit 630. In some embodiments, the design information is specified, wholly or partially, in the form of a netlist specifying cell library elements and their connectivity. Design information 615 acquired separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 615 may specify circuit elements to be manufactured but not their physical layout. In this case, design information 815 may need to be combined with layout information to actually manufacture the specified circuit system.

[0062] In various implementations, integrated circuit 630 may include one or more custom macrocells, such as memory, analog or mixed-signal circuitry, etc. In this case, design information 615 may include information associated with the included macrocells. Such information may include, but is not limited to, a circuit diagram capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0063] Semiconductor manufacturing system 620 may include any of the various suitable elements configured to manufacture integrated circuits. This may include elements for, for example, depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or modifying the dielectric constant using ultraviolet light treatment), etc. Semiconductor manufacturing system 820 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0064] In various embodiments, integrated circuit 630 is configured to operate according to a circuit design specified by design information 615, which may include any of the functions described herein. For example, integrated circuit 630 may include Figure 1 , Figure 2 , Figure 3 and Figure 5 Any of the various components shown herein. Additionally, integrated circuit 630 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0065] As used herein, a phrase in the form of “design information specifying the design of a circuit configured to…” does not imply that the circuit in question must be manufactured in order to satisfy this element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components.

[0066] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0067] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with an embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside this disclosure, any potential advantages described herein should not be construed as a claim limitation that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to show one or more types of improvements available to a designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0068] Unless otherwise indicated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even in cases where only a single example is described for a particular feature. The disclosed embodiments of the present invention are intended to be exemplary rather than limiting, without any contrary statement in this disclosure. Accordingly, this application intends to allow claims that cover the disclosed embodiments, as well as such alternative, modified, and equivalent forms, which will be apparent to those skilled in the art aware of the effective effects of this disclosure.

[0069] For example, the features in this application can be combined in any suitable manner. Thus, new claims can be made during the prosecution of this patent application (or a patent application claiming priority therefrom) for any such combination of features. Specifically, referring to the appended claims, the features of dependent claims can be combined with the features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, the features from corresponding independent claims can be combined where appropriate.

[0070] Thus, although the appended dependent claims can be drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with this disclosure is contemplated, and such combinations can be claimed in this patent application or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0071] Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0072] ***

[0073] Since this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs and the definitions provided throughout this disclosure will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0074] References to items in the singular form (i.e., a noun or noun phrase preceded by "a", "an", or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. A "plurality" of items means a collection of two or more items.

[0075] The word "may" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0076] The terms “include” and “including” and their forms are open-ended and mean “including but not limited to”.

[0077] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both,” and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0078] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0079] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0080] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0081] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor along with other unspecified factors. Consider the phrase “responding to B to execute A.” This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover implementations where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0082] ***

[0083] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as “configured” to perform a task refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions. This phrase is not used herein to refer to intangible things.

[0084] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0085] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0086] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 U.SC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) in the course of filing a U.S. patent application based on this disclosure, it will use the structure “means for [performing a function]” to state the elements of the claims.

[0087] Different “circuits” may be described in this disclosure. These circuits, or “circuitry”, constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuit systems.

[0088] Therefore, the circuits / units / components and other elements disclosed in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0089] In various implementations, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to perform, relative to each other, and the manner in which such circuits / cells / components interact, forms a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations are derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain the final design database that is transferred to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry system. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0090] The fact that a circuit of the same specifications can be implemented using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0091] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An integrated circuit IC, comprising: Storage elements, with inputs and outputs; as well as The control circuit is configured as follows: Receive clock enable control; as well as When the clock enable control indicates that the output of the storage element will be prohibited from switching back and forth, the input is set to a constant logic state to prevent the input of the storage element from switching back and forth without adding delay to the functional data input of the storage element.

2. The IC according to claim 1, wherein: The storage element is a dual-latch flip-flop (FF) comprising a primary latch and a secondary latch. When a clock signal is provided to the storage element, the control circuit is configured to set the primary latch to transparent mode, and To prevent the input of the storage element from switching back and forth, the control circuit is configured to set the input of the primary latch to the constant logic state.

3. The IC of claim 1, wherein the storage element comprises one or more latches, and wherein, when the input is set to the constant logic state, the control circuitry is configured to prevent any of the latches from switching when the output is prohibited from switching back and forth, regardless of whether the functional data input of the storage element is switching.

4. The IC of claim 1, wherein, in order to set the input to the constant logic state, the control circuitry includes a logic gate configured to set the memory element to a scan mode in response to the clock enable control disabling a clock signal provided to the memory element.

5. The IC of claim 1, wherein the control circuitry includes logic gates configured to set the input of the memory element to the constant logic state in response to the clock enable control disabling a clock signal provided to the memory element.

6. A method in an integrated circuit (IC), said integrated circuit including at least a memory element having inputs and outputs, the method comprising: Receive clock enable control; as well as When the clock enable control indicates that the output of the storage element will be prohibited from switching back and forth, the switching back and forth of the input of the storage element is prevented by setting the input to a constant logic state, without adding delay to the functional data input of the storage element.

7. The method according to claim 6, wherein: The storage element is a dual-latch flip-flop (FF) comprising a primary latch and a secondary latch. The gating provided to the memory element includes setting the primary latch to transparent mode, and Preventing the input of the storage element from switching back and forth includes setting the input of the primary latch to the constant logic state.

8. The method of claim 6, wherein the storage element comprises one or more latches, and wherein setting the input to the constant logic state comprises preventing any of the latches from switching while the output is prohibited from switching back and forth, regardless of whether the functional data input of the storage element is switching.

9. The method of claim 6, wherein setting the input of the storage element to the constant logic state comprises setting the storage element to a scan mode using logic gates in response to the clock enable control disabling the clock signal provided to the storage element.

10. The method of claim 6, wherein in response to the clock enable control disabling the clock signal provided to the memory element, a logic gate is used to set the input of the memory element to the constant logic state.

11. An apparatus including a processor, the processor comprising (i) a fetch circuit configured to fetch instructions and (ii) an execution circuit configured to execute instructions, wherein one or both of the fetch circuit and the execution circuit comprises: Storage elements, with inputs and outputs; as well as The control circuit is configured as follows: Receive clock enable control; as well as When the clock enable control indicates that the output of the storage element will be prohibited from switching back and forth, the input of the storage element is prevented from switching back and forth by setting the input to a constant logic state, without adding delay to the functional data input of the storage element.

12. The apparatus of claim 11, further comprising a display device and one or more input devices.

13. The apparatus according to claim 11, wherein: The storage element is a dual-latch flip-flop (FF) comprising a primary latch and a secondary latch. When a clock signal is provided to the storage element, the control circuit is configured to set the primary latch to transparent mode, and To prevent the input of the storage element from switching back and forth, the control circuit is configured to set the input of the primary latch to a constant logic state.

14. The apparatus of claim 11, wherein the storage element comprises one or more latches, and wherein, when the input is set to the constant logic state, the control circuitry is configured to prevent any of the latches from switching while the output is prohibited from switching back and forth, regardless of whether the functional data input is switching.

15. The apparatus of claim 11, wherein, in order to set the input to the constant logic state, the control circuitry includes a logic gate configured to set the memory element to a scan mode in response to the clock enable control disabling a clock signal provided to the memory element.

16. The apparatus of claim 11, wherein the control circuitry includes logic gates configured to set the input of the memory element to the constant logic state in response to the clock enable control disabling a clock signal provided to the memory element.

Images