TSV overlay offset detection structure and detection method thereof

Abstract

The invention provides a TSV (Through Silicon Via) overlay offset detection structure and a detection method thereof, the TSV overlay offset detection structure comprises a first wafer, a second wafer and a third wafer, the bonding surface of the first wafer is provided with a first metal layer; the second wafer is bonded with the first wafer, at least two TSV through holes are formed in the second wafer, a second metal layer is formed on the bonding surface of the second wafer, and a rewiring layer electrically connected with the TSV through holes is formed on the non-bonding surface of the second wafer; at least three test groups, wherein the preset offsets between the TSV through holes and the first metal layer in each test group are different; and the test probe is positioned on the rewiring layer and is used for applying a test signal and collecting electrical parameters. According to the corresponding relation, whether the wafer and the wafer bonding deviate or not can be judged, and the offset can be accurately calculated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processes, and more specifically, to a TSV overlay offset detection structure and its detection method. Background Technology

[0002] As the semiconductor industry continues to evolve towards higher density, higher performance, and lower power consumption, 3D hyper-integration technology breaks through the limits of 2D planar integration. Among them, through-silicon via (TSV) technology, as a key to 3D integration, realizes electrical interconnection between different chip layers by creating vertical conductive channels in silicon wafers. This significantly shortens the signal transmission path, significantly improves data bandwidth, and reduces signal latency and power consumption, providing key support for chip design in fields such as high-performance computing, artificial intelligence, and the Internet of Things.

[0003] To further meet the stringent requirements of 3D integration for vertical interconnect density, thermomechanical reliability, and electrical performance, high aspect ratio (AR) TSVs have become an inevitable trend in technological development. Current research reports indicate that AR TSVs can achieve aspect ratios exceeding 10:1, for example, TSV structures with a height of 50 μm and a diameter of only 5 μm. These structures can realize more interconnect channels within a limited wafer area, effectively improving integration density. However, regardless of advanced bonding technologies such as hybrid bonding and direct bonding, it is difficult to completely avoid TSV overlay misalignment in actual production. This misalignment between the TSV and the target metal layer, though seemingly minor, can drastically reduce the contact area between the TSV and the underlying metal electrode when the misalignment exceeds a critical value, leading to a surge in interconnect resistance and even complete open-circuit failure.

[0004] Currently, whether a bond has shifted depends solely on optical detection. However, optical detection can only identify macroscopic shifts and cannot quantify the actual impact of micrometer-level shifts on electrical parameters (such as capacitance and resistance). Electrical continuity tests can only determine binary results such as continuity or disconnection and cannot determine subcritical shift states. Summary of the Invention

[0005] In view of the problem that TSV overlay misalignment is difficult to detect in the prior art of wafer bonding, this application provides a TSV overlay misalignment detection structure and detection method, which directly correlates the effect of a preset misalignment on electrical properties through electrical detection.

[0006] To achieve the above and other related objectives, the present invention provides a TSV overlay offset detection structure, comprising: The first wafer has a first metal layer formed on its bonding surface; A second wafer is bonded to the first wafer. At least two TSV vias are formed in the second wafer. A second metal layer is formed on the bonding surface of the second wafer. A redistribution layer electrically connected to the TSV vias is formed on the non-bonding surface of the second wafer. At least three test groups, each with a different preset offset between the TSV via and the first metal layer; Test probes, located on the rewiring layer, are used to apply test signals and acquire electrical parameters.

[0007] Optionally, it also includes: The first dielectric layer is located on the side of the first metal layer away from the first wafer; A first connecting path is disposed within the first dielectric layer; The first pad is located on the side of the first dielectric layer away from the first metal layer, and the first pad is electrically connected to the first metal layer through the first connecting path; The second dielectric layer is located on the side of the second metal layer away from the second wafer; A second communication path is disposed within the second dielectric layer; The second pad is located on the side of the second dielectric layer away from the second metal layer, and the second pad is electrically connected to the second metal layer through the second communication path.

[0008] Optionally, the rerouting layer includes a start region and a finish region: The test probe includes an input probe and an output probe, with the input probe located in the head region and the output probe located in the tail region.

[0009] Optionally, the at least three test groups include: In the first test group, the TSV via is aligned with the center of the first metal layer, and the preset offset is zero. In the second test group, the preset offset between the TSV via and the first metal layer is less than the radius of the TSV via; In the third test group, the preset offset between the TSV via and the first metal layer is greater than the radius of the TSV via and less than the diameter of the TSV via.

[0010] On the other hand, a TSV overlay offset detection method is provided, which includes: A TSV overlay offset detection structure is provided, wherein a rerouting layer is formed on the TSV overlay offset detection structure, and the TSV overlay offset structure includes multiple test groups with different preset offsets. Set up test probes on the redistribution layer, apply test signals to the test group respectively and collect the corresponding result parameters; Based on the test signal and the result signal, analyze the correspondence between the preset offset and the change in electrical parameters.

[0011] Optionally, the TSV overlay offset detection structure includes: A first wafer is provided, and a first metal layer is formed on the bonding surface of the first wafer; A second wafer is provided, in which at least two TSV vias are formed, and a second metal layer is formed on the bonding surface of the second wafer, wherein the second metal layer is electrically connected to the TSV vias. A redistribution layer is formed on the non-bonding surface of the second wafer, wherein the redistribution layer is electrically connected to the second metal layer through the TSV vias. The first metal layer of the first wafer is bonded to the second metal layer of the second wafer to form an electrical connection path between the first metal layer and the redistribution layer of the second wafer through the TSV via.

[0012] Optionally, the plurality of test groups with different preset offsets include: In the first test group, the TSV via is aligned with the center of the first metal layer, and the preset offset is zero. In the second test group, the preset offset between the TSV via and the first metal layer is less than the radius of the TSV via; In the third test group, the preset offset between the TSV via and the first metal layer is greater than the radius of the TSV via and less than the diameter of the TSV via.

[0013] Optionally, it further includes: establishing a mathematical model between the preset offset and the electrical parameters, and inferring the actual bonding offset by measuring the actual electrical parameters.

[0014] Optionally, analyzing the correspondence between the preset offset and the change in electrical parameters based on the test signal and the result signal includes: offset testing based on contact resistance and offset testing based on contact capacitance.

[0015] As described above, the TSV overlay offset detection method, its manufacturing method, and the display device provided by the present invention have at least the following beneficial technical effects: By establishing a precise mathematical model between electrical parameters and offset, minute offsets can be accurately deduced, resulting in high detection accuracy. Furthermore, the entire detection process does not require damage to the wafer or packaging structure and can be performed directly after bonding, making it suitable for inspecting finished or semi-finished products on the production line. This forms a closed loop for detection optimization: based on the correspondence between the detected offset and electrical parameters, it can be directly fed back to the alignment platform of the bonding equipment to adjust equipment parameters (such as displacement accuracy and pressure control), reducing TSV contact problems, resistance surges, and even open circuits caused by offset, thereby lowering the risk of interconnect failure. Attached Figure Description

[0016] Figure 1 The diagram shown is a schematic diagram of the TSV overlay offset detection structure provided by the present invention.

[0017] Figure 2 The diagram shown is a top view of the TSV overlay offset detection structure provided in Embodiment 1.

[0018] Figure 3 The flowchart shown is a TSV overlay offset detection method provided in Example 2.

[0019] Figure 4 The diagram shows a structural schematic of the first wafer.

[0020] Figure 5 The diagram shows a structure for providing a second wafer.

[0021] Figure 6 The diagram shows a structure in which a redistribution layer is formed on the unbonded surface of the second wafer.

[0022] Reference numerals: 10, First wafer; 11, First metal layer; 12, First dielectric layer; 121, First connecting path; 13, First pad; 20, Second wafer; 21, Second metal layer; 22, TSV via; 23, Second dielectric layer; 231, Second connecting path; 24, Second pad; 25, Redistribution layer; 251, Head region; 252, Tail region; 253, Middle region; 31, Input probe; 32, Output probe. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0024] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0025] Example 1 This embodiment provides a TSV overlay offset detection structure, such as Figure 1 The diagram shown illustrates the structure of the TSV overlay offset detection structure provided in this embodiment, including: a first wafer 10, on which a first metal layer 11 is formed; a second wafer 20, bonded to the first wafer 10, wherein at least one set of TSV vias 22 is formed, a second metal layer 21 is formed on the bonding surface of the second wafer 20, and a redistribution layer 25 electrically connected to the TSV vias 22 is formed on the non-bonding surface of the second wafer 20; at least three test groups, each test group having a different preset offset between the TSV vias 22 and the first metal layer 11; and a test probe located on the redistribution layer 25 for applying test signals and acquiring electrical parameters.

[0026] In an optional embodiment, a first dielectric layer 12 and a first pad 13 are further formed on the bonding surface of the first wafer 10. A first connecting via 121 is formed within the first dielectric layer 12, and the first pad 13 is electrically connected to the first metal layer 11 through the first connecting via 121 formed within the first dielectric layer 12. A second dielectric layer 23 and a second pad 24 are further formed on the bonding surface of the second wafer 20. A second connecting via 231 is formed within the second dielectric layer 23, and the second pad 24 is electrically connected to the second metal layer 21 through the second connecting via 231 formed within the second dielectric layer 23. The second metal layer 21 is electrically connected to the TSV via 22.

[0027] Specifically, the bonding surfaces of the first wafer 10 and the second wafer 20 are bonded together via the first pad 13 and the second pad 24. A redistribution layer 25 is located on the side of the second wafer 20 away from the first wafer 10, and the redistribution layer 25 includes at least a beginning region 251 and a end region 252. Test probes include an input probe 31 and an output probe 32, with the input probe 31 disposed on the beginning region 251 of the redistribution layer 25 and the output probe 32 disposed on the end region 252 of the redistribution layer 25.

[0028] Input probe 31 (first region 251 of redistribution layer 25) → redistribution layer 25 (first region 251) → TSV via 22 → second metal layer 21 → second connecting path 231 → second pad 24 → first pad 13 → first connecting path 121 → first metal layer 11 → first connecting path 121 → first pad 13 → second pad 24 → second connecting path 231 → second metal layer 21 → TSV via 22 → redistribution layer 25 (tail region 252) → output probe 32 (on the tail region 252 of redistribution layer 25).

[0029] Optionally, the redistribution layer 25 includes a third pad on which test probes can be positioned to form an electrical path.

[0030] Optionally, the redistribution layer 25 also includes a plurality of intermediate regions 253 located between the first end region 251 and the last end region 252. The intermediate regions 253 enable communication between the first wafer 10 and the second wafer 20. Test probes, including an input probe 31 and an output probe 32, can be disposed on the intermediate regions 253, and the electrical path changes accordingly.

[0031] Specifically, the TSV overlay offset detection structure includes at least three test groups, each with a different preset offset between the TSV via 22 and the first metal layer 11; for example... Figure 2 The diagram shows a top view of the TSV overlay offset test structure provided in this embodiment. Within the plane of the first wafer 10, the direction parallel to the main positioning edge of the first wafer 10 is defined as the X direction, the direction perpendicular to the X direction is defined as the Y direction, and the thickness direction of the first wafer is defined as the Z direction. The TSV vias on the second wafer 20 are translated within the XY plane. The preset offset is the offset of the second wafer 20 relative to the first wafer 10 within the XY plane, specifically including the offset along the X direction and the offset along the Y direction.

[0032] This embodiment takes the Y direction as an example: the second wafer 20 includes a second metal layer 21 and a TSV via 22. The TSV overlay offset occurs along the Y direction. The radius of the TSV via 22 is defined as D. The small preset offset is between 0 and D, and the large preset offset is between D and 2D.

[0033] The TSV overlay offset structure provided in this embodiment includes three test groups: the first test group A, in which the center of the TSV via 22 is aligned with the center of the first metal layer 11 and the preset offset is zero; the second test group B, in which the preset offset between the TSV via 22 and the first metal layer 11 is less than the radius of the TSV via 22; and the third test group C, in which the preset offset between the TSV via 22 and the first metal layer 11 is greater than the radius of the TSV via 22.

[0034] Optionally, multiple test groups are set on the same TSV overlay offset test structure, including preset offsets between 0 and D, and preset offsets between D and 2D, and tests are performed separately to summarize the patterns.

[0035] Optionally, the TSV overlay offset detection structure is located within the dicing area of ​​the first wafer 10 and / or the second wafer 20, or exists as an independent test chip. The TSV overlay offset detection structure, located within the dicing area, does not occupy the effective area of ​​the product chip. It can be manufactured in the same batch as the product chip, with completely identical process conditions (such as bonding temperature, pressure, and time), and the test results better reflect the bonding state of the actual product.

[0036] Optionally, the structure may further include a fourth test group, wherein the TSV via 22 and the first metal layer 11 have a preset composite offset in both the X and Y directions, which is used to simulate an arbitrary directional offset in a two-dimensional plane.

[0037] The TSV overlay offset detection structure provided in this embodiment provides a standardized testing platform for quickly and non-destructively establishing a precise correspondence between preset offsets and electrical parameters by pre-designing and forming test groups with different known offsets during the manufacturing stage. It is suitable for the development, monitoring and reliability assessment of three-dimensional integration processes.

[0038] Example 2 This embodiment provides a TSV overlay offset detection method, such as Figure 3 The diagram shows a flowchart of the TSV overlay offset detection method provided in this embodiment. The TSV overlay offset detection method provided in this application includes the following steps: S1: Provide a TSV overlay offset detection structure, wherein a rerouting layer is provided on the TSV overlay offset detection structure, and the TSV overlay offset structure includes test groups with different preset offsets; S2: Set up test probes on the redistribution layer, apply test signals to the test group respectively and collect the corresponding result parameters; S3: Based on the test signal and result parameters, analyze the correspondence between the preset offset and the changes in the result parameters.

[0039] Specifically, the method for providing a TSV overlay offset detection structure includes: S11: Provide a first wafer and form a first metal layer on the bonding surface of the first wafer; S12: Provide a second wafer, in which at least two TSV vias are formed, and a second metal layer is formed on the bonding surface of the second wafer. The second metal layer is electrically connected to the TSV vias. A redistribution layer is formed on the non-bonding surface of the second wafer. The redistribution layer is electrically connected to the second metal layer through the TSV vias. S13: Bond the first metal layer of the first wafer to the second metal layer of the second wafer to form an electrical connection path between the first metal layer of the first wafer and the redistribution layer of the second wafer through a TSV via.

[0040] Specifically, such as Figure 4 As shown, S11: A first wafer 10 is provided, the first wafer 10 including bonding surfaces and non-bonding surfaces disposed opposite to each other; Figure 5 As shown, S12: A second wafer 20 is provided, which includes bonding and non-bonding surfaces arranged opposite to each other. Specifically, the first wafer 10 and the second wafer 20 can be standard silicon wafers or carrier boards with embedded functional devices. Specifically, different devices are formed inside the first wafer 10 and the second wafer 20. For example, logic operation units, sensor arrays, etc. can be integrated in the first wafer 10, and memory modules, radio frequency devices, or power management units, etc., can be integrated in the second wafer 20 (device structures are not shown in the figure).

[0041] A first metal layer 11 is formed on the bonding surface of the first wafer 10; a first dielectric layer 12 is formed on the bonding surface of the first wafer 10, i.e. the side of the first metal layer 11 away from the first wafer 10; a first connecting path 121 is formed in the first dielectric layer 12 to lead out the circuit of the first metal layer 11; a first pad 13 is formed on the side of the first dielectric layer 12 away from the first wafer 10; and the first pad 13 is electrically connected to the first metal layer 11. At least two TSV vias 22 are formed within the second wafer 20, and a second metal layer 21 is formed on the bonding surface of the second wafer 20. The second metal layer 21 is formed on the bonding surface of the second wafer 20, i.e., the side of the second metal layer 21 away from the second wafer 20, and is electrically connected to the TSV vias 22. A second dielectric layer 23 is formed on the side of the second metal layer 21 away from the second wafer 20, and a second connecting path 231 is formed within the second dielectric layer 23 to lead out the circuitry of the second metal layer 21. A second pad 24 is formed on the side of the second dielectric layer 23 away from the second wafer 20, and is electrically connected to the second metal layer 21. The materials of the first metal layer 11 and the second metal layer 21 include Cu, Al, and metal stacks with good conductivity (Ti, TiN, etc.). Specifically, the first metal layer 11 and the second metal layer 21 are not entirely metal surfaces, but rather patterned arrays formed by photolithography etching.

[0042] Generally, through-silicon vias (TSVs) are formed in the second wafer 20 through processes such as deep silicon etching, insulating layer deposition, seed layer growth, and electroplating filling, extending through its thickness direction. The aspect ratio of the TSV 22 is designed according to integration requirements. Optionally, the inner wall of the TSV 22 is covered with an insulating layer to prevent short circuits with the substrate of the second wafer 20, and the interior of the TSV 22 is filled with conductive material to achieve vertical conductivity. Generally, the first metal layer 11 and the second metal layer 21 are formed by semiconductor processes such as deposition, photolithography, and etching on the first wafer 10 and the second wafer 20. Specifically, the first metal layer 11 and the second metal layer 21 are periodically arranged electrode patterns, and the first metal layer 11 and the second metal layer 21 are made of conductive materials such as copper and aluminum. The first metal layer 11 is located on the bonding surface of the first wafer 10, and the second metal layer 21 is located on the non-bonding surface of the second wafer 20, and the second metal layer 21 is electrically connected to the TSV.

[0043] Optionally, such as Figure 6 As shown, the unbonded surface of the second wafer 20, i.e., the side away from the second metal layer 21, is thinned until TSV vias are exposed, forming a redistribution layer 25 on the unbonded surface of the second wafer 20. The redistribution layer 25 is electrically connected to the second metal layer 21 through TSV vias 22, and test probes are disposed on the redistribution layer 25. Optionally, a third pad is formed on the side of the redistribution layer 25 away from the second wafer 20. Test probes are disposed on the third pad and communicate with the redistribution layer 25.

[0044] The rerouting layer 25 includes at least a start area 251 and a finish area 252. Optionally, as... Figure 5 As shown, the rerouting layer 25 also includes at least one intermediate region 253, which is located between the beginning region 251 and the end region 252.

[0045] like Figure 1 As shown, the first metal layer 11 of the first wafer 10 is bonded to the second metal layer 21 of the second wafer 20 so that the first metal layer 11 and the redistribution layer 25 are interconnected through TSV vias 22.

[0046] Specifically, the bonding surface of the first wafer 10 (including the first metal layer 11) and the bonding surface of the second wafer 20 (including the second metal layer 21) are bonded under precise alignment control using a wafer bonding machine. The first metal layer 11 and the TSV via 22 form direct or indirect electrical contact, thereby realizing signal interconnection between the internal devices of the two wafers.

[0047] Specifically, in designing TSV via 22, the key is to pre-design TSV via groups with different offsets. For example... Figure 3As shown, within the plane of the first wafer 10, the direction parallel to the main positioning edge of the first wafer 10 is defined as the X direction, the direction perpendicular to the X direction is defined as the Y direction, and the direction along the thickness direction of the first wafer is defined as the Z direction. Through photolithography mask design, the TSV vias 22 in different test groups and the test electrodes of the first metal layer 11 have different relative positions in the XY plane, thereby forming different preset offsets. Definition: The TSV via 22 is circular, and the diameter of the TSV via 22 is 2D. The preset offset between the first wafer 10 and the second wafer 20 is considered a small offset if it is between 0 and D; the preset offset between the first wafer 10 and the second wafer 20 is considered a large offset if it is between D and 2D.

[0048] like Figure 2 As shown, it is displayed as Figure 1 The diagram shows a top view of the bonding structure. Within the same TSV overlay offset structure, at least three sets of structures are designed, specifically including: First test group A: The TSV via 22 is aligned with the center of the first metal layer 11, and no TSV overlay offset occurs between the first wafer 10 and the second wafer 20; Second test group B: The preset offset of the TSV via 22 relative to the first metal layer 11 is less than the radius D of the TSV via; Second test group C: The preset offset of the TSV via 22 relative to the first metal layer 11 is greater than the radius D of the TSV via but less than its diameter 2D. Optionally, to obtain more comprehensive data, multiple structures with different specific offsets can be designed within the second test group B and the second test group C, and tested separately to summarize patterns.

[0049] The bonded stacked wafers are placed on a precision probe stage. An input probe 31 is positioned on the first region 251 of the redistribution layer 25, and an output probe 32 is positioned on the last region 252 of the redistribution layer 25. Generally, independent test pads are provided in different regions of the redistribution layer 25. These test pads are directly connected to the internal wiring of the second metal layer 21, forming an electrical path. Typically, the probes are made of highly conductive and high-hardness materials, such as tungsten alloys or gold-plated probes, to reduce the contact resistance between the metal layer pads and the probes.

[0050] Specifically, the TSV overlay offset test structure provided in this embodiment (including the first metal layer 11 of the first wafer 10, the second metal layer 21 of the second wafer 20, and the redistribution layer 25) is located within the dicing lane. A set of test structures is placed every 2 to 4 chips to ensure that the test data can cover different areas of the wafer and improve the representativeness of batch testing. After the first wafer 10 and the second wafer 20 are bonded, there is no need to dicing; the entire wafer can be directly fixed on the probe station for measurement.

[0051] like Figure 2As shown, in the first test group A: the first metal layer 11 and the second metal layer 21 are completely aligned in the vertical direction, and the TSV via 22 coincides with the geometric center of the first metal layer 11. Therefore, the bonding of the first wafer 10 and the second wafer 20 is considered to be without offset. In this state, the contact area between the TSV via 22 and the first metal layer 11 reaches its maximum (theoretically equal to the cross-sectional area of ​​the TSV), thus forming a stable electrical connection. With the first metal layer 11 and the second metal layer 21 aligned in the vertical direction and the TSV via 22 coinciding with the geometric center of the first metal layer 11, and without any TSV overlay offset, a preset test signal is input to the input probe 31 or the output probe 32, and the output signal is acquired from the corresponding input probe 31 or the output probe 32. On the one hand, by detecting the integrity of the output signal and whether there are abnormal current surges, it is determined whether there are basic process defects such as short circuits or open circuits in the bonding structure; on the other hand, the reference electrical parameters at this time, such as the initial contact resistance value and capacitance value, are recorded to provide a comparison benchmark for subsequent offset state tests.

[0052] like Figure 2 As shown, in the second test group B, the first and second wafers are slightly offset. At this time, the TSV via 22 is offset relative to the first metal layer 11 along the Y direction, but the offset distance does not exceed its radius D. In this state, although the contact area between the TSV via 22 and the first metal layer 11 is smaller than in the unoffset state (the overlap area is 50%~100% of the TSV cross-sectional area), an effective electrical connection is still maintained. A test signal is input to the input probe 31, and the output probe 32 acquires the test signal. In this state, the total resistance Rt increases slowly and approximately linearly with the increase of the offset. Recording the electrical parameters corresponding to different small offsets (such as 0.2D, 0.5D, 0.8D) shows that the contact resistance increases slowly and linearly with the increase of the offset.

[0053] like Figure 2As shown, the third test group C: a schematic diagram of a structure with a large TSV overlay offset. At this point, the offset distance of the TSV via 22 along the Y direction exceeds its radius D (but does not reach 2D). In this state, the contact area between the TSV via 22 and the first metal layer 11 is significantly reduced (the overlap area is 0-50% of the TSV cross-sectional area), and some areas may experience edge contact or local disconnection. The testing process is consistent with the small offset state: the second wafer 20 is controlled to continue moving along the Y direction via a displacement platform, gradually increasing the offset from D to 2D (e.g., 1.2D, 1.5D, 1.8D). After each offset, a test signal is input and output parameters are collected. During this stage, nonlinear changes in electrical parameters can be observed: when the offset approaches D, the contact resistance Rc begins to rise nonlinearly and rapidly; when the offset approaches 2D, the contact area approaches zero, and the total resistance Rt increases sharply until it approaches infinity (open circuit), indicating that the electrical connection is about to completely fail.

[0054] Specifically, in this embodiment, a preset parameter signal is input to the output probe 32. Generally, the preset parameter signal includes a DC voltage signal or a low-frequency AC signal, and the output signal is acquired through the input probe 31. For example... Figure 2 As shown, the second wafer 20 includes a second metal layer 21 with TSV overlay offset along the Y direction. The radius of the TSV via 22 is defined as D, with a small preset offset between 0 and D, and a large preset offset between D and 2D. By gradually moving the offset between the second wafer 20 (including the second metal layer 21) and the first wafer 10 (including the first metal layer 11) along the X direction, a test signal is input to the input probe 31 or the output probe 32, and an output signal is acquired from the input probe 31 or the output probe 32. The relationship between the offset and electrical parameters is analyzed. Specifically, the electrical parameters include capacitance, resistance, and inductance values.

[0055] Specifically, the testing methods include offset testing based on contact resistance and offset testing based on contact capacitance. This embodiment uses offset testing based on contact resistance as an example. The basis of offset testing based on contact resistance is that contact resistance is inversely proportional to the effective contact area. Contact resistance refers to the contact resistance between the TSV via 22 and the first metal layer 11, and the effective contact area refers to the contact area between the TSV via 22 and the first metal layer 11. When bonding offset occurs, the effective contact area between the TSV via 22 and the first metal layer 11 decreases, resulting in an increase in the contact resistance between them. Therefore, by monitoring the change in contact resistance, the offset can be deduced.

[0056] Offset testing based on contact resistance includes the following steps: A test signal is input through input probe 31. Specifically, the test signal input to input probe 31 is a constant current signal (current value I). The current value is set according to the material characteristics of the metal layer and TSV. An output voltage signal (voltage value U) is acquired through output probe 32. The total resistance Rt in the circuit is calculated according to Ohm's law: Rt = U / I. The total resistance Rt includes the resistance Rtsv of the TSV via 22 itself, the resistance Rm of the second metal layer 21, and the resistance of the TSV via 22 and... The contact resistance Rc between the first metal layers 11 is generally Rtsv and Rm are fixed values. Therefore, the change in the total resistance Rt is the change in the contact resistance Rc. Specifically, the relationship between the preset offset and the corresponding total resistance Rt can be expressed as: Rt∝K / A, where A is the effective contact area between the TSV via 22 and the first metal layer 11, and K is a proportionality coefficient, which is related to the resistivity of the contact material.

[0057] Then, a mathematical model is established between the preset offset and the electrical parameters. Generally, the mathematical model of the proportional relationship includes querying a database and fitting a curve. In this embodiment, a database or fitting curve of offset-resistance is established by setting the preset offset and the corresponding total resistance value Rt. In actual testing, the actual bonding offset is deduced by measuring the actual electrical parameters. In this embodiment, an accurate R-ΔX / Y calibration curve is obtained through the above steps. For the test sample with an unknown offset, only its total resistance Rt needs to be measured, and the specific offset value and direction can be directly and quantitatively deduced by querying the database or fitting curve.

[0058] Similarly, the offset test based on contact capacitance includes: inputting an AC test signal to the input probe, the frequency of which is between 1 kHz and 10 MHz; measuring the coupling capacitance value at the output probe; recording the corresponding coupling capacitance values ​​at different preset offsets, and establishing a database of preset offsets and coupling capacitance values. The specific steps are similar to those of the offset test based on resistance, and will not be described in detail here.

[0059] Therefore, by analyzing the trend and rate of resistance change, not only can the offset be quantified, but the reliability status of the bonding interface can also be evaluated.

[0060] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A TSV overlay offset detection structure, characterized in that, include The first wafer has a first metal layer formed on its bonding surface; A second wafer is bonded to the first wafer. At least two TSV vias are formed in the second wafer. A second metal layer is formed on the bonding surface of the second wafer. A redistribution layer electrically connected to the TSV vias is formed on the non-bonding surface of the second wafer. At least three test groups, each with a different preset offset between the TSV via and the first metal layer; Test probes, located on the rewiring layer, are used to apply test signals and acquire electrical parameters.

2. The TSV overlay offset detection structure according to claim 1, characterized in that, Also includes: The first dielectric layer is located on the side of the first metal layer away from the first wafer; A first connecting path is disposed within the first dielectric layer; The first pad is located on the side of the first dielectric layer away from the first metal layer, and the first pad is electrically connected to the first metal layer through the first connecting path; The second dielectric layer is located on the side of the second metal layer away from the second wafer; A second communication path is disposed within the second dielectric layer; The second pad is located on the side of the second dielectric layer away from the second metal layer, and the second pad is electrically connected to the second metal layer through the second communication path.

3. The TSV overlay offset detection structure according to claim 1, characterized in that, The rerouting layer includes a start region and a tail region: The test probe includes an input probe and an output probe, with the input probe located in the head region and the output probe located in the tail region.

4. The TSV overlay offset detection structure according to claim 1, characterized in that, The at least three test groups include: In the first test group, the TSV via is aligned with the center of the first metal layer, and the preset offset is zero. In the second test group, the preset offset between the TSV via and the first metal layer is less than the radius of the TSV via; In the third test group, the preset offset between the TSV via and the first metal layer is greater than the radius of the TSV via and less than the diameter of the TSV via.

5. The TSV overlay offset detection structure according to claim 1, characterized in that, The TSV overlay offset detection structure is located within the dicing area of ​​the first wafer and / or the second wafer.

6. A method for detecting bond offset, characterized in that, include: A TSV overlay offset detection structure is provided, wherein a rewiring layer is formed on the TSV overlay offset detection structure, and the bonding offset structure includes multiple test groups with different preset offsets. Set up test probes on the redistribution layer, apply test signals to the test group respectively and collect the corresponding result parameters; Based on the test signal and the result signal, analyze the correspondence between the preset offset and the change in electrical parameters.

7. The bonding offset detection method according to claim 6, characterized in that, The TSV overlay offset detection structure includes: A first wafer is provided, and a first metal layer is formed on the bonding surface of the first wafer; A second wafer is provided, in which at least two TSV vias are formed, and a second metal layer is formed on the bonding surface of the second wafer, wherein the second metal layer is electrically connected to the TSV vias. A redistribution layer is formed on the non-bonding surface of the second wafer, wherein the redistribution layer is electrically connected to the second metal layer through the TSV vias. The first metal layer of the first wafer is bonded to the second metal layer of the second wafer to form an electrical connection path between the first metal layer and the redistribution layer of the second wafer through the TSV via.

8. The bonding offset detection method according to claim 7, characterized in that, The multiple test groups with different preset offsets include: In the first test group, the TSV via is aligned with the center of the first metal layer, and the preset offset is zero. In the second test group, the preset offset between the TSV via and the first metal layer is less than the radius of the TSV via; In the third test group, the preset offset between the TSV via and the first metal layer is greater than the radius of the TSV via and less than the diameter of the TSV via.

9. The bonding offset detection method according to claim 6, characterized in that, Also includes: A mathematical model is established between the preset offset and the electrical parameters, and the actual bonding offset is deduced by measuring the actual electrical parameters.

10. The bonding offset detection method according to claim 6, characterized in that, Based on the test signal and the result signal, the analysis of the correspondence between the preset offset and the change of electrical parameters includes: offset test based on contact resistance and offset test based on contact capacitance.

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