Driving control method and circuit of multiphase resonant conversion circuit, and electronic equipment

Abstract

The invention discloses a driving control method and circuit of a multi-phase resonant conversion circuit and electronic equipment. The driving control method comprises the following steps: acquiring a first resonant signal in a master-phase resonant conversion circuit, a second resonant signal in a slave-phase resonant conversion circuit and an output voltage; generating a first control signal using the first resonant signal and the output voltage; generating a second control signal using the second resonant signal and the output voltage; acquiring an interval pulse width between a first rising edge of the first control signal and a second rising edge of the second control signal; performing dead-time compensation on the first control signal or the second control signal in response to a comparison result between the interval pulse width and a target pulse width threshold range; and the first control signal and the second control signal after dead-time compensation are respectively sent to the master phase resonant conversion circuit and the slave phase resonant conversion circuit so as to adjust the output voltage. Through the above mode, the driving control method enables the multi-phase resonant conversion circuit to effectively realize current sharing and phase dislocation, and reduces output ripples.

Description

Technical Field

[0001] This application relates to the field of circuit control technology, and in particular to a driving control method, circuit, and electronic equipment for a multiphase resonant converter circuit. Background Technology

[0002] Today, with the rapid development of power electronics technology and the advent of the era of cloud computing and big data, power converters with high efficiency, high power density, and low electromagnetic interference have become critical requirements. LLC (inductance inductance capacitor, which includes an additional inductor, along with two other inductors and a capacitor) resonant converters are widely used in the field of switching power supplies due to their natural soft-switching characteristics and high-efficiency energy conversion capabilities.

[0003] However, to improve power density, it is usually necessary to supply power through multiple LLC resonant converter circuits in parallel. But connecting multiple LLC resonant converters in parallel has problems such as large output current ripple, inability to achieve current sharing, complex control methods for each LLC resonant converter, and slow response. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a driving control method, circuit, and electronic equipment for a multiphase resonant converter circuit. This method can solve the problems in related technologies where parallel power supply of multiple LLC resonant converters results in large output current ripple, inability to achieve current sharing, complex control methods for each LLC resonant converter, and slow response.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a driving control method for a multiphase resonant converter circuit, the multiphase resonant converter circuit including a master phase resonant converter circuit and a slave phase resonant converter circuit connected in parallel, wherein the driving control method includes: acquiring a first resonant signal in the master phase resonant converter circuit, a second resonant signal in the slave phase resonant converter circuit, and an output voltage; generating a first control signal using the first resonant signal and the output voltage; generating a second control signal using the second resonant signal and the output voltage; acquiring the pulse width interval between the first rising edge of the first control signal and the second rising edge of the second control signal; performing dead-time compensation on the first dead time of the first control signal or the second dead time of the second control signal in response to a comparison result between the pulse width interval and a target pulse width threshold range; and sending the dead-time compensated first control signal and second control signal to the master phase resonant converter circuit and the slave phase resonant converter circuit respectively to trigger the master phase resonant converter circuit and the slave phase resonant converter circuit to change their switching states, thereby adjusting the output voltage.

[0006] The step of performing dead-time compensation on the first dead time of the first control signal or the second dead time of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range includes: detecting whether the interval pulse width is lower than the target pulse width threshold range; if the interval pulse width is lower than the target pulse width threshold range, adding the middle value of the target pulse width threshold range to the second dead time and subtracting the interval pulse width.

[0007] The drive control method further includes: if the interval pulse width exceeds the target pulse width threshold range, adding the interval pulse width to the first dead time and subtracting the median value of the target pulse width threshold range.

[0008] The drive control method further includes: if the interval pulse width is within the target pulse width threshold range, detecting whether the first pulse width is greater than the second pulse width; if the first pulse width is equal to the second pulse width, maintaining the first dead time and the second dead time unchanged.

[0009] The drive control method further includes: if the first pulse width is greater than the second pulse width, adding a dead-time compensation time to the second dead-time; wherein the dead-time compensation time is greater than or equal to twice the absolute value of the first pulse width minus the second pulse width. If the first pulse width is less than the second pulse width, adding a dead-time compensation time to the first dead-time.

[0010] The step of performing dead-time compensation for the first dead time of the first control signal or the second dead time of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range includes: performing dead-time compensation for the first dead time of the first control signal or the second dead time of the second control signal on a falling edge that is relatively lagging behind the falling edge of the first control signal and the falling edge of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range.

[0011] The total number of master-phase resonant converter circuits and slave-phase resonant converter circuits is a predetermined number. Before the step of performing dead-time compensation on the first dead time of the first control signal or the second dead time of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range, the method further includes: dividing the first pulse width of the first control signal by a predetermined number to obtain a first reference pulse width; dividing the sum of the first pulse width and the first dead time by a predetermined number to obtain a second reference pulse width; dividing the second pulse width of the second control signal by a predetermined number to obtain a third reference pulse width; dividing the sum of the second pulse width and the second dead time by a predetermined number to obtain a fourth reference pulse width; dividing the sum of the first pulse width, the first dead time, the second pulse width, and the second dead time by a predetermined number and then by 2 to obtain a fifth reference pulse width; and setting the minimum and maximum values ​​of the first, second, third, fourth, and fifth reference pulse widths as the lower limit and upper limit of the target pulse width threshold range, respectively.

[0012] Before the step of obtaining the pulse width of the interval between the first rising edge of the first control signal and the second rising edge of the second control signal, the method further includes: sequentially performing phase modulation on each second control signal in response to the total number of phase resonant conversion circuits.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a drive control circuit, wherein the drive control circuit is coupled to the main phase resonant converter circuit and the slave phase resonant converter circuit, and the main phase resonant converter circuit and the slave phase resonant converter circuit are connected in parallel; wherein the drive control circuit uses the drive control method described in any of the above claims to drive and control the main phase resonant converter circuit and the slave phase resonant converter circuit.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a housing and a drive control circuit connected to the housing; wherein the drive control circuit is the drive control circuit as described above.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, the drive control method provided in this application acquires the first resonant signal in the main phase resonant converter circuit, the second resonant signal in the slave phase resonant converter circuit, and the output voltage. It then uses the first resonant signal and the output voltage to generate a first control signal, and uses the second resonant signal and the output voltage to generate a second control signal, allowing the two phase resonant converter circuits to operate independently to achieve current sharing. Furthermore, it acquires the pulse width interval between the first rising edge of the first control signal and the second rising edge of the second control signal, and adjusts the first dead time of the first control signal or the second dead time of the second control signal in response to the comparison result between the pulse width interval and the target pulse width threshold range. Dead-time compensation allows for dynamic adjustment of the phase difference between the first and second control signals by intervening in their actual dead time. This achieves phase misalignment adjustment closer to the ideal state. When the dead-time-compensated first and second control signals are sent to the master-phase resonant converter circuit and the slave-phase resonant converter circuit respectively to trigger them to change their switching states and adjust the output voltage, phase misalignment adjustment can be effectively achieved while simultaneously achieving current sharing, thus reducing output ripple. Furthermore, the dead-time-compensated phase misalignment adjustment method is simpler, lower in cost, and has a faster signal response compared to phase misalignment adjustment using a hardware phase modulator. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a flowchart illustrating the first embodiment of the drive control method of this application; Figure 2 This is a schematic diagram of the structure of the first embodiment of the drive control circuit of this application; Figure 3 This is a flowchart illustrating the second embodiment of the drive control method of this application; Figure 4 This is a schematic diagram of the second embodiment of the drive control circuit of this application; Figure 5 yes Figure 4 A schematic diagram of the waveforms of the relevant signals generated by the drive control circuit to produce the first control signal; Figure 6 yes Figure 3 A schematic diagram of the waveforms of the relevant signals in the drive control method; Figure 7This is a flowchart illustrating the third embodiment of the drive control method of this application; Figure 8 This is a schematic diagram of one embodiment of the electronic device of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0019] In this document, the term "implementation" means that a specific feature, structure, or characteristic described in connection with an implementation may be included in at least one implementation of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same implementation, nor is it a separate or alternative implementation mutually exclusive with other implementations. It will be explicitly and implicitly understood by those skilled in the art that the implementations described herein can be combined with other implementations.

[0020] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] Please refer to the following: Figure 1 and Figure 2 ,in, Figure 1 This is a flowchart illustrating the first embodiment of the drive control method of this application. Figure 2This is a schematic diagram of the first embodiment of the drive control circuit of this application. Specifically, it may include the following steps: S11: Obtain the first resonant signal in the main phase resonant converter circuit, the second resonant signal in the slave phase resonant converter circuit, and the output voltage.

[0022] It is understood that the drive control method in this embodiment is specifically applied to, for example... Figure 2 The drive control of the first multiphase resonant converter circuit 20 shown includes a first master phase resonant converter circuit 21 and a first slave phase resonant converter circuit 22 connected in parallel. A first drive control circuit 30 is coupled to the first master phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22. The first drive control circuit 30 uses the drive control method described in any one of the present invention to drive the first master phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22.

[0023] It is worth noting that the first master phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22 may be the same or different, and may be a half-bridge LLC converter, a full-bridge LLC converter or any other reasonable LLC circuit topology. This embodiment does not limit this.

[0024] In some embodiments, the number of the first primary phase resonant converter circuit 21 is one, while the number of the first secondary phase resonant converter circuit 22 is one or more, such as first secondary phase resonant converter circuit 1, first secondary phase resonant converter circuit 2, ..., first secondary phase resonant converter circuit n (n is 1 or an integer greater than 1), and this application does not limit this.

[0025] In some embodiments, the first drive control circuit 30 may specifically include any reasonable circuit unit with signal processing function, such as a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a microcontroller, a field-programmable gate array, a programmable logic device, discrete gate or transistor logic devices, or discrete hardware. This application does not limit this.

[0026] Furthermore, the term "coupled" in this document refers to any direct or indirect connection. Therefore, if the document describes a first circuit coupled to a second circuit, it means that the first circuit can be directly connected to the second circuit via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly connected to the second circuit via other circuits or connection methods via electrical connection or signal connection.

[0027] Specifically, the first drive control circuit 30 obtains the first resonant signal and output voltage in real time from the first main phase resonant converter circuit 21, and obtains the second resonant signal in real time from the first slave phase resonant converter circuit 22. For example, it obtains the first resonant signal from the primary side of the first main phase resonant converter circuit 21 through a current transformer, voltage divider, sampling resistor or other arbitrary reasonable circuit unit, and obtains the first resonant signal from the primary side of the first slave phase resonant converter circuit 22, and obtains the output voltage from the common output terminal of the first main phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22.

[0028] S12: Generate the first control signal using the first resonant signal and the output voltage.

[0029] Based on the currently acquired first resonant signal and output voltage, the signal adjustment amount and characteristic parameters are calculated in real time to generate the first control signal. For example, proportional-integral-derivative adjustment, proportional-integral adjustment, proportional-integral and ramp compensation adjustment or other control strategies are adopted to ensure that the drive control of its internal switching elements can be accurately adjusted according to the current working state of the first multiphase resonant converter circuit 20.

[0030] S13: Generate a second control signal using the second resonant signal and the output voltage.

[0031] Similarly, based on the currently acquired second resonant signal and output voltage, the signal adjustment amount and characteristic parameters are calculated in real time to generate the second control signal. For example, proportional-integral-derivative regulation, proportional-integral regulation, proportional-integral and ramp compensation regulation or other control strategies are adopted to ensure that the drive control of its internal switching elements can be accurately adjusted according to the current working state of the first multiphase resonant converter circuit 20.

[0032] In some embodiments, the first control signal and the second control signal may be one or more of any reasonable control signals such as PWM (Pulse Width Modulation) signal or PFM (Pulse Frequency Modulation) signal, and this application does not limit them.

[0033] The first control signal and the second control signal each have a rising edge and a falling edge in each signal cycle, and each has a dead time. For ease of understanding, the rising edge of the first control signal in the current signal cycle is defined as the first rising edge, its falling edge is defined as the first falling edge, and its dead time is defined as the first dead time; and the rising edge of the second control signal in the current signal cycle is defined as the second rising edge, its falling edge is defined as the second falling edge, and its dead time is defined as the second dead time.

[0034] It is worth noting that the first dead time and the second dead time can be understood as the initial dead time set according to the physical characteristics of the internal switching elements of the first master phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22, respectively, and cannot be adjusted or reduced. The dead time compensation described in this article is actually extended based on the initial dead time, so as to increase the turn-off time of the current signal cycle of the first control signal or the second control signal by extending the initial dead time, that is, the duration of the first control signal or the second control signal being low, so as to adjust the phase difference between the first control signal and the second control signal.

[0035] S14: Obtain the pulse width between the first rising edge of the first control signal and the second rising edge of the second control signal.

[0036] The first rising edge of the first control signal and the second rising edge of the second control signal in the current signal cycle are detected, and the interval duration between the first rising edge and the second rising edge is calculated by the controller counter, i.e., the interval pulse width; or, in response to the first rising edge and the second rising edge, a reference pulse width signal is generated, such as adjusting the signal level state by corresponding the first rising edge and the second rising edge to the rising edge and the falling edge of the current signal cycle of the reference pulse width signal, respectively, to generate the reference pulse width signal, and the pulse width of the reference pulse width signal is calculated to obtain the interval pulse width.

[0037] S15: In response to the comparison result between the interval pulse width and the target pulse width threshold range, perform dead-time compensation on the first dead time of the first control signal or the second dead time of the second control signal.

[0038] Understandably, a target pulse width threshold range and corresponding compensation logic are set based on the actual phase misalignment adjustment requirements.

[0039] Specifically, it detects whether the currently acquired interval pulse width is within the target pulse width threshold range. Based on the comparison between the two, if the interval pulse width is lower than the target pulse width threshold range, exceeds the target pulse width threshold range, or is within the target pulse width threshold range, the first dead time of the first control signal or the second dead time of the second control signal is extended to delay the phase of the current signal period of the first or second control signal, thereby reducing or increasing the phase difference between the first and second control signals; or, the first dead time and the second dead time are kept unchanged to maintain normal operation without adjustment.

[0040] It is worth noting that in the actual operation of the first multiphase resonant converter circuit 20, there is theoretically an ideal phase misalignment adjustment state. For example, when there is one first master phase resonant converter circuit 21 and one first slave phase resonant converter circuit 22, the output ripple will theoretically reach its optimal value if the corresponding first control signal and the second control signal are out of phase by 90 degrees in each signal cycle. Therefore, in order to get as close to this goal as possible, the target pulse width threshold range can be set according to the ideal phase misalignment adjustment state. The phase difference between the first control signal and the second control signal can be adjusted in real time by the dead zone compensation of the first dead time or the second dead time through the corresponding control logic, so as to make it close to the ideal phase misalignment angle, thereby effectively reducing the output ripple.

[0041] S16: The first and second control signals after dead-time compensation are sent to the main phase resonant converter circuit and the slave phase resonant converter circuit respectively to trigger the main phase resonant converter circuit and the slave phase resonant converter circuit to change the switching state, thereby adjusting the output voltage.

[0042] The first control signal and the second control signal after dead-zone compensation are sent to the first master phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22 respectively to trigger the corresponding switching elements in the first master phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22 to change their states, and to make the first master phase resonant converter circuit 21 and the first slave phase resonant converter circuit 22 work in an interleaved manner to jointly adjust the output voltage of the first multiphase resonant converter circuit 20 to ensure stable and efficient energy conversion.

[0043] The above scheme achieves current sharing by allowing the two-phase resonant converter circuits to operate independently. Then, by compensating for the first or second dead time, it intervenes in the actual dead time of the first or second control signal, dynamically adjusting the phase difference between the first and second control signals to achieve phase misalignment adjustment closer to the ideal state. This allows for effective phase misalignment adjustment while achieving current sharing, thereby reducing output ripple. Furthermore, the phase misalignment adjustment method based on dead time compensation is simpler, lower in cost, and has a faster signal response compared to phase misalignment adjustment using a hardware phase modulator.

[0044] Furthermore, through multi-phase coordinated control, precise synchronization between multi-phase resonant converters can be effectively achieved, improving efficiency and stability. Adaptive dead-time compensation, which automatically adjusts the dead time based on pulse interval changes, avoids shoot-through risks. Strong anti-disturbance capability is achieved through closed-loop regulation using output voltage feedback and resonant signals, enhancing anti-interference ability. Synchronous control and adaptive dead-time compensation between phases are realized, improving overall efficiency and reliability. Dynamic response performance is optimized through pulse interval detection and dead-time compensation.

[0045] Furthermore, in one embodiment, the above-mentioned S15 may further include: in response to the comparison result between the interval pulse width and the target pulse width threshold range, performing dead-time compensation on the first dead time of the first control signal or the second dead time of the second control signal by a falling edge that is relatively lagging behind the falling edge of the first control signal and the falling edge of the second control signal.

[0046] Understandably, dead-time compensation for the first or second dead-time corresponds to extending the total off-time of the first or second control signal in the current signal cycle. This dead-time compensation utilizes the pulse width interval. Therefore, the falling edge of the first or second control signal in the current signal cycle that is relatively lagging can be used as the starting time to trigger dead-time compensation. For example, a control counter can be used to delay the next rising edge of the first or second control signal by a specific time, or an interrupt function can be triggered at the aforementioned relatively lagging falling edge to handle dead-time changes and intervene in phase adjustment.

[0047] In other embodiments, the start time for triggering dead-zone compensation can be any time after a relatively lagging falling edge between the falling edges of the first and second control signals, and before a relatively leading rising edge between the next rising edge of the first control signal predicting no dead-zone compensation and the next rising edge of the second control signal predicting no dead-zone compensation. This application does not limit this time.

[0048] It is worth noting that this interrupt function refers to the process where, when the computer processor is executing a task, an event or an interrupt request suddenly occurs, the processor will interrupt the current task and jump to the pre-set interrupt vector address to execute the interrupt handler.

[0049] Furthermore, in one embodiment, the process after S13 and before S14 may specifically include: sequentially performing phase modulation on each second control signal in response to the total number of first phase resonant conversion circuits 22.

[0050] Understandably, when the total number of the first phase resonant converter circuits 22 is different, the phase misalignment of each second control signal relative to the first control signal will also be different in order to satisfy the better output ripple; and in the first wave of the second control signal, that is, the first signal cycle, the phase misalignment of each second control signal can be adjusted by the pulse width of the first wave of the currently acquired first control signal, and after the second signal cycle of the first control signal and the second control signal, the phase misalignment of the second control signal relative to the first control signal is dynamically adjusted by the dead zone compensation corresponding to S14 mentioned above.

[0051] In some embodiments, the first multiphase resonant converter circuit 20 may specifically include at least two resonant converter circuits, wherein any one of the first multiphase resonant converter circuits 20 is a first master phase resonant converter circuit 21, and the other first multiphase resonant converter circuits 20 are first slave phase resonant converter circuits 22.

[0052] Specifically, when the first phase resonant converter circuit 22 is set to 1, in the first signal cycle, the second control signal is adjusted to be 90 degrees out of phase with the first control signal. For example, when the controller counter counts to half the pulse width of the first wave of the first control signal, the first rising edge of the second control signal is given. Alternatively, it can be understood that when the first wave of the second control signal is sent, the second dead time of the second control signal is compensated with the first rising edge of the first control signal as the starting time, and the current compensation amount is half the pulse width of the first wave of the first control signal. Or, when the first wave of the second control signal is sent, the second control signal is directly phase-shifted to be 90 degrees out of phase with the first control signal. After the second signal cycle of the first and second control signals, the first dead time of the first control signal or the second dead time of the second control signal is dynamically compensated in real time with the goal of adjusting the second control signal to be 90 degrees out of phase with the first control signal.

[0053] When the number of first phase resonant converter circuits 22 is 2, the two second control signals obtained are adjusted to be out of phase with the first control signal by 60 degrees and 120 degrees respectively. That is, the first rising edge of the second control signal is given by 1 / 3 and 2 / 3 of the first pulse width of the first control signal respectively. After the second signal cycle of the first control signal and the second control signal, the dynamic dead zone compensation is performed with the two second control signals being out of phase with the first control signal by 60 degrees and 120 degrees respectively as the ideal phase misalignment target.

[0054] Similarly, when the first phase resonant converter circuit 22 is n, the corresponding n second control signals are adjusted to be out of phase with the first control signal by 180 / (n+1) degrees, 2*180 / (n+1) degrees, ..., n*180 / (n+1) degrees, respectively. That is, the first rising edge of the second control signal is given by 1 / (n+1), 2 / (n+1), ..., n / (n+1) of the first pulse width of the first control signal. After the second signal cycle of the first control signal and the second control signal, the first dead time of the first control signal or the second dead time of each second control signal is dynamically compensated with the ideal phase misalignment target of each second control signal being out of phase with the first control signal by 180 / (n+1) degrees, 2*180 / (n+1) degrees, ..., n*180 / (n+1) degrees.

[0055] It is worth noting that in the dead zone compensation for the first dead time or the second dead time, the corresponding target pulse width threshold range can be specifically obtained according to the above-mentioned ideal phase misalignment target setting. For example, if the first pulse width of the current signal cycle of the first control signal is Ta and the first dead time is Tdba, then the intermediate values ​​of the target pulse width threshold range can be Ta / (n+1), 2*Ta / (n+1), ..., n*Ta / (n+1), or (Ta+Tdba) / (n+1), 2*(Ta+Tdba) / (n+1), ..., n*(Ta+Tdba) / (n+1). The group interval of the target pulse width threshold range can be set and adjusted according to actual needs, which will not be elaborated here.

[0056] In another embodiment, in the dead-time compensation control strategy, in the hardware circuit arrangement of the first multiphase resonant converter circuit 20, one of every two adjacent resonant converter circuits is set as the first master phase resonant converter circuit 21, and the other is set as the first slave phase resonant converter circuit 22. Similarly, taking the first slave phase resonant converter circuit 22 as specifically including first slave phase resonant converter circuit 1, first slave phase resonant converter circuit 2, ..., first slave phase resonant converter circuit n, and corresponding to the second control signal 1, second control signal 2, ..., second control signal n respectively, it can be seen that the first slave phase resonant converter circuit 1 is a slave phase relative to the first master phase resonant converter circuit 21, and the target pulse width threshold range 1 is set with the second control signal 1 being out of phase with the first control signal by 180 / (n+1) degrees as the ideal phase misalignment target, and dead-time compensation is performed on the first dead time of the first control signal or the second dead time 1 of the second control signal 1. When performing phase misalignment adjustment on the first slave phase resonant converter circuit 2, the first slave phase resonant converter circuit 1 is the master phase relative to the first slave phase resonant converter circuit 2. The target pulse width threshold range 2 is set with the phase misalignment target of 180 / (n+1) degrees between the second control signal 2 and the second control signal 1 as the ideal phase misalignment target. Dead time compensation is performed on the second dead time 1 of the second control signal 1 or the second dead time 2 of the second control signal 2. Similarly, the first slave phase resonant converter circuit n is the slave phase relative to the first slave phase resonant converter circuit (n-1). The target pulse width threshold range n is set with the phase misalignment target of 180 / (n+1) degrees between the second control signal n and the second control signal (n-1) as the ideal phase misalignment target. Dead time compensation is performed on the second dead time (n-1) of the second control signal (n-1) or the second dead time n of the second control signal n. This achieves current sharing while also realizing phase misalignment adjustment and reducing output ripple. Further details are omitted here.

[0057] Please see Figure 3 and Figure 4 ,in, Figure 3 This is a flowchart illustrating the second embodiment of the drive control method of this application. Figure 4This is a schematic diagram of the second embodiment of the drive control circuit. The drive control method of this embodiment is... Figure 1 A detailed implementation diagram of the drive control method is shown, which specifically includes the following steps: S41: Obtain the first resonant signal in the main phase resonant converter circuit, the second resonant signal in the slave phase resonant converter circuit, and the output voltage.

[0058] S42: Generate the first control signal using the first resonant signal and the output voltage.

[0059] S43: Generate a second control signal using the second resonant signal and the output voltage.

[0060] S44: Obtain the pulse width between the first rising edge of the first control signal and the second rising edge of the second control signal.

[0061] Among them, S41, S42, S43 and S44 and Figure 1 S11, S12, S13 and S14 are the same. Please refer to the textual descriptions of S11, S12, S13 and S14 and their related texts for details. They will not be repeated here.

[0062] S45: Detect whether the pulse width of the detection interval is lower than the target pulse width threshold range.

[0063] Please continue reading. Figure 4 , Figure 4 This is a schematic diagram of the second embodiment of the drive control circuit.

[0064] It is understood that the drive control method in this embodiment can specifically be as follows: Figure 4The second drive control circuit 60 shown implements drive control for the second multiphase resonant converter circuit 50. The second multiphase resonant converter circuit 50 includes a second main-phase resonant converter circuit 51 and a second slave-phase resonant converter circuit 52. The second main-phase resonant converter circuit 51 includes a first power switch circuit 511, a first freewheeling circuit 512, a first resonant circuit 513, a first isolation transformer 514, a first rectifier circuit 515, and a regulated output circuit 516. The second slave-phase resonant converter circuit 52 includes a second power switch circuit 521, a second freewheeling circuit 522, a second resonant circuit 523, a second isolation transformer 524, and a second rectifier circuit 525. The first power switch circuit 511 includes a first switching transistor Q11 and a second switching transistor... Q12; The first switching freewheeling circuit 512 includes a first freewheeling resistor Rc11, a second freewheeling resistor Rc12, a first freewheeling capacitor C11, a second freewheeling capacitor C12, a first diode D11, and a second diode D12; The first resonant circuit 513 includes a first resonant capacitor Cr11, a second resonant capacitor Cr12, and a first resonant inductor Lr1; The first isolation transformer 514 includes a first primary winding Lm1, a first secondary winding Ln11, and a second secondary winding Ln12; The first rectifier circuit 515 includes a third diode D13 and a fourth diode D14; The regulated output circuit 516 further includes a regulated resistor Ro and a regulated capacitor Co. The second power switching circuit 521 includes a third switching transistor Q21 and a fourth switching transistor Q22; the second freewheeling circuit 522 includes a third freewheeling resistor Rc21, a fourth freewheeling resistor Rc22, a third freewheeling capacitor C21, a fourth freewheeling capacitor C22, a fifth diode D21, and a sixth diode D6; the second resonant circuit 523 includes a third resonant capacitor Cr21, a fourth resonant capacitor Cr22, and a second resonant inductor Lr2; the second isolation transformer 524 includes a second primary winding Lm2, a third secondary winding Ln21, and a fourth secondary winding Ln22; and the second rectifier circuit 525 includes a seventh diode D23 and an eighth diode D24.

[0065] Specifically, the first terminal of the first switch Q11 is coupled to the first terminal of the first freewheeling resistor Rc11, the second terminal of the first diode D11, the first terminal of the first resonant capacitor Cr11, the first terminal of the third switch Q21, the first terminal of the third freewheeling resistor Rc21, the second terminal of the fifth diode D21, and the first terminal of the third resonant capacitor Cr21, and is used to couple to the first terminal of the power supply circuit 101. The second terminal of the second switch Q12 is coupled to the second terminal of the second freewheeling capacitor C12, the first terminal of the second diode D12, and the second terminal of the second resonant capacitor Cr12. The second terminal of the fourth switch Q22 is coupled to the second terminal of the fourth freewheeling capacitor C22, the first terminal of the sixth diode D6, and the second terminal of the fourth resonant capacitor Cr22, and is used to couple to the second terminal of the power supply circuit 101. The second terminal of the first freewheeling resistor Rc11 is coupled to the first terminal of the first freewheeling capacitor C11, and the second terminal of the first freewheeling capacitor C11 is coupled to the first terminal of the first diode D11, the second terminal of the first switch Q11, the first terminal of the second switch Q12, and the first terminal of the second freewheeling resistor Rc12. The second terminal of the second diode D12 is coupled to the first terminal of the first resonant inductor Lr1. The second terminal of the second freewheeling resistor Rc12 is coupled to the first terminal of the second freewheeling capacitor C12. The second terminal of the first resonant capacitor Cr11 is coupled to the first terminal of the second resonant capacitor Cr12 and the second terminal of the first primary winding Lm1. The second terminal of the first resonant inductor Lr1 is coupled to the first terminal of the first primary winding Lm1. The second terminal of the third freewheeling resistor Rc21 is coupled to the first terminal of the third freewheeling capacitor C21. The second terminal of the third freewheeling capacitor C21 is coupled to the fifth diode. The first terminal of transistor D21, the second terminal of the third switching transistor Q21, the first terminal of the fourth switching transistor Q22, the first terminal of the fourth freewheeling resistor Rc22, the second terminal of the sixth diode D6, and the first terminal of the second resonant inductor Lr2 are connected. The second terminal of the fourth freewheeling resistor Rc22 is coupled to the first terminal of the fourth freewheeling capacitor C22. The second terminal of the third resonant capacitor Cr21 is coupled to the first terminal of the fourth resonant capacitor Cr22 and the second terminal of the second primary winding Lm2. The second terminal of the second resonant inductor Lr2 is coupled to the first terminal of the second primary winding Lm2.

[0066] The first primary winding Lm1 is coupled to the first secondary winding Ln11 and the second secondary winding Ln12. The first end of the third diode D13 is coupled to the first end of the first secondary winding Ln11. The second end of the third diode D13 is coupled to the second end of the fourth diode D14, the first end of the voltage regulator Ro, the second end of the seventh diode D23, and the second end of the eighth diode D24, and is used to couple to the first end of the load circuit 102. The first end of the fourth diode D14 is coupled to the second end of the second secondary winding Ln12. The second end of the voltage regulator Ro is coupled to the first end of the voltage regulator Co. The second end of the voltage regulator Co is coupled to the second end of the first secondary winding Ln11, the first end of the second secondary winding Ln12, the second end of the third secondary winding Ln21, and the first end of the fourth secondary winding Ln22, and is used to couple to the second end of the load circuit 102.

[0067] In some embodiments, the first switch Q11, the second switch Q12, the third switch Q21, and the fourth switch Q22 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a transistor, a thin film transistor, a field effect transistor, or any other reasonable switch, and this application does not limit them.

[0068] It is worth noting that, to distinguish the two ends of each switching transistor except for the control terminal, one terminal is referred to as the first terminal and the other as the second terminal. When each switching transistor is a bipolar junction transistor (BJT), the control terminal, i.e., the third terminal, can specifically be the base, the first terminal as the collector, and the second terminal as the emitter; or, the third terminal can specifically be the base, the first terminal as the emitter, and the second terminal as the collector.

[0069] When the switching transistors mentioned above are MOSFETs, thin-film transistors, or field-effect transistors, the third terminal can be the gate, the first terminal is the drain, and the second terminal is the source; or, the third terminal can also be the gate, the first terminal is the source, and the second terminal is the drain.

[0070] In particular, when each switching transistor is a MOSFET, a thin film transistor, or a field-effect transistor, it can also be a composite transistor or a single transistor, which is not limited in this application.

[0071] It is worth noting that, in other embodiments, the second primary phase resonant converter circuit 51 and the second secondary phase resonant converter circuit 52 may specifically be a half-bridge LLC converter, a full-bridge LLC converter, or any other reasonable LLC circuit topology. For example, the first power switch circuit 511 and the second power switch circuit 521 may specifically be a full-bridge switch circuit or an asymmetrical half-bridge switch circuit. The first rectifier circuit 515 and the second rectifier circuit 525 may specifically be a full-bridge rectifier circuit or a half-bridge rectifier circuit composed of various switching transistors, or any reasonable circuit form for realizing AC to DC conversion. Furthermore, the load circuit 102 may specifically include a load resistor R, and / or a load capacitor, a load inductor, or any reasonable circuit constituent unit. This application does not limit this.

[0072] Specifically, the first control signal further includes a first drive signal PWMA and a second drive signal PWMB, and the second control signal further includes a third drive signal PWMH and a fourth drive signal PWML.

[0073] In some embodiments, the power supply circuit 101 may specifically include a mains power frequency power supply and a PFC (Power Factor Correction) circuit. After the mains power is rectified by the PFC circuit, the output is a DC power supply, but it will be accompanied by power frequency ripple. After the second main phase resonant converter circuit 51 and the second slave phase resonant converter circuit 52 obtain the input voltage from the DC power supply, they are controlled by the second drive control circuit 60 to adjust the input voltage to supply power to the load circuit 102.

[0074] In some embodiments, the second drive control circuit 60 further includes a first sampling integration circuit 61, a second sampling integration circuit 62, a first proportional filter correction processing circuit 63, a second proportional filter correction processing circuit 64, and a control sub-circuit 65. The first sampling integration circuit 61 includes a first current transformer CT1 and a first integrating sampling capacitor CJ1, and the second sampling integration circuit 62 includes a second current transformer CT2 and a second integrating sampling capacitor CJ2.

[0075] The first current transformer CT1 is coupled to the second terminal of the first resonant capacitor Cr11, the first terminal of the second resonant capacitor Cr12, and the first terminal of the first integrating sampling capacitor CJ. The second terminal of the first current transformer CT1 is coupled to the second terminal of the first primary winding Lm1 and the second terminal of the first integrating sampling capacitor CJ1. The first terminal of the second current transformer CT2 is coupled to the second terminal of the third resonant capacitor Cr21, the first terminal of the fourth resonant capacitor Cr22, and the first terminal of the second integrating sampling capacitor CJ2. The second terminal of the second current transformer CT2 is coupled to the second terminal of the second primary winding Lm2 and the second terminal of the second integrating sampling capacitor CJ2. The first proportional filter correction processing circuit 63 is coupled to the first terminal of the voltage stabilizing resistor Ro, the second terminal of the voltage stabilizing capacitor Co, and the control sub-circuit 65. The second proportional filter... The correction processing circuit 64 is coupled to the first integrating sampling capacitor CJ1, the second integrating sampling capacitor CJ2, and the control sub-circuit 65. The control sub-circuit 65 is coupled to the third terminal of the first switch Q11, the third terminal of the second switch Q12, the third terminal of the third switch Q21, and the third terminal of the fourth switch Q22. It can use the first current transformer CT1 to sample and obtain the first resonant current signal in the second main phase resonant conversion circuit 51, and use the first integrating sampling capacitor CJ1 to integrate the first resonant current signal to obtain the first resonant capacitor voltage Vcs1. It can also use the second current transformer CT2 to sample and obtain the second resonant current signal in the second slave phase resonant conversion circuit 52, and use the second integrating sampling capacitor CJ2 to integrate the second resonant current signal to obtain the second resonant capacitor voltage Vcs2.

[0076] The first proportional filter correction processing circuit 63 is used to obtain the output voltage Vo of the voltage regulator output circuit 516 to the load circuit 102, and sequentially compares the output voltage Vo with the reference value, filters and corrects it to obtain the filtered output signal; the second proportional filter correction processing circuit 64 is used to obtain the first resonant capacitor voltage Vcs1 in the first sampling integration circuit 61 and the second resonant capacitor voltage Vcs2 in the second sampling integration circuit 62, and sequentially compares the first resonant capacitor voltage Vcs1 and the second resonant capacitor voltage Vcs2 with the reference value, filters and corrects them to obtain the first resonant signal and the second resonant signal, so as to provide a more suitable high-quality input for the control sub-circuit 65, thereby effectively optimizing the overall performance and reliability of the control sub-circuit 65 to achieve efficient control.

[0077] The control sub-circuit 65 is further used to receive the filtered output signal, the first resonant signal and the second resonant signal, and to obtain the first drive signal PWMA, the second drive signal PWMB, the third drive signal PWMH and the fourth drive signal PWML using the filtered output signal, the first resonant signal and the second resonant signal.

[0078] Please continue reading. Figure 5 , Figure 5 yes Figure 4 A schematic diagram of the waveforms of the relevant signals generated by the second drive control circuit in the middle to generate the first control signal.

[0079] In some embodiments, the control sub-circuit 65 integrates a logic comparator. The high-side terminal of the logic comparator receives the first resonant signal and the second resonant signal, or the first resonant capacitor voltage Vcs1 and the second resonant capacitor voltage Vcs2. The low-side terminal of the logic comparator is the adjusted output signal Vt obtained by the voltage loop controller through proportional-integral adjustment of the error value between the target reference voltage and the output voltage Vo. The adjusted output signal Vt is then slope-compensated to obtain the feedback adjustment signal Ft.

[0080] In this circuit, ramp compensation is triggered when the count for the next cycle is 0 after each wave generation cycle ends. The voltage loop controller in the control sub-circuit 65 adjusts the input voltage amplitude of the low terminal of the logic comparator according to the error. When the high terminal of the logic comparator is greater than the low terminal potential, i.e., when the voltage of the first resonant capacitor Vcs1 or the first resonant signal is greater than the feedback adjustment signal Ft, the output turns off the first drive signal PWMA. When the counter of the voltage loop controller is 0, the first drive signal PWMA is turned on. The second drive signal PWMB is turned on after the first drive signal PWMA is turned off, and its pulse width replicates the width of the first drive signal PWMA. The second drive signal PWMB is turned off after its pulse width is equal to the pulse width of the first drive signal PWMA. At this time, the counter of the voltage loop controller is cleared and starts counting again from 0.

[0081] Similarly, when the voltage of the second resonant capacitor Vcs2 or the second resonant signal is greater than the feedback adjustment signal Ft, the logic comparator outputs the third drive signal PWMH to be turned off; when the counter of the voltage loop controller is 0, the third drive signal PWMH is turned on; the fourth drive signal PWML is turned on after the third drive signal PWMH is turned off, and its pulse width replicates the width of the third drive signal PWMH. The fourth drive signal PWML is turned off after its pulse width is equal to the pulse width of the third drive signal PWMH. At this time, the counter of the voltage loop controller is cleared and starts counting from 0 again.

[0082] It is worth noting that the aforementioned first drive signal PWMA, second drive signal PWMB, third drive signal PWMH, and fourth drive signal PWML can actually be understood as the initial drive signals before phase misalignment adjustment, i.e., before dead time compensation, and each has an initial dead time set. Furthermore, since the second drive signal PWMB is obtained from the first drive signal PWMA, and the fourth drive signal PWML is obtained from the third drive signal PWMH, the following explanation can be based on the phase misalignment adjustment and dead time compensation of the third drive signal PWMH relative to the first drive signal PWMA.

[0083] Please continue reading. Figure 6 , Figure 6 yes Figure 3 A schematic diagram of the waveforms of the relevant signals in the drive control method.

[0084] Specifically, the control sub-circuit 65 acquires the first rising edge and the second rising edge of the current signal period of the first driving signal PWMA and the third driving signal PWMH to calculate the interval pulse width Tp. Specifically, it can calculate the pulse width of the current signal period of the reference pulse width signal based on the reference pulse width calculation signal, and set the target pulse width threshold range according to the ideal phase misalignment target to detect whether the interval pulse width Tp is lower than the target pulse width threshold range.

[0085] In this example, taking the first pulse width of the first driving signal PWMA as Ta and the first dead time as Tdba in the current signal period, the second pulse width of the third driving signal PWMH as Th and the second dead time as Tdbh, and the median value of the target pulse width threshold range as Tx, the actual signal period of the first driving signal PWMA is 2*(Ta+Tdba), the actual signal period of the third driving signal PWMH is 2*(Th+Tdbh), and the first pulse width Ta and the second pulse width Th can be specifically calculated using the first pulse width calculation signal and the second pulse width calculation signal.

[0086] If the interval pulse width Tp is lower than the target pulse width threshold range, then S46 is executed; if the interval pulse width Tp exceeds the target pulse width threshold range, then S47 is executed; if the interval pulse width Tp is within the target pulse width threshold range, then S48 is executed.

[0087] S46: Add the second dead time to the midpoint of the target pulse width threshold range and subtract the interval pulse width.

[0088] When the interval pulse width Tp is determined to be lower than the target pulse width threshold range, the second dead time Tdbh is added to the median value Tx of the target pulse width threshold range, and the interval pulse width Tp is subtracted. That is, Tdbh + (Tx - Tp) is used as the actual dead time of the third drive signal PWMH after dead time compensation in the current signal period, so as to delay the triggering of the next rising edge of the third drive signal PWMH, thereby realizing the phase misalignment adjustment of the third drive signal PWMH relative to the first drive signal PWMA.

[0089] The median value Tx of the target pulse width threshold range can be understood as the average value between the upper and lower limits of the target pulse width threshold range.

[0090] S47: Add the interval pulse width to the first dead time and subtract the median value of the target pulse width threshold range.

[0091] When the interval pulse width Tp exceeds the target pulse width threshold range, the first dead time Tdba is added to the interval pulse width Tp and the median value Tx of the target pulse width threshold range is subtracted. That is, Tdba + (Tp - Tx) is taken as the actual dead time of the first drive signal PWMA after dead time compensation in the current signal period, so as to delay the triggering of the next rising edge of the first drive signal PWMA, thereby realizing the phase misalignment adjustment of the third drive signal PWMH relative to the first drive signal PWMA.

[0092] S48: Detect whether the first pulse width of the first control signal is greater than the second pulse width of the second control signal.

[0093] When the interval pulse width Tp is determined to be within the target pulse width threshold range, it is further detected whether the first pulse width Ta of the first driving signal PWMA is greater than the second pulse width Th of the third driving signal PWMH.

[0094] If the first pulse width Ta is greater than the second pulse width Th, then S49 is executed; if the first pulse width Ta is less than the second pulse width Th, then S410 is executed; if the first pulse width Ta is equal to the second pulse width Th, then S411 is executed.

[0095] S49: Add the dead zone compensation time to the second dead zone time.

[0096] When it is determined that the first pulse width Ta is greater than the second pulse width Th, the second dead time Tdbh is added to the dead time compensation time ∆T, that is, (Tdbh+∆T) is used as the actual dead time of the third drive signal PWMH after dead time compensation in the current signal period, so as to delay the triggering of the next rising edge of the third drive signal PWMH, thereby realizing the phase misalignment adjustment of the third drive signal PWMH relative to the first drive signal PWMA.

[0097] In some embodiments, the dead zone compensation time ∆T can be greater than or equal to twice the absolute value of the first pulse width Ta minus the second pulse width Th, i.e., ∆T≥2*|Ta-Th|, or it can be greater than or equal to twice the absolute value of the first pulse width Ta minus the second pulse width Th, and less than or equal to four times the absolute value of the first pulse width Ta minus the second pulse width Th, i.e., 4*|Ta-Th|≥∆T≥2*|Ta-Th|. This application does not limit it in this way.

[0098] S410: Add the dead time compensation time to the first dead time.

[0099] When it is determined that the first pulse width Ta is less than the second pulse width Th, the first dead time Tdba is added to the dead time compensation time ∆T, that is, (Tdba+∆T) is used as the actual dead time of the first drive signal PWMA after dead time compensation in the current signal period, so as to delay the triggering of the next rising edge of the first drive signal PWMA, thereby realizing the phase misalignment adjustment of the third drive signal PWMH relative to the first drive signal PWMA.

[0100] S411: Keep the first dead time and the second dead time unchanged.

[0101] Understandably, when the first pulse width Ta is determined to be equal to the second pulse width Th, it can be determined that the phase difference between the current third driving signal PWMH and the first driving signal PWMA is close to the ideal phase misalignment state, and there is no need to compensate for the first dead time Tdba and the second dead time Tdbh, that is, to keep the first dead time Tdba and the second dead time Tdbh unchanged.

[0102] S410: The first and second control signals after dead-time compensation are sent to the main phase resonant converter circuit and the slave phase resonant converter circuit respectively to trigger the main phase resonant converter circuit and the slave phase resonant converter circuit to change the switching state, thereby adjusting the output voltage.

[0103] The control sub-circuit 65 sends the first drive signal PWMA, the second drive signal PWMB, the third drive signal PWMH, and the fourth drive signal PWML, which are obtained after the aforementioned dead-time compensation, to the third terminals of the first switch Q11, the second switch Q12, the third switch Q21, and the fourth switch Q22, respectively, to trigger the first switch Q11, the second switch Q12, the third switch Q21, and the fourth switch Q22 to turn on or off, thereby adjusting the output voltage Vo of the voltage regulator output circuit 516 to respond to load changes more flexibly and efficiently, ensuring that the output voltage Vo is stable and efficient.

[0104] Furthermore, in one embodiment, the above-mentioned S45 may further include: detecting whether the interval pulse width Tp is lower than the target pulse width threshold range at a falling edge that is relatively lagging behind the falling edge of the first control signal and the falling edge of the second control signal.

[0105] Understandably, the control sub-circuit 65 actually obtains the first pulse width Ta of the first driving signal PWMA and the second pulse width Th of the third driving signal PWMH at a relatively lagging falling edge between the first falling edge of the first driving signal PWMA and the second falling edge of the third driving signal PWMH. The target pulse width threshold range can be specifically set according to the first pulse width Ta and / or the second pulse width Th, and adjusted in real time. Therefore, the relatively lagging falling edge between the first falling edge of the first driving signal PWMA and the second falling edge of the third driving signal PWMH in the current signal period needs to be used as the starting time for triggering dead-time compensation.

[0106] In some embodiments, the control sub-circuit 65 may specifically trigger an interrupt function in response to the interrupt trigger signal INT at a relatively delayed falling edge obtained above, such as at the corresponding time of the second falling edge, or at any time after a relatively delayed falling edge in the first falling edge of the first drive signal PWMA and the second falling edge of the third drive signal PWMH, and before a relatively advanced rising edge in the next rising edge predicted by the first drive signal PWMA without dead-time compensation and the next rising edge predicted by the third drive signal PWMH without dead-time compensation, so as to handle dead-time changes and intervene in phase adjustment through the interrupt function. This application does not limit this.

[0107] Please see Figure 7 , Figure 7 This is a flowchart illustrating the third embodiment of the drive control method of this application. The drive control method of this embodiment... Figure 1 A detailed implementation diagram of the drive control method is shown, which specifically includes the following steps: S71: Obtain the first resonant signal in the main phase resonant converter circuit, the second resonant signal in the slave phase resonant converter circuit, and the output voltage.

[0108] S72: Generate the first control signal using the first resonant signal and the output voltage.

[0109] S73: Generates a second control signal using the second resonant signal and the output voltage.

[0110] S74: Obtain the pulse width between the first rising edge of the first control signal and the second rising edge of the second control signal.

[0111] Among them, S71, S72, S73 and S74 and Figure 1 S11, S12, S13 and S14 are the same. Please refer to the textual descriptions of S11, S12, S13 and S14 and their related texts for details. They will not be repeated here.

[0112] S75: Divide the first pulse width of the first control signal by the set number to obtain the first reference pulse width.

[0113] It is understandable that the total number of the second main phase resonant converter circuit 51 and the second slave phase resonant converter circuit 52 is a set number m (m is a positive integer greater than 1), and since there is actually only one second main phase resonant converter circuit 51, the set number m can be understood as (n+1).

[0114] Specifically, the first pulse width Ta of the first control signal is divided by a set number m to obtain the first reference pulse width Tc1, i.e., Tc1=Ta / m.

[0115] S76: The sum of the first pulse width and the first dead time is divided by a set number to obtain the second reference pulse width.

[0116] The second reference pulse width Tc2 is obtained by dividing the sum of the first pulse width Ta and the first dead time Tdba by the set number m, i.e., Tc2 = (Ta + Tdba) / m.

[0117] S77: Divide the second pulse width of the second control signal by the set number to obtain the third reference pulse width.

[0118] Divide the second pulse width Th of the second control signal by the set number m to obtain the third reference pulse width Tc3, i.e., Tc3=Th / m.

[0119] S78: The sum of the second pulse width and the second dead time is divided by the set number to obtain the fourth reference pulse width.

[0120] The fourth reference pulse width Tc4 is obtained by adding the second pulse width Th to the second dead time Tdbh and dividing by the set number m, i.e., Tc4 = (Th + Tdbh) / m.

[0121] S79: Divide the sum of the first pulse width, the first dead time, the second pulse width, and the second dead time by the set quantity, and then divide by 2 to obtain the fifth reference pulse width.

[0122] The sum of the first pulse width Ta, the first dead time Tdba, the second pulse width Th, and the second dead time Tdbh is divided by the set quantity m, and then divided by 2 to obtain the fifth reference pulse width Tc5, that is, Tc5 = (Ta + Tdba + Th + Tdbh) / (2 * m).

[0123] S710: Set the minimum and maximum values ​​of the first reference pulse width, second reference pulse width, third reference pulse width, fourth reference pulse width, and fifth reference pulse width as the lower limit and upper limit of the target pulse width threshold range, respectively.

[0124] Understandably, when the first reference pulse width Tc1, the second reference pulse width Tc2, the third reference pulse width Tc3, the fourth reference pulse width Tc4, and the fifth reference pulse width Tc5 of the current signal period are obtained, the minimum and maximum values ​​of these can be set to obtain the lower limit and upper limit of the target pulse width threshold range, so as to improve the stability of subsequent dead zone compensation by utilizing the hysteresis interval formed by the target pulse width threshold range.

[0125] It is worth noting that the hysteresis interval refers to the stable range between upper and lower thresholds set in control or signal processing to avoid frequent output switching caused by small fluctuations in the input signal. It is widely used in fields such as electronic circuits, automatic control systems, and structural engineering.

[0126] The hysteresis interval, by setting different trigger and release thresholds, forms a "buffer band" for the input signal. Its core logic is as follows: Input ≥ upper limit threshold: Output state switching (e.g., high level or function activation); Input ≤ lower threshold: Output state reverses (e.g., low level or function off); If the input is within the range: keep the previous state unchanged.

[0127] S711: In response to the comparison result between the interval pulse width and the target pulse width threshold range, perform dead-time compensation on the first dead time of the first control signal or the second dead time of the second control signal.

[0128] S712: The first and second control signals after dead-time compensation are sent to the master phase resonant converter circuit and the slave phase resonant converter circuit respectively to trigger the master phase resonant converter circuit and the slave phase resonant converter circuit to change the switching state, thereby adjusting the output voltage.

[0129] Among them, S711 and S712 and Figure 1 S15 and S16 are the same. Please refer to S15 and S16 and their related textual descriptions for details. They will not be repeated here.

[0130] Furthermore, in one embodiment, the above-mentioned S75 may further include: dividing the first pulse width Ta of the first control signal by a set number m to obtain the first reference pulse width Tc1 at a falling edge that is relatively lagging between the falling edge of the first control signal and the falling edge of the second control signal.

[0131] Similarly, in response to the corresponding interrupt trigger signal INT, the first reference pulse width Tc1, the second reference pulse width Tc2, the third reference pulse width Tc3, the fourth reference pulse width Tc4, and the fifth reference pulse width Tc5 of the current signal cycle are calculated in sequence to further set the target pulse width threshold range, and the target pulse width threshold range is dynamically adjusted in subsequent signal cycles.

[0132] Furthermore, in one embodiment, the above-mentioned S710 can be replaced by: selecting any one of the first reference pulse width Tc1, the second reference pulse width Tc2, the third reference pulse width Tc3, the fourth reference pulse width Tc4, and the fifth reference pulse width Tc5 as the median value Tx of the target pulse width threshold range, and setting the group interval of the target pulse width threshold range as the hysteresis interval value.

[0133] The hysteresis interval value can be set and adjusted according to the actual phase misalignment adjustment scenario, and this application does not limit it.

[0134] This application also provides an electronic device, please refer to... Figure 8 , Figure 8 This is a schematic diagram of one embodiment of the electronic device of this application. In this embodiment, the electronic device 80 includes a housing 81 and a third drive control circuit 82 connected to the housing 81.

[0135] It should be noted that the third drive control circuit 82 described in this embodiment is either the first drive control circuit 30 or the second drive control circuit 60 described in any of the above embodiments. Please refer to [link / reference] for details. Figures 1-7 The relevant textual content will not be elaborated upon here.

[0136] The beneficial effects of this application are as follows: Unlike existing technologies, the drive control method provided in this application acquires the first resonant signal in the main phase resonant converter circuit, the second resonant signal in the slave phase resonant converter circuit, and the output voltage. It then uses the first resonant signal and the output voltage to generate a first control signal, and uses the second resonant signal and the output voltage to generate a second control signal, allowing the two phase resonant converter circuits to operate independently to achieve current sharing. Furthermore, it acquires the pulse width interval between the first rising edge of the first control signal and the second rising edge of the second control signal, and adjusts the first dead time of the first control signal or the second dead time of the second control signal in response to the comparison result between the pulse width interval and the target pulse width threshold range. Dead-time compensation allows for dynamic adjustment of the phase difference between the first and second control signals by intervening in their actual dead time. This achieves phase misalignment adjustment closer to the ideal state. When the dead-time-compensated first and second control signals are sent to the master-phase resonant converter circuit and the slave-phase resonant converter circuit respectively to trigger them to change their switching states and adjust the output voltage, phase misalignment adjustment can be effectively achieved while simultaneously achieving current sharing, thus reducing output ripple. Furthermore, the dead-time-compensated phase misalignment adjustment method is simpler, lower in cost, and has a faster signal response compared to phase misalignment adjustment using a hardware phase modulator.

[0137] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A driving control method for a multiphase resonant converter circuit, wherein the multiphase resonant converter circuit comprises a master phase resonant converter circuit and a slave phase resonant converter circuit connected in parallel, characterized in that, The drive control method includes: Acquire the first resonant signal in the master phase resonant converter circuit, the second resonant signal in the slave phase resonant converter circuit, and the output voltage; A first control signal is generated using the first resonant signal and the output voltage; A second control signal is generated using the second resonant signal and the output voltage; Obtain the pulse width interval between the first rising edge of the first control signal and the second rising edge of the second control signal; Dead-time compensation is performed on the first dead time of the first control signal or the second dead time of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range. The first control signal and the second control signal after dead-zone compensation are sent to the main phase resonant converter circuit and the slave phase resonant converter circuit respectively to trigger the main phase resonant converter circuit and the slave phase resonant converter circuit to change the switching state, thereby adjusting the output voltage.

2. The drive control method according to claim 1, characterized in that, The step of performing dead-time compensation on the first dead-time of the first control signal or the second dead-time of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range includes: Detect whether the interval pulse width is lower than the target pulse width threshold range; If the interval pulse width is lower than the target pulse width threshold range, the second dead time is added to the median value of the target pulse width threshold range, and the interval pulse width is subtracted.

3. The drive control method according to claim 2, characterized in that, The drive control method further includes: If the interval pulse width exceeds the target pulse width threshold range, the first dead time is added to the interval pulse width and subtracted from the middle value of the target pulse width threshold range.

4. The drive control method according to claim 2, characterized in that, The drive control method further includes: If the interval pulse width is within the target pulse width threshold range, detect whether the first pulse width of the first control signal is greater than the second pulse width of the second control signal; If the first pulse width is equal to the second pulse width, the first dead time and the second dead time remain unchanged.

5. The drive control method according to claim 2, characterized in that, The drive control method further includes: If the first pulse width of the first control signal is greater than the second pulse width of the second control signal, the second dead time is added to the dead time compensation time; wherein the dead time compensation time is greater than or equal to twice the absolute value of the first pulse width minus the second pulse width; If the first pulse width is less than the second pulse width, the first dead time is added to the dead time compensation time.

6. The drive control method according to claim 1, characterized in that, The step of performing dead-time compensation on the first dead-time of the first control signal or the second dead-time of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range includes: In response to the comparison between the interval pulse width and the target pulse width threshold range, dead time compensation is performed on the first dead time of the first control signal or the second dead time of the second control signal at a falling edge that is relatively lagging between the falling edge of the first control signal and the falling edge of the second control signal.

7. The drive control method according to any one of claims 1-6, characterized in that, The total number of the master phase resonant converter circuit and the slave phase resonant converter circuit is a predetermined number. Before the step of performing dead-time compensation on the first dead time of the first control signal or the second dead time of the second control signal in response to the comparison result between the interval pulse width and the target pulse width threshold range, the method further includes: The first reference pulse width is obtained by dividing the first pulse width of the first control signal by the set number. The second reference pulse width is obtained by adding the first pulse width to the first dead time and dividing by the set number. The third reference pulse width is obtained by dividing the second pulse width of the second control signal by the set number. The fourth reference pulse width is obtained by adding the second pulse width to the second dead time and dividing by the set number. The sum of the first pulse width, the first dead time, the second pulse width, and the second dead time is divided by the set number, and then divided by 2 to obtain the fifth reference pulse width. The minimum and maximum values ​​of the first reference pulse width, the second reference pulse width, the third reference pulse width, the fourth reference pulse width, and the fifth reference pulse width are respectively set as the lower limit and the upper limit of the target pulse width threshold range.

8. The drive control method according to any one of claims 1-6, characterized in that, Before the step of obtaining the pulse width interval between the first rising edge of the first control signal and the second rising edge of the second control signal, the method further includes: In response to the total number of phase resonant conversion circuits, each of the second control signals is sequentially phase-modulated.

9. A drive control circuit, characterized in that, The drive control circuit is coupled to the main phase resonant converter circuit and the slave phase resonant converter circuit, and the main phase resonant converter circuit and the slave phase resonant converter circuit are connected in parallel. The drive control circuit uses the drive control method as described in any one of claims 1-8 to drive and control the master phase resonant converter circuit and the slave phase resonant converter circuit.

10. An electronic device, characterized in that, The electronic device includes a housing and a drive control circuit connected to the housing; The drive control circuit is the drive control circuit as described in claim 9.

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