Power-up mechanism, test system and method
By combining a DC current source meter and a power switch driver with a multi-channel discrete probe assembly, the problems of low efficiency and high cost in testing high-power semiconductor laser chips are solved, achieving efficient chip pulse power-up and photoelectric performance testing, and reducing production costs.
Patent Information
- Application Number
- CN202511068912.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-18
AI Technical Summary
Existing high-power semiconductor laser chip testing is inefficient, costly, and requires a large amount of testing equipment; traditional pulse current source meters are also expensive.
A DC current source meter and a power switch driver are used in conjunction with a multi-channel discrete probe assembly. The power switch driver controls the instantaneous switching of each chip to achieve pulse power-on. The power-on and power-off times of the chips in the same group are synchronously distributed to adjacent chips to achieve the ON state. Combined with a synchronous acquisition driver and an optoelectronic test unit, electrical and optical signals are efficiently acquired.
It improves testing efficiency, reduces production costs, reduces the time for pin lifting and lateral displacement, lowers source table costs, and achieves efficient chip pulse power-up.
Smart Images
Figure CN120971931A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optical communication technology, specifically to a power-on mechanism, a testing system, and a method. Background Technology
[0002] High-power semiconductor lasers are one of the most mature and widely used types of semiconductor laser technology. On the one hand, with the rapid development of artificial intelligence and data centers, the demand for AI computing power and high-speed optical modules in data centers is increasing, and high-power semiconductor lasers are mainly used as the mainstream light source in these fields. On the other hand, the explosive growth in demand from fields such as autonomous driving, robotics, and smart cities is also leading to a growing demand for LiDAR applications. As the main chip in LiDAR transmitters, the application demand for high-power semiconductor lasers is also increasing. They have advantages such as high power, high electro-optical conversion efficiency, small size, and long lifespan.
[0003] To ensure the quality and reliability of high-power semiconductor laser chips, all such chips require automated photoelectric performance testing. Because of their high power and relatively thick thickness, chip testing generates significant heat; therefore, these high-power semiconductor laser chip-level tests typically employ pulsed current application schemes. Pulsed testing source meters are relatively expensive, and testing a large number of chips also increases costs. Furthermore, high-power chip applications require large current points, necessitating a large current application range during PIV testing. Consequently, high-power semiconductor laser testing is time-consuming, inefficient, and costly. Therefore, there is a need in this field for a low-cost, high-efficiency high-power semiconductor laser testing solution.
[0004] Existing testing solutions generally involve pairing each testing device with a corresponding pulse current source meter based on the number of temperature stations; each high-power semiconductor laser chip is tested sequentially on the testing machine. For high-power semiconductor laser chips, the current application range is very large, and completing the test of one chip takes more than ten seconds, which is inefficient; mass production in factories requires a large number of testing devices, resulting in high production costs. Summary of the Invention
[0005] The purpose of this invention is to provide an energizing mechanism, a testing system, and a method, which can at least solve some of the defects in the prior art.
[0006] To achieve the above objectives, embodiments of the present invention provide the following technical solution: a power-on mechanism, comprising a DC current source meter, a power switch driver, and a multi-channel discrete probe assembly.
[0007] The DC current source meter is used to output several step DC currents.
[0008] The power switch driver is used to perform instantaneous switching control on the multi-channel discrete probe assembly according to the control command for each step DC current switch.
[0009] The multi-channel separation probe assembly is used to output each of the step DC currents sequentially to different chips under test in a timing sequence.
[0010] Furthermore, the DC current source meter and the power switch driver are connected via an electrical channel board, and the multi-channel discrete probe assembly is also connected to the power switch driver via an electrical channel board.
[0011] Furthermore, the multi-channel separation probe assembly is also used to separate each of the step DC currents into short-pulse currents to power up the chip under test.
[0012] Furthermore, the multi-channel separation probe assembly has several independent probe channels, each of which independently contacts the power-on pad of the chip under test.
[0013] This invention provides another technical solution: a testing system, including a synchronous acquisition driver, a photoelectric testing unit, and the aforementioned power-on mechanism. The synchronous acquisition driver is used to issue instructions for acquiring signals, and the photoelectric testing unit is used to receive the instructions for acquiring signals issued by the synchronous acquisition driver and to acquire electrical and optical signals.
[0014] Furthermore, the synchronous acquisition driver is linked to the power switch driver, and the power switch driver operates first, while the synchronous acquisition driver operates after a delay.
[0015] Furthermore, the photoelectric testing unit includes an electrical signal acquisition source table for reading the electrical signals of the chip under test and an optical signal acquisition source table for reading the optical signals of the chip under test.
[0016] Furthermore, the electrical signal acquisition source meter is connected to the probe of the multi-channel separation probe assembly, and the optical signal acquisition source meter is connected to the light receiving assembly.
[0017] This invention provides another technical solution: a testing method, comprising the following steps:
[0018] S1 uses a DC current source meter to output several step DC currents;
[0019] S2, a power switch driver is used to perform instantaneous switching control of the multi-channel separation probe assembly according to the control command of each step DC current switch. The multi-channel separation probe assembly receives the control command and outputs each step DC current sequentially to different chips under test in a time sequence.
[0020] S3, after the power switch driver has finished operating, the synchronous acquisition driver gives the instruction to acquire the signal;
[0021] S4, the photoelectric test unit receives the acquisition signal instruction issued by the synchronous acquisition driver and acquires electrical and optical signals.
[0022] Furthermore, the multi-channel separation probe assembly simultaneously probes the chips in the same group, and the power switch driver controls the time domain switch of the chips in the same group to synchronously allocate the time of the power-on OFF state to the adjacent chips in the same group to achieve the power-on state.
[0023] Compared with the prior art, the beneficial effects of the present invention are:
[0024] 1. A structure is proposed that uses a DC current source meter with an external power switch driver and a multi-channel discrete probe assembly. By controlling the instantaneous switching of the power switch driver and using the multi-channel discrete probe assembly, each step DC current output by the DC current source meter is sequentially output to different chips under test, achieving the effect of actual pulse power-up on each chip. This provides a more efficient alternative to chip pulse power-up.
[0025] 2. A multi-channel separate probe assembly is used to simultaneously probe the chips in the same group, and the time-domain switching of the chips in the same group is controlled by a power switch driver; the time synchronization of the power-off state in the traditional pulse power-on test scheme is utilized and distributed to the adjacent chips in the same group to achieve the power-on state (for example, when sample chip 1 is in the four "OFF" states, it corresponds to the "ON" states of sample chips 2, 3, 4, and 5 respectively); the test efficiency is greatly improved and the production cost is reduced.
[0026] 3. The use of a multi-channel separate probe assembly to simultaneously probe the same group of chips reduces the time for probe lifting and lateral displacement, thereby improving testing efficiency and reducing production costs.
[0027] 4. It can achieve pulse power-up effect simply by using a DC current source meter, which reduces the cost of the source meter. Attached Figure Description
[0028] Figure 1 A schematic diagram illustrating the chip test pulse effect of a test system provided in an embodiment of the present invention;
[0029] Figure 2 A schematic diagram of a power switch driver switching control (5mA 1000us decomposed into 5 chips) of a test system provided in an embodiment of the present invention;
[0030] Figure 3 This is a schematic diagram of the shunting effect of a power switch driver in a test system provided in an embodiment of the present invention (5mA 1000us decomposed into 5 chips). Detailed Implementation
[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] Please see Figure 1 This invention provides a power-on mechanism, including a DC current source meter, a power switch driver, and a multi-channel separation probe assembly. The DC current source meter outputs several step DC currents. The power switch driver controls the instantaneous switching of the multi-channel separation probe assembly according to control commands for switching on each step DC current. The multi-channel separation probe assembly sequentially outputs each step DC current to different chips under test in a time sequence. Existing testing schemes generally involve matching each testing device with a corresponding pulse current source meter based on the number of temperature stations; each high-power semiconductor laser chip is tested sequentially on the testing machine. For high-power semiconductor laser chips, the current application range is very large, and testing a single chip takes tens of seconds, resulting in low efficiency. Mass production requires a large number of testing equipment, leading to high production costs. In this embodiment, a DC current source meter with an external power switch driver and a multi-channel discrete probe assembly is used. By controlling the instantaneous switching of the power switch driver, the multi-channel discrete probe assembly sequentially outputs each step DC current from the DC current source meter to different chips under test, achieving the effect of actual pulsed power application to each chip. This provides a more efficient alternative for chip pulsed power application. The main function of the DC current source meter is to output step DC current; the main function of the power switch driver is to decompose the single-step DC current to each chip by setting the control switching time period and the number of switching cycles of the discrete channels, achieving a pulsed step DC current power application effect; the main function of the multi-channel discrete probe assembly is to ensure consistent switching cycles with the power switch driver, achieving the effect of pulsed step DC current power application to each chip.
[0033] Specifically, the DC current source meter can power the product under test by preset current range, single-step DC current power-up time, and DC current value per step via a host computer. The output of each step DC current is a DC waveform. The power-up range, number of steps, single-step DC current power-up time, and DC current value per step can all be set. Additionally, a power switch driver is connected to the DC current source meter via an electrical channel board. The host computer's preset control commands for each step DC current switch provide instantaneous switching control for each powered probe in the multi-channel separation probe assembly. The high-speed power switch time and the number of switching cycles for the separation channels can be set. The effect is that the power-off time in the traditional pulse power-up mode can be utilized and allocated to adjacent chips in the same group for power-on, greatly improving testing efficiency. The power switch driver primarily uses a TTL trigger mechanism. The multi-channel separation probe assembly is located at the rear end of the power switch driver and the front end of the chip under test (DUT). The front end is connected to the power switch driver via an electrical channel board. Its main function is to work with the power switch driver to separate the DC current of each step into short-pulse DC currents to power the DUT, forming an equivalent pulse power-up under all preset steps. The number of separation channels and the switching state of each channel can be set according to the actual power-up conditions and the required pulse width and off-time of the actual pulse current. The multi-channel separation probe assembly can also be designed independently according to the structure of the DUT; for example, each probe can independently contact the power-up pads of the DUT. The more independent probe channels the multi-channel separation probe assembly has, the higher the testing efficiency. This is achieved through a customized pluggable probe card, which provides higher conduction efficiency and stability for board-type electrical transmission. The host computer mainly sets the test program algorithm, power-up specifications, and grading parameters.
[0034] As an optimized embodiment of the present invention, the power switch driver and the multi-channel discrete probe assembly decompose the step DC current into step pulse currents applied to the chip. The number of probe channels x1 in the multi-channel discrete probe assembly depends on the single step DC current power-on time T, the required pulse power-on duty cycle DC, and the required pulse width t, as shown in the formula: The switching frequency of the power switch driver's discrete channels is consistent with the number of probe channels. The acquisition delay t1 of the synchronous acquisition drive system's acquisition driver must not be less than 3% of the pulse width to ensure signal acquisition only after power-on stabilization. The acquisition duration t2 should be set according to the principle of t2 < t - t1 to ensure acquisition occurs within the power-on range. t2 can be set based on the product's heat generation; if reducing heat generation is the primary concern, then t2 should be as small as possible while maintaining power test stability.
[0035] This invention provides a testing system including a synchronous acquisition driver, a photoelectric testing unit, and the aforementioned power-on mechanism. The synchronous acquisition driver is used to issue instructions for acquiring signals, and the photoelectric testing unit is used to receive the acquisition signal instructions issued by the synchronous acquisition driver and acquire electrical and optical signals. In this embodiment, using the aforementioned power-on mechanism in the testing system can more efficiently apply pulse power to the chip under test. Combined with the synchronous acquisition driver and the photoelectric testing unit, the chip under test can be tested. The main function of the synchronous acquisition driver is to control the acquisition of data by the photoelectric power meter by setting the acquisition delay time and acquisition time. This testing system can be used for semiconductor laser testing, specifically for bar chip testing systems, COC testing systems with array test fixtures, or even TO testing systems with array test fixtures. In addition to the aforementioned components, this testing system may also include a loading / unloading mechanism and a monitoring mechanism. The loading / unloading mechanism is used to load and unload bar chips, COC fixtures, or TO fixtures, while the monitoring mechanism mainly performs product handling and performance demonstration. Furthermore, this embodiment can also be independently configured in other systems requiring pulse current testing according to actual needs.
[0036] As an optimized embodiment of the present invention, the synchronous acquisition driver is linked with the power switch driver, and the power switch driver operates first, while the synchronous acquisition driver operates with a delay. Preferably, the photoelectric testing unit includes an electrical signal acquisition source meter for reading the electrical signal of the chip under test and an optical signal acquisition source meter for reading the optical signal of the chip under test. The electrical signal acquisition source meter is connected to the probes of the multi-channel separation probe assembly, and the optical signal acquisition source meter is connected to the light receiving assembly. In this embodiment, when each step DC current is separated by the power switch driver to apply a short pulse width DC current to the chip, the synchronous acquisition driver delays and synchronously acquires the photoelectric performance of the chip to complete the photoelectric performance test. The operation of the synchronous acquisition driver is linked with the channel switching control of the power switch driver, and there is a very small delay response setting to ensure the accuracy and stability of the test results. The synchronous acquisition driver is connected to the power-on probe, and then connected to the electrical signal acquisition source meter to test the electrical performance of the chip; the synchronous acquisition driver is connected to the light receiving assembly, and then connected to the optical signal acquisition source meter to test the optical performance of the chip. The light-collecting component is paired with a large-area photodiode or an integrating sphere with an incident aperture diameter of 50mm or more to ensure the accuracy of optical power testing for each chip when multiple chips are simultaneously powered separately. The effective light-collecting diameter Φ of the light-collecting component is more than 1.5 times the distance L between the two chips simultaneously compatible with the multi-channel separation probe component.
[0037] The following are the specific implementation methods:
[0038] To achieve a current application range of 0 to 300 mA to the laser chip, with a DC current step of 1 mA, a pulse width of 200 µs (power-on delay of 20 µs, signal acquisition duration of 100 µs), and a duty cycle of 20%, the present invention can be designed to achieve this as follows:
[0039] (1) A multi-channel separation probe assembly with 5 sets of probes, with each probe contacting the corresponding chip's power pad;
[0040] (2) Set a DC current source meter power-on waveform in the host computer software with a power-on range of 0 to 300mA, a DC current value of 1mA per step, and a DC current power-on time of 1000us per step.
[0041] (3) In the host computer software, the control switching time period of the power switch driver is set to 200us, and the switching frequency of the separation channel is set to 5.
[0042] (4) In the host computer software, set the acquisition delay time of the acquisition driver of the synchronous acquisition drive system to 20us and the acquisition duration to 100us.
[0043] (5) On each step DC current, the power switch driver controls the power-on switch of the 5 corresponding chips. The sample chip 1 is controlled with "ON", "OFF", "OFF", "OFF", "OFF" for a period of 200us. The sample chip 2 is controlled with "OFF", "ON", "OFF", "OFF", "OFF" for a period of 200us. The sample chip 3 is controlled with "OFF", "OFF", "ON", "OFF", "OFF" for a period of 200us. The sample chip 4 is controlled with "OFF", "OFF", "OFF", "ON", "OFF" for a period of 200us. The sample chip 5 is controlled with "OFF", "OFF", "OFF", "OFF", "ON" for a period of 200us. This effect is to apply an equivalent pulse current with a pulse width of 200us and a duty cycle of 20% to each chip on a single step DC current. The four "OFF" states of sample chip 1 correspond to the "ON" states of sample chips 2, 3, 4 and 5 respectively.
[0044] (6) The synchronous acquisition system controls the electrical signal acquisition source meter connected to the probe to perform electrical performance testing according to the above parameters; and controls the optical signal acquisition source meter connected to the light receiving component to perform optical performance testing.
[0045] (7) Until all step DC current control power-up and photoelectric performance tests are completed.
[0046] This invention provides a testing method comprising the following steps: S1, using a DC current source meter to output several step DC currents; S2, using a power switch driver to perform instantaneous switching control on a multi-channel separation probe assembly according to a control command for switching on each of the step DC currents, wherein the multi-channel separation probe assembly receives the control command and sequentially outputs each of the step DC currents to different chips under test in a time sequence; S3, after the power switch driver completes its operation, using a synchronous acquisition driver to issue a signal acquisition command; S4, using a photoelectric testing unit to receive the signal acquisition command issued by the synchronous acquisition driver and acquire electrical and optical signals. In this embodiment, a host computer sets the output of a step-current (DC waveform) from the control source meter according to a program. The power switch driver controls the multi-channel discrete probe assembly to output each step-current to a different chip in sequence until all preset step-currents are fully powered on (the actual power-on effect for each chip is a pulse waveform). While the power switch driver controls the current to power on each chip for each step-current, it simultaneously collects data from the power meter controlled by the drive system to complete the photoelectric performance test (synchronous performance acquisition). Finally, for each chip, the actual power-on effect is a pulse current with the same ON / OFF mode formed by all preset current steps. The test result is the photoelectric performance test of a single chip under pulse current (independent pulse power-on waveform and synchronous acquisition test for each chip). Figure 2 and Figure 3 This demonstrates an example of the shunt effect of a power switch driver under single-step DC current.
[0047] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A power-up mechanism, characterized by: The power supply switch driver is used for instant switch control of the multi-channel separated probe assembly according to the control instruction of the switch on each step direct current. The direct current source table is used for outputting a plurality of step direct currents. The power supply switch driver is used for instant switch control of the multi-channel separated probe assembly according to the control instruction of the switch on each step direct current. The multi-channel separated probe assembly is used for sequentially outputting each step direct current to different chips to be tested in time sequence.
2. The power-up mechanism of claim 1, wherein: The direct current source table and the power supply switch driver are connected through an electric channel board card, and the multi-channel separated probe assembly and the power supply switch driver are also connected through an electric channel board card.
3. The power-up mechanism of claim 1, wherein: The multi-channel separated probe assembly is also used for separating each step direct current into short pulse width current to power on the chip to be tested.
4. The power-up mechanism of claim 1, wherein: The multi-channel separated probe assembly has a plurality of independent probe channels, and each independent probe channel independently contacts a power-on pad of the chip to be tested.
5. A test system, characterized by: The photoelectric test unit is used for receiving the instruction of the collection signal sent by the synchronous collection driver and collecting the electric signal and the optical signal.
6. The test system of claim 5, wherein: The synchronous collection driver is connected with the power supply switch driver in linkage, and the power supply switch driver is first actuated, and the synchronous collection driver is actuated with a time delay.
7. The test system of claim 5, wherein: The photoelectric test unit includes an electric signal collection source table used for reading the electric signal of the chip to be tested and an optical signal collection source table used for reading the optical signal of the chip to be tested.
8. The test system of claim 7, wherein: The electric signal collection source table is connected with the probe of the multi-channel separated probe assembly, and the optical signal collection source table is connected with a light receiving assembly.
9. A test method characterized by, The method comprises the following steps: S1, a direct current source table is used for outputting a plurality of step direct currents; S2, a power supply switch driver is used for instant switch control of the multi-channel separated probe assembly according to the control instruction of the switch on each step direct current, and the multi-channel separated probe assembly receives the control instruction and sequentially outputs each step direct current to different chips to be tested in time sequence; S3, after the power supply switch driver is actuated, a synchronous collection driver is used for giving an instruction of a collection signal; S4, a photoelectric test unit is used for receiving the instruction of the collection signal sent by the synchronous collection driver and collecting the electric signal and the optical signal.
10. The test method of claim 9, wherein: The multi-channel separated probe assembly simultaneously pricks the chips in the same group, and the power supply switch driver performs time domain switch control on the chips in the same group to synchronously distribute the time of the power-off state to the chips in the same group to perform the power-on state.