Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a plurality of terminals, a gate drive circuit unit, a control signal line and a first common voltage line, the plurality of terminals are arranged in a terminal area at intervals, the gate drive circuit unit is arranged in a non-display area, the control signal line is arranged in the non-display area, and the first common voltage line is arranged between the gate drive circuit unit and the control signal line. The first common voltage line is arranged in the non-display area, the first common voltage line is led into the terminal area, wiring is carried out through the space in the terminal area, and therefore the first common voltage line can avoid the control signal line, and the display effect is improved. The cross short circuit of the first common voltage line and the control signal line is avoided, so that a conductive layer does not need to be additionally arranged in the flexible circuit board for layered arrangement of the first common voltage line and the control signal line, and the production cost can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] TED (Timing Controller Embedded Driver) IC is a kind of high-integration chip architecture that embeds timing control chip, level shifter and other chips into display driving chip. TED IC has the advantages of high integration and low cost, and is gradually widely used in display devices.

[0003] Due to the embedded timing control chip and level shifter in TED IC, the control signal line needs to be led out from the TED IC, while the common voltage signal is generated by the power management chip on the circuit board and transmitted to the common electrode through the common voltage line inside the display panel. The common voltage line and the control signal line may be short-circuited. At present, the number of conductive layers in the flexible circuit board is usually increased to lead the control signal line in the display panel to the double-layer or multi-layer conductive structure of the flexible circuit board, and then the common voltage line is separated and wired, which can prevent the common voltage line and the control signal line from being short-circuited. However, increasing the number of conductive layers in the flexible circuit board will increase the production cost.

[0004] Therefore, it is necessary to provide a display panel and a display device to improve this defect. SUMMARY

[0005] The embodiments of the present application provide a display panel and a display device, which can reduce the production cost.

[0006] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, which has a display area, a first non-display area, a second non-display area (NA3) and a third non-display area (NA2), the second non-display area and the third non-display area are located on both sides of the display area in a first direction, the first non-display area is located on one side of the display area in a second direction, the first direction (X) is different from the second direction (Y) and both are perpendicular to the thickness direction of the display panel, the first non-display area includes a terminal area, and the display panel comprises:

[0007] a plurality of terminals arranged at intervals in the terminal area;

[0008] a gate drive circuit unit arranged in at least one of the second non-display area and the third non-display area;

[0009] a control signal line arranged in the first non-display area and electrically connected with the gate drive circuit unit and the corresponding terminal.

[0010] a first common voltage line, partially located in the first non-display area, and arranged around the display area;

[0011] wherein the first common voltage line passes through the terminal area and avoids the control signal line.

[0012] Optionally, a projection of the first common voltage line on a reference plane is separated from a projection of the control signal line on the reference plane, the reference plane being parallel to a light-out plane of the display panel.

[0013] Optionally, the first common voltage line and the control signal line are arranged in the same layer and are made of the same material.

[0014] Optionally, the first common voltage line extends from a first position of a first side of the terminal area into the terminal area, and is led out of the terminal area from a second position of the first side, the first side being a side of the terminal area close to the display area.

[0015] Optionally, the control signal line is led out of the terminal area from a third position of the first side;

[0016] wherein, in the first direction, the third position is located between the first position and the second position.

[0017] Optionally, a projection of the first common voltage line on a reference plane is arranged between projections of adjacent terminals on the reference plane, the reference plane being parallel to a light-out plane of the display panel.

[0018] Optionally, a line width of a portion of the first common voltage line located in the terminal area is less than or equal to a line width of a portion of the first common voltage line located outside the terminal area.

[0019] Optionally, a plurality of the terminals are arranged at intervals along the first direction, and the plurality of the terminals include a first terminal, the first terminal being electrically connected to the control signal line.

[0020] wherein the first common voltage line extends from a side of the first terminal in the first direction into the terminal area along the second direction, and is led out of the terminal area from another side of the first terminal in the first direction along a direction opposite to the second direction.

[0021] Optionally, the first common voltage line includes at least a first sub-portion, a second sub-portion and at least a third sub-portion located in the terminal area.

[0022] The first sub-portion is located on one side of the first terminal in the first direction, the third sub-portion is located on the other side of the first terminal in the first direction, and the second sub-portion is connected between the first sub-portion and the third sub-portion and located on the side of the first terminal close to the display area.

[0023] Optionally, the plurality of terminals include:

[0024] at least one second terminal disposed on one side of the first terminal in the first direction and adjacent to the first terminal; and

[0025] at least one third terminal disposed on the other side of the first terminal in the first direction and adjacent to the first terminal.

[0026] The first sub-portion is disposed between the second terminal and the first terminal, or the first sub-portion is disposed on the side of the second terminal away from the first terminal.

[0027] The third sub-portion is disposed between the third terminal and the first terminal, or the third sub-portion is disposed on the side of the third terminal away from the first terminal.

[0028] Optionally, the first terminal and the second terminal are virtual terminals.

[0029] Optionally, the first common voltage line includes at least two first sub-portions, the orthographic projection of each first sub-portion on a reference plane is disposed between the orthographic projections of two adjacent terminals on the reference plane, and the at least two first sub-portions are connected in parallel, the reference plane being parallel to the light exit surface of the display panel.

[0030] Optionally, the first common voltage line includes at least two third sub-portions, the orthographic projection of each third sub-portion on the reference plane is located between the orthographic projections of two adjacent terminals on the reference plane, and the at least two third sub-portions are connected in parallel.

[0031] Optionally, the first common voltage line further includes a fourth sub-portion and a fifth sub-portion located outside the terminal area, the fourth sub-portion is connected to the first sub-portion, and the fifth sub-portion is connected to the third sub-portion.

[0032] The line width of the fourth sub-portion is greater than the line widths of the first sub-portion, the second sub-portion, and the third sub-portion, and the line width of the fifth sub-portion is greater than the line widths of the first sub-portion, the second sub-portion, and the third sub-portion.

[0033] Optionally, a part of the normal projection of the first common voltage line on a reference plane is arranged between the normal projection of the gate drive circuit unit on the reference plane and the display area, and the reference plane is parallel to the light exit surface of the display panel.

[0034] According to a second aspect of the present application, a display device is provided, comprising:

[0035] a display panel as described above;

[0036] a driving chip arranged in the terminal area;

[0037] a flexible circuit board electrically connected to the display panel;

[0038] a power management chip electrically connected to the flexible circuit board, so as to provide a common voltage signal to the display panel through the flexible circuit board.

[0039] Optionally, the driving chip comprises:

[0040] a timing control module, configured to provide a control signal to the gate drive circuit unit through the control signal line; and

[0041] a display driving module, configured to provide a display signal to the display panel.

[0042] Optionally, the flexible circuit board is a single-layer conductive structure.

[0043] In the display panel of the embodiments of the present application, the first common voltage line is introduced into the terminal area, and the space in the terminal area is used for wiring, so that the first common voltage line avoids the control signal line and avoids short circuit caused by the intersection of the first common voltage line and the control signal line. Therefore, it is not necessary to add a conductive layer in the flexible circuit board for layering arrangement of the first common voltage line and the control signal line, so that the production cost can be reduced.

[0044] Other features and advantages of the present application will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0046] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0047] Figure 1 A top view of a display panel provided for an embodiment of the present application;

[0048] Figure 2 A partial enlarged view of a1 of the display panel shown in Figure 1

[0049] Figure 3 A partial enlarged view of another display panel provided for an embodiment of the present application;

[0050] Figure 4 A structural schematic view of a display device provided for an embodiment of the present application;

[0051] Figure 5 A schematic view of a driving chip in a display device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative effort fall within the protection scope of the present application.

[0053] The embodiments of the present application provide a display panel, which has a display area, a first non-display area, a second non-display area and a third non-display area, the second non-display area and the third non-display area are located on two sides of the display area in a first direction, the first non-display area is located on one side of the display area in a second direction, the first direction is different from the second direction and both are perpendicular to the thickness direction of the display panel, the first non-display area includes a terminal area, the display panel includes a plurality of terminals, a gate driving circuit unit, a control signal line and a first common voltage line, the plurality of terminals are arranged in the terminal area at intervals, the gate driving circuit unit is arranged in at least one of the second non-display area and the third non-display area, the control signal line is arranged in the first non-display area and electrically connected to the terminal corresponding to the gate driving circuit unit, and the first common voltage line is partially arranged in the first non-display area and arranged around the display area, the first common voltage line passes through the terminal area and avoids the control signal line.

[0054] In the embodiments of the present application, the first common voltage line is introduced into the terminal area to utilize the space in the terminal area for wiring, so that the first common voltage line can avoid the control signal line and avoid short circuit caused by the intersection of the first common voltage line and the control signal line, thus it is not necessary to additionally add a conductive layer in the flexible circuit board for layering arrangement of the first common voltage line and the control signal line, so that the production cost can be reduced.

[0055] Please refer to Figure 1 and Figure 2 ,​Figure 1 a top view of a display panel provided for an embodiment of the present application, Figure 2 a1 of the display panel shown in FIG. 1, Figure 1 An enlarged schematic view of a1 of the display panel shown in FIG. 1, the display panel 100 has a display area AA and a non-display area NA, the display area AA is an area for displaying a picture, the non-display area NA is arranged at the periphery of the display area AA and surrounds the display area AA, and the non-display area NA is an area for placing a gate drive circuit unit and a signal trace.

[0056] The non-display area NA includes a first non-display area NA1 located at one side of the display area AA in the second direction Y, which can be regarded as a lower frame area of the display panel, and the first non-display area NA1 can include a fan-out trace area (not shown in the figure) and a terminal area NA11, which is an area for binding with a driving chip.

[0057] The display panel 100 includes a plurality of terminals 1, a gate drive circuit unit 2, a control signal line 3 and a first common voltage line 4, the plurality of terminals 1 are arranged at intervals in the terminal area NA1, and the terminals 1 are used for binding with the driving chip.

[0058] The non-display area NA further includes a second non-display area NA2 and a third non-display area NA3 located at both sides of the display area AA in the first direction X, the gate drive circuit unit 2 is arranged in at least one of the second non-display area NA2 and the third non-display area NA3, the control signal line 3 is arranged in the first non-display area NA1 and electrically connected with the gate drive circuit unit 2 and the corresponding terminal 1, and the driving chip can provide a control signal to the gate drive circuit unit 2 through the control signal line 3.

[0059] As shown in FIG. 1 and FIG. 2, the first common voltage line 4 is partially located in the first non-display area NA1 and arranged around the display area AA, and the first common voltage line 4 passes through the terminal area NA11 and avoids the control signal line 3. Figure 1 and Figure 2 By introducing the first common voltage line into the terminal area, the space in the terminal area is used for wiring to make the first common voltage line avoid the control signal line, so as to avoid the first common voltage line and the control signal line from crossing and short-circuiting, and thus it is not necessary to add a conductive layer in the flexible circuit board for layering arrangement of the first common voltage line and the control signal line, thereby reducing the production cost.

[0060] It should be noted that if the control signal lines in the display panel are led out to the flexible circuit board with double or multi-layer conductive structure through increasing the number of conductive layers in the flexible circuit board, and then introduced into the display panel to prevent the common voltage lines and the control signal lines from crossing and short-circuiting, not only the production cost of the display panel will be increased, but also the thickness of the flexible circuit board will be increased, which will increase the bending stress of the flexible circuit board after bending, and even cause the flexible circuit board to break down and fail, and finally cause the problem of display abnormality. In addition, the flexible circuit board with large thickness will also have the problem of twisted abnormal sound under long-term bending.

[0061] In the embodiments of the present application, the first common voltage line is introduced into the terminal area to utilize the space in the terminal area for wiring, so that the first common voltage line avoids the control signal lines and avoids crossing and short-circuiting with the control signal lines. Therefore, it is not necessary to add conductive layers in the flexible circuit board for layered arrangement of the first common voltage line and the control signal lines. Not only the number of conductive layers in the flexible circuit board can be reduced to reduce the production cost, but also the thickness of the flexible circuit board can be reduced to reduce the bending stress of the flexible circuit board after bending, and the risk of breakage and failure of the flexible circuit board can be reduced, so that the problem of display abnormality can be avoided. In addition, the risk of twisted abnormal sound of the flexible circuit board under long-term bending can also be reduced.

[0062] In some embodiments, the orthogonal projection of the first common voltage line 4 on the reference plane is separated from the orthogonal projection of the control signal line 3 on the reference plane, and the reference plane is parallel to the light exit surface of the display panel.

[0063] In combination with FIGS. 1-3, Figure 1 and Figure 2 As shown in FIG. 4, the orthogonal projection of the first common voltage line 4 on the reference plane is separated from the orthogonal projection of the control signal line 3 on the reference plane, and there is no intersecting part between the two. In this way, the first common voltage line 4 and the control signal line 3 can be prevented from crossing and short-circuiting.

[0064] In some embodiments, the first common voltage line 4 is arranged in the same layer as the control signal line 3 and is made of the same material, and the first common voltage line 4 and the control signal line 3 can be prepared by the same metal film forming process. By introducing the first common voltage line into the terminal area, the space in the terminal area is used for wiring to avoid the first common voltage line from crossing the control signal line in the same layer, thereby avoiding short circuit between the first common voltage line and the control signal line in the same layer. Therefore, it is not necessary to add a conductive layer in the flexible circuit board for arranging the first common voltage line and the control signal line in different layers. This can not only reduce the number of conductive layers in the flexible circuit board, thereby reducing the production cost, but also reduce the thickness of the flexible circuit board, thereby reducing the bending stress of the flexible circuit board after bending and reducing the risk of fracture failure of the flexible circuit board, so that the problem of display abnormality can be avoided.

[0065] In some embodiments, the first common voltage line 4 extends from the first position P1 on the first side S1 of the terminal area NA11 into the terminal area NA11, and is led out of the terminal area NA11 from the second position P2 on the same side of the terminal area NA11. The first side S1 of the terminal area NA11 is the side of the terminal area NA11 away from the display area AA.

[0066] As Figure 2 described, the first position P1 and the second position P2 are located on the side of the terminal area NA11 away from the display area AA, and the first position P1 and the second position P2 are arranged at intervals along the first direction X. By extending the first common voltage line 4 from the first position P1 into the terminal area NA11 and leading the first common voltage line 4 out of the terminal area NA11 from the second position P2 on the first side S1 of the terminal area NA11, the first common voltage line 4 can be prevented from crossing other wires in the terminal area NA11, on the opposite sides of the terminal area NA11 in the first direction X, and on the other side of the terminal area NA11 in the second direction Y.

[0067] In the embodiments of the present application, the first direction X and the second direction Y are different and both perpendicular to the thickness direction of the display panel. The first direction X can be regarded as a direction parallel to the upper and lower side edges of the display panel, and the second direction Y can be regarded as a direction parallel to the left and right side edges of the display panel.

[0068] In some embodiments, the control signal line 3 is led out of the terminal area NA11 from the third position P3 on the first side S1 of the terminal area NA11. In the first direction X, the third position P3 is located between the first position P1 and the second position P2.

[0069] As Figure 2As shown, the first position P1, the second position P2 and the third position P3 are located on the side of the terminal area NA11 away from the display area AA, the first position P1, the third position P3 and the second position P2 are sequentially and spaced apart along the first direction X, and the control signal line 3 is led out from the third position P3 on the side of the terminal area NA11 away from the display area AA. In this way, the control signal line 3 can be prevented from being short-circuited with the first common voltage line 4.

[0070] In some embodiments, a part of the first common voltage line 4 in the reference plane is located between the projections of the adjacent terminals 1 in the reference plane.

[0071] In combination with Figure 1 and Figure 2 As shown, the terminal area NA1 is provided with a plurality of terminals 1, the plurality of terminals 1 are spaced apart along the first direction X, the first common voltage line 4 extends into the terminal area NA1 through the gap between the adjacent two terminals 1 at the first position P1, and is led out from the terminal area NA11 through the gap between the other adjacent two terminals 1 at the second position P2. By using the gap between the adjacent terminals 1 in the terminal area NA11 for wiring, the width of the first non-display area NA1 can be prevented from being increased, and the first common voltage line 4 can be prevented from being short-circuited with the control signal line 3, the terminals in the terminal area NA11 and the pins of the driving chip.

[0072] In some embodiments, as shown in Figure 2 The line width of the part of the first common voltage line 4 located in the terminal area NA11 is equal to the line width of the part of the first common voltage line 4 located outside the terminal area NA11.

[0073] In some embodiments, the line width of the part of the first common voltage line 4 located in the terminal area NA11 is smaller than the line width of the part of the first common voltage line 4 located outside the terminal area NA11. By reducing the line width of the first common voltage line 4 in the terminal area NA11, the risk of short-circuiting between the first common voltage line 4 and the terminals 1 and the cathode of the driving chip can be further reduced.

[0074] In some embodiments, in combination with Figure 2 As shown, the plurality of terminals 1 includes a first terminal 11, the first terminal 11 is an output terminal, one end of the control signal line 3 is connected with the first terminal 11, the other end of the control signal line 3 is led out from the third position P3 on the side of the terminal area NA11 away from the display area AA in the direction opposite to the second direction Y, and extends to the corresponding gate drive circuit unit to transmit the control signal output by the driving chip to the corresponding gate drive circuit unit 2.

[0075] As shown in Figure 2As shown, the first common voltage line 4 extends from the first terminal 11 along the second direction Y to the terminal area NA11 on one side of the first direction X, and is led out from the terminal area NA11 along the opposite direction of the second direction Y from the first terminal 11 on the other side of the first direction X. The first terminal 11 is located between the portion of the first common voltage line 4 introduced from the terminal area NA11 and the portion led out from the terminal area NA11. This facilitates the control signal line 3 to be led out from the third position P3 on the side of the terminal area NA11 away from the display area AA along the opposite direction of the second direction Y, and extended to connect with the corresponding gate drive circuit unit, so as to transmit the control signal output by the drive chip to the corresponding gate drive circuit unit 2, thereby avoiding the control signal line 3 and the first common voltage line 4 from crossing and short-circuiting.

[0076] In some embodiments, the first common voltage line 4 includes at least one first sub-part 41, a second sub-part 42, and at least one third sub-part 43 located in the terminal area NA11. The first sub-part 41 is located on one side of the first terminal 11 in the first direction X, the third sub-part 43 is located on the other side of the first terminal 11 in the first direction X, and the second sub-part 42 is connected between the first sub-part 41 and the third sub-part 43 and is located on the side of the first terminal 11 near the display area AA.

[0077] In some embodiments, such as Figure 2 As shown, the first common voltage line 4 includes a first sub-section 41, a second sub-section 42, and a third sub-section 43. The orthographic projection of the first sub-section 41 on the reference plane is located on one side of the orthographic projection of the first terminal 11 on the reference plane in the first direction X, and is located between the orthographic projections of the first terminal 11 and the adjacent terminal 1 on the reference plane. The orthographic projection of the third sub-section 43 on the reference plane is located on the other side of the orthographic projection of the first terminal 11 on the reference plane in the first direction X, and is located between the orthographic projections of the first terminal 11 and the adjacent terminal 1 on the reference plane. The second sub-section 42 connects the first sub-section 41 and the third sub-section 43, and is located on the side of the orthographic projection of the first terminal 11 on the reference plane closer to the display area AA.

[0078] In some embodiments, such as Figure 2 As shown, the plurality of terminals 1 also includes at least one second terminal 12, which is disposed on one side of the first terminal 11 in the first direction X and adjacent to the first terminal 11. The first sub-part 41 is disposed on the side of the second terminal 12 away from the first terminal 11, so that the first sub-part 41 can be moved away from the first terminal 11 to reduce the risk of short circuit between the first sub-part 41 and the first terminal 11.

[0079] In some embodiments, such as Figure 2As shown, the plurality of terminals 11 can include 2 or more second terminals 12, which are arranged at intervals on one side of the first terminal 11, and the orthographic projection of the first sub-portion 41 on the reference plane can be arranged between the orthographic projections of the two adjacent second terminals 12 on the one side of the first terminal 11 on the reference plane.

[0080] In some embodiments, as shown, Figure 2 As shown, the plurality of terminals 1 further includes at least one third terminal 13, which is arranged on the other side of the first terminal 11 in the first direction X and adjacent to the first terminal 11, and the third sub-portion 43 is arranged on the side of the third terminal 13 away from the first terminal 11, so that the third sub-portion 43 is away from the first terminal 11, thereby reducing the risk of short circuit between the third sub-portion 43 and the first terminal 11.

[0081] In some embodiments, as shown, Figure 2 As shown, the plurality of terminals 1 can include 2 or more third terminals 13, which are arranged at intervals on the other side of the first terminal 11, and the third sub-portion 43 can be arranged between the two adjacent third terminals 13 on the other side of the first terminal 11.

[0082] In some embodiments, as shown, Figure 2 As shown, the second terminal 12 and the third terminal 13 can be virtual terminals, which can not be connected with the signal lines, and can not only serve to fix the pins of the driving chip, but also serve to isolate the first common voltage line 4 from the first terminal 11 and the control signal line 3, so that even if the first common voltage line 4 is overlapped with the second terminal 12 or the third terminal 13, no short circuit will occur, thereby further reducing the risk of short circuit between the first common voltage line 4 and the first terminal 11 or the control signal line 3.

[0083] In other embodiments, the orthographic projection of the first sub-portion 41 on the reference plane can be arranged between the orthographic projections of the second terminal 12 and the first terminal 11 on the reference plane, and the orthographic projection of the third sub-portion 43 on the reference plane can be arranged between the orthographic projections of the third terminal 13 and the first terminal 11 on the reference plane, so that the same effect of avoiding the first common voltage line 4 and the control signal line 3 from being short-circuited can also be achieved.

[0084] In some embodiments, as shown, Figure 2 As shown, the first common voltage line 4 includes a fourth sub-portion 44 and a fifth sub-portion 45 outside the terminal area NA11, the fourth sub-portion 44 is connected to the first sub-portion 41, the fifth sub-portion 45 is connected to the third sub-portion 43, and the fifth sub-portion 45 further extends to be connected with the gate driving circuit unit 2.

[0085] In some embodiments, asFigure 2 As shown, the line width of the fourth sub-part 44 is equal to that of the fifth sub-part 45, the first sub-part 41, the second sub-part 42, and the third sub-part 43.

[0086] In some embodiments, the line width of the fourth sub-part 44 is greater than the line widths of the first sub-part 41, the second sub-part 42, and the third sub-part 43, and the line width of the fifth sub-part 45 is greater than the line widths of the first sub-part 41, the second sub-part 42, and the third sub-part 43. By reducing the line widths of the first sub-part 41, the second sub-part 42, and the third sub-part 43 located within the terminal area NA11, the risk of short circuit between the first common voltage line 4 within the terminal area NA11 and the terminals within the terminal area NA11 can be further reduced.

[0087] In some embodiments, the non-display area NA includes a second non-display area NA2 and a third non-display area NA3 located on both sides of the display area AA. At least one of the second non-display area NA2 and the third non-display area NA3 of the gate drive circuit unit 2 is provided with a gate drive circuit unit 2. The gate drive circuit unit 2 may include multiple cascaded gate drive circuits. The control signal line 3 is electrically connected to the gate drive circuit unit 2 to transmit the timing control signal output by the drive chip to the gate drive single-channel unit 21. The first common voltage line 4 is partially disposed between the gate drive circuit unit 2 and the display area AA.

[0088] In some embodiments, combined with Figure 1 As shown, the array substrate includes two gate driving circuit units 2, which are respectively disposed in the second non-display area NA2 and the third non-display area NA3.

[0089] In some embodiments, such as Figure 1 As shown, the non-display area NA also includes a fourth non-display area NA4, which is located on the opposite side of the display area AA from the first non-display area NA1. The first common voltage line 4 passes sequentially from the first non-display area NA1 through the second non-display area NA2, the fourth non-display area NA4, and the third non-display area NA3, and then loops back to the first non-display area NA1 to partially surround the display area AA. A portion of the first common voltage line 4 is located between one of the gate driving circuit units 2 and the display area AA, and another portion is located between the other gate driving circuit unit 2 and the display area AA.

[0090] In some embodiments, the display panel 100 includes a common electrode located in the display area AA and the non-display area NA. A first common voltage line 4 may partially surround the common electrode and be electrically connected to the common electrode at multiple locations to reduce the potential difference of the common electrode in each area, thereby improving the uniformity of the brightness of the display panel.

[0091] In some embodiments, the display panel 100 further includes a second common voltage line 5. The second common voltage line 5 originates from the first non-display area NA1, passes sequentially through the second non-display area NA2, the fourth non-display area NA4, and the third non-display area NA3, and loops back to the first non-display area NA1 to partially surround the display area AA. A portion of the second common voltage line 5 is disposed on the side of one gate driving circuit unit 2 away from the display area AA, and a portion of the second common voltage line 5 is disposed on the side of another gate driving circuit unit 2 away from the display area AA. The potential of the second common voltage line 5 is the same as the potential of the first common voltage line 4. The second common voltage line 5 can be connected in parallel with the first common voltage line 4 and electrically connected to a common electrode at multiple points to further reduce the potential difference of the common electrode in each area, thereby further improving the uniformity of the brightness of the display panel.

[0092] Combination Figure 3 As shown, Figure 3 A partially enlarged schematic diagram of another display panel provided for an embodiment of this application, the structure of which is similar to... Figure 2 The structures of the display panels shown are roughly the same, with the following differences: the first common voltage line 4 includes at least two first sub-sections 41, the orthographic projection of each first sub-section 41 on the reference plane is disposed between the orthographic projections of two adjacent terminals 1 on the reference plane, and the at least two first sub-sections 41 are connected in parallel; and / or, the first common voltage line 4 includes at least two third sub-sections 43, the orthographic projection of each third sub-section 43 on the reference plane is disposed between the orthographic projections of two adjacent terminals 1 on the reference plane, and the at least two third sub-sections 43 are connected in parallel.

[0093] In some embodiments, such as Figure 3 As shown, the first common voltage line 4 includes three first sub-sections 41, which are spaced apart along a first direction X. The plurality of terminals 1 include a plurality of second terminals 12. The orthographic projection of one first sub-section 41 onto the reference plane is positioned between the orthographic projections of the second terminal 12 and the first terminal 11 onto the reference plane. The orthographic projections of the other two first sub-sections 41 are respectively positioned between the orthographic projections of two adjacent second terminals 12 onto the reference plane. The three first sub-sections 41 are connected in parallel. The first sub-sections 41 are connected to a fourth sub-section 44, and the line width of the first sub-section 41 is smaller than the line width of the fourth sub-section 44. By reducing the line width of the first sub-section 41, the risk of short circuit between the first sub-section 41 and the terminals in the terminal area NA11 can be reduced. By increasing the number of first sub-sections 41 and connecting multiple first sub-sections 41 in parallel, the impedance of the first common voltage line 4 can be reduced.

[0094] In practical applications, the number of first sub-parts 41 in the first common voltage line 4 is not limited to the three in the above embodiment. The first common voltage line 4 may also have two, three, four or more first sub-parts 41. In this way, the impedance of the first common voltage line 4 can be reduced, and the risk of short circuit between the first common voltage line 4 and the terminals in the terminal area NA11 can also be reduced.

[0095] In some embodiments, such as Figure 3 As shown, the first common voltage line 4 includes three third sub-sections 43, which are spaced apart along the first direction X. The plurality of terminals 1 include a plurality of third terminals 13. The orthographic projection of one third sub-section 43 on the reference plane is positioned between the orthographic projections of the third terminal 13 and the first terminal 11 on the reference plane. The orthographic projections of the other two third sub-sections 43 are respectively positioned between the orthographic projections of two adjacent third terminals 13 on the reference plane. The three third sub-sections 43 are connected in parallel. The third sub-sections 43 are connected to the fifth sub-section 45, and the line width of the third sub-section 43 is smaller than the line width of the fifth sub-section 45. By reducing the line width of the third sub-section 43, the risk of short circuit between the third sub-section 43 and the terminals in the terminal area NA11 can be reduced. By increasing the number of third sub-sections 43 and connecting multiple third sub-sections 43 in parallel, the impedance of the first common voltage line 4 can be further reduced.

[0096] In practical applications, the number of third sub-parts 43 in the first common voltage line 4 is not limited to the three in the above embodiment. The first common voltage line 4 may also have two, three, four or more third sub-parts 43. In this way, the impedance of the first common voltage line 4 can be reduced, and the risk of short circuit between the first common voltage line 4 and the terminals in the terminal area NA11 can also be reduced.

[0097] In some embodiments, such as Figure 3 As shown, the second terminal 12 and the third terminal 13 can be virtual terminals, meaning they can be unconnected to signal lines. During the display phase, the second terminal 12 and the third terminal 13 are in a floating state. The second terminal 12 and the third terminal 13 not only serve to fix the pins of the driver chip but also isolate the first common voltage line 4 from the first terminal 11 and the control signal line 3. Even if the first common voltage line 4 surrounds the second terminal 12 and the third terminal 13, or even connects to either the second terminal 12 or the third terminal 13, a short circuit will not occur, thus further reducing the risk of a short circuit between the first common voltage line 4 and the first terminal 11 or the control signal line 3.

[0098] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to [link to relevant documentation]. Figure 4 , Figure 4This is a schematic diagram of the structure of a display device provided in an embodiment of this application. The display device 1000 includes a display panel 100, which can be any of the display panels 100 provided in the above embodiments. The display device 1000 provided in the embodiments of this application can achieve the same technical effects as the display panel 100 provided in the above embodiments, and will not be described in detail here.

[0099] like Figure 4 As shown, the display device 1000 also includes a driver chip 200, a flexible circuit board 300, and a power management chip 400. The driver chip 200 is disposed in the terminal area NA11 and is bound to terminal 1 of the terminal area NA11. The flexible circuit board 300 is electrically connected to the display panel 100, and the power management chip 400 is electrically connected to the flexible circuit board 300 to provide a common voltage signal to the display panel 100 through the flexible circuit board 300.

[0100] In some embodiments, such as Figure 5 As shown, Figure 5 This is a schematic diagram of a driver chip in a display device provided in an embodiment of this application. The driver chip 200 is a timing controller embedded in a display driver chip. The driver chip 200 includes a timing control module 210 and a display driver module 220. The timing control module 210 is used to provide control signals to the gate drive circuit unit 2 through the control signal line 3. The control signals may include timing control signals. The display driver module 220 is used to provide display signals to the display panel 100. The display signals may include data signals.

[0101] In some embodiments, such as Figure 5 As shown, the driver chip 200 may also include a level shifting module 230, which is used to provide a level shifting control signal to the gate drive circuit unit 2.

[0102] In some embodiments, such as Figure 5 As shown, the flexible circuit board 300 has a single-layer conductive structure. In this embodiment, by introducing the first common voltage line into the terminal area, the space within the terminal area is utilized for routing. This allows the first common voltage line to avoid the control signal line, preventing short circuits caused by crossover between the first common voltage line and the control signal line. Therefore, there is no need to add a conductive layer to the flexible circuit board for layered arrangement of the first common voltage line and control signal line; a single-layer conductive flexible circuit board is sufficient to meet signal transmission requirements. This not only reduces production costs but also lowers the risk of flexible circuit board breakage and failure, avoiding display abnormalities. Furthermore, it reduces the risk of twisting and abnormal noise from the flexible circuit board under long-term bending.

[0103] In some embodiments, the display device 1000 further includes a printed circuit board 500, a flexible circuit board 300 connected between the display panel 100 and the printed circuit board 500, and a power management chip 400 bonded to the printed circuit board 500.

[0104] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a display device. The display panel includes multiple terminals, a gate driving circuit unit, a control signal line, and a first common voltage line. The multiple terminals are arranged at intervals in the terminal area. The gate driving circuit unit is disposed in the non-display area. The control signal line is disposed in the first non-display area and is electrically connected to the terminal corresponding to the gate driving circuit unit. The first common voltage line is partially located in the first non-display area and is disposed around the display area. By introducing the first common voltage line into the terminal area, the space in the terminal area is used for wiring. In this way, the first common voltage line can avoid the control signal line and avoid the first common voltage line and the control signal line crossing and short-circuiting. Therefore, it is not necessary to add a conductive layer in the flexible circuit board for layered arrangement of the first common voltage line and the control signal line, thereby reducing production costs.

[0105] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0106] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0107] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0108] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area, a first non-display area, a second non-display area, and a third non-display area. The second and third non-display areas are located on opposite sides of the display area in a first direction, and the first non-display area is located on one side of the display area in a second direction. The first direction and the second direction are opposite and both are perpendicular to the thickness direction of the display panel. The first non-display area includes a terminal area. The display panel includes: Multiple terminals are arranged at intervals in the terminal area; A gate driving circuit unit is disposed in at least one of the second non-display area and the third non-display area; A control signal line is provided in the first non-display area and is electrically connected to the gate drive circuit unit and the corresponding terminal. A first common voltage line is partially located in the first non-display area and is arranged around the display area; The first common voltage line passes through the terminal area and avoids the control signal line.

2. The display panel as described in claim 1, characterized in that, The orthographic projection of the first common voltage line on the reference plane is separate from the orthographic projection of the control signal line on the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

3. The display panel as described in claim 1, characterized in that, The first common voltage line and the control signal line are arranged in the same layer and are made of the same material.

4. The display panel as described in claim 1, characterized in that, The first common voltage line extends from a first position on a first side of the terminal area into the terminal area, and is led out from a second position on the first side of the terminal area, the first side being the side of the terminal area closest to the display area.

5. The display panel as described in claim 4, characterized in that, The control signal line is led out from the terminal area from the third position on the first side; In the first direction, the third position is located between the first position and the second position.

6. The display panel as described in claim 1, characterized in that, The orthographic projection of the first common voltage line onto the reference plane is disposed between the orthographic projections of the adjacent terminals onto the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

7. The display panel as described in claim 1, characterized in that, The line width of the portion of the first common voltage line located within the terminal area is less than or equal to the line width of the portion of the first common voltage line located outside the terminal area.

8. The display panel as claimed in any one of claims 1 to 7, characterized in that, The plurality of terminals are arranged at intervals along the first direction, and the plurality of terminals include a first terminal, which is electrically connected to the control signal line; The first common voltage line extends from the first terminal on one side of the first direction into the terminal area along the second direction, and is led out from the terminal area from the first terminal on the other side of the first direction in a direction opposite to the second direction.

9. The display panel as described in claim 8, characterized in that, The first common voltage line includes at least one first sub-section, a second sub-section, and at least one third sub-section located in the terminal area; The first sub-part is located on one side of the first terminal in the first direction, the third sub-part is located on the other side of the first terminal in the first direction, and the second sub-part is connected between the first sub-part and the third sub-part, and is located on the side of the first terminal closer to the display area.

10. The display panel as claimed in claim 9, characterized in that, The plurality of terminals include: At least one second terminal is disposed on one side of the first terminal in the first direction and is adjacent to the first terminal; and At least one third terminal is disposed on the other side of the first terminal in the first direction and is adjacent to the first terminal; Wherein, the first sub-part is disposed between the second terminal and the first terminal, or the first sub-part is disposed on the side of the second terminal away from the first terminal; The third sub-part is disposed between the third terminal and the first terminal, or the third sub-part is disposed on the side of the third terminal away from the first terminal.

11. The display panel as claimed in claim 10, characterized in that, The first terminal and the second terminal are virtual terminals.

12. The display panel as claimed in claim 9, characterized in that, The first common voltage line includes at least two first sub-sections, and the orthographic projection of each first sub-section on the reference plane is located between the orthographic projections of two adjacent terminals on the reference plane. The at least two first sub-sections are connected in parallel, and the reference plane is parallel to the light-emitting surface of the display panel. And / or, the first common voltage line includes at least two of the third sub-sections, each of the third sub-sections having its orthographic projection on the reference plane located between the orthographic projections of two adjacent terminals on the reference plane, and the at least two third sub-sections being connected in parallel.

13. The display panel as claimed in claim 10, characterized in that, The first common voltage line also includes a fourth sub-section and a fifth sub-section located outside the terminal area, wherein the fourth sub-section is connected to the first sub-section and the fifth sub-section is connected to the third sub-section; The line width of the fourth sub-part is greater than that of the first sub-part, the second sub-part, and the third sub-part, and the line width of the fifth sub-part is greater than that of the first sub-part, the second sub-part, and the third sub-part.

14. The display panel as claimed in any one of claims 1 to 7, characterized in that, The orthographic projection of the first common voltage line onto the reference plane is disposed between the orthographic projection of the gate driving circuit unit onto the reference plane and the display area, wherein the reference plane is parallel to the light-emitting surface of the display panel.

15. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 14; The driver chip is located in the terminal area; The flexible circuit board is electrically connected to the display panel; A power management chip is electrically connected to the flexible circuit board to provide a common voltage signal to the display panel through the flexible circuit board.

16. The display device as claimed in claim 15, characterized in that, The driver chip includes: A timing control module is configured to provide control signals to the gate drive circuit unit via the control signal line; and The display driver module is used to provide display signals to the display panel.

17. The display device as claimed in claim 15, characterized in that, The flexible circuit board has a single-layer conductive structure.

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