Display device

Abstract

A display device comprises an array substrate and a driving circuit assembly. The array substrate is provided with a display area and a joint area which are adjacent to each other, the display area is provided with a transparent display area and a non-transparent display area which are adjacent to each other, and the non-transparent display area is provided with a first area which is not overlapped with the transparent display area and a second area which is overlapped with the transparent display area. The array substrate comprises a first data line and a second data line which are respectively arranged in the first area and the second area, a connecting line which extends from the first area to the second area and is electrically connected with the first data line and the second data line, and a multiplexer which is arranged in the bonding area and is electrically connected with the first data line, and the driving circuit assembly is electrically connected with the multiplexer in the bonding area. A first data signal is provided to the first data lines through the multiplexer, and a second data signal is provided to the second data lines through the multiplexer, the first data lines and the connecting lines.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, and in particular, to a display device having a transparent display region and a non-transparent display region. BACKGROUND

[0002] With the popularity of full screen and the pursuit of one-piece body of consumer electronics, screen-under sensing technology has become the focus of development of small and medium-sized display devices. Since general display media, such as liquid crystal cells or organic light-emitting diodes, need to be matched with backlight or pixel circuit, it is not easy to achieve a transparent display region that can overlap with an optical sensing component (such as a lens).

[0003] However, if the entire display device uses display media that can achieve a transparent display region overlapping with an optical sensing component, such as micro-LED (μLED), the production cost is too high. Therefore, developing a display device using transparent display regions and non-transparent display regions of different display media, and the layout of the circuit of the non-transparent display region does not affect the light transmittance of the transparent display region, is one of the goals to be achieved in this technical field. SUMMARY

[0004] The present application provides a display device having a transparent display region and a non-transparent display region, and the layout of the circuit of the non-transparent display region does not affect the light transmittance of the transparent display region.

[0005] The display device provided by at least one embodiment of the present application includes an array substrate and a driving circuit component. The array substrate has a display region and a peripheral region adjacent to the display region, the display region has a transparent display region and a non-transparent display region adjacent to the transparent display region, and the peripheral region has a bonding region and an opposite region opposite to the bonding region in a first direction, the non-transparent display region has a first region not overlapping with the transparent display region in the first direction and a second region overlapping with the transparent display region, and the array substrate includes a plurality of first data lines, a plurality of second data lines, a plurality of first connection lines, and a plurality of first taskers. The first data lines are disposed in the first region, and the second data lines are disposed in the second region. The first connection lines extend from the first region to the second region, and each first connection line electrically connects one of the first data lines and one of the second data lines. The first taskers are disposed in the bonding region and are respectively electrically connected to the first data lines. The driving circuit component is electrically connected to the first taskers in the bonding region, respectively provides first data signals to the first data lines through the first taskers, and respectively provides second data signals to the second data lines through the first taskers, the first data lines, and the first connection lines.

[0006] In at least one embodiment of the present invention, the array substrate further includes a plurality of pixels, scan lines, and auxiliary scan lines. These pixels are disposed in the display area and arranged in a plurality of pixel rows and a plurality of pixel columns, and these pixel columns include a first pixel column. Scan lines are disposed in the display area, and a first pixel of the first pixel column is electrically connected to one of the plurality of first data lines. The scan line is activated during a first period to allow the first pixel to receive an output data signal generated by the first pixel receiving a first data signal provided by the driving circuit component to one of the plurality of first data lines via one of the plurality of first multiplexers. Auxiliary scan lines are disposed in the display area, and a second pixel of the first pixel column is electrically connected to one of the plurality of second data lines. The auxiliary scan line is activated during a second period to allow the second pixel to receive an output data signal generated by the second pixel receiving a second data signal provided by the driving circuit component to one of the plurality of second data lines via one of the plurality of first multiplexers, one of the plurality of first data lines, and one of the plurality of first connection lines.

[0007] In at least one embodiment of the present invention, one of the plurality of first multiplexers includes a first switching component and a second switching component. The first switching component is turned on during a first period to cause the first pixel to receive an output data signal generated by the first data signal provided by the driving circuit component to one of the plurality of first data lines via the first switching component. The second switching component is turned on during a second period to cause the second pixel to receive an output data signal generated by the driving circuit component via the second switching component, one of the plurality of first data lines, and one of the plurality of first connection lines to one of the plurality of second data lines.

[0008] In at least one embodiment of the present invention, the array substrate further includes a plurality of pixels. These pixels are disposed in the display area, and each of the first connecting lines extends along a second direction different from the first direction, and in the second direction, each of the first connecting lines spans the same number of pixels.

[0009] In at least one embodiment of the present application, the array substrate further comprises a plurality of third data lines, a plurality of fourth data lines, a plurality of second connection lines and a plurality of second multi-taskers. The third data lines are disposed in the second area, and the fourth data lines are disposed in the second area. Each second connection line electrically connects one of the third data lines and one of the fourth data lines. The second multi-taskers are disposed in the bonding area and are electrically connected to the third data lines, respectively. The driving circuit component is electrically connected to the second multi-taskers in the bonding area, provides third data signals to the third data lines through the second multi-taskers, respectively, and provides fourth data signals to the fourth data lines through the second multi-taskers, the third data lines and the second connection lines, respectively.

[0010] In at least one embodiment of the present application, the array substrate further comprises a plurality of pixels. The pixels are disposed in the display area, each of the first connection lines and each of the second connection lines extends along a second direction different from the first direction, and in the second direction, the number of pixels crossed by each of the first connection lines is the same as the number of pixels crossed by each of the second connection lines.

[0011] In at least one embodiment of the present application, the array substrate further comprises a plurality of pixels, a first scan line and a second scan line. The pixels are disposed in the display area and are arranged into a plurality of pixel rows and a plurality of pixel columns, and the pixel rows include a first pixel row located in the first area and a second pixel row located in the second area. The first scan line is disposed in the display area, a first pixel of the first pixel row is electrically connected to one of the first data lines, and the first scan line is turned on in a first period to enable the first pixel to receive an output data signal generated by the first data signal provided by the driving circuit component to the one of the first data lines through one of the first multi-taskers. The second scan line is disposed in the display area, a second pixel of the second pixel row is electrically connected to one of the second data lines, and the second scan line is turned on in a second period to enable the second pixel to receive an output data signal generated by the second data signal provided by the driving circuit component to the one of the second data lines through the one of the first multi-taskers, the one of the first data lines and one of the first connection lines.

[0012] In at least one embodiment of the present application, the array substrate further comprises a plurality of first auxiliary data lines, a plurality of second auxiliary data lines, a plurality of auxiliary connection lines and a plurality of auxiliary taskers. The first auxiliary data lines are disposed in the first area, the second auxiliary data lines are disposed in the second area. The auxiliary connection lines extend from the first area to the second area, each auxiliary connection line electrically connects one of the first auxiliary data lines and one of the second auxiliary data lines. The auxiliary taskers are disposed in the bonding area and are electrically connected to the first auxiliary data lines, respectively. The driving circuit components are electrically connected to the auxiliary taskers in the bonding area, respectively, to provide first auxiliary data signals to the first auxiliary data lines via the auxiliary taskers, respectively, and to provide second auxiliary data signals to the second auxiliary data lines via the auxiliary taskers, the first auxiliary data lines and the auxiliary connection lines, respectively.

[0013] In at least one embodiment of the present application, a third pixel of the first pixel row is electrically connected to one of the first auxiliary data lines, and the second scan line is turned on during the second period to make the third pixel receive an output data signal generated by the first auxiliary data signal provided by the driving circuit components to the one of the first auxiliary data lines via one of the auxiliary taskers. A fourth pixel of the second pixel row is electrically connected to one of the second auxiliary data lines, and the first scan line is turned on during the first period to make the fourth pixel receive an output data signal generated by the second data auxiliary signal provided by the driving circuit components to the one of the second auxiliary data lines via the one of the auxiliary taskers, the one of the first auxiliary data lines and one of the auxiliary connection lines.

[0014] In at least one embodiment of the present application, each of the first connection lines and each of the auxiliary connection lines extends along a second direction different from the first direction, in the second direction, the number of pixels crossed by each of the first connection lines is the same as the number of pixels crossed by each of the auxiliary connection lines.

[0015] In at least one embodiment of the present application, the display device further comprises a plurality of liquid crystal cells or a plurality of organic light emitting diodes disposed in the opaque display area, and a plurality of micro light emitting diodes disposed in the transparent display area.

[0016] In at least one embodiment of the present application, the display device further comprises a sensing component. The display device has a display surface and a bottom surface opposite to the display surface, the sensing component is disposed between the display surface and the bottom surface, and overlaps with the transparent display area in a normal line of the display surface. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a top view schematic diagram of a display device according to at least one embodiment of the present application.

[0018] Figure 2 is a partial sectional view schematic diagram of a display device according to at least one embodiment of the present application.

[0019] Figure 3 is an enlarged schematic diagram of a partial area of an array substrate of a display device according to at least one embodiment of the present application.

[0020] Figure 4 is a waveform schematic diagram of a display device according to at least one embodiment of the present application during a frame period.

[0021] Figure 5 is an enlarged schematic diagram of a partial area of an array substrate of a display device according to at least another embodiment of the present application.

[0022] Figure 6 is a waveform schematic diagram of a display device according to at least another embodiment of the present application during a frame period.

[0023] Figure 7 is a top view schematic diagram of a display device according to at least another embodiment of the present application.

[0024] wherein the reference numerals:

[0025] 10, 10': display device

[0026] 100, 100A: array substrate

[0027] 200: drive circuit component

[0028] 300: sensing component

[0029] 400: counter substrate

[0030] 500: first display medium

[0031] 502: second display medium

[0032] 600: backlight module

[0033] AA: display area

[0034] BA: bonding area

[0035] BS: bottom surface

[0036] C11, C12, C13, C14, C15: first connection line

[0037] C21: second connection line

[0038] CA: auxiliary connection line

[0039] D1: first direction

[0040] D11, D12, D13, D14, D15: first data line

[0041] D2: second direction

[0042] D21, D22, D23, D24, D25: second data line

[0043] D31: third data line

[0044] D41: fourth data line

[0045] DA1: first auxiliary data line

[0046] DA2: second auxiliary data line

[0047] DE: drain

[0048] Dn: output data signal

[0049] DS1: first data signal

[0050] DS2: second data signal

[0051] F: frame period

[0052] G: scan line

[0053] G1: first scan line

[0054] G2: second scan line

[0055] GA: auxiliary scan line

[0056] GE: gate

[0057] M11, M12, M13, M14, M15: first multiplexer

[0058] M21: second multiplexer

[0059] MA: auxiliary multiplexer

[0060] OA, OA': opaque display area

[0061] PA: peripheral area

[0062] PC1: first pixel row

[0063] PC2: second pixel row

[0064] PR1: first pixel column

[0065] PX1: first pixel

[0066] PX2: second pixel

[0067] PX3: Third Pixel

[0068] PX4: Fourth pixel

[0069] R1: Zone 1

[0070] R2: Second Zone

[0071] RA: contralateral zone

[0072] S1: First switch assembly

[0073] S2: Second switch assembly

[0074] SE: Source

[0075] T1: First Period

[0076] T2: Second Period

[0077] TA, TA': Transparent display area

[0078] TS: Display Surface Detailed Implementation

[0079] In the following text, to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of components (e.g., layers, films, substrates, and regions) in the drawings will be enlarged proportionally, and the number of some components may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of components in the drawings or the size and shape of the components, but should cover the dimensions, shapes, and deviations from both caused by actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the components presented in the drawings of the present invention are mainly for illustration and are not intended to accurately depict the actual shape of the components, nor are they intended to limit the scope of the claims of the present invention.

[0080] Secondly, the terms "approximately," "about," or "substantially" used in this invention not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understandable to those skilled in the art to which this invention pertains. This deviation range can be determined by errors generated during measurement, which may arise from limitations of the measurement system or process conditions, for example. For instance, two objects (e.g., planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular," where "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects can include non-parallelism and non-perpendicularity caused by permissible deviation ranges.

[0081] Spatially relative terms, such as "under", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over in use or operation, a relative preposition to the device can change. Thus, under the devices can become above the devices, etc. Likewise, a device can be oriented in any direction, upward or otherwise, and the spatially relative terms used herein can be interpreted therefrom. The spatially relative terms used herein are intended to encompass different orientations of the device in use or operation and to cover the various modifications and configurations to position the device in various orientations under use or operation.

[0082] It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is to be understood that the terms "or", "and" and "both" are used herein to mean "and / or" unless the context clearly dictates otherwise. It is to be understood that the terms "comprising", "including", "characterized by" and "having" are used herein to mean "including but not limited to" unless the context clearly dictates otherwise.

[0083] It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is to be understood that the terms "or", "and" and "both" are used herein to mean "and / or" unless the context clearly dictates otherwise. It is to be understood that the terms "comprising", "including", "characterized by" and "having" are used herein to mean "including but not limited to" unless the context clearly dictates otherwise.

[0084] Figure 1 is a top view schematic diagram of a display device 10 according to at least one embodiment of the present disclosure. Referring to Figure 1 The display device 10 includes an array substrate 100 and a driving circuit assembly 200. The array substrate 100 has a display area AA and a peripheral area PA adjacent to the display area AA, the display area AA has a transparent display area TA and an opaque display area OA adjacent to the transparent display area TA, and the peripheral area PA has a bonding area BA and an opposite area RA opposite to the bonding area BA in a first direction D1, the opaque display area OA has a first area R1 not overlapping with the transparent display area TA in the first direction D1 and a second area R2 overlapping with the transparent display area TA.

[0085] The array substrate 100 includes a plurality of first data lines D11, D12, D13, D14, D15, a plurality of second data lines D21, D22, D23, D24, D25, a plurality of first connection lines C11, C12, C13, C14, C15, and a plurality of first taskers M11, M12, M13, M14, M15. The first data lines D11, D12, D13, D14, D15 are disposed in the first region R1, and the second data lines D21, D22, D23, D24, D25 are disposed in the second region R2. The first connection lines C11, C12, C13, C14, C15 extend from the first region R1 to the second region R2, and each of the first connection lines C11, C12, C13, C14, C15 electrically connects one of the first data lines D11, D12, D13, D14, D15 and one of the second data lines D21, D22, D23, D24, D25. The first taskers M11, M12, M13, M14, M15 are disposed in the bonding area BA and are respectively electrically connected to the first data lines D11, D12, D13, D14, D15.

[0086] The driving circuit assembly 200 is electrically connected to the first taskers M11, M12, M13, M14, M15 in the bonding area BA, provides first data signals to the first data lines D11, D12, D13, D14, D15 through the first taskers M11, M12, M13, M14, M15, respectively, and provides second data signals to the second data lines D21, D22, D23, D24, D25 through the first taskers M11, M12, M13, M14, M15, the first data lines D11, D12, D13, D14, D15, and the first connection lines C11, C12, C13, C14, C15, respectively.

[0087] Since the driving circuit assembly 200 provides second data signals to the second data lines D21, D22, D23, D24, D25 through the first taskers M11, M12, M13, M14, M15, the first data lines D11, D12, D13, D14, D15, and the first connection lines C11, C12, C13, C14, C15, respectively, the second data lines D21, D22, D23, D24, D25 disposed in the second region R2 overlapping the transparent display region TA do not need to pass through the transparent display region TA for electrical connection to the driving circuit assembly 200 in the bonding area BA, so the layout of the lines of the opaque display region OA of the display device 10 does not affect the light transmittance of the transparent display region TA.

[0088] In detail, as shown in FIG. 1, the display device 10 includes a transparent display region TA and an opaque display region OA. The transparent display region TA is disposed in the first region R1, and the opaque display region OA is disposed in the second region R2. Figure 1As shown, the first data lines D11, D12, D13, D14, D15 and the second data lines D21, D22, D23, D24, D25 extend along a first direction D1, the first connection lines C11, C12, C13, C14, C15 extend along a second direction D2 different from the first direction D1, the first data lines D11, D12, D13, D14, D15 are electrically connected to the second data lines D21, D22, D23, D24, D25 through the first connection lines C11, C12, C13, C14, C15 respectively, and the first data lines D11, D12, D13, D14, D15 are electrically connected to the first multi-taskers M11, M12, M13, M14, M15 at the bonding area BA respectively, and the driving circuit assembly 200 is electrically connected to the first multi-taskers M11, M12, M13, M14, M15 at the bonding area BA.

[0089] The driving circuit assembly 200 provides the first data signals to the first data lines D11 through the first multi-tasker M11, provides the first data signals to the first data lines D12 through the first multi-tasker M12, provides the first data signals to the first data lines D13 through the first multi-tasker M13, provides the first data signals to the first data lines D14 through the first multi-tasker M14, and provides the first data signals to the first data lines D15 through the first multi-tasker M15.

[0090] The driving circuit assembly 200 provides the second data signals to the second data lines D21 through the first multi-tasker M11, the first data line D11 and the first connection line C11, provides the second data signals to the second data lines D22 through the first multi-tasker M12, the first data line D12 and the first connection line C12, provides the second data signals to the second data lines D23 through the first multi-tasker M13, the first data line D13 and the first connection line C13, provides the second data signals to the second data lines D24 through the first multi-tasker M14, the first data line D14 and the first connection line C14, and provides the second data signals to the second data lines D25 through the first multi-tasker M15, the first data line D15 and the first connection line C15.

[0091] In some embodiments, an included angle between the first direction D1 and the second direction D2 is greater than 0 degree and less than 180 degree. In the present embodiment, the first direction D1 and the second direction D2 are substantially perpendicular to each other, i.e. the included angle between them is about 90 degree. However, the present application is not limited thereto, and in other embodiments, the first direction D1 and the second direction D2 can have other included angles.

[0092] In the first direction Dl, a portion of the opaque display region OA is located between the bonding region BA and the transparent display region TA, and a portion of the opaque display region OA is located between the transparent display region TA and the opposite region RA, i.e., the second region R2 of the opaque display region OA is located on opposite sides of the transparent display region TA. In the second direction D2, the first region Rl of the opaque display region OA is located on opposite sides of the transparent display region TA. That is, the opaque display region OA surrounds the transparent display region TA.

[0093] Please continue to refer to Figure 1 The array substrate 100 further includes a third data line D31, a fourth data line D41, a second connection line C21, and a second tasker M21. The third data line D31 and the fourth data line D41 extend along the first direction Dl, and the second connection line C21 extends along the second direction D2.

[0094] It is noted that, in order to make the expression of the drawings more simple, Figure 1 Only five first data lines D11, D12, D13, D14, D15, five second data lines D21, D22, D23, D24, D25, five first connection lines C11, C12, C13, C14, C15, five first taskers M11, M12, M13, M14, M15, one third data line D31, one fourth data line D41, one second connection line C21, and one second tasker M21 are shown for the purpose of representation. However, it is understood that the array substrate 100 can further include other first data lines, second data lines, first connection lines, first taskers, third data lines, fourth data lines, second connection lines, and second taskers.

[0095] The third data line D31 is disposed in the second region R2, and the fourth data line D41 is disposed in the second region R2. The second connection line C21 electrically connects the third data line D31 and the fourth data line D41. The second tasker M21 is disposed in the bonding region BA and electrically connected to the third data line D31. The driving circuit component 200 is electrically connected to the second tasker M21 in the bonding region BA, provides a third data signal to the third data line D31 via the second tasker M21, and provides a fourth data signal to the fourth data line D41 via the second tasker M21, the third data line D31, and the second connection line C21.

[0096] In addition, the array substrate 100 further includes a plurality of pixels (not shown in the figure). The pixels are disposed in the display region AA, and in the second direction D2, the number of pixels crossed by each first connection line C11, C12, C13, C14, C15 is the same, and the number of pixels crossed by each first connection line C11, C12, C13, C14, C15 is the same as the number of pixels crossed by the second connection line C21.

[0097] By the above design, the capacitive load between the third data line D31 and the fourth data line D41 is substantially the same as the capacitive load between the first data lines D11, D12, D13, D14, D15 and the second data lines D21, D22, D23, D24, D25, so that the display device 10 is prevented from having uneven brightness, and the display quality is improved.

[0098] In some embodiments, the first data lines D11, D12, D13, D14, D15, the second data lines D21, D22, D23, D24, D25, the third data line D31 and the fourth data line D41 can be formed by the same film layer structure, the first connection lines C11, C12, C13, C14, C15 and the second connection lines C21 can be formed by another same film layer structure, and the other same film layer structure forming the connection lines is disposed on the same film layer structure forming the data lines.

[0099] Figure 2 FIG. 1 is a schematic view of a display device 10 according to at least one embodiment of the present application. Figure 2 The display device 10 further includes a sensing component 300, a counter substrate 400, a first display medium 500, a second display medium 502 and a backlight module 600. The display device 10 has a display surface TS and a bottom surface BS opposite to the display surface TS, the sensing component 300 is disposed between the display surface TS and the bottom surface BS, and overlaps the transparent display area TA in the normal line of the display surface TS. The counter substrate 400 is disposed opposite to the array substrate 100, the first display medium 500 and the second display medium 502 are disposed between the array substrate 100 and the counter substrate 400, and the backlight module 600 is disposed corresponding to the second display medium 502.

[0100] For example, the first display medium 500 can include a plurality of micro light emitting diodes disposed in the transparent display area TA, and the second display medium 502 can include a plurality of liquid crystal cells or a plurality of organic light emitting diodes disposed in the opaque display area OA. In the present embodiment, the second display medium 502 includes a plurality of liquid crystal cells, so the display device 10 further includes the backlight module 600 disposed corresponding to the second display medium 502 and a color filter layer (not labeled) disposed on the counter substrate 400 and corresponding to the second display medium 502. In some embodiments, the micro light emitting diodes can be disposed in part of the opaque display area OA to cover the frame of the backlight module 600, so that dark lines do not appear on the picture, and the display quality is improved.

[0101] Figure 3 FIG. 2 is an enlarged schematic view of a partial area of the array substrate 100 of the display device 10 according to at least one embodiment of the present application. Figure 4is a waveform diagram of the display device 10 of at least one embodiment of the present invention during one frame period F. Please refer to Figure 1 , Figure 3 and Figure 4 The array substrate 100 further includes a plurality of pixels, a scan line G, and an auxiliary scan line GA.

[0102] The pixels are disposed in the display area AA and arranged in a plurality of pixel rows and a plurality of pixel columns, and the pixel columns include a first pixel column PR1. The scan line G is disposed in the display area AA and extends along the second direction D2, and a first pixel PX1 of the first pixel column PR1 is electrically connected to one of the first data lines D11, D12, D13, such as the first data line D11. The auxiliary scan line GA is disposed in the display area AA and extends along the second direction D2, and a second pixel PX2 of the first pixel column PR1 is electrically connected to one of the second data lines D21, D22, D23, such as the second data line D21.

[0103] The scan line G is turned on during the first period T1 to cause the first pixel PX1 to receive an output data signal Dn (i.e., the waveform labeled D11 in Figure 4 ) generated by the driving circuit component 200 via one of the first taskers M11, M12, M13, such as the first tasker M11, and provided to the first data line D11. Figure 4 The auxiliary scan line GA is turned on during the second period T2 to cause the second pixel PX2 to receive an output data signal Dn (i.e., the waveform labeled D21 in ) generated by the driving circuit component 200 via the first tasker M11, the first data line D11, and one of the first connection lines C11, C12, such as the first connection line C11 electrically connecting the first data line D11 and the second data line D21, and provided to the second data line D21.

[0104] Figure 1 , Figure 3 and Figure 4 The first tasker M11 includes a first switch component S1 and a second switch component S2. The first switch component S1 is turned on during the first period T1 to cause the first pixel PX1 to receive an output data signal Dn (i.e., the waveform labeled D11 in Figure 4 ) generated by the driving circuit component 200 via the first switch component S1 and provided to the first data line D11, and the second switch component S2 is turned on during the second period T2 to cause the second pixel PX2 to receive an output data signal Dn (i.e., the waveform labeled D21 in Figure 4 ) generated by the driving circuit component 200 via the second switch component S2, the first data line D11, and the first connection line C11, and provided to the second data line D21.

[0105] In detail, the first and second switch components S1 and S2 respectively include a gate electrode GE, a source electrode SE and a drain electrode DE. The gate electrode GE is configured to receive a signal for turning on or off the first and second switch components S1 and S2. The source electrode SE is configured to receive the first and second data signals DS1 and DS2 provided by the driving circuit component 200. The drain electrode DE is electrically connected to the first data line D11 for transmitting the first and second data signals DS1 and DS2 when the first and second switch components S1 and S2 are turned on.

[0106] In some embodiments, the first and second switch components S1 and S2 are turned on earlier than the scan line G and the auxiliary scan line GA are turned on, respectively, and the first and second switch components S1 and S2 are turned off later than the scan line G and the auxiliary scan line GA are turned off, respectively.

[0107] In some embodiments, the scan line G, the auxiliary scan line GA and the gate electrode GE can be formed by a first film layer structure, the first data lines D11, D12, D13, the second data lines D21, D22, D23, the source electrode SE and the drain electrode DE can be formed by a second film layer structure, the first connection lines C11, C12 can be formed by a third film layer structure, and the second film layer structure is disposed on the first film layer structure, and the third film layer structure is disposed on the second film layer structure.

[0108] Please refer to Figure 1 and Figure 3 , the third pixel PX3 of the first pixel column PR1 is electrically connected to one of the first data lines D11, D12, D13 (e.g. the second data line D12), and the fourth pixel PX4 of the first pixel column PR1 is electrically connected to one of the second data lines D21, D22, D23 (e.g. the second data line D22).

[0109] The scan line G is turned on during the first period T1 to enable the fourth pixel PX4 to receive an output data signal generated by the driving circuit component 200 via the first multiplexer M12, the first data line D12 and one of the first connection lines C11, C12 (i.e. the first connection line C12 electrically connected to the first data line D12 and the second data line D22) to the second data line D22. The auxiliary scan line GA is turned on during the second period T2 to enable the third pixel PX3 to receive an output data signal generated by the driving circuit component 200 via the first multiplexer M12 to the first data line D12.

[0110] Figure 5 is a magnified schematic view of a partial region of an array substrate 100A of a display device according to at least another embodiment of the present application. Figure 6is a waveform diagram of the display device of at least another embodiment of the present application in a frame period F. Figure 5 The embodiment of Figure 3 is substantially the same as the embodiment of Figure 5 , and Figure 3 The top view diagram of the display device of

[0111] Please refer to Figure 1 , Figure 5 and Figure 6 , the array substrate 100A further includes a plurality of pixels, a first scan line G1 and a second scan line G2. The pixels are arranged in the display area AA and are arranged in a plurality of pixel rows and a plurality of pixel columns, and the pixel rows include a first pixel row PC1 located in the first area R1 and a second pixel row PC2 located in the second area R2. The first scan line G1 is arranged in the display area AA and extends along the second direction D2, and the first pixel PX1 of the first pixel row PC1 is electrically connected to one of the first data lines D11, D12 (for example, the first data line D11). The second scan line G2 is arranged in the display area AA and extends along the second direction D2, and the second pixel PX2 of the second pixel row PC2 is electrically connected to one of the second data lines D21, D22 (for example, the second data line D21).

[0112] The first scan line G1 is turned on in the first period T1 to enable the first pixel PX1 to receive the output data signal Dn (i.e. the waveform denoted as D11 in Figure 6 ) generated by the driving circuit component 200 provided to the first data line D11 via one of the first multiplexers M11, M12 (for example, the first multiplexer M11). The second scan line G2 is turned on in the second period T2 to enable the second pixel PX2 to receive the output data signal Dn (i.e. the waveform denoted as D21 in Figure 6 ) formed by the driving circuit component 200 provided to the second data line D21 via the first multiplexer M11, the first data line D11 and the first connection line C11, C12.

[0113] Please continue to refer to Figure 5 , the array substrate 100A further includes a first auxiliary data line DA1, a second auxiliary data line DA2, an auxiliary connection line CA and an auxiliary multiplexer MA. The first auxiliary data line DA1 and the second auxiliary data line DA2 extend along the first direction D1, and the auxiliary connection line CA extends along the second direction D2.

[0114] The first auxiliary data line DA1 is disposed in the first region R1, and the second auxiliary data line DA2 is disposed in the second region R2. The auxiliary connection line CA extends from the first region R1 to the second region R2, and electrically connects the first auxiliary data line DA1 and the second auxiliary data line DA2. The auxiliary multiplexer MA is disposed in the bonding region BA, and electrically connected to the first auxiliary data line DA1. The driving circuit assembly 200 is electrically connected to the auxiliary multiplexer MA in the bonding region BA, and provides the first auxiliary data signal to the first auxiliary data line DA1 via the auxiliary multiplexer MA, and provides the second auxiliary data signal to the second auxiliary data line DA2 via the auxiliary multiplexer MA, the first auxiliary data line DA1 and the auxiliary connection line CA.

[0115] The third pixel PX3 of the first pixel row PC1 is electrically connected to the first auxiliary data line DA1, and the second scan line G2 is turned on in the second period T2 to make the third pixel PX3 receive the output data signal generated by the driving circuit assembly 200 providing the first auxiliary data signal to the first auxiliary data line DA1 via the auxiliary multiplexer MA. The fourth pixel PX4 of the second pixel row PC2 is electrically connected to the second auxiliary data line DA2, and the first scan line G1 is turned on in the first period T1 to make the fourth pixel PX4 receive the output data signal generated by the driving circuit assembly 200 providing the second data auxiliary signal to the second auxiliary data line DA2 via the auxiliary multiplexer MA, the first auxiliary data line DA1 and the auxiliary connection line CA.

[0116] In some embodiments, in the second direction D2, the number of pixels crossed by the first connection line C11 is the same as the number of pixels crossed by the auxiliary connection line CA. The first auxiliary data line DA1 and the second auxiliary data line DA2 can be formed by the same film layer structure, the auxiliary connection line CA can be formed by another same film layer structure, and another same film layer structure forming the connection line is disposed on the same film layer structure forming the data line.

[0117] Figure 7 is a top view schematic diagram of a display device 10' of at least another embodiment of the present application. Figure 7 Embodiments of Figure 1 Most of the component structures and relative positional relationships of embodiments of Figure 7 The display device 10' of Figure 1 The main difference between the display device 10' of

[0118] Please refer to Figure 7In the first direction D1, the opaque display area OA' is located between the transparent display area TA' and the opposite area RA, and the transparent display area TA' and the bonding area BA do not have an opaque display area therebetween. In the second direction D2, the first area R1 of the opaque display area OA' is located on opposite sides of the transparent display area TA'.

[0119] In summary, in the display device of at least one embodiment of the present application, the driving circuit assembly provides the second data signal to the second data line via the first multiplexer, the first data line and the first connection line, respectively. The second data line provided in the opaque display area overlapping the transparent display area does not need to pass through the transparent display area for electrical connection with the driving circuit assembly in the bonding area. Therefore, the line layout of the opaque display area of the display device does not affect the light transmittance of the transparent display area.

[0120] Although the present application has been disclosed with the above embodiments, it is not intended to limit the present application. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of the present application is defined by the appended claims.

Claims

1. A display device, characterized in that, include: An array substrate has a display area and a peripheral area adjacent to the display area. The display area has a transparent display area and an opaque display area adjacent to the transparent display area. The peripheral area has a bonding area and a pair of side areas opposite to the bonding area in a first direction. The opaque display area has a first area that does not overlap with the transparent display area and a second area that overlaps with the transparent display area in the first direction. The array substrate includes: Multiple first data lines are located in this first zone; Multiple second data lines are located in this second zone; Multiple first connection lines extend from the first area to the second area, wherein each of the first connection lines is electrically connected to one of the multiple first data lines and one of the multiple second data lines; and Multiple first multiplexers are disposed in the junction area and are electrically connected to the multiple first data lines respectively; and A drive circuit assembly is electrically connected to the plurality of first multiplexers in the junction area, and provides a first data signal to the plurality of first data lines via the plurality of first multiplexers, and provides a second data signal to the plurality of second data lines via the plurality of first multiplexers, the plurality of first data lines and the plurality of first connection lines.

2. The display device as described in claim 1, characterized in that, The array substrate also includes: Multiple pixels are disposed in the display area and arranged into multiple pixel rows and multiple pixel columns, and the multiple pixel columns include a first pixel column; A scan line is disposed in the display area, wherein a first pixel of the first pixel column is electrically connected to one of the plurality of first data lines, and the scan line is turned on during a first period to enable the first pixel to receive an output data signal generated by the first data signal provided by the driving circuit component to one of the plurality of first data lines via one of the plurality of first multiplexers; and An auxiliary scan line is disposed in the display area, wherein a second pixel of the first pixel column is electrically connected to one of the plurality of second data lines, and the auxiliary scan line is turned on during a second period to enable the second pixel to receive an output data signal generated by the driving circuit component through one of the plurality of first multiplexers, one of the plurality of first data lines and one of the plurality of first connection lines to one of the plurality of second data lines.

3. The display device as described in claim 2, characterized in that, One of the multiple first multitasking units includes: A first switching component and a second switching component, wherein the first switching component is turned on during the first period to enable the first pixel to receive an output data signal generated by the driving circuit component through the first switching component to one of the plurality of first data lines, and the second switching component is turned on during the second period to enable the second pixel to receive an output data signal generated by the driving circuit component through the second switching component, one of the plurality of first data lines and one of the plurality of first connecting lines to one of the plurality of second data lines.

4. The display device as claimed in claim 1, characterized in that, The array substrate also includes: Multiple pixels are disposed in the display area, wherein each of the first connecting lines extends along a second direction different from the first direction, and in the second direction, each of the first connecting lines spans the same number of pixels.

5. The display device as claimed in claim 1, characterized in that, The array substrate also includes: Multiple third data lines are located in this second zone; Multiple fourth data lines are located in this second zone; Multiple second connection lines, wherein each of the second connection lines is electrically connected to one of the multiple third data lines and one of the multiple fourth data lines; and Multiple second multiplexers are disposed in the junction area and electrically connected to the multiple third data lines respectively. The drive circuit assembly is electrically connected to the multiple second multiplexers in the junction area, and provides a third data signal to the multiple third data lines through the multiple second multiplexers, and provides a fourth data signal to the multiple fourth data lines through the multiple second multiplexers, the multiple third data lines, and the multiple second connection lines respectively.

6. The display device as claimed in claim 5, characterized in that, The array substrate also includes: Multiple pixels are disposed in the display area, wherein each of the first connecting lines and each of the second connecting lines extends along a second direction different from the first direction, and in the second direction, the number of pixels spanned by each of the first connecting lines is the same as the number of pixels spanned by each of the second connecting lines.

7. The display device as claimed in claim 1, characterized in that, The array substrate also includes: Multiple pixels are disposed in the display area and arranged into multiple pixel rows and multiple pixel columns, wherein the multiple pixel rows include a first pixel row located in the first area and a second pixel row located in the second area; A first scan line is disposed in the display area, wherein a first pixel of the first pixel row is electrically connected to one of the plurality of first data lines, and the first scan line is turned on during a first period to enable the first pixel to receive an output data signal generated by the first data signal provided by the driving circuit component to one of the plurality of first data lines via one of the plurality of first multiplexers; and A second scan line is disposed in the display area, wherein a second pixel of the second pixel row is electrically connected to one of the plurality of second data lines, and the second scan line is turned on during a second period so that the second pixel receives the second data signal provided by the driving circuit component to one of the plurality of second data lines via one of the plurality of first multiplexers, one of the plurality of first data lines, and one of the plurality of first connection lines, thereby generating an output data signal.

8. The display device as claimed in claim 7, characterized in that, The array substrate also includes: Multiple first auxiliary data lines are located in this first zone; Multiple secondary auxiliary data lines are located in this second zone; Multiple auxiliary connection lines extend from the first area to the second area, wherein each auxiliary connection line is electrically connected to one of the multiple first auxiliary data lines and one of the multiple second auxiliary data lines; and Multiple auxiliary multiplexers are disposed in the junction area and electrically connected to the multiple first auxiliary data lines respectively. The drive circuit assembly is electrically connected to the multiple auxiliary multiplexers in the junction area. The multiple auxiliary multiplexers provide a first auxiliary data signal to the multiple first auxiliary data lines respectively, and provide a second auxiliary data signal to the multiple second auxiliary data lines respectively through the multiple auxiliary multiplexers, the multiple first auxiliary data lines, and the multiple auxiliary connection lines.

9. The display device as claimed in claim 8, characterized in that, A third pixel in the first pixel row is electrically connected to one of the plurality of first auxiliary data lines, and the second scan line is turned on during the second period so that the third pixel receives an output data signal generated by the driving circuit component through the first auxiliary data signal provided to one of the plurality of first auxiliary data lines via one of the plurality of auxiliary multiplexers. A fourth pixel in the second pixel row is electrically connected to one of the plurality of second auxiliary data lines, and the first scan line is turned on during the first period so that the fourth pixel receives an output data signal generated by the driving circuit component through the second data auxiliary signal provided to one of the plurality of second auxiliary data lines via one of the plurality of auxiliary multiplexers, one of the plurality of first auxiliary data lines, and one of the plurality of auxiliary connection lines.

10. The display device as claimed in claim 8, characterized in that, Each of the first connecting lines and each of the auxiliary connecting lines extends along a second direction different from the first direction, wherein the number of pixels spanned by each of the first connecting lines is the same as the number of pixels spanned by each of the auxiliary connecting lines in the second direction.

11. The display device as claimed in claim 1, characterized in that, Also includes: Multiple liquid crystal cells or multiple organic light-emitting diodes are disposed in the opaque display area; and Multiple miniature light-emitting diodes are disposed in the transparent display area.

12. The display device as claimed in claim 1, characterized in that, Also includes: A sensing component, wherein the display device has a display surface and a bottom surface opposite to the display surface, the sensing component is disposed between the display surface and the bottom surface and on a normal line of the display surface, and the sensing component overlaps with the transparent display area.

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