Clock data recovery method, device and system and storage medium

Abstract

The embodiment of the invention provides a clock data recovery method, device and system and a storage medium. The clock data recovery method comprises the following steps: after a BMCDR system enters an open-loop state, carrying out signal sampling on a lead code of input data based on a sampling clock moving in a single direction; searching the edge of a lead code according to the signal sampling results of the current beat and the previous beat; after the edge of the lead code is determined and found, a target sampling position is determined based on the edge, and the BMCDR system is switched back to a closed loop state; and performing data sampling based on the target sampling position in a closed-loop state, and performing clock data recovery based on the sampled data. According to the scheme of the embodiment, the BMCDR can quickly find the optimal sampling position in the lead code stage in a high-speed application scene, and the system complexity is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a clock data recovery method, apparatus, system, and storage medium. Background Technology

[0002] It is projected that by 2050, over 68% of the global population will live in urban areas, leading to a surge in demand for data services. From 2015 to 2021, the number of global internet users increased by 60%, while global internet traffic grew by 440%, and data center capacity increased by 260%. With the widespread adoption of data-intensive applications such as streaming video, artificial intelligence, and blockchain, the robust growth in demand for data network services will continue. The need for massive data processing places higher demands on the bandwidth of communication interfaces; currently, the speed of data mobility is primarily limited by high-speed SerDes.

[0003] The receiver section mainly consists of an analog front end (AFE), a clock and data recovery (CDR) circuit, and a demultiplexer. The CDR circuit is an important module in SerDes (serializer and deserializer). The main functions of the CDR circuit in the receiver are: to generate a clock aligned with the optimal sampling position of the input signal; to recover a clean and correct data signal; and to reduce its own noise introduction into the system.

[0004] Burst-Mode CDR (BMCDR) is a special application of CDR, primarily used in SerDes (Servlet Dependencies) of Passive Optical Networks (PONs). PONs can provide high bandwidth over long distances, making them a viable solution to bandwidth issues and widely used for fiber-to-the-home (FTTH) implementations. PONs use fiber optic cabling to provide Ethernet connectivity from the main data source to the end users. A PON system consists of an operator-operated central office equipment (Optical Line Terminal, OLT), a Passive Optical Splitter (POS), and multiple Optical Network Units (ONUs) for end users. Summary of the Invention

[0005] This disclosure provides a clock data recovery method, apparatus, system, and storage medium.

[0006] In a first aspect, embodiments of this disclosure provide a clock data recovery method, the method including:

[0007] After the BMCDR system enters the open-loop state, the preamble of the input data is sampled based on the sampling clock that moves in one direction.

[0008] The edge of the preamble is found based on the signal sampling results of the current and previous sampling times.

[0009] After determining that the edge of the preamble has been found, the target sampling position is determined based on the edge, and the BMCDR system is switched back to the closed-loop state.

[0010] In the closed-loop state, data is sampled based on the target sampling position, and clock data is recovered based on the sampled data.

[0011] Secondly, embodiments of this disclosure provide a clock data recovery apparatus, which may include:

[0012] One or more processors;

[0013] A memory having stored one or more programs, which, when executed by one or more processors, enable the one or more processors to implement the clock data recovery method.

[0014] One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.

[0015] Thirdly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the clock data recovery method.

[0016] Fourthly, embodiments of this disclosure provide a clock data recovery system, which may include: a mode switching module, a sampling module, and an edge finding module;

[0017] The sampling module is configured to sample the preamble of the input data based on a unidirectionally moving sampling clock after the BMCDR system enters the open-loop state.

[0018] The edge finding module is configured to find the edge of the preamble based on the signal sampling results of the current frame and the signal sampling results of the previous frame.

[0019] The mode switching module is configured to, after determining that the edge of the preamble has been found, determine the target sampling position based on the edge and switch the BMCDR system back to the closed-loop state.

[0020] The sampling module is further configured to perform data sampling based on the target sampling position in the closed-loop state, and to recover clock data based on the sampled data.

[0021] This embodiment of the disclosure improves the open-loop gain by sampling the preamble of the input data based on a unidirectional moving sampling clock after the BMCDR system enters the open-loop state. The large open-loop gain makes it possible to quickly find the optimal sampling position. Furthermore, by using a unidirectional moving sampling clock, the sampling clock moves only in one direction during the search for the optimal sampling position in the open-loop state, which facilitates rapid location of the optimal sampling position and avoids the prolonged search time caused by moving the sampling clock in multiple directions (e.g., moving back and forth in opposite directions). In addition, by finding the edge of the preamble based on the signal sampling results of the current and previous frames, the embodiment of the disclosure enables a simple and rapid determination of whether the current sampling position is the edge of the preamble, facilitating rapid edge confirmation. This further accelerates the search speed by simultaneously controlling the sampling clock to move in one direction and utilizing the periodic changes in the preamble to find the optimal sampling position. After determining the edge of the preamble, the target sampling position (i.e., the optimal sampling position) is determined based on the edge. The BMCDR system is then switched back to the closed-loop state. In the closed-loop state, data is sampled based on the target sampling position, and clock data is recovered based on the sampled data. This enables the timely data recovery based on the optimal sampling position determined by the scheme of this embodiment, thereby improving the overall performance of the BMCDR system and reducing the complexity of the system design. Attached Figure Description

[0022] In the accompanying drawings of the embodiments disclosed herein:

[0023] Figure 1 A flowchart of a clock data recovery method provided in this embodiment of the disclosure;

[0024] Figure 2 A schematic diagram of a clock data recovery method provided in an embodiment of this disclosure;

[0025] Figure 3 A flowchart illustrating a method for finding the edge of a preamble based on the signal sampling results of the current and previous frames, provided in this embodiment of the disclosure.

[0026] Figure 4 A schematic diagram illustrating the movement of the sampling clock on the data symbols of the preamble to find the edge, as provided in the embodiments of this disclosure;

[0027] Figure 5 A schematic diagram for finding the edge of a sampling clock provided in an embodiment of this disclosure;

[0028] Figure 6 This is a schematic diagram of the compensation strategy that incorporates gyration value provided in an embodiment of the present disclosure;

[0029] Figure 7 A diagram showing the change of the phase change circuit control code in two cases where the data clock and edge clock respectively search for the edge of the data symbol of the preamble in an embodiment of this disclosure.

[0030] Figure 8 A block diagram of a clock data recovery device provided in an embodiment of this disclosure;

[0031] Figure 9 A block diagram of a clock data recovery system provided in this embodiment of the disclosure;

[0032] Figure 10 This is a schematic diagram of the clock data recovery system structure provided in an embodiment of this disclosure. Detailed Implementation

[0033] To enable those skilled in the art to better understand the technical solutions of this disclosure, the communication-sensing data processing method and computer-readable storage medium provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0034] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0035] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0036] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0037] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0038] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0039] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0040] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0041] It is projected that by 2050, over 68% of the global population will live in urban areas, leading to a surge in demand for data services. From 2015 to 2021, the number of global internet users increased by 60%, while global internet traffic grew by 440%, and data center capacity increased by 260%. With the widespread adoption of data-intensive applications such as streaming video, artificial intelligence, and blockchain, the robust growth in demand for data network services will continue. The need for massive data processing places higher demands on the bandwidth of communication interfaces; currently, the speed of data mobility is primarily limited by high-speed SerDes.

[0042] The receiver section mainly consists of an analog front end (AFE), a clock and data recovery (CDR) circuit, and a demultiplexer. The CDR circuit is an important module in SerDes (serializer and deserializer). The main functions of the CDR circuit in the receiver are: to generate a clock aligned with the optimal sampling position of the input signal; to recover a clean and correct data signal; and to reduce its own noise introduction into the system.

[0043] Burst-Mode CDR (BMCDR) is a special application of CDR, primarily used in SerDes (Servlet Dependencies) of Passive Optical Networks (PONs). PONs can provide high bandwidth over long distances, making them a viable solution to bandwidth issues and widely used for fiber-to-the-home (FTTH) implementations. PONs use fiber optic cabling to provide Ethernet connectivity from the main data source to the end users. A PON system consists of an operator-operated central office equipment (Optical Line Terminal, OLT), a Passive Optical Splitter (POS), and multiple Optical Network Units (ONUs) for end users.

[0044] PON employs Time Division Multiple Access (TDMA) technology, meaning the data received by the OLT is an independent burst. Because the aging of each user's equipment and the channel loss connecting to the POS vary, the data arriving at the OLT has different amplitudes and phases, thus posing entirely new requirements for the OLT receiver design. For the CDR section, each data segment is independent and has a different phase. Therefore, the conventional continuous CDR model, which allows for a relatively long locking time followed by signal recovery, can no longer meet the requirements. Thus, the concept of BMCDR (Browser-Controlled Receiver) was proposed. BMCDR needs to stably track the data signal like a conventional CDR, while also achieving locking as quickly as possible upon data arrival. BMCDR also differs from conventional CDR in its input signal. The signal input to the BMCDR circuit can be preceded by a short segment (tens to hundreds of UIs, one UI being one data width) of a fixed code pattern (e.g., "0101" pattern, PRBS7 pattern, etc.). This short segment is called the preamble. The role of the preamble is to help BMCDR lock quickly. How to make good use of the preamble to achieve the fastest possible locking time is one of the key aspects of BMCDR design.

[0045] In BMCDR mode, there are currently three main design structures: 1) BMCDR based on Gated Voltage-Controlled Oscillator (GVCO) and its derivatives; 2) Oversampling BMCDR and its derivatives; and 3) PI-based BMCDR structure. GVCO-based BMCDRs can achieve fast phase locking due to their automatic alignment characteristics. However, both level-triggered and edge-injected locked GVCO-based BMCDR structures are easily affected by PVT (Potentially Transient Voltage). Consistency issues between components in the circuit can lead to frequency mismatch between the output clock frequencies of the two VCOs or between the VCO output clock and the reference clock, thus affecting the CDR circuit's tolerance for consecutive identical digits (CID). Furthermore, gated oscillators are generally based on ring oscillators, which can easily lead to higher phase noise and lower operating speeds. Most seriously, due to the open-loop feedforward operation mode of GVCO-based BMCDRs, their resistance to jitter propagation is poor. While this problem can be mitigated by introducing a PLL (Phase-Locked Loop), this results in increased area and power consumption. The main issue with oversampled BMCDRs stems from their need for multi-phase clocks, leading to higher power consumption and larger area. For oversampled BMCDRs, more clock phases are needed to ensure the selection of the clock closest to the optimal sampling position for more reliable sampled data. In high-data-rate applications, the generation conditions for multi-phase clocks become increasingly stringent due to the shrinking clock pulse width, requiring higher current and lower circuit noise to ensure clock purity. Because of the limitations of GVCO-type CDRs and oversampled CDRs in high-speed applications, this proposal designs a fast locking logic based on a third approach to match BMCDRs used in high-speed scenarios.

[0046] In current multi-channel applications of SerDes, the PI (Phase Interpolator) type CDR structure avoids the use of independent PLLs in each channel, thereby reducing chip area and power consumption, and also avoiding phase deviations in clocks across different channels. Simultaneously, the PI-based CDR circuit itself has a fast lock-in time. Thanks to the characteristics of digital circuits, special algorithms can be designed in the preamble stage to help the PI-based CDR circuit achieve fast locking and output a stable tracking clock in the load data stage, thus realizing the function of BMCDR. The essence of the PI-based CDR circuit is to continuously track input data by using PI to change the phase of the clock. BMCDR applications require the CDR loop to reach the convergence position as quickly as possible; that is, the PI needs to move the clock to the optimal sampling position as quickly as possible.

[0047] In this embodiment of the disclosure, a new burst mode clock data recovery technology is proposed to address this problem. While avoiding the problems of poor consistency due to device mismatch and large area and power consumption in other burst mode clock data recovery technologies, it can achieve fast locking of BMCDR in the preamble stage (i.e., quickly find the best sampling position) in high-speed burst mode clock data recovery scenarios, and supports use in multi-channel scenarios, reducing the complexity of system design.

[0048] This embodiment of the disclosure improves the open-loop gain by sampling the preamble of the input data based on a unidirectional moving sampling clock after the BMCDR system enters the open-loop state. The large open-loop gain makes it possible to quickly find the optimal sampling position. Furthermore, by generating a sampling clock that moves in a preset unidirectional direction for signal sampling, the sampling clock moves only in one direction during the search for the optimal sampling position in the open-loop state. This facilitates rapid finding of the optimal sampling position and avoids the prolonged search time caused by the sampling clock moving in multiple directions (e.g., moving back and forth in opposite directions). In addition, the preamble edge is found based on the signal sampling results of the current and previous frames. This allows for a simple and rapid determination of whether the current sampling position is the edge of the preamble, facilitating rapid edge confirmation. It also allows the embodiment of the disclosure to simultaneously control the sampling clock to move in one direction while utilizing the periodic changes in the preamble to find the optimal sampling position, further accelerating the search speed. After identifying the edge of the preamble, the BMCDR system is switched back to closed-loop state, and data sampling is performed in closed-loop state. Clock data is recovered based on the sampled data. This enables the optimal sampling position to be quickly determined and data recovery to be performed in a timely manner based on the scheme of this embodiment, thereby improving the overall performance of the BMCDR system and reducing the complexity of system design.

[0049] The clock data recovery method of this disclosure can be applied to, but is not limited to, burst mode (BM) clock data recovery in a high-speed passive optical network (PON) optical line terminal (SerDes) receiver.

[0050] The embodiments of this disclosure will be described in detail below.

[0051] This disclosure provides a clock data recovery method, such as... Figure 1 , Figure 2 As shown, the method includes steps S11-S14:

[0052] S11. After the BMCDR system enters the open-loop state, the preamble of the input data is sampled based on the sampling clock that moves in one direction.

[0053] In this embodiment of the disclosure, based on the linear model of a general simulated CDR, there is a formula for calculating the loop gain of the CDR linear model:

[0054]

[0055] Among them, L(Z) -1 () is the signal Z -1 The loop gain, K V The gain correction factor for the bang-bang phase detector is as follows: For example, the loop gain caused by the preamble of the input data being "0101" code and the preamble of the PRBS31 code are completely different. This is because the PRBS31 code preamble will have up to 31 consecutive identical digits (UI, Unit Interval, or data width). In this case, the bang-bang phase detector will not output a result. If only K is used... PD Using coefficients for modeling can lead to model distortion, so K needs to be introduced. V The coefficients are supplemented and corrected; Includes all latency caused by analog or digital means; K DPC It is the gain of the PI or VCDL (Voltage Controlled Delay Line), which is related to the phase that the PI can shift in one step; phug and frug are the proportional path coefficient and integral path coefficient of the loop filter.

[0056] In this embodiment, the loop is disconnected, putting the BMCDR system in an open-loop state. An external digital control module directly controls the PI controller to rotate. From the loop gain calculation formula of the CDR linear model described above, the open-loop transfer function of the BMCDR system at this time can be derived as follows:

[0057]

[0058] Among them, L(Z) -1 () is the signal Z -1 The open-loop transfer coefficient.

[0059] In this embodiment of the disclosure, as can be seen from the open-loop transfer function described above, the open-loop transfer coefficient is mainly determined by K. DPC Control, the circuit in the embodiment of this disclosure generates K DPC The gain component is a PI converter, so K can be increased by externally controlling the PI converter to move a greater distance. DPC This increases the open-loop gain (i.e., the open-loop transfer coefficient), and a large open-loop gain makes it possible to quickly find the optimal sampling position. However, this open-loop mode means that the PI can only move in one direction and cannot stay at the optimal sampling position.

[0060] In this embodiment of the disclosure, considering the above factors, the present embodiment proposes a scheme: In the burst CDR phase, the system is first in an open-loop state, while controlling the sampling clock to move in one direction, and utilizing the periodic change characteristics of the preamble (e.g., including but not limited to the "0101" preamble) (such as the periodic change of the "0101" preamble every 2 UIs), the sampling result of the current step is calculated with the sampling result of the previous step (e.g., XOR calculation) to quickly find the data edge (i.e., the optimal sampling position). After the sampling clock is placed at the optimal sampling position, the system is switched back to the closed-loop system; In the continuous CDR phase (i.e., in the closed-loop state), stable and continuous data tracking is performed based on the binary phase detector.

[0061] In this embodiment of the disclosure, in order to achieve the above technical solution, it is first necessary to make the BMCDR system enter an open-loop state after the burst clock data recovery BMCDR system is started.

[0062] In this embodiment of the disclosure, after the Burst Clock Data Recovery (BMCDR) system is started, enabling the BMCDR system to enter an open-loop state may include:

[0063] Acquire the BMCDR control signal and generate a mode switching control signal based on the BMCDR control signal;

[0064] Based on the mode switching control signal, only the step value is collected so that the BMCDR system enters the open-loop state; the step value is used to control the movement value of each step in the process of the sampling clock moving in one direction.

[0065] In this embodiment of the disclosure, the BMCDR control signal can be an indication signal transmitted from the upper-level system, such as a CDR function start indication signal. That is, after the CDR function is started, the BMCDR system can first enter the open-loop state to execute the fast locking scheme of this embodiment of the disclosure.

[0066] In this embodiment of the disclosure, a detailed implementation of the scheme for entering the open-loop state may include: during the burst CDR phase, a preset switching control module can receive a BMCDR control signal. After receiving the BMCDR control signal, the switching control module can generate a mode switching control signal based on the BMCDR control signal and send the mode switching control signal to a preset data selector. A preset step control module then starts outputting a fixed step value BMSTEP. At this time, the data selector only collects the step value output by the step control module based on the mode switching control signal, thus enabling the BMCDR system to enter the open-loop state. In the closed-loop state, the data selector would normally only collect the input data of a preset low-pass filter. This low-pass filter receives the output data of a binary phase detector, which receives the signal sampling result after the sampling module samples the input data based on a sampling clock. After entering the open-loop state, the data selector no longer collects the output data of the low-pass filter, but only collects the fixed step value BMSTEP output by the step control module, and provides this step value to the preset counting decoder. At this time, the counting decoder only accepts input from the step control module. The counting decoder is connected to the phase changing circuit (which may include, but is not limited to, a phase interpolator PI and / or a voltage-controlled delay line VCDL). The step value counted by the counting decoder serves as the input of the phase changing circuit. Therefore, under the control of the step value output by the counting decoder, the phase changing circuit controls the system clock to move, obtaining the sampling clock of this embodiment. There can be multiple sampling clocks, and different sampling clocks can have a certain phase difference to achieve different sampling functions. The phase of each sampling clock movement is equal to the phase of the step value.

[0067] In the embodiments disclosed herein, the binary phase detector described above may include, but is not limited to, a bang-bang phase detector (BBPD), a Mueller-Muller phase detector (MMPD), etc.

[0068] In this embodiment, the binary phase detector system described above can be an arbitrary rate binary phase detector system. The detailed rate can be defined according to requirements and is not limited here. For example, it can include, but is not limited to, quarter rate, half rate, and full rate. Among them, quarter rate means that the clock frequency of the sampling clock is 1 / 4 of the data rate, half rate means that the clock frequency of the sampling clock is 1 / 2 of the data rate, and full rate means that the clock frequency of the sampling clock is equal to the data rate.

[0069] In this embodiment of the disclosure, the following description uses a half-rate bang-bang phase detector system as an example to illustrate the solution of this embodiment.

[0070] In this embodiment of the disclosure, in the half-rate bang-bang phase detector system, each UI data is sampled by two signals (edge ​​signal and data signal; the edge signal refers to the signal at the edge of a UI data, and the data signal refers to the signal sampled at the optimal sampling position of a UI data; the edge signal can be sampled by the edge clock in the sampling clock, and the data signal can be sampled by the data signal in the sampling clock; the edge clock and the sampling clock are exactly half a UI apart). Ideally, after the sampling clock is locked (i.e., the data clock in the sampling clock is exactly at the optimal sampling position), one of the two signals (edge ​​signal and data signal) is sampled from the edge of a UI data symbol, and the other is sampled from the center of that UI data symbol. Thus, we can define: the sampling clock whose rising edge is aligned with the edge of the preamble data symbol during locking is the edge clock, and the signal sampled by the edge clock is the edge signal of the data; conversely, the sampling clock whose rising edge is aligned with the optimal sampling position at the center of the preamble data symbol during locking is the data clock, and the signal sampled by the data clock is the data signal, i.e., the recovered data.

[0071] In this embodiment of the disclosure, after the BMCDR system enters the open-loop state, a sampling clock that moves in a preset unidirectional direction can be generated for subsequent signal sampling.

[0072] In this embodiment of the disclosure, generating a sampling clock that moves in a preset unidirectional direction includes:

[0073] A sampling clock with a corresponding clock frequency is generated based on the data rate of the input data and the preset rate requirement, and the movement value of each step in the sampling clock is determined based on the step value.

[0074] In this embodiment of the disclosure, the unidirectional direction can be defined according to requirements, and the specific direction of the unidirectional direction is not limited herein. For example, Figure 4 In one embodiment, the movement is forward when moving in one direction; in another embodiment, it can also be set to move backward.

[0075] In this embodiment of the disclosure, the preset rate requirement is the quarter rate, half rate, full rate, etc. mentioned above. The preset rate requirement can be defined according to the needs. There is no limitation on the detailed rate requirement here. The preset rate requirement may include, but is not limited to, one-eighth rate, quarter rate, half rate, full rate, etc.

[0076] In this embodiment of the disclosure, the sampling clock can be generated using the phase changing circuit described above. The phase changing circuit can determine the required clock frequency based on the data rate of the input data and the preset rate requirement, and adjust the system clock (CLK0°~CLK270°) based on the required clock frequency to obtain a sampling clock with the required clock frequency. The sampling clock is then moved based on the aforementioned step value to obtain the sampling clock required by the scheme of this embodiment of the disclosure.

[0077] In this embodiment of the disclosure, the sampling clock may include multiple clocks, such as the aforementioned edge clock and data clock.

[0078] In the embodiments of this disclosure, in a half-rate four-phase clock system, only the edge clock or the data clock can be used; in a full-rate clock system, data can be acquired using both the rising and falling edges of the sampling clock, or only the rising or falling edge of the sampling clock can be used. In a quarter-rate clock system, all clocks (such as the edge clock and the data clock) can be used, or only a single clock (such as the edge clock or the data clock) can be used.

[0079] In this embodiment of the disclosure, after the input data is sampled by a sampling clock, the input data of the serial signal can be converted into a multi-bit parallel signal. For example, the input data of the serial signal can be converted into a multi-bit parallel signal with each parallel signal having a width of 8 bits. For example, after the input data of the serial signal is sampled by multiple edge clocks, multi-bit parallel edge signals can be obtained; after the input data of the serial signal is sampled by multiple data clocks, multi-bit parallel data signals can be obtained.

[0080] S12. Find the edge of the preamble based on the signal sampling results of the current shot and the signal sampling results of the previous shot.

[0081] In the embodiments disclosed herein, such as Figure 3 As shown, finding the edge of the preamble based on the signal sampling results of the current and previous frames can include steps S21-S23:

[0082] S21. Obtain the signal sampling results of the current frame and the signal sampling results of the previous frame.

[0083] In the embodiments disclosed herein, such as Figure 4 The diagram shows an embodiment of the sampling clock moving on the data symbol of the preamble to find the edge. Line a refers to the edge signal obtained in the current step, and line b refers to the edge signal obtained in the previous step.

[0084] S22. Perform a preset calculation by combining the signal sampling results of the current shot with the signal sampling results of the previous shot.

[0085] In this embodiment of the disclosure, the preset calculation can be defined according to different needs, and no detailed limitation is made here. For example, the corresponding preset calculation can be determined according to different preamble types.

[0086] In this embodiment of the disclosure, for example, for the "0101" preamble, the preset calculation may include, but is not limited to, XOR calculation. The following uses XOR calculation as an example to illustrate the scheme of this embodiment of the disclosure.

[0087] In this embodiment of the disclosure, the edge signal obtained in the previous step and the edge signal obtained in the current step can be XORed to obtain the calculation result.

[0088] In this embodiment of the disclosure, if the sampling clock has not yet moved to the edge, such as Figure 4 As shown, the signal sampling result of the current frame and the signal sampling result of the previous frame may both be 1, or both may be 0. After XORing, the result of the calculation is 0. If the sampling clock has moved to the edge, such as Figure 5 As shown, the signal sampling result of the current frame and the signal sampling result of the previous frame may be 1 and 0 respectively. After XORing these two signal sampling results, the result will definitely be 1.

[0089] S23. If the calculation result corresponding to the preset calculation meets the first preset requirement, determine that the sampling clock has crossed the edge of the preamble.

[0090] In this embodiment of the disclosure, the first preset requirement can be defined according to different needs, and the details are not limited here. For example, for the preset calculation mentioned above, a corresponding first data threshold (or first threshold value) can be preset, and the calculation result can be compared with the first data threshold. When the comparison result meets the requirements, it can be determined that the calculation result meets the first preset requirement.

[0091] In this embodiment of the disclosure, the first data threshold can be defined according to the requirements, and no detailed limitation is made here. For example, the first data threshold can be set according to the selected preset calculation.

[0092] In this embodiment of the disclosure, for example, regarding the XOR calculation described above, a first data threshold can be set to 0. The calculation result is compared with 0. When the calculation result is greater than 0, it can be determined that the comparison result meets the requirements. Therefore, the calculation result meets the first preset requirement, and it can be determined that the sampling clock has crossed the edge of the preamble. Conversely, when the calculation result is less than or equal to 0, it can be determined that the comparison result does not meet the requirements. Therefore, the calculation result does not meet the first preset requirement, and it can be determined that the sampling clock has not crossed the edge of the preamble.

[0093] In this embodiment of the disclosure, for example, in the case where the sampling clock has already moved to the edge, the signal sampling result of the current frame and the signal sampling result of the previous frame may be 1 and 0 respectively. The result of XORing these 1 and 0 will definitely be 1, which is greater than the set first data threshold of 0. Based on this detection, it can be detected that the sampling clock has moved to the edge. Conversely, in the case where the sampling clock has not moved to the edge, the signal sampling result of the current frame and the signal sampling result of the previous frame are both 1. The result of XORing these two 1s will definitely be 0, which is equal to the set first data threshold of 0. Based on this detection, it can be detected that the sampling clock has not yet moved to the edge.

[0094] In this embodiment, the operation of finding the edge of the preamble based on the signal sampling results of the current and previous frames can be performed by a preset burst mode phase detector. The burst mode phase detector can receive the signal sampling results output by the sampling module (including the signal sampling results of the current and previous frames) and determine whether the sampling clock has moved to the edge based on the signal sampling results. The sampling module can include a sampler and a demultiplexer. Specifically, the burst mode phase detector receives the output signal of the demultiplexer. The function of the demultiplexer is to convert the high-speed serial signal into a low-speed parallel signal; the number of parallel signals is the "bit width".

[0095] In this embodiment of the disclosure, when the signal sampling result is a multi-bit parallel signal, the method may further include:

[0096] The calculation is performed based on multiple calculation results from the multi-bit signal sampling results;

[0097] If the result of the operation satisfies the second preset requirement, it is determined that the edge clock has crossed the edge of the preamble.

[0098] In this embodiment of the disclosure, the second preset requirement can be defined according to different needs, and the details are not limited here. For example, for the above operation, a corresponding second data threshold (or second threshold value) can be preset, and the operation result can be compared with the second data threshold. When the comparison result meets the requirements, it can be determined that the operation result meets the second preset requirement.

[0099] In this embodiment of the disclosure, since the bit width of the digital circuit can be multiple bits, the burst mode phase detector can simultaneously perform preset calculations (e.g., XOR calculations) on the sampling results of multiple bits of signal in each frame and obtain multiple calculation results.

[0100] In this embodiment of the disclosure, the above operations can be defined according to requirements, and no specific operation method is limited here; for example, the operation performed on multiple calculation results may include, but is not limited to, addition.

[0101] In this embodiment of the disclosure, the following description uses the sampling result of a parallel signal with a bit width of 8 as an example. The logical expression of the operation can be expressed as follows:

[0102] SUM = sum(SIG_8⊕SIG_d_8);

[0103] Here, SIG_8 is the signal sampling result obtained in the current frame, SIG_d_8 is the signal sampling result obtained in the previous frame, ⊕ refers to performing an XOR operation (i.e., the operation mentioned above), and sum() is the summation function, which here refers to calculating the sum of the XOR values ​​of the sampling results of the previous and next frames of the 8-bit parallel signal (i.e., the operation result).

[0104] In this disclosure embodiment, for example, Figure 10 The letter N (N is a positive integer) following the splitter 2022 represents the line width (or bit width). In this embodiment, N = 8.

[0105] In this embodiment of the disclosure, a second data threshold (or second threshold value) can also be set for the calculation result, and the calculation result can be compared with the second data threshold. When the comparison result meets the requirements, it can be determined that the calculation result meets the second preset requirements.

[0106] In this embodiment of the disclosure, the second data threshold can be defined according to the requirements, and no detailed limitation is made here. For example, the second data threshold can be set according to the selected preset calculation.

[0107] In this embodiment of the disclosure, the calculation result can be compared with a second data threshold. If the calculation result is greater than the second data threshold, it is determined that the calculation result meets the second preset requirement, and it can be determined that the sampling clock has moved to the edge. Conversely, if the calculation result is less than or equal to the second data threshold, it is determined that the calculation result does not meet the second preset requirement, and it can be determined that the sampling clock has not yet moved to the edge.

[0108] In this embodiment of the disclosure, the determination of the first data threshold and the second data threshold is sufficient to prove that the sampling clock has reached the edge of the preamble, rather than a misjudgment caused by jitter or noise.

[0109] In this embodiment of the disclosure, the sampling clock may include an edge clock, and the signal sampling result may include: the edge signal obtained after the edge clock samples the input data;

[0110] And / or,

[0111] The sampling clock may include a data clock, and the sampling result of the signal may include: the data signal obtained after the data clock samples the input data.

[0112] In this embodiment of the disclosure, the edge of the preamble can be found based solely on the edge signal, solely on the data signal, or jointly on both the edge signal and the data signal. Detailed implementation schemes can be defined according to requirements and are not limited here.

[0113] In the embodiments of this disclosure, the schemes for finding the edges of the preamble based solely on edge signals and based solely on data signals are described in detail below.

[0114] In this embodiment of the disclosure, the preset calculation includes: a first preset calculation; the first preset requirement includes: a first sub-preset requirement; when the sampling clock includes an edge clock and the signal sampling result includes: the edge signal obtained after the edge clock samples the input data, finding the edge of the preamble based on the signal sampling result of the current frame and the signal sampling result of the previous frame may include:

[0115] Acquire the edge signal obtained in the previous frame and the edge signal obtained in the current frame;

[0116] Perform a first preset calculation on the edge signal obtained in the previous shot and the edge signal obtained in the current shot;

[0117] If the first calculation result corresponding to the first preset calculation satisfies the first sub-preset requirement, it is determined that the edge clock has crossed the edge of the preamble.

[0118] In this embodiment of the disclosure, the above operation includes a first operation; the second preset requirement includes a second sub-preset requirement; when the edge signal is a multi-bit parallel signal, the method may further include:

[0119] The first operation is performed based on multiple first calculation results of multi-bit edge signals;

[0120] If the result of the first operation corresponding to the first operation satisfies the second sub-preset requirement, it is determined that the edge clock has crossed the edge of the preamble.

[0121] In this embodiment of the disclosure, the preset calculation includes: a second preset calculation; the first preset requirement includes: a third sub-preset requirement; when the sampling clock includes a data clock and the signal sampling result includes: the data signal obtained after the data clock samples the input data, finding the edge of the preamble based on the signal sampling result of the current frame and the signal sampling result of the previous frame includes:

[0122] Acquire the data signal obtained in the previous frame and the data signal obtained in the current frame;

[0123] Perform a second preset calculation using the data signal obtained in the previous frame and the data signal obtained in the current frame;

[0124] If the second calculation result corresponding to the second preset calculation satisfies the third sub-preset requirement, it is determined that the data clock has crossed the edge of the preamble.

[0125] In this embodiment of the disclosure, the above operation includes a second operation; the second preset requirement includes a fourth sub-preset requirement; when the data signal is a multi-bit parallel signal, the method further includes:

[0126] A second operation is performed based on multiple second calculation results of multi-bit data signals;

[0127] If the result of the second operation corresponding to the second operation satisfies the fourth sub-preset requirement, it is determined that the data clock has crossed the edge of the preamble.

[0128] In this embodiment of the disclosure, by using the above-mentioned schemes of finding the edge of the preamble based solely on the edge signal and solely on the data signal together, it is possible to find the edge of the preamble based on both the edge signal and the data signal.

[0129] In this embodiment of the disclosure, if only the edge clock is used for edge finding, the edge clock needs to be shifted by at most 1 UI data unit to find the edge of the preamble. If both the edge clock and the data clock are used for edge finding, the edge of the preamble only needs to be shifted by at most 0.5 UI data units. Therefore, finding the edge of the preamble by using both the edge signal and the data signal can further accelerate the finding speed.

[0130] In this embodiment of the disclosure, when the bit width of the digital circuit is multi-bit, each step of the burst mode phase detector can simultaneously perform XOR judgments on multi-bit edge signals and multi-bit data signals. The multiple XOR judgments are added together to obtain the burst mode phase detection statistical result DSUM (i.e., the aforementioned calculation result SUM) for the data signal and the burst mode phase detection statistical result ESUM (i.e., the aforementioned calculation result SUM) for the edge signal. Taking an 8-bit bit width as an example, the logical expressions for the operations on the digital signal and the edge signal can be expressed as follows:

[0131]

[0132] Where Data_8 and Edge_8 are the 8-bit data signal and 8-bit edge signal obtained from the current sampling, respectively, and Data_d_8 and Edge_d_8 are the 8-bit data signal and 8-bit edge signal obtained from the previous sampling, respectively.

[0133] In the embodiments disclosed herein, such as Figure 2As shown, DSUM and ESUM are compared with their respective data thresholds (or cutoff values), and the comparison results determine whether the data clock and edge clock have reached their edges. For example, if DSUM is greater than the data threshold set based on the data signal, it can be confirmed that the data clock has reached its edge, and the process can proceed to the next step. If DSUM is less than or equal to the data threshold set based on the data signal, it can be confirmed that the data clock has not yet reached its edge, and the current state can remain unchanged, continuing to control the data clock to move in one direction to find the edge. Similarly, if ESUM is greater than the data threshold set based on the edge signal, it can be confirmed that the edge clock has reached its edge, and the process can proceed to the next step. If ESUM is less than or equal to the data threshold set based on the edge signal, it can be confirmed that the edge clock has not yet reached its edge, and the current state can remain unchanged, continuing to control the edge clock to move in one direction to find the edge.

[0134] S13. After determining that the edge of the preamble has been found, the target sampling position is determined based on the edge, and the BMCDR system is switched back to the closed-loop state.

[0135] In this embodiment of the disclosure, switching the BMCDR system back to closed-loop state may include:

[0136] Modify the burst termination signal corresponding to the signal sampling result;

[0137] The BMCDR system is controlled to enter a closed-loop state based on the modified burst termination signal.

[0138] In this embodiment of the disclosure, when the BMCDR system is in an open-loop state, the preset burst end signal BMDONE can be set to an initial value, which indicates that the BMCDR system is in an open-loop state. The specific value of the initial value is not limited here and can be defined according to requirements; for example, BMDONE can be set to 0.

[0139] In this embodiment of the disclosure, after determining that the edge of the preamble has been found, the initial value of the burst end signal BMDONE can be modified. This initial value can be modified to any value different from the initial value. The specific value of the modification is not limited here and can be defined according to requirements. For example, it may include, but is not limited to, flipping the initial value, such as changing it from 1 to 0, or from 0 to 1, or from a positive value to a negative value, or from a negative value to a positive value.

[0140] In this embodiment of the disclosure, the modified burst end signal can be used to control the BMCDR system to enter a closed-loop state.

[0141] In this embodiment of the disclosure, the sampling clock may include an edge clock, and the signal sampling result may include: an edge signal obtained after the edge clock samples the input data, and the burst end signal includes a first burst end signal corresponding to the edge signal;

[0142] And / or,

[0143] The sampling clock may include the data clock, and the signal sampling result may include: the data signal obtained after the data clock samples the input data, and the burst end signal includes the second burst end signal corresponding to the data signal.

[0144] In this embodiment of the disclosure, as can be seen from the foregoing, it is possible to determine whether the sampling clock has found an edge based solely on the edge signal or the data signal, or it is possible to determine whether the sampling clock has found an edge using both the edge signal and the data signal.

[0145] In this embodiment of the disclosure, corresponding burst end signals BMDONE can also be set for the edge signal and the data signal respectively. For example, a first burst end signal BMDONE_Edge can be set for the edge signal, and a second burst end signal BMDONE_Data can be set for the data signal, such as... Figure 2 As shown.

[0146] In this embodiment, the initial value of the first burst end signal BMDONE_Edge corresponding to the edge signal can be 0, and the initial value of the second burst end signal BMDONE_Data corresponding to the data signal can also be 0. That is, when the BMCDR system enters the closed-loop state, BMDONE_Edge = 0 and BMDONE_Data = 0. After the edge clock detects an edge, the value of the first burst end signal BMDONE_Edge can be modified (e.g., toggled), for example, modified to BMDONE_Edge = 1; after the data clock detects an edge, the value of the second burst end signal BMDONE_Data can be modified, for example, modified to BMDONE_Data = 1. If neither the edge clock nor the data clock detects an edge, neither the first burst end signal BMDONE_Edge nor the second burst end signal BMDONE_Data is modified (e.g., neither is toggled), the CDR remains in the open-loop state, the sampling clock continues to move under the control of the step control module, and the sampling module continues sampling for the next cycle.

[0147] In this embodiment of the disclosure, during the burst CDR phase, the movement of the sampling clock and the edge detection function of the burst mode phase detector are performed in parallel. The phase change circuit (e.g., PI) will continue to rotate forward by a fixed step value every time until the burst mode phase detector determines that the sampling clock has reached the edge and modifies the BMDONE signal.

[0148] In this embodiment of the disclosure, when the burst end signal BMDONE is modified (e.g., from low level to high level), it represents the end of the burst CDR phase. The switching control module receives the modified burst end signal BMDONE. At this time, the switching control module generates a mode switching control signal based on the modified burst end signal BMDONE, so that the data selector only collects the input signal of the low-pass filter based on the mode switching control signal, and the step control module stops outputting the step value, so that the BMCDR system enters a closed-loop state, that is, the CDR circuit is switched to the continuous CDR phase by the switching control module.

[0149] In this embodiment, when both the edge clock and the data clock are searching for the preamble edge, if the data clock finds the edge first, the burst mode phase detector will first modify the BMDONE_Data value, for example, by toggling the BMDONE_Data signal to a high level. At this time, the switching control module will switch the BMCDR system to a closed-loop state based on the modified BMDONE_Data value. If the edge clock finds the edge first, the burst mode phase detector will first modify the BMDONE_Edge value, for example, by toggling the BMDONE_Edge signal to a high level. At this time, the switching control module will switch the BMCDR system to a closed-loop state based on the modified BMDONE_Edge value. That is, after detecting any one or more changes to the burst end signal, the system state can be switched to a closed-loop state.

[0150] In this embodiment of the disclosure, the sampling clock includes a data clock; after modifying the burst end signal corresponding to the signal sampling result, the method may further include:

[0151] A preset compensation strategy is used to compensate for the modification lag of the burst end signal, so that the sampling position of the sampling clock is located at the target sampling position on the preamble before data sampling is performed based on the data clock in the closed loop state.

[0152] In this embodiment, because the entire system is a mixed-signal system, in reality, there will be delays in the analog circuit due to the response speed of the devices and delays in the digital circuit due to the clock timing required for function triggering. The sum of these two delays constitutes the possible delay in the entire loop. Due to these delays, the time from the sampling module acquiring the result to the final system response is not real-time. Even if the sampling clock has reached its edge, the counter decoder will continue to operate according to the previously set open-loop control phase-changing circuit (e.g., PI). As a result, when the burst end signal BMDONE is changed to a high level and the system switches to the continuous CDR stage, the sampling clock is no longer at the edge of the signal. Correspondingly, the data clock will not be exactly at the optimal sampling position, but will deviate a certain distance in the open-loop movement direction. The magnitude of this distance mainly comes from the delay caused by the timing of the digital circuit's function implementation.

[0153] In this embodiment of the disclosure, based on the above reasons, in order to compensate for the clock position error caused by loop delay, a preset compensation strategy can be used to compensate for the modification lag of the burst end signal, so that the sampling position of the sampling clock is located at the target sampling position on the preamble before data sampling is performed based on the data clock in the closed loop state.

[0154] In the embodiments of this disclosure, two situations can be considered when performing compensation: one is the case where the data clock is involved in finding the edge (e.g., finding the edge solely through the data clock, or finding the edge together using the data clock and the edge clock), and the other is the case where the data clock is not involved in finding the edge (e.g., finding the edge solely through the edge clock). Since the compensation strategies for the data clock and the edge clock are different, the compensation strategies can be described separately for the above two situations.

[0155] In the embodiments of this disclosure, the following describes a compensation strategy for the edge clock when finding the edge solely through the edge clock.

[0156] In this embodiment of the disclosure, the sampling clock further includes an edge clock; the compensation strategy for the modification lag of the burst end signal using a preset compensation strategy may include:

[0157] When the edge clock reaches the preamble edge, the preset first cyclic value is added to the total step value of the edge clock to compensate for the modification lag of the burst end signal.

[0158] In this embodiment of the disclosure, Figure 6 This illustration shows a compensation strategy diagram incorporating a rotation value (such as the first rotation value described above) according to an embodiment of this disclosure. The diagram incorporates a delayed rotation mechanism. Figure 6The vertical axis represents the control code (i.e., step value) of the phase-changing circuit (e.g., PI) output by the counter decoder, and the horizontal axis represents time. Line 1 shows the process of the control code signal of the phase-changing circuit changing over time under this proposal, and line 2 is the burst end signal BMDONE. Before the burst end signal BMDONE is modified, the phase-changing circuit (e.g., PI) is controlled in an open loop by the counter decoder, rotating stably at a certain number of steps. Due to the effect of delay, there is a certain gap between the phase-changing circuit (e.g., PI) control code corresponding to the position flipped by the burst end signal BMDONE and the range of the phase-changing circuit (e.g., PI) control code that finally stabilizes. The compensation strategy helps the phase-changing circuit (e.g., PI) control code return to the correct position. From then on, the phase-changing circuit (e.g., PI) control code fluctuates within an optimal sampling range around the final stopping position. Figure 6 The diagram illustrates the case where the edge clock detects the edge of the preamble. At this point, the rollback control module receives the BMDONE_Edge signal. Therefore, the rollback value output by the rollback control module only needs to compensate for the loop delay. The first rollback value, Rollback value1, can be expressed as:

[0159] Rollback value1=-N×BMSTEP;

[0160] Where BMSTEP is the step value, N is the rotation coefficient, N is a positive number, and N can be an empirical value.

[0161] In this embodiment, a slew rate N is set, representing that the burst end signal BMDONE is modified only after a delay of N system clock cycles. If an edge is detected by an edge clock, a certain slew rate is used to compensate for the lag in BMDONE signal modification caused by loop delay.

[0162] In the embodiments of this disclosure, a compensation strategy for the data clock is described below when the edge is found solely by the data clock.

[0163] In this embodiment of the disclosure, a preset compensation strategy is used to compensate for the modification lag of the burst termination signal, which may include:

[0164] When the data clock reaches the preamble edge, the preset second cyclic value is added to the total step value of the data clock, and the preset data unit is moved additionally.

[0165] In this embodiment of the disclosure, the data width corresponding to the preset data unit can be equal to the data bit width difference between the data clock and the edge clock.

[0166] In this embodiment, since the edge always has a certain phase difference with the data clock, and since the optimal sampling position for the data clock to acquire data is the middle position of a UI data, if the edge is detected by the data clock, after the edge is detected, in addition to backing up the total step value of the data clock by using a rotation value (such as a second rotation value), the data clock also needs to be moved to the middle position. For example, for a half-rate bang-bang phase detector, the data clock needs to continue to move forward (because the sampling clocks in this embodiment are all unidirectional) by 0.5 UI. For different binary phase detectors, the required phase to be moved (i.e., the aforementioned preset data unit) may be different. The detailed value of the preset data unit is not limited here, and can be defined according to the requirements.

[0167] In the embodiments disclosed herein, the aforementioned first rotation value and second rotation value may be the same or different, and no limitation is made herein; both can be determined based on empirical values.

[0168] In this embodiment of the disclosure, when using the data clock and the edge clock to find the edge together, the edge clock can be compensated by the compensation strategy corresponding to the edge clock, and the data clock can be compensated by the compensation strategy corresponding to the data clock.

[0169] In this embodiment of the disclosure, Figure 7 This diagram illustrates the changes in the control code of a phase-changing circuit (e.g., a PI converter) in two scenarios: the data clock and the edge clock respectively reach the edge of the preamble data symbol. Line 3 represents the case where the edge clock reaches the edge, and line 4 represents the case where the data clock reaches the edge. Unlike the case where the edge clock arrives first, the data clock, after arriving first, "rotates" in the opposite direction. To avoid excessively large shifts in a single operation based on the aforementioned compensation strategy, which could lead to race conditions in the control signal of the phase-changing circuit (e.g., a PI converter) due to path delay errors, the data clock is shifted by 0.5 UI in the opposite direction of delay compensation. Therefore, the second rollback value (Rollback value2) and the total rollback value for the data clock at this time are as follows:

[0170] Rollback value2=-N×BMSTEP;

[0171]

[0172] In this embodiment of the disclosure, when the data clock detects an edge, the above-mentioned total rollback value can be used to compensate the data clock, so that after the data clock finds the edge and compensates for the above-mentioned second rollback value, an additional phase shift of 0.5UI is performed, thereby aligning the data clock with the optimal sampling position of the data symbol of the preamble.

[0173] In this embodiment, the aforementioned first rollback value Rollbackvalue1, second rollback value Rollback value2, and total rollback value Rollback value can be generated by a preset rollback control module. For edge clock compensation, the rollback control module can output a one-time (-N×BMSTEP) value to the counting decoder, so that the counting decoder can compensate for the edge clock based on the first rollback value Rollback value1; for data clock compensation, the rollback control module can output a one-time... The counting decoder is used to compensate the data clock based on the total rollback value.

[0174] S14. In the closed-loop state, data is sampled based on the target sampling position, and clock data is recovered based on the sampled data.

[0175] In this embodiment of the disclosure, after the BMDONE modification (such as flipping) is completed, the counter decoder can record the termination value of the burst CDR phase (i.e. the final total step value) and use it as the starting value of the continuous CDR phase, and perform subsequent locking and data recovery work on this basis to prevent phase abrupt changes.

[0176] In this embodiment of the disclosure, a bang-bang phase detector is used in the closed-loop state, and its logical expression may include:

[0177]

[0178] The phase detection result Err is: Err = sum(late-early). This value is processed by the loop filter and then transmitted to the counting decoder to control the phase changing circuit (e.g., PI) for continuous phase tracking. Data is the data signal of the current beat, Data[k-1] is the data signal of the previous beat, Edge[k-1] is the edge signal of the previous beat, and late and early are the delay value and the lead value, respectively.

[0179] In summary, the embodiments of this disclosure provide a Burst-Mode Clock and Data Recovery (BMCDR) technology for achieving fast locking. Analysis of the current research status of BMCDR technology both domestically and internationally reveals issues such as poor consistency or high area and power consumption in mainstream BMCDR structures. To address these issues, a PI-based CDR structure is proposed, employing an edge detection technique based on a "0101" preamble. Utilizing the periodic variation of the "0101" preamble every two UI data points, while the PI is fixedly moved in one direction under open-loop control, the signal sampling results of the current and previous frames are XORed and compared to quickly locate the symbol edge (optimal sampling position).

[0180] This disclosure embodiment includes at least the following advantages:

[0181] 1. It enables BMCDR to lock as quickly as possible during the preamble stage in high-speed application scenarios.

[0182] 2. By not using traditional GVCO-based and oversampling schemes, the complexity of system design is reduced, the consistency problem between components in the circuit is avoided, and the chip area and power consumption are reduced.

[0183] 3. A novel fast locking logic is provided, based on the "0101" preamble, which can realize burst mode clock data recovery application in the SerDes receiver of high-speed passive optical network optical line terminal.

[0184] This disclosure also provides a clock data recovery device 100, such as... Figure 8 As shown, it may include:

[0185] One or more processors 101;

[0186] The memory 102 stores one or more programs, which, when executed by the one or more processors 101, enable the one or more processors 101 to implement the clock data recovery method.

[0187] One or more input / output (I / O) interfaces 103 are connected between the processor 101 and the memory 102 and configured to enable information interaction between the processor 101 and the memory 102.

[0188] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the clock data recovery method.

[0189] This disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements the clock data recovery method.

[0190] This disclosure also provides a clock data recovery system 200, such as... Figure 9 As shown, it includes: a mode switching module 201, a sampling module 202, and an edge finding module 203;

[0191] The sampling module 202 is configured to sample the preamble of the input data based on a unidirectionally moving sampling clock after the BMCDR system enters the open-loop state.

[0192] Edge finding module 203 is configured to find the edge of the preamble based on the signal sampling results of the current frame and the signal sampling results of the previous frame;

[0193] The mode switching module 201 is further configured to, after determining that the edge of the preamble has been found, determine the target sampling position based on the edge and switch the BMCDR system back to the closed-loop state.

[0194] The sampling module 202 is also configured to perform data sampling based on the target sampling position and to recover clock data based on the sampled data in closed-loop state.

[0195] In this embodiment of the disclosure, the sampling module 202 may include a sampler 2021 and a tap 2022.

[0196] In this embodiment of the disclosure, the mode switching module 201 is further configured to cause the BMCDR system to enter an open-loop state after the burst clock data recovery BMCDR system is started.

[0197] In the embodiments disclosed herein, such as Figure 10 As shown, the mode switching module 201 includes: a switching control module 2011, a step control module 2012, and a data selector 2013;

[0198] The switching control module 2011 is configured to acquire the BMCDR control signal and generate a mode switching control signal based on the BMCDR control signal.

[0199] The step control module 2012 is configured to generate step values; these step values ​​are used to control the movement of the sampling clock in a single direction at each step.

[0200] The data selector 2013 is configured to acquire only step values ​​based on the mode switching control signal, so that the BMCDR system enters an open-loop state. In this embodiment, the clock data recovery system 200 may further include: a sampling clock generation module 204;

[0201] The sampling clock generation module 204 is configured to generate a sampling clock that moves in a preset unidirectional direction.

[0202] In this embodiment of the disclosure, the sampling clock generation module 204 includes: a counter decoder 2041 and a phase changing circuit 2042;

[0203] The counter decoder 2041 is configured to perform statistics on the step values ​​collected by the data selector 2013;

[0204] The phase changing circuit 2042 is configured to generate a sampling clock with a corresponding clock frequency based on the data rate of the input data and the preset rate requirement, and to determine the movement value of each step in the sampling clock moving in a preset unidirectional direction based on the step value statistically obtained by the counter decoder.

[0205] In this embodiment of the disclosure, the phase changing circuit 2042 may include a phase interpolator PI and / or a voltage-controlled delay line VCDL.

[0206] In this embodiment of the disclosure, the edge-finding module 203 may include: a burst mode phase detector 2031; the burst mode phase detector 2031 is configured as follows:

[0207] Obtain the signal sampling results of the current frame and the signal sampling results of the previous frame;

[0208] The signal sampling results of the current shot are compared with the signal sampling results of the previous shot to perform a preset calculation;

[0209] If the calculation result corresponding to the preset calculation meets the first preset requirement, it is determined that the sampling clock has crossed the edge of the preamble.

[0210] In this embodiment of the disclosure, when the signal sampling result is a multi-bit parallel signal, the burst mode phase detector 2031 is further configured as follows:

[0211] The calculation is performed based on multiple calculation results from the multi-bit signal sampling results;

[0212] If the result of the operation meets the second preset requirement, it is determined that the sampling clock has crossed the edge of the preamble.

[0213] In this embodiment of the disclosure, the preset calculation includes: a first preset calculation; the first preset requirement includes: a first sub-preset requirement; the sampling clock includes an edge clock; and the signal sampling result includes: the edge signal obtained after the edge clock samples the input data.

[0214] The burst mode phase detector 2031 is also configured as follows:

[0215] Acquire the edge signal obtained in the previous frame and the edge signal obtained in the current frame;

[0216] Perform a first preset calculation on the edge signal obtained in the previous shot and the edge signal obtained in the current shot;

[0217] If the first calculation result corresponding to the first preset calculation satisfies the first sub-preset requirement, it is determined that the edge clock has crossed the edge of the preamble.

[0218] In this embodiment of the disclosure, the above operation includes a first operation, and the second preset requirement includes a second sub-preset requirement; when the edge signal is a multi-bit parallel signal, the burst mode phase detector 2031 is further configured as follows:

[0219] The first operation is performed based on multiple first calculation results of multi-bit edge signals;

[0220] If the result of the first operation corresponding to the first operation satisfies the second sub-preset requirement, it is determined that the edge clock has crossed the edge of the preamble.

[0221] In this embodiment of the disclosure, the preset calculation includes: a second preset calculation; the first preset requirement includes: a third sub-preset requirement; the sampling clock includes a data clock; and the signal sampling result includes: the data signal obtained after the data clock samples the input data.

[0222] The burst mode phase detector 2031 is also configured as follows:

[0223] Acquire the data signal obtained in the previous frame and the data signal obtained in the current frame;

[0224] Perform a second preset calculation using the data signal obtained in the previous frame and the data signal obtained in the current frame;

[0225] If the second calculation result corresponding to the second preset calculation satisfies the third sub-preset requirement, it is determined that the data clock has crossed the edge of the preamble.

[0226] In this embodiment of the disclosure, the above operation includes a second operation, and the second preset requirement includes: a fourth sub-preset requirement; when the data signal is a multi-bit parallel signal, the burst mode phase detector 2041 is further configured as follows:

[0227] A second operation is performed based on multiple second calculation results of multi-bit data signals;

[0228] If the result of the second operation corresponding to the second operation satisfies the fourth sub-preset requirement, it is determined that the data clock has crossed the edge of the preamble.

[0229] In this embodiment of the disclosure, the edge finding module 203 includes: a burst mode phase detector 2031;

[0230] The burst mode phase detector 2031 is configured to modify the burst end signal corresponding to the signal sampling result after determining that the edge of the preamble has been found.

[0231] The mode switching module 201 is also configured to control the BMCDR system to enter a closed-loop state based on the modified burst end signal.

[0232] In this embodiment of the disclosure, the mode switching module 201 includes: a switching control module 2011 and a data selector 2013; the mode switching module 201 controls the BMCDR system to enter a closed-loop state based on the modified burst end signal, including:

[0233] Switch control module 2011 is configured to acquire the burst end signal and generate a mode switchback control signal based on the burst end signal;

[0234] The data selector 2013 is configured to acquire only the input signal of the low-pass filter connected to the binary phase detector based on the mode back-cut control signal, so that the BMCDR system enters a closed-loop state.

[0235] In this embodiment of the disclosure, the sampling clock includes a data clock; the edge finding module 203 includes a rotation control module 2032;

[0236] The slewing control module 2032 is configured as follows:

[0237] After the burst mode phase detector 2031 modifies the burst end signal corresponding to the signal sampling result, a preset compensation strategy is used to compensate for the modification lag of the burst end signal, so that the sampling position of the sampling clock is located at the target sampling position on the preamble before data sampling is performed based on the data clock in the closed loop state.

[0238] In this embodiment of the disclosure, the sampling clock further includes an edge clock;

[0239] The slewing control module 2032 employs a preset compensation strategy to compensate for the lag in the modification of the sudden termination signal, including:

[0240] When the edge clock reaches the preamble edge, a preset gyration value is added to the total step value of the edge clock to compensate for the modification lag of the burst end signal.

[0241] In this embodiment of the disclosure, the slewing control module 2032 uses a preset compensation strategy to compensate for the modification lag of the sudden end signal, and further includes:

[0242] When the data clock reaches the preamble edge, a preset rotation value is added to the total step value of the data clock, and a preset data unit is moved additionally.

[0243] In this embodiment of the disclosure, the data width corresponding to the preset data unit can be equal to the data bit width difference between the data clock and the edge clock.

[0244] In this embodiment, after the system enters a closed-loop state, the data selector 2013 only collects the input data of a preset low-pass filter 205. This low-pass filter 205 receives the output data of a binary phase detector 206 (e.g., a bang-bang phase detector). The binary phase detector receives the signal sampling result obtained by the sampling module 202 sampling the input data based on a sampling clock at the optimal sampling position. The input data of the low-pass filter 205 collected by the data selector 2013 is sent to the phase-change circuit 2042 via a counter decoder 2041, so that the phase-change circuit 2042 maintains the sampling clock within a stable range based on the input data of the low-pass filter 205, thereby achieving accurate and stable clock data recovery.

[0245] Those skilled in the art will understand that all or some of the functional modules / units disclosed above can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0246] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0247] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0248] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A clock data recovery method, characterized in that, The method includes: After the BMCDR system enters the open-loop state, the preamble of the input data is sampled based on the sampling clock that moves in one direction. The edge of the preamble is found based on the signal sampling results of the current and previous sampling times. After determining that the edge of the preamble has been found, the target sampling position is determined based on the edge, and the BMCDR system is switched back to the closed-loop state. In the closed-loop state, data is sampled based on the target sampling position, and clock data is recovered based on the sampled data.

2. The clock data recovery method according to claim 1, characterized in that, The step of finding the edge of the preamble based on the signal sampling results of the current frame and the signal sampling results of the previous frame includes: Obtain the signal sampling result of the current frame and the signal sampling result of the previous frame; The signal sampling result of the current frame and the signal sampling result of the previous frame are subjected to a preset calculation; If the calculation result corresponding to the preset calculation meets the first preset requirement, it is determined that the sampling clock has crossed the edge of the preamble.

3. The clock data recovery method according to claim 2, characterized in that, When the signal sampling result is a multi-bit parallel signal, the method further includes: The calculation is performed based on multiple calculation results of the multi-bit signal sampling results; If the result of the operation satisfies the second preset requirement, it is determined that the sampling clock has crossed the edge of the preamble.

4. The clock data recovery method according to claim 2 or 3, characterized in that, The sampling clock includes an edge clock, and the signal sampling result includes: the edge signal obtained after the edge clock samples the input data; And / or, The sampling clock includes a data clock, and the signal sampling result includes: the data signal obtained after the data clock samples the input data.

5. The clock data recovery method according to claim 1, characterized in that, Switching the BMCDR system back to closed-loop state includes: Modify the burst termination signal corresponding to the signal sampling result; The BMCDR system is controlled to enter a closed-loop state based on the modified burst termination signal.

6. The clock data recovery method according to claim 5, characterized in that, The sampling clock includes a data clock; after modifying the burst end signal corresponding to the signal sampling result, the method further includes: A preset compensation strategy is used to compensate for the modification lag of the burst end signal, so that the sampling position of the sampling clock is located at the target sampling position on the preamble before data sampling is performed based on the data clock in the closed-loop state.

7. The clock data recovery method according to claim 6, characterized in that, The sampling clock also includes an edge clock; The method of compensating for the modification lag of the burst termination signal using a preset compensation strategy includes: When the edge clock reaches the preamble edge, a preset first cyclic value is added to the total step value of the edge clock to compensate for the modification lag of the burst end signal.

8. The clock data recovery method according to claim 6, characterized in that, The method of compensating for the modification lag of the burst termination signal using a preset compensation strategy includes: When the data clock reaches the edge of the preamble, a preset second cyclic value is added to the total step value of the data clock, and a preset data unit is moved additionally.

9. A clock data recovery device, characterized in that, include: One or more processors; A memory having stored one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the clock data recovery method according to any one of claims 1-8; One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.

10. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the clock data recovery method according to any one of claims 1-8.

11. A clock data recovery system, characterized in that, include: Mode switching module, sampling module, and edge finding module; The sampling module is configured to sample the preamble of the input data based on a unidirectionally moving sampling clock after the BMCDR system enters the open-loop state. The edge finding module is configured to find the edge of the preamble based on the signal sampling results of the current frame and the signal sampling results of the previous frame. The mode switching module is configured to, after determining that the edge of the preamble has been found, determine the target sampling position based on the edge and switch the BMCDR system back to the closed-loop state. The sampling module is further configured to perform data sampling based on the target sampling position in the closed-loop state, and to recover clock data based on the sampled data.

12. The clock data recovery system according to claim 11, characterized in that, The edge-finding module includes a burst mode phase detector; the burst mode phase detector is configured as follows: Obtain the signal sampling result of the current frame and the signal sampling result of the previous frame; The signal sampling result of the current frame and the signal sampling result of the previous frame are subjected to a preset calculation; If the calculation result corresponding to the preset calculation meets the first preset requirement, it is determined that the sampling clock has crossed the edge of the preamble.

13. The clock data recovery system according to claim 12, characterized in that, When the signal sampling result is a multi-bit parallel signal, the burst mode phase detector is further configured as follows: The calculation is performed based on multiple calculation results of the multi-bit signal sampling results; If the result of the operation satisfies the second preset requirement, it is determined that the sampling clock has crossed the edge of the preamble.

14. The clock data recovery system according to claim 11, characterized in that, The edge-finding module includes: a burst mode phase detector; The burst mode phase detector is configured to modify the burst end signal corresponding to the signal sampling result after determining that the edge of the preamble has been found. The mode switching module is also configured to control the BMCDR system to enter a closed-loop state based on the modified burst end signal.

15. The clock data recovery system according to claim 14, characterized in that, The sampling clock includes a data clock; the edge finding module includes a rotation control module; The slewing control module is configured as follows: After the burst mode phase detector modifies the burst end signal corresponding to the signal sampling result, a preset compensation strategy is used to compensate for the modification lag of the burst end signal, so that before data sampling is performed based on the data clock in the closed-loop state, the sampling position of the sampling clock is located at the target sampling position on the preamble.

16. The clock data recovery system according to claim 15, characterized in that, The sampling clock also includes an edge clock; The slewing control module employs a preset compensation strategy to compensate for the modification lag of the sudden end signal, including: When the edge clock reaches the preamble edge, a preset gyration value is added to the total step value of the edge clock to compensate for the modification lag of the burst end signal.

17. The clock data recovery system according to claim 15, characterized in that, The slewing control module employs a preset compensation strategy to compensate for the modification lag of the sudden end signal, including: When the data clock reaches the edge of the preamble, a preset rotation value is added to the total step value of the data clock, and a preset data unit is moved additionally.

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